Display device

Abstract

The present invention relates to a display device capable of manufacturing a fine pattern even with high reflectivity, the display device comprising: a substrate (SSUB); a first electrode (AND) on the substrate; a light emitting layer (ES) on the first electrode; and a second electrode (CAT) on the light emitting layer. The first electrode includes: a first pattern layer (PTL1) including aluminum; a second pattern layer (PTL2) disposed on the first pattern layer and containing a transparent conductive material; a third pattern layer (PTL3) disposed on the second pattern layer and containing silver; and a fourth pattern layer (PTL4) disposed on the third pattern layer and containing a transparent conductive material.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly to a display device that can achieve the manufacture of fine patterns while having a high reflectivity. Background Art

[0002] A head-mounted display (HMD) is an image display device that is worn on a user's head in the form of glasses or a helmet, so as to form a focused image at a distance in front of the user's eyes. The head-mounted display can achieve virtual reality (VR) or augmented reality (AR).

[0003] The head-mounted display magnifies and displays the image displayed by a small display device using a plurality of lenses. Therefore, a display device suitable for a head-mounted display needs to provide an image with a high resolution, for example, an image with a resolution of 3000 PPI (Pixels Per Inch) or more. For this purpose, as a display device suitable for a head-mounted display, a silicon-based OLED (Organic Light Emitting Diode on Silicon, OLEDoS), which is a small high-resolution organic light-emitting display device, is used. OLEDoS is a device that displays an image by disposing an organic light-emitting diode (OLED) on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is configured.

[0004] Prior Art Documents

[0005] Patent Documents

[0006] Korean Patent Publication No. 10-2023-0030078 (published on March 6, 2023) Summary of the Invention

[0007] An object of the present invention is to provide a display device, an optical device, and a method for manufacturing a display device that can achieve the manufacture of fine patterns while having a high reflectivity.

[0008] The object of the present invention is not limited to the above-mentioned technical problems, and those skilled in the art can clearly understand other technical problems not mentioned from the following description.

[0009] A display device according to an embodiment of the present invention for achieving the above-described purpose includes: a substrate SSUB; a first electrode AND on the substrate; a light-emitting layer ES on the first electrode; and a second electrode CAT on the light-emitting layer. The first electrode includes: a first pattern layer PTL1 containing aluminum; a second pattern layer PTL2 disposed on the first pattern layer and containing a transparent conductive material; a third pattern layer PTL3 disposed on the second pattern layer and containing silver; and a fourth pattern layer TL4 disposed on the third pattern layer and containing a transparent conductive material.

[0010] The first pattern layer has a greater thickness than the third pattern layer.

[0011] The thickness of the first pattern layer is more than four times the thickness of the third pattern layer.

[0012] The first pattern layer has to a thickness of.

[0013] The third pattern layer has to a thickness of.

[0014] The second pattern layer has a thickness of below.

[0015] The fourth pattern layer has a thickness of below.

[0016] Viewed from a planar perspective, the first pattern layer has a larger area than the third pattern layer.

[0017] Viewed from a planar perspective, the first pattern layer has a larger area than the second pattern layer or the fourth pattern layer.

[0018] The third pattern layer is surrounded by the second pattern layer and the fourth pattern layer.

[0019] A display device according to an embodiment of the present invention further includes a pixel definition film PDL disposed on the first electrode.

[0020] The pixel definition film is disposed on the second pattern layer in a manner overlapping with an edge region of the first pattern layer.

[0021] The pixel definition film is disposed on the second pattern layer and the fourth pattern layer in a manner overlapping with an edge region of the first pattern layer.

[0022] The transparent conductive material includes indium tin oxide (ITO).

[0023] Moreover, an optical device according to an embodiment of the present invention for achieving the above-described purpose includes: a display device; and a light path conversion member on the display device. The display device includes: a substrate; a first electrode on the substrate; a light-emitting layer on the first electrode; and a second electrode on the light-emitting layer. The first electrode includes: a first pattern layer containing aluminum; a second pattern layer disposed on the first pattern layer and containing a transparent conductive material; a third pattern layer disposed on the second pattern layer and containing silver; and a fourth pattern layer disposed on the third pattern layer and containing a transparent conductive material.

[0024] The first pattern layer has a greater thickness than the third pattern layer.

[0025] Viewed from a planar perspective, the first pattern layer has a larger area than the third pattern layer.

[0026] Viewed from a planar perspective, the first pattern layer has a larger area than the second pattern layer or the fourth pattern layer.

[0027] Moreover, a method of manufacturing a display device according to an embodiment of the present invention for achieving the above-described purpose includes the step of forming a first electrode on a substrate. The step of forming the first electrode includes: sequentially forming a first material layer containing aluminum, a second material layer containing a transparent conductive material, a third material layer containing silver, and a fourth material layer containing a transparent conductive material; the step of forming a photoresist pattern on the fourth material layer; the step of forming a fourth pattern layer by wet-etching the fourth material layer using the photoresist pattern as a mask; the step of forming a third pattern layer by wet-etching the third material layer using the photoresist pattern as a mask; and the step of forming a second pattern layer and a first pattern layer by dry-etching the second material layer and the first material layer respectively using the photoresist pattern as a mask.

[0028] The method of manufacturing a display device according to an embodiment of the present invention further includes: the step of forming a pixel defining film on the first electrode having the first pattern layer, the second pattern layer, the third pattern layer, and the fourth pattern layer; the step of forming a light-emitting layer on the first electrode and the pixel defining film; and the step of forming a second electrode on the light-emitting layer.

[0029] Specific contents of other embodiments are included in the detailed description and the drawings.

[0030] (Advantages of the Invention)

[0031] According to the display device, the optical device, and the method of manufacturing a display device of the present invention, it is possible to manufacture a first electrode as a fine pattern while making it have a high reflectivity.

[0032] In addition, the effects achievable in the present invention are not limited to those mentioned above. Those of ordinary skill in the technical field to which the present invention pertains can clearly understand other effects not mentioned from the following descriptions. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is an exploded perspective view of a display device showing an embodiment.

[0034] Figure 2 is a block diagram of a display device showing an embodiment.

[0035] Figure 3 is an equivalent circuit diagram of a first pixel showing an embodiment.

[0036] Figure 4 is a layout diagram of an example of a display panel showing an embodiment.

[0037] Figure 5 and Figure 6 is showing Figure 4 a layout diagram of an embodiment of the display area of.

[0038] Figure 7 is a cross-sectional view of an example of a display panel taken along the I1-I1' line along Figure 5 .

[0039] Figure 8 is a top view of a display device showing an embodiment.

[0040] Figure 9 is a cross-sectional view taken along the I-I' line along Figure 8 .

[0041] Figure 10 is a cross-sectional view of a display device showing an embodiment.

[0042] Figure 11 is a top view of a display device showing an embodiment.

[0043] Figure 12 is along Figure 11 a cross-sectional view taken along the II-II' line of.

[0044] Figure 13 is a cross-sectional view of a display device showing an embodiment.

[0045] Figures 14 to 20 is a process cross-sectional view for explaining a manufacturing method of a display device showing an embodiment.

[0046] Figure 21 is a perspective view of a head-mounted display device showing an embodiment.

[0047] Figure 22 is an exploded perspective view showing an example of a head-mounted display device. Figure 21

[0048] Figure 23 is a perspective view showing a head-mounted display device according to an embodiment.

[0049] Description of Reference Numerals

[0050] INS: Insulating film; ES: Stack layer; PDL: Pixel definition film; PTL1: First pattern layer; PTL2: Second pattern layer; PTL3: Third pattern layer; PTL4: Fourth pattern layer; AND: First electrode; CAT: Second electrode; LE: Light-emitting element; CEA: Central region; EGA: Edge region; TFE: Encapsulation layer; EA1: First light-emitting region; EA2: Second light-emitting region; TK1, TK2: Thickness Detailed Description of Embodiments

[0051] Advantages, features, and methods for implementing the present invention can be clearly understood by referring to the accompanying drawings and embodiments described in detail therewith below. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms. Only, these embodiments are provided to completely disclose the present invention and fully disclose the scope of the present invention to those of ordinary skill in the technical field to which the present invention pertains. The present invention is only defined by the scope of the appended claims.

[0052] When an element or layer is "on" another element or layer, it includes a case where it is directly disposed above another element, or a case where another element is disposed between them. Throughout the specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for illustrating embodiments are merely illustrative, and the present invention is not limited to what is illustrated.

[0053] Although first, second, etc. are used to describe various components, these components are of course not limited by these terms. These terms are only used to distinguish one component from another. Thus, the first component mentioned below can of course also be the second component within the technical idea of the present invention.

[0054] Each feature of various embodiments of the present invention can be partially or wholly combined or combined with each other, and various linkages and drives can be achieved technically. Each embodiment can be implemented independently of each other or implemented together in an associated relationship.

[0055] Hereinafter, specific embodiments will be described with reference to the drawings. ​

[0056] Figure 1 is an exploded perspective view showing a display device according to an embodiment. Figure 2 is a block diagram showing a display device according to an embodiment.

[0057] Referring to Figure 1 and Figure 2 , a display device 10 according to an embodiment is a device that displays dynamic images or static images. The display device 10 according to an embodiment can be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic manuals, e-books, portable multimedia players (PMPs), navigation devices, ultra-mobile personal computers (UMPCs), etc. For example, the display device 10 according to an embodiment can be used as a display unit for a television, a notebook, a monitor, an advertising board, or the Internet of Things (IoT). Alternatively, the display device 10 according to an embodiment can be applied to smart watches, watch phones, and head-mounted display devices (HMDs) for realizing virtual reality and augmented reality.

[0058] The display device 10 according to an embodiment includes: a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit 400, and a power supply circuit 500.

[0059] The display panel 100 can be formed in a planar shape similar to a quadrilateral. For example, the display panel 100 can have a planar shape similar to a quadrilateral with a short side in a first direction DR1 and a long side in a second direction DR2 that intersects the first direction DR1. In the display panel 100, the corners where the short side in the first direction DR1 and the long side in the second direction DR2 meet can be formed roundly with a predetermined curvature or at right angles. The planar shape of the display panel 100 is not limited to a quadrilateral and can be formed similar to other polygons, circles, or ellipses. The planar shape of the display device 10 can follow the planar shape of the display panel 100, but the embodiments of this specification are not limited thereto.

[0060] As Figure 2 shown, the display panel 100 can include a display area DAA for displaying an image and a non-display area NDA for not displaying an image.

[0061] The display area DAA includes: a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL.

[0062] A plurality of pixels PX can be arranged in a matrix form in a first direction DR1 and a second direction DR2. A plurality of scan lines SL and a plurality of light emission control lines EL can extend in the first direction DR1 and are arranged in the second direction DR2. A plurality of data lines DL can extend in the second direction DR2 and are arranged in the first direction DR1.

[0063] The plurality of scan lines SL include: a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines GBL. The plurality of light emission control lines EL include a plurality of first light emission control lines EL1 and a plurality of second light emission control lines EL2.

[0064] The plurality of unit pixels UPX include a plurality of pixels PX1, PX2, PX3. As Figure 3 shown, the plurality of pixels PX1, PX2, PX3 include a plurality of pixel transistors, and the plurality of pixel transistors can be formed using a semiconductor process and are arranged on a semiconductor substrate ( Figure 7 SSUB). For example, the plurality of pixel transistors of the data driving unit 700 can be formed of CMOS (Complementary Metal Oxide Semiconductor).

[0065] Each pixel among the plurality of pixels PX1, PX2, PX3 can be connected to one write scan line GWL among the plurality of write scan lines GWL, one control scan line GCL among the plurality of control scan lines GCL, one bias scan line GBL among the plurality of bias scan lines GBL, one first light emission control line EL1 among the plurality of first light emission control lines EL1, one second light emission control line EL2 among the plurality of second light emission control lines EL2, and one data line DL among the plurality of data lines DL. Each pixel among the plurality of pixels PX1, PX2, PX3 can receive the data voltage of the data line DL according to the write scan signal of the write scan line GWL, and cause the light emitting element to emit light according to the data voltage.

[0066] The non-display area NDA includes: a scan driving unit 610, a light emission driving unit 620, and a data driving unit 700.

[0067] The scan driving unit 610 includes a plurality of scan transistors, and the light emission driving unit 620 includes a plurality of light emission transistors. The plurality of scan transistors and the plurality of light emission transistors can be formed using a semiconductor process and are formed on a semiconductor substrate ( Figure 7 SSUB). For example, the plurality of scan transistors and the plurality of light emission transistors can be formed of CMOS. Although Figure 2In the example, the scan driving unit 610 is disposed on the left side of the display area DAA, and the light emitting driving unit 620 is disposed on the right side of the display area DAA. However, the embodiments of this specification are not limited thereto. For example, the scan driving unit 610 and the light emitting driving unit 620 may be disposed on both the left and right sides of the display area DAA.

[0068] The scan driving unit 610 may include: a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the output units, namely the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613, may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate a write scan signal according to the scan timing control signal SCS of the timing control circuit 400, and sequentially output it to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal according to the scan timing control signal SCS, and sequentially output it to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal according to the scan timing control signal SCS, and sequentially output it to the bias scan line EBL.

[0069] The light emitting driving unit 620 includes a first light emitting control driving unit 621 and a second light emitting control driving unit 622. Each of the driving units, namely the first light emitting control driving unit 621 and the second light emitting control driving unit 622, may receive a light emitting timing control signal ECS from the timing control circuit 400. The first light emitting control driving unit 621 may generate a first light emitting control signal according to the light emitting timing control signal ECS, and sequentially output it to the first light emitting control line EL1. The second light emitting control driving unit 622 may generate a second light emitting control signal according to the light emitting timing control signal ECS, and sequentially output it to the second light emitting control line EL2.

[0070] The data driving unit 700 includes a plurality of data transistors. The plurality of data transistors may be formed using a semiconductor process and formed on a semiconductor substrate ( Figure 7 of the SSUB). For example, the plurality of data transistors may be formed of CMOS.

[0071] The data driving unit 700 may receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driving unit 700 transforms the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs it to the data line DL. In this case, the pixels PX1, PX2, and PX3 may be selected according to the write scan signal of the scan driving unit 610, and the data voltage may be supplied to the selected pixels PX1, PX2, and PX3.

[0072] The heat dissipation layer 200 may overlap with the display panel 100 in the thickness direction of the display panel 100, i.e., the third direction DR3. The heat dissipation layer 200 may be disposed on one side of the display panel 100, for example, on the back surface. The heat dissipation layer 200 functions to release the heat generated in the display panel 100. The heat dissipation layer 200 may include a metal layer such as graphite, silver (Ag), copper (Cu), or aluminum (Al) having a high thermal conductivity.

[0073] The circuit board 300 may be electrically connected to the plurality of first pads ( Figure 4 PD1 of PDA1) of the first pad portion of the display panel 100 by using a conductive adhesive member such as an anisotropic conductive film. Figure 4 The circuit board 300 may be a flexible printed circuit board or a flexible film made of a flexible material. Although the circuit board 300 is illustrated as being in an unfolded state in Figure 1 , the circuit board 300 may be bent. In this case, one end of the circuit board 300 may be disposed on the back surface of the display panel 100 and / or the back surface of the heat dissipation layer 200. One end of the circuit board 300 may be the opposite end of the other end of the circuit board 300 that is connected to the plurality of first pads ( Figure 4 PD1 of PDA1) of the first pad portion of the display panel 100 by using a conductive adhesive member. Figure 4

[0074] The timing control circuit 400 may receive digital video data and timing signals from the outside. The timing control circuit 400 may generate a scan timing control signal SCS, a light emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100 according to the timing signals. The timing control circuit 400 may output the scan timing control signal SCS to the scan driving unit 610 and output the light emission timing control signal ECS to the light emission driving unit 620. The timing control circuit 400 may output the digital video data and the data timing control signal DCS to the data driving unit 700.

[0075] The power supply circuit 500 may generate a plurality of panel driving voltages according to the power supply voltage from the outside. For example, the power supply circuit 500 may generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT and supply them to the display panel 100. The description of the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT will be described later in conjunction with Figure 3 .

[0076] ​The timing control circuit 400 and the power supply circuit 500 can be respectively formed as integrated circuits (ICs) and attached to one side of the circuit board 300. In this case, the scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 through the circuit board 300. Also, the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 through the circuit board 300.

[0077] Alternatively, the timing control circuit 400 and the power supply circuit 500 can be respectively arranged in the non-display area NDA of the display panel 100 in a similar manner to the scan driving unit 610, the emission driving unit 620, and the data driving unit 700. In this case, the timing control circuit 400 can include a plurality of timing transistors, and the power supply circuit 500 includes a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors can be formed using a semiconductor process and formed on a semiconductor substrate ( Figure 7 of SSUB). For example, the plurality of timing transistors and the plurality of power transistors can be formed of CMOS. The timing control circuit 400 and the power supply circuit 500 can be respectively arranged between the data driving unit 700 and the first pad unit ( Figure 4 of PDA1).

[0078] Figure 3 is an equivalent circuit diagram of the first pixel of an embodiment.

[0079] Referring to Figure 3 , the first pixel PX1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line EBL, the first emission control line EL1, the second emission control line EL2, and the data line DL. Also, the first pixel PX1 can be connected to the first driving voltage line VSL, the second driving voltage line VDL, and the third driving voltage line VIL. The first driving voltage line VSL is connected to the first driving voltage VSS equivalent to a low potential voltage, the second driving voltage line VDL is connected to the second driving voltage VDD equivalent to a high potential voltage, and the third driving voltage line VIL is connected to the third driving voltage VINT equivalent to an initialization voltage. That is, the first driving voltage line VSL can be a low potential voltage line, the second driving voltage line VDL is a high potential voltage line, and the third driving voltage line VIL is an initialization voltage line. At this time, the first driving voltage VSS can be a voltage lower than the third driving voltage VINT. The second driving voltage VDD can be a voltage higher than the third driving voltage VINT.

[0080] The first pixel PX1 includes: a plurality of transistors T1 to T6, a light emitting element (Light Emitting Element, LE), a first capacitor CP1, and a second capacitor CP2.

[0081] The light emitting element LE emits light based on the drive current Ids flowing through the channel of the first transistor T1. The light emission amount of the light emitting element LE can be proportional to the drive current Ids. The light emitting element LE can be disposed between the fourth transistor T4 and the first drive voltage line VSL. The first electrode of the light emitting element LE can be connected to the drain electrode of the fourth transistor T4, and the second electrode is connected to the first drive voltage line VSL. The first electrode of the light emitting element LE can be an anode electrode, and the second electrode of the light emitting element LE is a cathode electrode. The light emitting element LE can be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer disposed between the first electrode and the second electrode, but the embodiments of this specification are not limited thereto. For example, the light emitting element LE can be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. In this case, the light emitting element LE can be a micro light emitting diode.

[0082] The first transistor T1 can be a drive transistor that controls the source-drain current (Ids, hereinafter referred to as "drive current") flowing between the source electrode and the drain electrode according to the voltage applied to the gate electrode. The first transistor T1 includes: a gate electrode connected to the first node N1; a source electrode connected to the drain electrode of the sixth transistor T6; and a drain electrode connected to the second node N2.

[0083] The second transistor T2 can be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by the write scan signal of the write scan line GWL, and connects one electrode of the first capacitor CP1 to the data line DL. Thus, the data voltage of the data line DL can be applied to one electrode of the first capacitor CP1. The second transistor T2 includes: a gate electrode connected to the write scan line GWL; a source electrode connected to the data line DL; and a drain electrode connected to one electrode of the first capacitor CP1.

[0084] The third transistor T3 may be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by a write control signal applied to the write control line GCL to connect the first node N1 and the second node N2. Thus, since the gate electrode and the source electrode of the first transistor T1 are connected, the first transistor T1 can operate like a diode. The third transistor T3 includes a gate electrode connected to the write control line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0085] The fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by a first light emission control signal applied to the first light emission control line EL1 to connect the second node N2 and the third node N3. Thus, the drive current of the first transistor T1 can be supplied to the light emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first light emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0086] The fifth transistor T5 may be disposed between the third node N3 and the third drive voltage line VIL. The fifth transistor T5 is turned on by a bias scan signal applied to the bias scan line EBL to connect the third node N3 and the third drive voltage line VIL. Thus, the third drive voltage VINT of the third drive voltage line VIL can be applied to the first electrode of the light emitting element LE. The fifth transistor T5 includes a gate electrode connected to the bias scan line EBL, a source electrode connected to the third node N3, and a drain electrode connected to the third drive voltage line VIL.

[0087] The sixth transistor T6 may be disposed between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by a second light emission control signal applied to the second light emission control line EL2 and connects the source electrode of the first transistor T1 and the second drive voltage line VDL. Thus, the second drive voltage VDD of the second drive voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second light emission control line EL2, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0088] The first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 includes one electrode connected to the drain electrode of the second transistor T2 and another electrode connected to the first node N1.

[0089] A second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor CP2 includes one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second driving voltage line VDL.

[0090] The first node N1 is a connection point of the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, another electrode of the first capacitor CP1, and one electrode of the second capacitor CP2. The second node N2 is a connection point of the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a connection point of the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0091] Each of the first to sixth transistors T1 to T6 may be a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). For example, each of the first to sixth transistors T1 to T6 may be a P-type MOSFET, but the embodiments of the present specification are not limited thereto. Each of the first to sixth transistors T1 to T6 may be an N-type MOSFET. Alternatively, some of the first to sixth transistors T1 to T6 may be P-type MOSFETs respectively, and the remaining transistors may be N-type MOSFETs respectively.

[0092] Although it is illustrated in Figure 3 that the first pixel PX1 includes six transistors T1 to T6 and two capacitors C1 and C2, it should be noted that the equivalent circuit diagram of the first pixel PX1 is not limited to Figure 3 shown content. For example, the number of transistors and the number of capacitors of the first pixel PX1 are not limited to Figure 3 shown content.

[0093] And, the equivalent circuit diagrams of the second pixel PX2 and the third pixel PX3 may be substantially the same as the equivalent circuit diagram of the first pixel PX1 described in conjunction with Figure 3 Therefore, in the present specification, the description of the equivalent circuit diagrams of the second pixel PX2 and the third pixel PX3 will be omitted.

[0094] Figure 4 is a layout diagram showing an example of a display panel according to an embodiment.

[0095] Refer to Figure 4, the display area DAA of the display panel 100 according to an embodiment includes a plurality of pixels PX arranged in a matrix shape. The non-display area NDA of the display panel 100 according to an embodiment includes: a scan driving unit 610, a light emitting driving unit 620, a data driving unit 700, a first distribution circuit 710, a second distribution circuit 720, a first pad unit PDA1, and a second pad unit PDA2.

[0096] The scan driving unit 610 may be disposed on a first side of the display area DAA, and the light emitting driving unit 620 is disposed on a second side of the display area DAA. For example, the scan driving unit 610 may be disposed on one side in a first direction DR1 of the display area DAA, and the light emitting driving unit 620 is disposed on the other side in the first direction DR1 of the display area DAA. That is, the scan driving unit 610 may be disposed on the left side of the display area DAA, and the light emitting driving unit 620 is disposed on the right side of the display area DAA. However, the embodiments of the present specification are not limited thereto, and the scan driving unit 610 and the light emitting driving unit 620 may be disposed on both the first side and the second side of the display area DAA.

[0097] The first pad unit PDA1 may include a plurality of first pads PD1 connected to pads or bumps of the circuit board 300 by a conductive adhesive member. The first pad unit PDA1 may be disposed on a third side of the display area DAA. For example, the first pad unit PDA1 may be disposed on one side in a second direction DR2 of the display area DAA. That is, the first pad unit PDA1 may be disposed on the lower side of the display area DAA.

[0098] The first pad unit PDA1 may be disposed outside the data driving unit 700 in the second direction DR2. That is, the first pad unit PDA1 may be disposed at a position closer to the edge of the display panel 100 than the data driving unit 700.

[0099] The second pad unit PDA2 may include a plurality of second pads PD2 corresponding to inspection pads for inspecting whether the display panel 100 operates normally. The plurality of second pads PD2 may be connected to a jig or a probe, or connected to an inspection circuit board during an inspection process. The inspection circuit board may be a printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0100] The first distribution circuit 710 distributes the data voltage accessed through the first pad portion PDA1 to a plurality of data lines DL. For example, the first distribution circuit 710 can distribute the data voltage accessed through one first pad PD1 of the first pad portion PDA1 to P (P is a positive integer of 2 or more) data lines DL, thereby reducing the number of the plurality of first pads PD1. The first distribution circuit 710 can be disposed on the third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be disposed on one side in the second direction DR2 of the display area DAA. That is, the first distribution circuit 710 can be disposed on the lower side of the display area DAA.

[0101] The second distribution circuit 720 distributes the signal accessed through the second pad portion PDA2 to the scan driving unit 610, the light emitting driving unit 620, and the data lines DL. The second pad portion PDA2 and the second distribution circuit 720 can be a configuration for checking the operation of each pixel PX in the display area DAA. The second distribution circuit 720 can be disposed on the fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be disposed on the other side in the second direction DR2 of the display area DAA. That is, the second distribution circuit 720 can be disposed on the upper side of the display area DAA.

[0102] Figure 5 and Figure 6 is a layout diagram showing Figure 4 an embodiment of the display area.

[0103] Referring to Figure 5 and Figure 6 , each of the plurality of unit pixels UPX includes: a first light emitting area EA1 that is a light emitting area of the first pixel PX1; a second light emitting area EA2 that is a light emitting area of the second pixel PX2; and a third light emitting area EA3 that is a light emitting area of the third pixel PX3. In other words, the unit pixel UPX can include a unit light emitting area UEA, and the unit light emitting area UEA includes the aforementioned first light emitting area EA1, second light emitting area EA2, and third light emitting area EA3.

[0104] Referring to Figure 5 and Figure 6 , each unit light emitting area UEA includes: a first light emitting area EA1 that is a light emitting area of the first pixel PX1; a second light emitting area EA2 that is a light emitting area of the second pixel PX2; and a third light emitting area EA3 that is a light emitting area of the third pixel PX3.

[0105] Each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 can have a planar shape of a polygon, a circle, an ellipse, or an amorphous shape.

[0106] The maximum length of the first direction DR1 of the first light-emitting region EA1 can be less than the maximum length of the first direction DR1 of the second light-emitting region EA2 and the maximum length of the first direction DR1 of the third light-emitting region EA3. The maximum lengths of the first direction DR1 of the second light-emitting region EA2 and the third light-emitting region EA3 can be substantially the same.

[0107] The maximum length of the second direction DR2 of the first light-emitting region EA1 can be greater than the maximum length of the second direction DR2 of the second light-emitting region EA2 and the maximum length of the second direction DR2 of the third light-emitting region EA3. The maximum length of the second direction DR2 of the second light-emitting region EA2 can be greater than the maximum length of the second direction DR2 of the third light-emitting region EA3.

[0108] The first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 can have a planar shape of a hexagon composed of six straight lines as Figure 5 shown, but the embodiments of this specification are not limited thereto. The first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 can have other polygonal, circular, elliptical, or amorphous planar shapes in addition to the hexagon. Figure 6 As

[0109] shown, in each unit light-emitting region UEA, the first light-emitting region EA1 and the second light-emitting region EA2 can be adjacent in the first direction DR1. Also, the first light-emitting region EA1 and the third light-emitting region EA3 can be adjacent in the first direction DR1. Also, the second light-emitting region EA2 and the third light-emitting region EA3 can be adjacent in the second direction DR2. The areas of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 can be different from each other. Figure 5 Or, as

[0110] shown, the first light-emitting region EA1 and the second light-emitting region EA2 can be adjacent in the first direction DR1, while the second light-emitting region EA2 and the third light-emitting region EA3 are adjacent in the first diagonal direction DD1, and the first light-emitting region EA1 and the third light-emitting region EA3 are adjacent in the second diagonal direction DD2. The first diagonal direction DD1 is a direction between the first direction DR1 and the second direction DR2, which points in a direction inclined 45 degrees with respect to the first direction DR1 and the second direction DR2, and the second diagonal direction DD2 can be a direction orthogonal to the first diagonal direction DD1. Figure 6 As

[0111] The first light-emitting region EA1 can emit light of a first color, the second light-emitting region EA2 emits light of a second color, and the third light-emitting region EA3 emits light of a third color. Among them, the light of the first color can be light in the blue wavelength band, the light of the second color is light in the green wavelength band, and the light of the third color is light in the red wavelength band. For example, the blue wavelength band can refer to the wavelength band where the main peak wavelength of the light is approximately between 370 nm and 460 nm, the green wavelength band can refer to the wavelength band where the main peak wavelength of the light is approximately between 480 nm and 560 nm, and the red wavelength band indicates that the main peak wavelength of the light is approximately between 600 nm and 750 nm.

[0112] Although Figure 5 and Figure 6 illustrate that each unit light-emitting region UEA includes three light-emitting regions EA1, EA2, and EA3, the embodiments of this specification are not limited thereto. That is, each unit light-emitting region UEA can also include four light-emitting regions.

[0113] And, the arrangement of the light-emitting regions of the plurality of pixels PX is not limited to Figure 5 and Figure 6 shown. For example, the light-emitting regions of the plurality of pixels PX can be configured as a stripe structure in which the light-emitting regions are arranged in the first direction DR1, a corrugated tile structure in which the light-emitting regions have a diamond arrangement structure, or a hexagonal structure in which light-emitting regions having a hexagonal planar shape as shown in Figure 6 are arranged.

[0114] Figure 7 is a cross-sectional view showing an example of a display panel cut along the Figure 5 I1-I1' line.

[0115] Referring to Figure 7 , the display panel 100 includes: a semiconductor backplane SBP, a light-emitting element backplane EBP, a display element layer EML, a packaging layer TFE, an optical layer OPL, a cover layer CVL, and a polarizing plate POL.

[0116] The semiconductor backplane SBP includes: a semiconductor substrate SSUB including a plurality of pixel transistors PTR; a plurality of semiconductor insulating films covering the plurality of pixel transistors PTR; and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR respectively. The plurality of pixel transistors PTR can be the first to sixth transistors T1 to T6 described in combination with Figure 3 .

[0117] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type of impurity doping. A plurality of well regions WA can be disposed on the semiconductor substrate SSUB. The plurality of well regions WA can be regions doped with a second type of impurity. The second type of impurity can be different from the aforementioned first type of impurity. For example, when the first type of impurity is a p-type impurity, the second type of impurity can be an n-type impurity. Or, when the first type of impurity is an n-type impurity, the second type of impurity can be a p-type impurity.

[0118] Each of the plurality of well regions WA includes: a source region SA corresponding to the source electrode of the pixel transistor PTR; a drain region DA corresponding to the drain electrode; and a channel region CH disposed between the source region SA and the drain region DA.

[0119] A lower insulating film BINS can be disposed between the gate electrode GE and the well region WA. A side insulating film SINS can be disposed on the side of the gate electrode GE. The side insulating film SINS can be disposed on the lower insulating film BINS.

[0120] The source region SA and the drain region DA can each be a region doped with a first type of impurity. The gate electrode GE of the pixel transistor PTR can overlap the well region WA in the third direction DR3. The channel region CH can overlap the gate electrode GE in the third direction DR3. The source region SA can be disposed on one side of the gate electrode GE, and the drain region DA is disposed on the other side of the gate electrode GE.

[0121] Each of the plurality of well regions WA further includes: a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA; a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 can be a region having a lower impurity concentration than the source region SA under the action of the lower insulating film BINS. The second low-concentration impurity region LDD2 can be a region having a lower impurity concentration than the drain region DA under the action of the lower insulating film BINS. Under the action of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2, the distance between the source region SA and the drain region DA can be increased. Therefore, since the length of the channel region CH of each pixel transistor PTR can be increased, the punch-through effect and the hot carrier effect caused by a short channel can be prevented.

[0122] The first semiconductor insulating film SINS1 can be disposed on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 can be formed as an inorganic film of silicon carbonitride (SiCN) or silicon oxide (SiOx) series, but the embodiments of this specification are not limited thereto.

[0123] The second semiconductor insulating film SINS2 can be disposed on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 can be formed as an inorganic film of silicon oxide (SiOx) series, but the embodiments of this specification are not limited thereto.

[0124] A plurality of contact terminals CTE can be disposed on the second semiconductor insulating film SINS2. Each contact terminal among the plurality of contact terminals CTE can be connected to one of the gate electrode GE, source region SA, and drain region DA of each pixel transistor PTR through a hole penetrating the first semiconductor insulating film SINS1 and the second semiconductor insulating film INS2. The plurality of contact terminals CTE can be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of them.

[0125] A third semiconductor insulating film SINS3 can be disposed on the side surfaces of each contact terminal among the plurality of contact terminals CTE. The upper surface of each contact terminal among the plurality of contact terminals CTE can be exposed and not covered by the third semiconductor insulating film SINS3. The third semiconductor insulating film SINS3 can be formed of an inorganic film of silicon oxide (SiOx) series, but the embodiments of this specification are not limited thereto.

[0126] The semiconductor substrate SSUB can be replaced by a glass substrate or a polymer resin substrate such as polyimide. In this case, thin film transistors can be disposed on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that cannot be bent, and the polymer resin substrate is a flexible substrate that can be bent or curved.

[0127] The light-emitting element backplane EBP includes: a plurality of conductive layers ML1 to ML8, a plurality of vias VA1 to VA9, and a plurality of insulating films INS1 to INS9. Moreover, the light-emitting element backplane EBP includes a plurality of insulating films INS1 to INS9 disposed between the first to eighth conductive layers ML1 to ML8.

[0128] The first to eighth conductive layers ML1 to ML8 function to connect the plurality of contact terminals CTE exposed in the semiconductor backplane SBP to achieve Figure 4Function of the circuit of the first pixel PX1 shown. For example, only the first to sixth transistors T1 to T6 are formed on the semiconductor backplane SBP, and the connections of the first to sixth transistors T1 to T6, and the first capacitor CP1 and the second capacitor CP2 are realized by the first to eighth conductive layers ML1 to ML8. Also, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE is also realized by the first to eighth conductive layers ML1 to ML8.

[0129] The first insulating film INS1 can be disposed on the semiconductor backplane SBP. Each first via hole VA1 can penetrate the first insulating film INS1 and be connected to the contact terminal CTE exposed from the semiconductor backplane SBP. Each first conductive layer ML1 can be disposed on the first insulating film INS1 and be connected to the first via hole VA1.

[0130] The second insulating film INS2 can be disposed on the first insulating film INS1 and the first conductive layer ML1. Each second via hole VA2 can penetrate the second insulating film INS2 and be connected to the exposed first conductive layer ML1. Each second conductive layer ML2 can be disposed on the second insulating film INS2 and be connected to the second via hole VA2.

[0131] The third insulating film INS3 can be disposed on the second insulating film INS2 and the second conductive layer ML2. Each third via hole VA3 can penetrate the third insulating film INS3 and be connected to the exposed second conductive layer ML2. Each third conductive layer ML3 can be disposed on the third insulating film INS3 and be connected to the third via hole VA3.

[0132] The fourth insulating film INS4 can be disposed on the third insulating film INS3 and the third conductive layer ML3. Each fourth via hole VA4 can penetrate the fourth insulating film INS4 and be connected to the exposed third conductive layer ML3. Each fourth conductive layer ML4 can be disposed on the fourth insulating film INS4 and be connected to the fourth via hole VA4.

[0133] The fifth insulating film INS5 can be disposed on the fourth insulating film INS4 and the fourth conductive layer ML4. Each fifth via hole VA5 can penetrate the fifth insulating film INS5 and be connected to the exposed fourth conductive layer ML4. Each fifth conductive layer ML5 can be disposed on the fifth insulating film INS5 and be connected to the fifth via hole VA5.

[0134] The sixth insulating film INS6 can be disposed on the fifth insulating film INS5 and the fifth conductive layer ML5. Each sixth via hole VA6 can penetrate the sixth insulating film INS6 and be connected to the exposed fifth conductive layer ML5. Each sixth conductive layer ML6 can be disposed on the sixth insulating film INS6 and be connected to the sixth via hole VA6.

[0135] The seventh insulating film INS7 may be disposed on the sixth insulating film INS6 and the sixth conductive layer ML6. Each seventh via hole VA7 may penetrate the seventh insulating film INS7 and be connected to the exposed sixth conductive layer ML6. Each seventh conductive layer ML7 may be disposed on the seventh insulating film INS7 and be connected to the seventh via hole VA7.

[0136] The eighth insulating film INS8 may be disposed on the seventh insulating film INS7 and the seventh conductive layer ML7. Each eighth via hole VA8 may penetrate the eighth insulating film INS8 and be connected to the exposed seventh conductive layer ML7. Each eighth conductive layer ML8 may be disposed on the eighth insulating film INS8 and be connected to the eighth via hole VA8.

[0137] The first to eighth conductive layers ML1 to ML8 and the first to eighth via holes VA1 to VA8 may be substantially made of the same material. The first to eighth conductive layers ML1 to ML8 and the first to eighth via holes VA1 to VA8 may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of them. The first to eighth via holes VA1 to VA8 may be substantially made of the same material. The first to eighth insulating films INS1 to INS8 may be formed as an inorganic film of the silicon oxide (SiOx) series, but the embodiments of this specification are not limited thereto.

[0138] The thickness of each of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be greater than the thickness of each of the first via hole VA1, the second via hole VA2, the third via hole VA3, the fourth via hole VA4, the fifth via hole VA5, and the sixth via hole VA6. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be greater than the thickness of the first conductive layer ML1. The thicknesses of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be substantially the same. For example, the thickness of the first conductive layer ML1 may be about The thicknesses of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may each be about The thicknesses of the first vias VA1, the second vias VA2, the third vias VA3, the fourth vias VA4, the fifth vias VA5, and the sixth vias VA6 may each be approximately

[0139] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than the thickness of each of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than the thickness of each of the seventh vias VA7 and the eighth vias VA8. The thickness of each of the seventh vias VA7 and the eighth vias VA8 may be greater than the thickness of each of the first vias VA1, the second vias VA2, the third vias VA3, the fourth vias VA4, the fifth vias VA5, and the sixth vias VA6. The thicknesses of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be substantially the same. For example, the thicknesses of the seventh conductive layer ML7 and the eighth conductive layer ML8 may each be approximately The thicknesses of the seventh vias VA7 and the eighth vias VA8 may each be approximately

[0140] The ninth insulating film INS9 may be disposed on the eighth insulating film INS8 and the eighth conductive layer ML8. The ninth insulating film INS9 may be formed as an inorganic film of a silicon oxide (SiOx) series, but the embodiments of the present specification are not limited thereto.

[0141] Each ninth via VA9 may penetrate the ninth insulating film INS9 and be connected to the exposed eighth conductive layer ML8. The ninth via VA9 may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of them. The thickness of the ninth via VA9 may be approximately

[0142] The display element layer EML may be disposed on the light-emitting element backplane EBP. The display element layer EML may include a reflective electrode layer RL, tenth and eleventh insulating films INS10, INS11, a tenth via VA10, a light-emitting element LE, a pixel defining film PDL, and a plurality of trenches TRC. The light-emitting elements LE each include a first electrode AND, a light-emitting stack ES, and a second electrode CAT.

[0143] On the ninth insulating film INS9, a reflective electrode layer RL may be disposed. The reflective electrode layer RL may include one or more reflective electrodes RL1, RL2, RL3, RL4. For example, as Figure 7 shown, the reflective electrode layer RL may include first to fourth reflective electrodes RL1, RL2, RL3, RL4.

[0144] Each first reflective electrode RL1 may be disposed on the ninth insulating film INS9 and connected to the ninth via VA9. The first reflective electrode RL1 may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or an alloy containing one of them. For example, the first reflective electrode RL1 may include titanium nitride (TiN).

[0145] Each second reflective electrode RL2 may be disposed on the first reflective electrode RL1. The second reflective electrode RL2 may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or an alloy containing one of them. For example, the second reflective electrode RL2 may include aluminum (Al).

[0146] Each third reflective electrode RL3 may be disposed on the second reflective electrode RL2. The third reflective electrode RL3 may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or an alloy containing one of them. For example, the third reflective electrode RL3 may include titanium nitride (TiN).

[0147] Each fourth reflective electrode RL4 may be disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or an alloy containing one of them. For example, the fourth reflective electrode RL4 may include titanium (Ti).

[0148] Since the second reflective electrode RL2 is substantially the electrode that reflects the light from the light-emitting element LE, the thickness of the second reflective electrode RL2 may be greater than the thicknesses of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, the thicknesses of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 may be about while the thickness of the second reflective electrode RL2 may be about

[0149] The tenth insulating film INS10 may be disposed on the ninth insulating film INS9. The tenth insulating film INS10 may be disposed between reflective electrode layers RL adjacent to each other in the horizontal direction. The tenth insulating film INS10 may be disposed beside the reflective electrode layer RL in the third pixel PX3. The tenth insulating film INS10 may be formed as an inorganic film of the silicon oxide (SiOx) series, but the embodiments of the present specification are not limited thereto.

[0150] The eleventh insulating film INS11 may be disposed on the tenth insulating film INS10 and the reflective electrode layer RL. The eleventh insulating film INS11 may be formed as an inorganic film of the silicon oxide (SiOx) series, but the embodiments of the present specification are not limited thereto. The tenth insulating film INS10 and the eleventh insulating film INS11 may be optical auxiliary layers through which the light reflected by the reflective electrode layer RL among the light emitted from the light-emitting element LE passes.

[0151] In order for at least one of the first pixel PX1, the second pixel PX2, and the third pixel PX3 to be adapted to the resonance distance of the light emitted from the light-emitting element LE, the tenth insulating film INS10 and the eleventh insulating film INS11 may not be disposed under the first electrode AND of the first pixel PX1. The first electrode AND of the first pixel PX1 may be directly disposed on the reflective electrode layer RL. The eleventh insulating film INS11 may be disposed under the first electrode AND of the second pixel PX2. The tenth insulating film INS10 and the eleventh insulating film INS11 may be disposed under the first electrode AND of the third pixel PX3.

[0152] In summary, the distances between the first electrode AND and the reflective electrode layer RL of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may be different from each other. That is, in order to adjust the distance from the reflective electrode layer RL to the second electrode CAT according to the main wavelength of the light emitted from each of the first pixel PX1, the second pixel PX2, and the third pixel PX3, it is set whether the tenth insulating film INS10 and the eleventh insulating film INS11 exist in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3. For example, although Figure 7 it is illustrated that the distance between the first electrode AND and the reflective electrode layer RL in the third pixel PX3 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the second pixel PX2 and the distance between the first electrode AND and the reflective electrode layer RL in the first pixel PX1, and the distance between the first electrode AND and the reflective electrode layer RL in the second pixel PX2 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the first pixel PX1, the embodiments of the present specification are not limited thereto.

[0153] Also, although the tenth insulating film INS10 and the eleventh insulating film INS11 are illustrated in the embodiments of this specification, a twelfth insulating film disposed under the first electrode AND of the first pixel PX1 may be additionally provided. In this case, the eleventh insulating film INS11 and the twelfth insulating film INS12 may be disposed under the first electrode AND of the second pixel PX2, and the tenth insulating film INS10, the eleventh insulating film INS11, and the twelfth insulating film INS12 may be disposed under the first electrode AND of the third pixel PX3.

[0154] Each tenth via hole VA10 may penetrate the eleventh insulating film INS11 and be connected to the reflective electrode layer RL. The tenth via hole VA10 may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of them. The thickness of the tenth via hole VA10 in the second pixel PX2 may be less than the thickness of the tenth via hole VA10 in the third pixel PX3.

[0155] The first electrode AND of each light-emitting element LE may be disposed on the tenth insulating film INS10 and connected to the tenth via hole VA10. The first electrode AND of each light-emitting element LE may be connected to the drain region DA or the source region SA of the pixel transistor PTR through the tenth via hole VA10, the first to fourth reflective electrodes RL1 to RL4, the first to ninth via holes VA1 to VA9, the first to eighth conductive layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each light-emitting element LE may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of them. For example, the first electrode AND of each light-emitting element LE may be titanium nitride (TiN).

[0156] The pixel defining film PDL may be disposed on a partial region of the first electrode AND of each light-emitting element LE. The pixel defining film PDL may cover the edge of the first electrode AND of each light-emitting element LE. The pixel defining film PDL serves to divide the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3.

[0157] The first light-emitting region EA1 can be defined as the region where the first electrode AND, the light-emitting stack ES, and the second electrode CAT are sequentially stacked and emit light in the first pixel PX1. The second light-emitting region EA2 can be defined as the region where the first electrode AND, the light-emitting stack ES, and the second electrode CAT are sequentially stacked and emit light in the second pixel PX2. The third light-emitting region EA3 can be defined as the region where the first electrode AND, the light-emitting stack ES, and the second electrode CAT are sequentially stacked and emit light in the third pixel PX3.

[0158] The pixel definition layer PDL may include first to third pixel definition layers PDL1, PDL2, and PDL3. The first pixel definition layer PDL1 may be disposed on the edge of the first electrode AND of each light-emitting element LE, the second pixel definition layer PDL2 may be disposed on the first pixel definition layer PDL1, and the third pixel definition layer PDL3 may be disposed on the second pixel definition layer PDL2. The first pixel definition layer PDL1, the second pixel definition layer PDL2, and the third pixel definition layer PDL3 may be formed as inorganic films of the silicon oxide (SiOx) series, but the embodiments of the present specification are not limited thereto. The thickness of the first pixel definition layer PDL1, the thickness of the second pixel definition layer PDL2, and the thickness of the third pixel definition layer PDL3 may each be about

[0159] In the case where the first pixel definition layer PDL1, the second pixel definition layer PDL2, and the third pixel definition layer PDL3 are formed as one pixel definition layer, the height of the one pixel definition layer becomes high, so that the first encapsulation inorganic film TFE1 may be disconnected due to step coverage. Step coverage refers to the ratio of the film coverage of the inclined portion to the film coverage of the flat portion. The lower the step coverage, the higher the possibility that the film is disconnected at the inclined portion.

[0160] Therefore, in order to prevent the first encapsulation inorganic film TFE1 from being disconnected due to step coverage, the first pixel definition layer PDL1, the second pixel definition layer PDL2, and the third pixel definition layer PDL3 may have a cross-sectional structure with stepped steps. For example, the width of the first pixel definition layer PDL1 may be greater than the width of the second pixel definition layer PDL2 and the width of the third pixel definition layer PDL3, and the width of the second pixel definition layer PDL2 may be greater than the width of the third pixel definition layer PDL3. The width of the first pixel definition layer PDL1 refers to the horizontal length of the first pixel definition layer PDL1 defined by the first direction DR1 and the second direction DR2.

[0161] Multiple trench TRCs can penetrate through the first pixel definition layer PDL1, the second pixel definition layer PDL2, and the third pixel definition layer PDL3 respectively. Moreover, each trench among the multiple trench TRCs can penetrate through the eleventh insulating layer INS11. At each trench among the multiple trench TRCs, a part of the tenth insulating layer INS10 can be in a concave shape.

[0162] At least one trench TRC can be disposed between adjacent pixels PX1, PX2, and PX3. Although Figure 7 illustrates that two trench TRCs are disposed between adjacent pixels PX1, PX2, and PX3, the embodiments of this specification are not limited thereto.

[0163] The light-emitting stack ES can include multiple stack layers. Although Figure 7 illustrates that the light-emitting stack ES has a 3-tandem structure including a first stack layer IL1, a second stack layer IL2, and a third stack layer IL3, the embodiments of this specification are not limited thereto. For example, the light-emitting stack ES can have a 2-tandem structure including two intermediate layers.

[0164] In the 3-tandem structure, the light-emitting stack ES can have a tandem structure including multiple stack layers IL1, IL2, and IL3 that emit different lights from each other. For example, the light-emitting stack ES can include: a first stack layer IL1 that emits light of a first color; a second stack layer IL2 that emits light of a third color; and a third stack layer IL3 that emits light of a second color. The first stack layer IL1, the second stack layer IL2, and the third stack layer IL3 can be stacked in sequence.

[0165] The first stack layer IL1 can have a structure in which a first hole transport layer, a first organic light-emitting layer that emits light of a first color, and a first electron transport layer are stacked in sequence. The second stack layer IL2 can have a structure in which a second hole transport layer, a second organic light-emitting layer that emits light of a third color, and a second electron transport layer are stacked in sequence. The third stack layer IL3 can have a structure in which a third hole transport layer, a third organic light-emitting layer that emits light of a second color, and a third electron transport layer are stacked in sequence.

[0166] A first charge generation layer can be disposed between the first stack layer IL1 and the second stack layer IL2 for supplying charges to the second stack layer IL2 and supplying electrons to the first stack layer IL1. The first charge generation layer can include: an N-type charge generation layer for supplying electrons to the first stack layer IL1; and a P-type charge generation layer for supplying holes to the second stack layer IL2. The N-type charge generation layer can contain a dopant of a metal substance.

[0167] A second charge generation layer for supplying charge to the third stack layer IL3 and electrons to the second stack layer IL2 may be disposed between the second stack layer IL2 and the third stack layer IL3. The second charge generation layer may include: an N-type charge generation layer for supplying electrons to the second stack layer IL2; and a P-type charge generation layer for supplying holes to the third stack layer IL3.

[0168] The first stack layer IL1 may be disposed on the first electrode AND and the pixel defining film PDL, and on the bottom surface of each trench TRC of the trench TRC. Under the action of the trench TRC, the first stack layer IL1 may be disconnected between adjacent pixels PX1, PX2, PX3. The second stack layer IL2 may be disposed on the first stack layer IL1. Under the action of the trench TRC, the second stack layer IL2 may be disconnected between adjacent pixels PX1, PX2, PX3. A void ES or a blank space may be disposed between the first stack layer IL1 and the second stack layer IL2. The third stack layer IL3 may be disposed on the second stack layer IL2. The third stack layer IL3 may be configured not to be disconnected by the trench TRC and to cover the second stack layer IL2 at each trench TRC. That is, in the 3-series structure, each trench of the plurality of trenches TRC may be a structure for disconnecting the first to second stack layers IL1, IL2, the first charge generation layer, and the second charge generation layer of the display element layer EML between adjacent pixels PX1, PX2, PX3. And, in the 2-series structure, each trench of the plurality of trenches TRC may be a structure for disconnecting the charge generation layer disposed between the lower intermediate layer and the upper intermediate layer from the lower intermediate layer.

[0169] In order to stably disconnect the first to second stack layers IL1, IL2 of the display element layer EML between adjacent pixels PX1, PX2, PX3, the height of each trench of the plurality of trenches TRC may be greater than the height of the pixel defining film PDL. The height of each trench of the plurality of trenches TRC refers to the length of each trench of the plurality of trenches TRC in the third direction DR3. The height of the pixel defining film PDL refers to the length of the pixel defining film PDL in the third direction DR3. In order to disconnect the first to second stack layers IL1, IL2 of the display element layer EML between adjacent pixels PX1, PX2, PX3, other structures may be provided instead of the trench TRC. For example, an inverted conical partition wall may be disposed on the pixel defining film PDL instead of the trench TRC.

[0170] The number of stack layers IL1, IL2, IL3 that emit different lights is not limited to Figure 7The content shown. For example, the light-emitting stack ES may include two intermediate layers. In this case, one of the two intermediate layers is substantially the same as the first stack layer IL1, and the other intermediate layer may include: a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron transport layer. In this case, a charge generation layer for supplying electrons to one of the intermediate layers and supplying charges to the other intermediate layer may be disposed between the two intermediate layers.

[0171] And, although the case where the first to third stack layers IL1, IL2, IL3 are disposed in the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 is illustrated in Figure 7 , the embodiments of the present specification are not limited thereto. For example, the first stack layer IL1 may be disposed in the first light-emitting region EA1 and not disposed in the second light-emitting region EA2 and the third light-emitting region EA3. And, the second stack layer IL2 may be disposed in the second light-emitting region EA2 and not disposed in the first light-emitting region EA1 and the third light-emitting region EA3. And, the third stack layer IL3 may be disposed in the third light-emitting region EA3 and not disposed in the first light-emitting region EA1 and the second light-emitting region EA2. In this case, the first to third filter films CF1, CF2, CF3 of the optical layer OPL may be omitted.

[0172] The second electrode CAT may be disposed on the third stack layer IL3. The second electrode CAT may be disposed on the third stack layer IL3 of each of the plurality of trenches TRC. The second electrode CAT may be formed of a transparent conductive material (TCO, Transparent Conductive Material) such as ITO or IZO that allows light to transmit, or a semi-transmissive conductive material (Semi-transmissive Conductive Material) such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode CAT is formed of a semi-transmissive conductive material, the light extraction efficiency of each of the first to third pixels PX1, PX2, PX3 can be improved under the action of a micro cavity.

[0173] The encapsulation layer TFE may be disposed on the display element layer EML. The encapsulation layer TFE may include at least one inorganic film TFE1, TFE2 to prevent oxygen or moisture from penetrating into the display element layer EML. For example, the encapsulation layer TFE may include a first encapsulation inorganic film TFE1 and a second encapsulation inorganic film TFE2.

[0174] The first encapsulation inorganic film TFE1 can be disposed on the second electrode CAT. The first encapsulation inorganic film TFE1 can be formed as a multi-layer film in which one or more inorganic films such as silicon nitride (SiNx), silicon oxynitride (SiON), and silicon oxide (SiOx) are alternately stacked. The first encapsulation inorganic film TFE1 can be formed using a chemical vapor deposition (CVD) process.

[0175] The second encapsulation inorganic film TFE2 can be disposed on the first encapsulation inorganic film TFE1. The second encapsulation inorganic film TFE2 can be formed as a titanium oxide (TiOx) or an aluminum oxide layer (AlOx), but the embodiments of this specification are not limited thereto. The second encapsulation inorganic film TFE2 can be formed using an atomic layer deposition (ALD) process. The thickness of the second encapsulation inorganic film TFE2 can be less than the thickness of the first encapsulation inorganic film TFE1.

[0176] The organic film APL can be a layer for improving the interfacial adhesion between the encapsulation layer TFE and the optical layer OPL. The organic film APL can be an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0177] The optical layer OPL includes: a plurality of color filters CF1, CF2, CF3, a plurality of lenses LNS, and a filling layer FIL. The plurality of color filters CF1, CF2, CF3 can include first to third color filters CF1, CF2, CF3. The first to third color filters CF1, CF2, CF3 can be disposed on the organic film APL.

[0178] The first color filter CF1 can overlap with the first light-emitting region EA1 of the first pixel PX1. The first color filter CF1 can transmit light of a first color, that is, light in the blue wavelength band. The blue wavelength band can be approximately 370 nm to 460 nm. Therefore, the first color filter CF1 can transmit light of the first color in the light emitted from the first light-emitting region EA1.

[0179] The second color filter CF2 can overlap with the second light-emitting region EA2 of the second pixel PX2. The second color filter CF2 can transmit light of a second color, that is, light in the green wavelength band. The green wavelength band can be approximately 480 nm to 560 nm. Therefore, the second color filter CF2 can transmit light of the second color in the light emitted from the second light-emitting region EA2.

[0180] The third color filter CF3 may overlap with the third light-emitting region EA3 of the third pixel PX3. The third color filter CF3 may transmit light of a third color, that is, light in the red wavelength band. The blue wavelength band may be approximately 600 nm to 750 nm. Therefore, the third color filter CF3 may transmit light of the third color in the light emitted from the third light-emitting region EA3.

[0181] Each of the plurality of lenses LNS may be disposed on each of the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the plurality of lenses LNS may be a structure for increasing the ratio of light directed toward the front surface of the display device 10. Each of the lenses in the plurality of lenses LNS may have a cross-sectional shape that bulges upward.

[0182] The filling layer FIL may be disposed on the plurality of lenses LNS. The filling layer FIL may have a predetermined refractive index so that light travels in a third direction DR3 at the interface between the plurality of lenses LNS and the filling layer FIL. Also, the filling layer FIL may be a planarizing layer. The filling layer FIL may be an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0183] The cover layer CVL may be disposed on the filling layer FIL. The cover layer CVL may be a glass substrate or a polymer resin such as a resin. When the cover layer CVL is a glass substrate, it may be attached to the filling layer FIL. In this case, the filling layer FIL may serve to bond the cover layer CVL. When the cover layer CVL is a glass substrate, it may be used as an encapsulation substrate. When the cover layer CVL is a polymer resin such as a resin, it may be directly coated on the filling layer FIL.

[0184] The polarizing plate POL may be disposed on one surface of the cover layer CVL. The polarizing plate POL may be a structure for preventing a decrease in visibility caused by reflection of external light. The polarizing plate POL may include a linear polarizing plate and a phase retardation film. For example, the phase retardation film may be a quarter-wave plate, but the embodiments of the present specification are not limited thereto. However, when the visibility due to reflection of external light is sufficiently improved by using the first to third color filters CF1, CF2, and CF3, the polarizing plate POL may also be omitted.

[0185] Figure 8 is a top view of a display device according to an embodiment, Figure 9 is along Figure 8A cross-sectional view taken along the line I-I'.

[0186] As Figure 8 and Figure 9 shown, in each light-emitting region EA1, EA2, EA3, a first electrode AND can be correspondingly disposed. For example, in the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3, first electrodes AND can be respectively and correspondingly disposed. The first electrodes AND of the first to third light-emitting regions EA1, EA2, EA3 can have the same structure. Therefore, the following description will be centered around the first electrode AND of the first light-emitting region EA1.

[0187] As Figure 9 shown, the first electrode AND can include multiple layers (for example, a pattern layer). For example, the first electrode AND can include a first pattern layer PTL1, a second pattern layer PTL2, a third pattern layer PTL3, and a fourth pattern layer PTL4 that are sequentially stacked along the third direction DR3.

[0188] The first pattern layer PTL1 can be disposed on the insulating film INS. For example, the first pattern layer PTL1 can be disposed between the insulating film INS and the second pattern layer PTL2. The first pattern layer PTL1 can be electrically connected to the drain region DA of the pixel transistor PTR through at least one via and at least one conductive layer. The first pattern layer PTL1 can include a metal. For example, the first pattern layer PTL1 can include aluminum (Al). In one embodiment, among the multiple pattern layers of the first electrode AND, the first pattern layer PTL1 can have a greater thickness TK1 than other pattern layers to be able to improve the reflectivity of the first electrode AND. For example, the first pattern layer PTL1 can have a thickness four times that of the thickness TK2 of the third pattern layer PTL3, or a thickness greater than four times the thickness TK2 of the third pattern layer PTL3. In one embodiment, the first pattern layer PTL1 can have to a thickness TK1. According to one embodiment, the first pattern layer PTL1 can include a central region CEA defined by the third pattern layer PTL3 described later and an edge region EGA surrounding the central region CEA.

[0189] According to one embodiment, from a planar perspective, the distance d1 from the side surface of the third pattern layer PTL3 to the side surface of the first pattern layer PTL1 (or the second pattern layer PTL2) can be 2 μm or more.

[0190] The second pattern layer PTL2 can be disposed on the first pattern layer PTL1. For example, in order to prevent diffusion (e.g., metal diffusion) between aluminum (e.g., the aluminum included in the first pattern layer PTL1) and silver (e.g., the silver included in the third pattern layer PTL3 described later) within the first electrode AND, the second pattern layer PTL2 can be disposed between the first pattern layer PTL1 and the third pattern layer PTL3. The second pattern layer PTL2 can be in contact with the first pattern layer PTL1 and the third pattern layer PTL3 respectively. In one embodiment, the overall area of the second pattern layer PTL2 can overlap with the overall area of the first pattern layer PTL1. According to one embodiment, from a planar perspective, the area of the second pattern layer PTL2 can be the same as the area of the first pattern layer PTL1. The second pattern layer PTL2 can include a transparent conductive material. For example, the second pattern layer PTL2 can include a transparent conductive material (TCO, Transparent Conductive Material) such as indium tin oxide (Indium-Tin-Oxide, ITO) and indium zinc oxide (Indium-Zinc-Oxide, IZO). In one embodiment, the second pattern layer PTL2 can be made of a material containing ITO. The second pattern layer PTL2 can have a smaller thickness than the third pattern layer PTL3 described later. For example, the second pattern layer PTL2 can have the following thickness.

[0191] The third pattern layer PTL3 can be disposed on the second pattern layer PTL2. For example, the third pattern layer PTL3 can be disposed between the second pattern layer PTL2 and the fourth pattern layer PTL4. According to one embodiment, from a planar perspective as in Figure 8 the example shown, the third pattern layer PTL3 can have an area smaller than that of the first pattern layer PTL1. In one embodiment, the third pattern layer PTL3 can overlap with the first pattern layer PTL1. For example, the overall area of the third pattern layer PTL3 can overlap with the overall area of the first pattern layer PTL1. According to one embodiment for this purpose, from a planar perspective as in Figure 8From the perspective of the plane shown, the third pattern layer PTL3 can be surrounded by the edge of the first pattern layer PTL1. In other words, the third pattern layer PTL3 can be surrounded by the edge region EGA of the first pattern layer PTL1. According to an embodiment, the third pattern layer PTL3 can be disposed on the central region CEA of the first pattern layer PTL1. For example, the third pattern layer PTL3 can be disposed between the second pattern layer PTL2 and the fourth pattern layer PTL4 in the central region CEA of the first pattern layer PTL1. The third pattern layer PTL3 may not be disposed on the edge region EGA of the first pattern layer PTL1. The third pattern layer PTL3 may contain metal. At this time, the third pattern layer PTL3 may contain a metal different from the aforementioned first pattern layer PTL1. For example, the third pattern layer PTL3 may contain at least one of silver (Ag) and a silver alloy. In an embodiment, in order to implement the ultra-fine pattern process (e.g., dry etching process) of the first electrode AND, the third pattern layer PTL3 may have a thickness smaller than that of the first pattern layer PTL1 (TK2 < TK1). For example, the third pattern layer PTL3 may have a thickness of 1 / 4 times the thickness TK1 of the first pattern layer PTL1 or a thickness TK2 less than 1 / 4 times the thickness TK1 of the first pattern layer PTL1. In an embodiment, the third pattern layer PTL3 may have to a thickness of TK2.

[0192] The fourth pattern layer PTL4 can be disposed on the third pattern layer PTL3. The fourth pattern layer PTL4 may contain the same substance as the aforementioned second pattern layer PTL2. For example, the fourth pattern layer PTL4 may contain a transparent conductive substance (TCO, Transparent Conductive Material) such as ITO (Indium-Tin-Oxide) or IZO (Indium-Zinc-Oxide). In an embodiment, the fourth pattern layer PTL4 may be composed of a substance containing ITO. The fourth pattern layer PTL4 may have a thickness smaller than that of the third pattern layer PTL3. For example, the fourth pattern layer PTL4 may have a thickness of less than. In an embodiment, the thickness of the fourth pattern layer PTL4 may be the same as the thickness of the aforementioned second pattern layer PTL2. According to an embodiment, among the pattern layers PTL1-PTL4 of the first electrode AND, the second pattern layer PTL2 (and / or the fourth pattern layer PTL4) may have the smallest thickness.

[0193] The pixel definition layer PDL can define the light-emitting regions of the pixels. For example, the pixel definition layer PDL can define a first light-emitting region EA1, a second light-emitting region EA2, and a third light-emitting region EA3. Each light-emitting region EA1 - EA3 can penetrate the pixel definition layer PDL in a third direction DR3. The pixel definition layer PDL can be disposed on the first electrode AND. For example, the pixel definition layer PDL can be disposed on the second pattern layer PTL2 in a manner overlapping with the edge region EGA of the first pattern layer PTL1. In one embodiment, at least a portion of the pixel definition layer PDL can be disposed between adjacent first electrodes AND. Figure 9 The pixel definition layer PDL can include the aforementioned first pixel definition layer PDL1, second pixel definition layer PDL2, and third pixel definition layer PDL3. For Figure 9 the specific description of the pixel definition layer PDL, reference is made to the aforementioned Figure 7 description related to the pixel definition layer PDL.

[0194] The stack layer ES can be disposed on the first electrode AND and the pixel definition layer PDL. For example, the stack layer ES can be disposed on the second pattern layer PTL2, fourth pattern layer PTL4 of the first electrode AND, and the pixel definition layer PDL. At this time, the stack layer ES can be in contact with the second pattern layer PTL2, fourth pattern layer PTL4, and the pixel definition layer PDL respectively. As described above, the stack layer ES can include multiple stacks IL1, IL2, IL3. For Figure 9 the specific description of the stack layer ES, reference is made to the aforementioned Figure 7 description related to the stack layer ES.

[0195] The second electrode CAT can be disposed on the stack layer ES. For Figure 9 the specific description of the second electrode CAT, reference is made to the aforementioned Figure 7 description related to the second electrode CAT.

[0196] The encapsulation layer TFE can be disposed on the second electrode CAT. For Figure 9 the specific description of the second encapsulation layer TFE, reference is made to the aforementioned Figure 7 description related to the encapsulation layer TFE.

[0197] On the encapsulation layer TFE, an optical layer OPL, a cover layer CVL, and a polarizing plate POL as shown in Figure 7 can also be disposed.

[0198] According to one embodiment, the insulating film INS can correspond to Figure 7 the ninth insulating film INS. In such a case, below the Figure 9 insulating film INS, the aforementioned Figure 7The semiconductor backplane SBP and the light-emitting element backplane EBP.

[0199] According to an embodiment, the first electrode AND may include silver having a high reflectivity and aluminum that can be used to fabricate a fine pattern by dry etching. Therefore, the first electrode AND of the display device according to an embodiment can not only be fabricated as a fine pattern but also have a high reflectivity. For example, the first electrode AND containing aluminum can be fabricated by dry etching, so the first electrode AND can form a fine pattern. Moreover, the first electrode AND containing silver can have a high reflectivity, thereby reducing the driving voltage for driving the stack layer ES, and thus reducing power consumption. In other words, the efficiency of the display device 10 can be increased. Also, since the first electrode AND is defined by the first pattern layer PTL1 having a relatively large area, the area of the aperture ratio of the pixel can be maximized. And, since the second pattern layer PTL2 containing ITO is disposed between the first pattern layer PTL1 containing aluminum and the third pattern layer PTL3 containing silver, metal diffusion between aluminum and silver can be prevented.

[0200] According to an embodiment, from the planar angle as Figure 8 shown, the edge of the first light-emitting region EA1 may be disposed between the edge of the first pattern layer PTL1 and the edge of the third pattern layer PTL3. The second light-emitting region EA2 and the third light-emitting region EA3 may also have the same layout relationship as the aforementioned first light-emitting region EA1.

[0201] Figure 10 is a cross-sectional view of the display device according to an embodiment. For example, Figure 10 may be a cross-sectional view taken along the Figure 8 I-I' line.

[0202] Figure 10 The display device of Figure 9 differs from the aforementioned

[0203] As shown in Figure 10 the example, the third pattern layer PTL3 may be surrounded by the second pattern layer PTL2 and the fourth pattern layer PTL4. As an embodiment for this, as Figure 9 shown, the fourth pattern layer PTL4 may also be disposed on the side surface of the third pattern layer PTL3. For example, the fourth pattern layer PTL4 may be disposed along the side surface on the side surface of the third pattern layer PTL3.

[0204] As shown in Figure 10As shown, since the third pattern layer PTL3 is surrounded by the second pattern layer PTL2 and the fourth pattern layer PTL4, the anti-contact effect between the third pattern layer PTL3 and the first pattern layer PTL1 can be further improved, thereby more surely preventing the aforementioned metal diffusion problem.

[0205] According to an embodiment, from a planar perspective, the distance d2 from the fourth pattern layer PTL4 disposed on the side of the third pattern layer PTL3 to the side of the first pattern layer PTL1 (or the second pattern layer PTL2) may be 2 μm.

[0206] Figure 11 is a top view of a display device according to an embodiment, Figure 12 is along Figure 11 a cross-sectional view taken along line II-II'.

[0207] Figure 11 and Figure 12 The display device of Figure 8 and Figure 9 differs from the aforementioned

[0208] As Figure 11 and Figure 12 shown, the pixel definition film PDL may also overlap with the third pattern layer PTL3 and the fourth pattern layer PTL4 of the first electrode AND. For example, the pixel definition film PDL may also overlap with the edges of the third pattern layer PTL3 and the fourth pattern layer PTL4. Thereby, the sizes of the respective light-emitting regions EA1 - EA3 defined by the pixel definition film PDL can be reduced. However, since the step between the first pattern layer PTL1 and the third pattern layer PTL3 is excluded from the light-emitting region, the image quality of this light-emitting region can be improved.

[0209] According to an embodiment, from the planar perspective as Figure 11 shown, the edge of the third pattern layer PTL3 may be disposed between the edge of the first pattern layer PTL1 and the edge of the first light-emitting region EA1. The second light-emitting region EA2 and the third light-emitting region EA3 may also have the same layout relationship as the aforementioned first light-emitting region EA1.

[0210] Figure 13 is a cross-sectional view of a display device according to an embodiment. For example, Figure 13 may be a cross-sectional view taken along line II-II' of Figure 11

[0211] Figure 13 The display device of Figure 12 ​The display devices are different, so the following will focus on such differences for explanation.

[0212] As Figure 13 shown in the example, the third pattern layer PTL3 can be surrounded by the second pattern layer PTL2 and the fourth pattern layer PTL4. As an embodiment for this, as Figure 13 shown, the fourth pattern layer PTL4 can also be disposed on the side surface of the third pattern layer PTL3. For example, the fourth pattern layer PTL4 can be disposed along the side surface on the side surface of the third pattern layer PTL3.

[0213] Figures 14 to 20 is a process cross-sectional view for explaining a manufacturing method of a display device according to an embodiment. For example, Figures 14 to 20 can be a process cross-sectional view for explaining the manufacturing method of the display device shown in the foregoing Figure 9

[0214] First, as Figure 14 shown, the first material layer MAL1, the second material layer MAL2, the third material layer MAL3, and the fourth material layer MAL4 can be sequentially formed on the insulating film INS of the substrate. For example, the first material layer MAL1 can be deposited on the insulating film INS, then the second material layer MAL2 can be deposited on the first material layer MAL1, then the third material layer MAL3 can be deposited on the second material layer MAL2, and then the fourth material layer MAL4 can be deposited on the third material layer MAL3. Among them, the first material layer MAL1 can contain aluminum, the second material layer MAL2 can contain a transparent conductive material, the third material layer MAL3 can contain silver, and the fourth material layer MAL4 can contain a transparent conductive material.

[0215] Next, as Figure 15 shown, a photoresist pattern PR can be disposed on the fourth material layer MAL4. When the structure including the first material layer MAL1, the second material layer MAL2, the third material layer MAL3, and the fourth material layer MAL4 is defined as the first electrode material layer, the photoresist pattern PR can define the portion corresponding to the first electrode AND in the first electrode material layer.

[0216] Subsequently, as Figure 16 shown, a first etching process can be performed, that is, the fourth material layer MAL4 is selectively removed using the photoresist pattern PR as a mask. The first etching process can be performed in a wet etching manner. At this time, the first etching process can be performed in an isotropic etching manner. Thus, not only the portion of the fourth material layer MAL4 that is exposed without being blocked by the photoresist pattern PR, but also the portion of the fourth material layer MAL4 that overlaps with the edge of the photoresist pattern PR will be partially removed. As Figure 16 ​As shown, by selectively etching the fourth material layer MAL4 using the photoresist pattern PR as a mask, the fourth pattern layer PTL4 can be formed.

[0217] Next, as Figure 17 shown, a second etching process can be performed, that is, selectively removing the third material layer MAL3 using the aforementioned photoresist pattern PR as a mask. The second etching process can be carried out in a wet etching manner. At this time, the second etching process can be carried out in an isotropic etching manner. Thus, not only the portion of the third material layer MAL3 that is exposed without being blocked by the photoresist pattern PR, but also the portion of the third material layer MAL3 that overlaps with the edge of the photoresist pattern PR will be partially removed. As Figure 17 shown, by selectively etching the third material layer MAL3 using the photoresist pattern PR as a mask, the third pattern layer PTL3 can be formed.

[0218] Next, as Figure 18 shown, a third etching process can be performed, that is, selectively removing the second material layer MAL2 and the first material layer MAL1 respectively using the aforementioned photoresist pattern PR as a mask. The third etching process can be carried out in a dry etching manner. At this time, the third etching process can be carried out in an anisotropic etching manner. Thus, the portion of the second material layer MAL2 that is exposed without being blocked by the photoresist pattern PR and the portion of the first material layer MAL1 that is exposed without being blocked by the photoresist pattern PR can be selectively removed respectively. In addition, since the thickness of the second material layer MAL2 is quite small, during the aforementioned third etching process (for example, a dry etching process), it may be removed together with the first material layer MAL1. As Figure 18 shown, by selectively etching the second material layer MAL2 and the first material layer MAL1 using the photoresist pattern PR as a mask, the second pattern layer PTL2 and the first pattern layer PTL1 can be formed. As a result, when the third etching process as Figure 18 shown is performed and completed, the first electrode AND including the first pattern layer PTL1, the second pattern layer PTL2, the third pattern layer PTL3, and the fourth pattern layer PTL4 can be formed. For example, the first electrode AND can be disposed between the insulating film INS and the photoresist pattern PR.

[0219] Subsequently, as Figure 19 shown, the photoresist pattern PR on the first electrode AND can be removed. For example, the photoresist pattern PR can be removed using a strip process.

[0220] Next, as Figure 20As shown, the pixel definition film PDL for defining the light-emitting regions EA1 - EA3 can be disposed on the first electrode AND. For example, the pixel definition film PDL can be disposed on the edge of the second pattern layer PTL2 so as to overlap with the edge region EGA of the first pattern layer PTL1.

[0221] Next, as Figure 9 shown, a stack layer ES can be formed on the first electrode AND and the pixel definition film PDL, then a second electrode CAT can be formed on the stack layer ES, and then a packaging layer TFE can be formed on the second electrode CAT.

[0222] And, as Figure 7 shown, an organic film APL, an optical layer OPL, a cover layer CVL, and a polarizing plate POL can be sequentially formed on the packaging layer TFE.

[0223] Figure 21 is a perspective view showing a head-mounted display device according to an embodiment. Figure 22 is showing Figure 21 an exploded perspective view of an example of the head-mounted display device.

[0224] Referring to Figure 21 and Figure 22 , a head-mounted display device 1000 according to an embodiment includes: a first display device 10_1, a second display device 10_2, a display device storage unit 1100, a storage unit cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head-mounted band 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, and a control circuit board 1600.

[0225] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Since each of the display devices in the first display device 10_1 and the second display device 10_2 is substantially the same as the display device 10 described in conjunction with Figure 1 and Figure 2 , the description of the first display device 10_1 and the second display device 10_2 will be omitted.

[0226] The first optical member 1510 can be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical member 1520 can be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 can include at least one convex lens.

[0227] The intermediate frame 1400 can be disposed between the first display device 10_1 and the control circuit board 1600, and also between the second display device 10_2 and the control circuit board 1600. The intermediate frame 1400 serves to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0228] The control circuit board 1600 can be disposed between the intermediate frame 1400 and the display device housing portion 1100. The control circuit board 1600 can be connected to the first display device 10_1 and the second display device 10_2 through connectors. The control circuit board 1600 can convert an image source input from the outside into digital video data DATA, and transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 through the connectors.

[0229] The control circuit board 1600 can transmit the digital video data DATA corresponding to the left-eye image, which is most suitable for the user's left eye, to the first display device 10_1, and transmit the digital video data DATA corresponding to the right-eye image, which is most suitable for the user's right eye, to the second display device 10_2. Alternatively, the control circuit board 1600 can transmit the same digital video data DATA to the first display device 10_1 and the second display device 10_2.

[0230] The display device housing portion 1100 serves to house the first display device 10_1, the second display device 10_2, the intermediate frame 1400, the first optical member 1510, the second optical member 1520, and the control circuit board 1600. The housing cover 1200 is configured to cover the open side of the display device housing portion 1100. The housing cover 1200 can include a first eyepiece 1210 for configuring the user's left eye and a second eyepiece 1220 for configuring the user's right eye. Although in Figure 21 and Figure 22 it is illustrated that the first eyepiece 1210 and the second eyepiece 1220 are separately configured, the embodiments of the present specification are not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 can be combined into one.

[0231] The first eyepiece 1210 can be aligned with the first display device 10_1 and the first optical member 1510, and the second eyepiece 1220 can be aligned with the second display device 10_2 and the second optical member 1520. Therefore, the user can view the image of the first display device 10_1 magnified as a virtual image by the first optical member 1510 through the first eyepiece 1210, and can view the image of the second display device 10_2 magnified as a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0232] The head-mounted band 1300 functions to fix the display device housing unit 1100 to the user's head, so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 can be kept in a state where they are respectively disposed in front of the user's left eye and right eye. When the display device housing unit 1100 is implemented to be lightweight and compact, the head-mounted display device 1000 can have the Figure 23 frame shown.

[0233] In addition, the head-mounted display device 1000 may further include a battery for power supply, an external memory slot for accommodating an external memory, an external connection port for receiving an image source, and a wireless communication module. The external connection port may be a USB (Universal Serial Bus) terminal, a DisplayPort, or an HDMI (High-Definition Multimedia Interface) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a WiFi module, or a Bluetooth module.

[0234] Figure 23 FIG. is a perspective view of a head-mounted display device according to an embodiment.

[0235] Referring to Figure 23 , the head-mounted display device 1000_1 according to an embodiment may be a display device in the form of glasses in which the display device housing unit 1200_1 is implemented to be lightweight and compact. The head-mounted display device 1000_1 according to an embodiment may include a display device 10_3, a left-eye lens 1010, a right-eye lens 1020, a support frame 1030, temple arms 1040, 1050, an optical member 1600, a light path conversion member 1070, and a display device housing unit 1200_1.

[0236] The display device housing unit 1200_1 may include: a display device 10_3, an optical member 1600, and a light path conversion member 1070. The image displayed on the display device 10_3 may be magnified by the optical member 1600 and the light path may be converted by the light path conversion member 1070 and provided to the user's right eye through the right-eye lens 1020. Thus, the user can view, through the right eye, an augmented reality image in which a virtual image displayed on the display device 10_3 and a real image seen through the right-eye lens 1020 are superimposed.

[0237] Although in Figure 23The case where the display device storage unit 1200_1 is disposed at the right end of the support frame 1030 is illustrated, but the embodiments of the present specification are not limited thereto. For example, the display device storage unit 1200_1 may be disposed at the left end of the support frame 1030. In this case, the image of the display device 10_3 may be provided to the left eye of the user. Alternatively, the display device storage units 1200_1 may be disposed at both the left end and the right end of the support frame 1030. In this case, the user may view the image displayed on the display device 10_3 through both the left eye and the right eye.

[0238] Those of ordinary skill in the art to which the present specification pertains should understand that, without changing the technical idea or essential features of the present specification, it can be implemented in other specific forms. Therefore, the embodiments described above are to be understood as illustrative in all respects and not restrictive. Compared with the detailed description, the scope of the present specification is more represented by the scope of the claims. All changes or variations derived from the meaning, scope, and equivalent concepts of the appended claims should be construed as falling within the scope of the present specification.

[0239] In addition, although specific terms are used in the present specification and the drawings to disclose the preferred embodiments of the present specification, this is only for the purpose of easily explaining the technical content of the present specification and facilitating the understanding of the present specification, and is used in the ordinary meaning. It is not intended to limit the scope of the present specification. It is obvious to those of ordinary skill in the art to which the present specification pertains that, in addition to the embodiments disclosed herein, other variations based on the technical idea of the present specification can also be implemented.

Claims

1. A display device, Among them, including: a substrate, a first electrode on the substrate, a light-emitting layer on the first electrode, and a second electrode on the light-emitting layer; The first electrode includes: a first pattern layer containing aluminum, a second pattern layer disposed on the first pattern layer and containing a transparent conductive material, a third pattern layer disposed on the second pattern layer and containing silver, and a fourth pattern layer disposed on the third pattern layer and containing a transparent conductive material.

2. The display device according to claim 1, wherein, the first pattern layer has a larger thickness than the third pattern layer.

3. The display device according to claim 2, wherein, the thickness of the first pattern layer is more than four times the thickness of the third pattern layer.

4. The display device according to claim 1, wherein, The first pattern layer has to of thickness.

5. The display device according to claim 1, wherein, The third pattern layer has to thickness.

6. The display device according to claim 1, wherein, The second pattern layer has the following thickness.

7. The display device according to claim 1, wherein, The fourth pattern layer has a thickness of less than 8. The display device according to claim 1, wherein, viewed from a planar perspective, the first pattern layer has a larger area than the third pattern layer.

9. The display device according to claim 1, wherein, viewed from a planar perspective, the first pattern layer has a larger area than the second pattern layer or the fourth pattern layer.

10. The display device according to claim 1, wherein, the third pattern layer is surrounded by the second pattern layer and the fourth pattern layer.

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