Display device

Abstract

A display device is disclosed. The display device includes: a substrate including a display area and a non-display area; an undercut projection disposed on the substrate and disposed in the non-display area; a light emitting layer including an undercut light emitting layer separated on the undercut protrusion; a first cathode layer disposed on the light emitting layer and including an undercut cathode layer separated on the undercut protrusion; and a first insulating layer disposed to cover the first cathode layer, thereby preventing the light emitting layer from being damaged.

Description

Technical Field

[0001] Exemplary embodiments of the present disclosure relate to a display device, and more particularly, but not limited to, a display device including an insulating film capable of blocking external materials. Background Art

[0002] With the development of the information society, the demand for display devices to display images in various forms has been increasing. Therefore, in recent years, various display devices, such as liquid crystal displays and organic light emitting display devices, have been used.

[0003] A display device may include a pixel electrode, a light emitting layer, and a common electrode. Alternatively, a display device may include an anode electrode, a light emitting layer, and a cathode electrode.

[0004] The descriptions provided in the background art section should not be assumed to be prior art merely because they are mentioned in the background art section or are related to the descriptions in the background art section. The descriptions in the background art section may include information on one or more aspects of the described subject technology, and the descriptions in this section do not limit the present invention. Summary of the Invention

[0005] The inventors have recognized that the light emitting layer may be damaged when the light emitting layer is exposed to moisture / water or oxygen. Therefore, the display panel may also be damaged. Accordingly, exemplary embodiments of the present disclosure aim to provide a display device including an insulating film capable of blocking external materials.

[0006] Exemplary embodiments of the present disclosure may provide a display device including an insulating film capable of preventing damage to the light emitting layer.

[0007] Exemplary embodiments of the present disclosure may provide a display device capable of low power consumption by preventing damage to the light emitting layer.

[0008] A display device according to an exemplary embodiment of the present disclosure may include: a substrate including a display area and a non-display area; an undercut protrusion disposed on the substrate and in the non-display area; a light emitting layer including an undercut light emitting layer separated on the undercut protrusion; a first cathode layer disposed on the light emitting layer and including an undercut cathode layer separated on the undercut protrusion; and a first insulating layer disposed to cover the first cathode layer.

[0009] The first insulating layer may be disposed between a passivation layer of the undercut protrusion and the light emitting layer.

[0010] The first insulating layer may be disposed outside the light emitting layer corresponding to the display area.

[0011] The substrate may include a first region where the passivation layer overlaps with the electrode and a second region where the passivation layer does not overlap with the electrode. The first insulating layer may be disposed to surround the second region.

[0012] Other details of the exemplary embodiments are included in the detailed description and the drawings.

[0013] According to an exemplary embodiment of the present disclosure, a display device including an insulating film capable of blocking external materials may be provided.

[0014] According to an exemplary embodiment of the present disclosure, a display device including an insulating film capable of preventing damage to the light-emitting layer may be provided.

[0015] According to an exemplary embodiment of the present disclosure, a display device capable of low power consumption by preventing damage to the light-emitting layer may be provided.

[0016] The effects according to the present disclosure are not limited to those exemplified above, and more various effects are included in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other aspects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the drawings, in which:

[0018] Figure 1 is a system configuration diagram of a display device according to an exemplary embodiment of the present disclosure.

[0019] Figure 2 shows a display panel according to an exemplary embodiment of the present disclosure.

[0020] Figure 3 shows a display panel according to an exemplary embodiment of the present disclosure.

[0021] Figure 4 and Figure 5 is a cross-sectional view of a display panel according to an exemplary embodiment of the present disclosure.

[0022] Figure 6 and Figure 7 is a cross-sectional view of a display panel having a display area and a non-display area according to an exemplary embodiment of the present disclosure.

[0023] Figure 8 and Figure 9 is a cross-sectional view of a display panel for a display area according to an exemplary embodiment of the present disclosure.

[0024] Figure 10 shows a base voltage pad provided on a display panel according to an exemplary embodiment of the present disclosure.

[0025] Figure 11 A cross-sectional view of a base voltage pad according to an exemplary embodiment of the present disclosure.

[0026] Figure 12 A base voltage pad provided on a display panel according to an exemplary embodiment of the present disclosure is shown.

[0027] Figure 13 and Figure 14 A cross-sectional view of a base voltage pad according to an exemplary embodiment of the present disclosure.

[0028] Throughout the drawings and the detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the relative sizes and descriptions of these elements may be exaggerated. Detailed Embodiments

[0029] Now, embodiments of the present disclosure will be described in detail, examples of which can be shown in the drawings. The progress of the described processing steps and / or operations is an example; however, the order of the steps and / or operations is not limited to that described herein and may be changed as known in the art, except for steps and / or operations that must occur in a specific order. The names of the various elements used in the following description may be chosen only for the convenience of writing the specification and may thus be different from the names used in actual products.

[0030] In the following description of examples or exemplary embodiments of the present invention, reference will be made to the drawings, in which specific examples or exemplary embodiments that can be implemented are shown by way of illustration, and in which the same reference numerals and symbols may be used to represent the same or similar components, even when they are shown in different drawings from each other. Further, in the following description of examples or exemplary embodiments of the present invention, when it is determined that the description may make the subject matter in some exemplary embodiments of the present invention quite unclear, the detailed description of well-known functions and components incorporated herein will be omitted. Terms such as "comprising," "having," "including," "containing," "constituting," "made of," "formed by," "composed of," etc., used herein are generally intended to allow the addition of other components, unless the term is used together with the term "only." As used herein, the singular form is intended to include the plural form, unless the context clearly indicates otherwise.

[0031] The shapes, sizes, dimensions (e.g., length, width, height, thickness, radius, diameter, area, etc.), ratios, angles, quantities, etc. of the elements shown in the drawings used to describe the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally represent the same elements.

[0032] The dimensions, including the size and thickness, of the various components shown in the accompanying drawings are shown for convenience of description, and the present disclosure is not limited to the size and thickness of the components shown, but it should be noted that the relative dimensions, including the relative size, position, and thickness, of the components shown in the respective drawings submitted here are part of the present disclosure.

[0033] When using terms such as "on", "above", "over", "under", "below", "beside", "beneath", "near", "close to", "adjacent to", "on the side of", "proximate to" to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless such terms are used together with the terms "immediately" or "directly".

[0034] Spatially relative terms, such as "under", "below", "beneath", "lower", "above", "upper", etc., may be used herein to facilitate the description of the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that, in addition to the orientation shown in the figures, spatially relative terms may also include different orientations of the element during use or operation. For example, if the element in the figure is inverted, the element described as "under" or "below" other elements or features will be oriented "above" the other elements or features. Thus, the exemplary term "below" may include both the below and above orientations. Similarly, the exemplary terms "above" or "over" may include both the "above" and "below" orientations.

[0035] When an element or layer is disposed "on" another element or layer, yet another layer or yet another element may be directly interposed on the other element or between the two elements or layers.

[0036] Terms such as "first", "second", "A", "B", "(A)", or "(B)" may be used herein to describe the elements of the present invention. Each of these terms is not used to define the nature, order, sequence, or quantity of the element, etc., but is only used to distinguish the corresponding element from other elements.

[0037] In addition, when describing the components of the present disclosure, terms such as first, second, A, B, (a), (b), etc. may be used herein. Each of these terms is not used to define the nature, order, or sequence of the corresponding component, but is only used to distinguish the corresponding component from other components.

[0038] It should be understood that the term "at least one" includes all combinations related to any one item. For example, "at least one of the first element, the second element, and the third element" may include all combinations of two or more elements selected from the first element, the second element, and the third element, as well as each of the first element, the second element, and the third element.

[0039] As used herein, the term "device" may refer to a display device including a display panel and a driver for driving the display panel. Examples of the display device may include a light-emitting element and the like. Additionally, examples of the device may include a laptop computer, a television, a computer monitor, an automotive device, a wearable device, and an automotive equipment device, and complete product or final product sets of electronic devices (or equipment) or sets of devices (or equipment) respectively including a light-emitting element and the like, such as mobile electronic devices such as smartphones or electronic tablets, but the embodiments of the present disclosure are not limited thereto.

[0040] When referring to a first element being "connected or coupled to", "in contact with or overlapping" a second element, etc., it should be interpreted that not only can the first element be "directly connected or coupled to" the second element or be "directly in contact with or overlapping" the second element, but also a third element can be "interposed" between the first element and the second element, or the first element and the second element can be "connected or coupled", "in contact with or overlapping" etc. with each other via a fourth element. Here, the second element may be included in at least one of two or more elements that are "connected or coupled", "in contact with or overlapping" etc. with each other.

[0041] When relative time terms such as "after", "subsequently", "then", "before", etc. are used to describe a process or operation of an element or configuration, or a flow or step in an operation, a process, or a manufacturing method, these terms may be used to describe a non - continuous or non - sequential process or operation, unless the terms "directly" or "immediately" are used together.

[0042] Furthermore, when referring to any dimension, relative size, etc., it should be considered that the numerical value of an element or feature or corresponding information (e.g., level, range, etc.) includes a tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even when no relevant description is specified. Additionally, the term "may" fully encompasses all meanings of the term "can".

[0043] The features of the various exemplary embodiments of the present disclosure may be partially or completely attached to or combined with each other, and may be interlocked and operated in various technical ways, and the exemplary embodiments may be performed independently of or in association with each other.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0045] In aspects of the present disclosure, for ease of description, the source electrode and the drain electrode are distinguished from each other. However, the source electrode and the drain electrode may be used interchangeably. The source electrode may be the drain electrode, and the drain electrode may be the source electrode. In addition, the source electrode in any aspect of the present disclosure may be the drain electrode in another aspect of the present disclosure, and the drain electrode in any aspect of the present disclosure may be the source electrode in another aspect of the present disclosure.

[0046] Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0047] Figure 1 is a system configuration diagram of a display device 100 according to an exemplary embodiment of the present disclosure.

[0048] Referring to Figure 1 , a display device 100 according to an exemplary embodiment of the present disclosure may include a display panel 110 and a display driving circuit as components for displaying an image. The display driving circuit is a circuit for driving the display panel 110 and may include a data driving circuit 120, a gate driving circuit 130, and a display controller 140.

[0049] The display panel 110 may include a substrate 111 and a plurality of sub-pixels SP disposed on the substrate 111. Each of the plurality of sub-pixels SP is the smallest unit constituting the display area, and n sub-pixels SP form one pixel. Each of the plurality of sub-pixels SP may emit light having different wavelengths from each other. The plurality of sub-pixels may include a first sub-pixel, a second sub-pixel, and a third sub-pixel that emit light of different colors from each other. For example, the plurality of sub-pixels SP may include a red sub-pixel SP, a green sub-pixel SP, and a blue sub-pixel SP. According to this exemplary embodiment, at least some of the plurality of pixels may further include a white sub-pixel SP. The plurality of sub-pixels SP may be variously modified in color and configuration as needed. However, the present disclosure is not limited thereto.

[0050] For example, the multiple sub-pixels SP may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, where the red sub-pixel, the green sub-pixel, and the blue sub-pixel may be set in a repeating manner. Alternatively, the multiple sub-pixels SP may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, where the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel may be set in a repeating manner, or the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel may be set in a quadrilateral type. For example, the red sub-pixel, the blue sub-pixel, and the green sub-pixel may be sequentially set along the row direction, or the red sub-pixel, the blue sub-pixel, the green sub-pixel, and the white sub-pixel may be sequentially set along the row direction. However, in the embodiments of the present disclosure, the color type, the arrangement type, and the arrangement order of the sub-pixels are not limited, and can be configured in various forms according to the light-emitting characteristics, the device lifetime, and the device specifications.

[0051] In addition, according to the light-emitting characteristics, the sub-pixels may have different light-emitting areas. For example, the sub-pixels that emit light of a color different from the color of the blue sub-pixel may have a light-emitting area different from that of the blue sub-pixel. For example, the red sub-pixel, the blue sub-pixel, and the green sub-pixel or the red sub-pixel, the blue sub-pixel, the white sub-pixel, and the green sub-pixel may each have a different light-emitting area.

[0052] The substrate 111 of the display panel 110 may include a display area DA capable of displaying an image and a non-display area NDA located outside the display area DA. The non-display area NDA may partially or entirely surround the display area DA. All or part of the non-display area NDA may be an area visible from the front of the display device 100, or may be curved and invisible from the front of the display device 100.

[0053] A plurality of sub-pixels SP for image display may be provided in the display area DA, and the non-display area NDA may include a pad area PA located in a first direction of the display area DA.

[0054] In the display panel 110 according to an exemplary embodiment of the present disclosure, the non-display area NDA may be very small. In this specification, the non-display area NDA may also be referred to as a "bezel".

[0055] For example, the non-display area NDA may include a first non-display area located outside the display area DA in a first direction, a second non-display area located outside the display area DA in a second direction intersecting the first direction, a third non-display area located outside the display area DA in a direction opposite to the first direction, and a fourth non-display area located outside the display area DA in a direction opposite to the second direction. One or two of the first non-display area to the fourth non-display area may include a pad area connected or joined to the data driving circuit 120. Among the first non-display area to the fourth non-display area, the sizes of two or three that do not include the pad area may be very small.

[0056] For another example, the boundary area between the display area DA and the non-display area NDA may be curved such that the non-display area NDA may be located below the display area. In this case, when the user views the display device 100 from the front, little or no non-display area NDA may be visible to the user.

[0057] Various types of signal lines for driving the plurality of sub-pixels SP may be provided on the substrate 111 of the display panel 110.

[0058] The display device 100 according to an exemplary embodiment of the present disclosure may be a liquid crystal display device or the like, or may be a self-emitting display device in which the display panel 110 emits light by itself. When the display device 100 according to an exemplary embodiment of the present disclosure is a self-emitting display device, each of the plurality of sub-pixels SP may include a light-emitting device.

[0059] For example, the display device 100 according to an exemplary embodiment of the present disclosure may be an organic light-emitting display device in which the light-emitting device is implemented as an organic light-emitting diode (OLED). For another example, the display device 100 according to an exemplary embodiment of the present disclosure may be an inorganic light-emitting display device in which the light-emitting device is implemented as an inorganic-based light-emitting diode. For another example, the display device 100 according to an exemplary embodiment of the present disclosure may be a quantum dot display device that uses quantum dots to implement the light-emitting device, and quantum dots are semiconductor crystals that emit light by themselves.

[0060] The structure of each of the plurality of sub-pixels SP may vary according to the type of the display device 100. For example, if the display device 100 is a self-emitting display device having individually light-emitting sub-pixels SP, each sub-pixel SP may include a self-emitting light-emitting device, one or more transistors, and one or more capacitors. The transistor may be a thin film transistor TFT.

[0061] The active layer of the thin film transistor TFT may be formed of a semiconductor material such as an oxide semiconductor, an amorphous semiconductor, or a polycrystalline semiconductor, but is not limited thereto.

[0062] Oxide semiconductor materials can have excellent effects in preventing leakage current and relatively low manufacturing costs. Oxide semiconductors can be made of metal oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or combinations of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti) and their oxides. Specifically, oxide semiconductors can include zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO), but are not limited thereto.

[0063] Polycrystalline semiconductor materials have fast moving speeds of carriers such as electrons and holes, and thus have high mobilities, and have low power consumption and excellent reliability. Polycrystalline semiconductors can be made of polycrystalline silicon (poly-Si), but are not limited thereto.

[0064] Amorphous semiconductor materials can be made of amorphous silicon (a-Si), but are not limited thereto.

[0065] For example, various types of signal lines can include a plurality of data lines DL for supplying data signals (also referred to as data voltages or image signals) and a plurality of gate lines GL for transmitting gate signals (also referred to as scan signals).

[0066] For example, the plurality of data lines DL and the plurality of gate lines GL can cross each other. Each of the plurality of data lines DL can be arranged to extend in a first direction. Each of the plurality of gate lines GL can be arranged to extend in a second direction. Here, the first direction can be the column direction, and the second direction can be the row direction. Alternatively, the first direction can be the row direction, and the second direction can be the column direction. Hereinafter, for ease of explanation, the case where each of the plurality of data lines DL is arranged in the column direction and each of the plurality of gate lines GL is arranged in the row direction will be illustrated.

[0067] The data driving circuit 120 is a circuit for driving the plurality of data lines DL, and can output data signals to the plurality of data lines DL. For example, the data driving circuit 120 outputs data voltages through the plurality of data lines DL.

[0068] The data driving circuit 120 can receive image data in digital form from the display controller 140, and convert the received image data into an analog data signal to output to the plurality of data lines DL.

[0069] For example, the data driving circuit 120 may be connected to the display panel 110 using a tape automated bonding (TAB) method, or may be connected to the bonding pads of the display panel 110 using a chip on glass (COG) or chip on printed circuit board (COP) method, or may be implemented and connected to the display panel 110 using a chip on film (COF) method.

[0070] The data driving circuit 120 may be connected to one side (e.g., the upper side or the lower side) of the display panel 110. Depending on the driving method, panel design method, etc., the data driving circuit 120 may be connected to both sides (e.g., the upper side and the lower side) of the display panel 110, or may be connected to two or more sides of the four sides of the display panel 110.

[0071] The data driving circuit 120 may be connected to the outside of the display area DA of the display panel 110, but alternatively, it may be disposed in the display area DA of the display panel 110.

[0072] The gate driving circuit 130 is a circuit for driving a plurality of gate lines GL, and may output a gate signal to the plurality of gate lines GL. For example, the gate driving circuit 130 outputs a scanning signal to the sub-pixels through the plurality of gate lines GL.

[0073] The gate driving circuit 130 may receive a first gate voltage corresponding to a conductive level voltage, a second gate voltage corresponding to a cut-off level voltage, and various gate driving control signals GCS, and may generate a gate signal and supply the generated gate signal to the plurality of gate lines GL.

[0074] In the display device 100 according to an exemplary embodiment of the present disclosure, the gate driving circuit 130 may be built in the display panel 110 as a gate in panel (GIP) type. If the gate driving circuit 130 is a gate in panel type, the gate driving circuit 130 may be formed on the substrate of the display panel 110 during the manufacturing process of the display panel 110.

[0075] In the display device 100 according to an exemplary embodiment of the present disclosure, the gate driving circuit 130 may be disposed in the display area DA of the display panel 110. For example, the gate driving circuit 130 may be disposed in a first partial area (e.g., the left area or the right area within the display area DA) within the display area DA. Again, for example, the gate driving circuit 130 may be disposed in a first partial area (e.g., the left area or the right area within the display area DA) and a second partial area (e.g., the right area or the left area within the display area DA) within the display area DA.

[0076] In the present disclosure, the gate driving circuit 130 built in the display panel 110 as a gate in panel type may be referred to as a "gate in panel circuit".

[0077] The display controller 140 may be a device for controlling the data driving circuit 120 and the gate driving circuit 130, and may control the driving timings of the plurality of data lines DL and the driving timings of the plurality of gate lines GL.

[0078] The display controller 140 may supply a data driving control signal DCS to the data driving circuit 120 to control the data driving circuit 120, and may supply a gate driving control signal GCS to the gate driving circuit 130 to control the gate driving circuit 130.

[0079] The display controller 140 may receive input image data from the host system 150 and supply image data DATA to the data driving circuit 120 based on the input image data.

[0080] The display controller 140 may be implemented as a component separate from the data driving circuit 120, or may be integrated with the data driving circuit 120 and implemented as an integrated circuit.

[0081] The display controller 140 may be a timing controller used in typical display technologies, or may be a control device capable of further performing other control functions including a timing controller, or may be a control device different from a timing controller, or may be a control device other than a timing controller, or may be a circuit within a control device. In an exemplary embodiment, the gate driving circuit 130 (e.g., embedded in the display panel 110) may receive a plurality of gate control signals from the display controller 140. In addition, the data driving circuit 120 may receive a plurality of data control signals from the display controller 140. The display controller 140 may be implemented with various circuits or electronic components, such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a processor.

[0082] The display controller 140 may be mounted on a printed circuit board, a flexible printed circuit, etc., and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through a printed circuit board, a flexible printed circuit, but is not limited thereto.

[0083] The display controller 240 may transmit and receive data with the data driving circuit 120 according to one or more predetermined interfaces. For example, the interface may include a low voltage differential signaling (LVDS) interface, an embedded clock point-to-point interface (EPI) interface, or a serial peripheral interface (SPI), but is not limited thereto. In addition, the display controller 140 may transmit and receive signals with the gate driving circuit 130, and includes a storage medium such as one or more registers.

[0084] In order to provide not only an image display function but also a touch sensing function, the display device 100 according to an exemplary embodiment of the present disclosure may include a touch sensor and a touch sensing circuit, and the touch sensing circuit is configured to detect the occurrence of a touch of a touch object such as a finger or a pen or to detect a touch position by sensing the touch sensor.

[0085] The touch sensing circuit may include: a touch driving circuit configured to drive and sense the touch sensor to generate and output touch sensing data; and a touch controller configured to use the touch sensing data to detect the occurrence of a touch or to detect a touch position.

[0086] The touch sensor may include a plurality of touch electrodes. The touch sensor may further include a plurality of touch lines to electrically connect the plurality of touch electrodes to the touch driving circuit.

[0087] The touch sensor may exist in the form of a touch panel outside the display panel 110, or may exist inside the display panel 110. If the touch sensor exists in the form of a touch panel outside the display panel 110, the touch sensor may be referred to as an external type. If the touch sensor is of the external type, the touch panel and the display panel 110 may be separately manufactured and combined during the assembly process. The external touch panel may include a touch panel substrate and a plurality of touch electrodes on the touch panel substrate.

[0088] If the touch sensor exists inside the display panel 110, the touch sensor may be formed on the substrate together with signal lines and electrodes related to display driving during the manufacturing process of the display panel 110.

[0089] The touch driving circuit may supply a touch driving signal to at least one of the plurality of touch electrodes and generate touch sensing data by sensing at least one of the plurality of touch electrodes.

[0090] The touch sensing circuit may perform touch sensing using a self-capacitance sensing method or a mutual-capacitance sensing method.

[0091] If the touch sensing circuit performs touch sensing using the self-capacitance sensing method, the touch sensing circuit may perform touch sensing based on the capacitance between each touch electrode and a touch object (e.g., a finger, a pen, etc.). According to the self-capacitance sensing method, each touch electrode among the plurality of touch electrodes may be used as a driving touch electrode and a sensing touch electrode. The touch driving circuit 260 may drive all or part of the plurality of touch electrodes and sense all or part of the plurality of touch electrodes.

[0092] If the touch sensing circuit performs touch sensing using a mutual capacitance sensing method, the touch sensing circuit may perform touch sensing based on the capacitance between touch electrodes. According to the mutual capacitance sensing method, a plurality of touch electrodes may be divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit may drive the driving touch electrodes and sense the sensing touch electrodes.

[0093] The touch driving circuit and the touch controller included in the touch sensing circuit may be implemented as separate devices or as one device. Additionally, the touch driving circuit and the data driving circuit may be implemented as separate devices or as one device.

[0094] The display device 100 may further include a power supply circuit that supplies various types of power to the display driving circuit and / or the touch sensing circuit.

[0095] The display device 100 according to an exemplary embodiment of the present disclosure may be a mobile terminal such as a smartphone or a tablet, or a monitor or a television of various sizes, but is not limited thereto, and may be various types and sizes of displays capable of displaying information or images.

[0096] The display device 100 according to an exemplary embodiment of the present disclosure may further include electronic devices such as a camera (e.g., an image sensor) and a detection sensor. For example, the detection sensor may be a sensor for detecting an object or a human body by receiving light such as infrared rays, ultrasonic waves, or ultraviolet rays.

[0097] Refer to Figure 2 , the display panel 110 may include a substrate 111 disposed in a plurality of sub-pixels SP and an encapsulation layer 200 on the substrate 111. Here, the encapsulation layer 200 may also be referred to as an encapsulation substrate or an encapsulation unit.

[0098] Refer to Figure 2 , when the display device 100 according to an exemplary embodiment of the present disclosure is a self-emitting display device, each sub-pixel among the plurality of sub-pixels SP may include a light-emitting device ED and a sub-pixel circuit SPC for driving the light-emitting device ED.

[0099] Refer to Figure 2 , the sub-pixel circuit SPC may include a plurality of pixel driving transistors and at least one capacitor for driving the light-emitting device ED. In the present disclosure, the sub-pixel circuit SPC may drive the light-emitting device ED by supplying a driving current to the light-emitting device ED at a predetermined timing. The light-emitting device ED may be driven by the driving current and emit light.

[0100] The plurality of pixel driving transistors may include a driving transistor DT for driving the light-emitting device ED and a scanning transistor ST that is turned on or off according to a scanning signal SC.

[0101] The driving transistor DT can supply a driving current to the light-emitting device ED.

[0102] The scanning transistor ST can be configured to control the electrical state of a corresponding node in the sub-pixel circuit SPC or control the state or operation of the driving transistor DT.

[0103] At least one capacitor can include a storage capacitor Cst to maintain a constant voltage during a frame.

[0104] To drive the sub-pixel SP, a data signal VDATA as an image signal and a scan signal SC as a gate signal can be applied to the sub-pixel SP. In addition, a common pixel driving voltage including a first driving voltage VDD and a second driving voltage VSS can be applied to the sub-pixel SP to drive the sub-pixel SP.

[0105] The light-emitting device ED can include an anode AND, a light-emitting device intermediate layer (light-emitting layer) EL, and a cathode CAT. The light-emitting device intermediate layer EL can be a layer provided between the anode AND and the cathode CAT.

[0106] For example, the anode AND can be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). However, the present disclosure is not limited thereto.

[0107] In addition, in the case where the display device according to an exemplary embodiment of the present disclosure is a top-emitting type display device, the anode AND can further include a reflective layer made of a metal material having excellent reflection efficiency, such as a material such as aluminum (Al) or silver (Ag), so that the light emitted from the light-emitting layer EL is reflected by the anode AND and propagates in an upward direction, that is, toward the cathode CAD. Conversely, in the case where the display device is a bottom-emitting type display device, the anode AND can be made of only a transparent conductive material.

[0108] Since the cathode CAD supplies electrons to the light-emitting layer EL, the cathode CAD can be made of a conductive material having a low work function. For example, the cathode CAD can be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or an alloy of ytterbium (Yb). The cathode CAD can also include a metal-doped layer. However, the present disclosure is not limited thereto.

[0109] When the light-emitting device ED is an organic light-emitting device, the intermediate layer EL of the light-emitting device may include a light-emitting layer EML, a first common intermediate layer COM1 located between the anode AND and the light-emitting layer EML, and a second common intermediate layer COM2 located between the light-emitting layer EML and the cathode. The light-emitting layer EML may be provided in each sub-pixel SP. In contrast, the first common intermediate layer COM1 and the second common intermediate layer COM2 may be commonly provided across multiple sub-pixels SP. The light-emitting layer EML may be provided in each light-emitting region, and the first common intermediate layer COM1 and the second common intermediate layer COM2 may be commonly provided across multiple light-emitting regions and non-light-emitting regions. The first common intermediate layer COM1 and the second common intermediate layer COM2 may be collectively referred to as the common intermediate layer EL_COM.

[0110] For example, the first common intermediate layer COM1 may include a hole injection layer HIL and a hole transport layer HTL. The second common intermediate layer COM2 may include an electron transport layer ETL and an electron injection layer EIL. The hole injection layer may inject holes from the anode AND into the hole transport layer, the hole transport layer may transport the holes to the light-emitting layer EML, the electron injection layer may inject electrons from the cathode CAT into the electron transport layer, and the electron transport layer may transport the electrons to the light-emitting layer EML.

[0111] For example, the cathode CAT may be electrically connected to the second common driving voltage line VSSL. As a second common driving voltage VSS of a common pixel driving voltage, the second common driving voltage VSS may be applied to the cathode CAT through the second common driving voltage line VSSL. The anode AND may be electrically connected to the first node N1 of the driving transistor DT of each sub-pixel SP. In the present disclosure, the second common driving voltage VSS may also be referred to as the base voltage VSS, and the second common driving voltage line VSSL may also be referred to as the base voltage line VSSL.

[0112] For example, the anode AND may be a pixel electrode provided in each sub-pixel SP, and the cathode CAT may be a common electrode commonly provided across multiple sub-pixels SP. As another example, the cathode CAT may be a pixel electrode provided in each sub-pixel SP, and the anode AND may be a common electrode commonly provided across multiple sub-pixels SP. Hereinafter, for the sake of convenience of description, it is assumed that the anode AND is a pixel electrode and the cathode CAT is a common electrode.

[0113] Each light-emitting device ED may be composed of an overlapping portion of an anode AND, a light-emitting device intermediate layer EL, and a cathode CAT. Each light-emitting device ED may form a predetermined light-emitting region. For example, the light-emitting region of each light-emitting device ED may include the region where the anode AND, the light-emitting device intermediate layer EL, and the cathode CAT overlap. For example, the light-emitting device ED may be an organic light-emitting diode (OLED), an inorganic light-emitting diode, or a quantum dot light-emitting device. For example, when the light-emitting device ED is an organic light-emitting diode OLED, the light-emitting device intermediate layer EL in the light-emitting device ED may include an organic light-emitting device intermediate layer EL containing an organic material.

[0114] The driving transistor DT may be a driving transistor for supplying a driving current to the light-emitting device ED. The driving transistor DT may be connected between a first common driving voltage line VDDL and the light-emitting device ED.

[0115] The driving transistor DT may include a first node N1 electrically connected to the light-emitting device ED, a second node N2 to which a data signal VDATA is applied, and a third node N3 to which a driving voltage VDD is applied from a driving voltage line DVL.

[0116] In the driving transistor DT, the second node N2 may be a gate node, the first node N1 may be a source node or a drain node, and the third node N3 may be a drain node or a source node. Hereinafter, for ease of explanation, the case where the second node N2 in the driving transistor DT is a gate node, the first node N1 is a source node, and the third node N3 is a drain node will be described.

[0117] Included in Figure 2 The scanning transistor ST in the shown sub-pixel circuit SPC may be a switching transistor for transmitting a data signal VDATA, which is an image signal, to a second node N2, which is the gate node of the driving transistor DT.

[0118] The scanning transistor ST may be controlled to be turned on and off by a scanning signal SC, which is a strobe signal applied through a scanning line SCL as a kind of gate line GL, and may control the electrical connection between the second node N2 of the driving transistor DT and a data line DL. The drain electrode or the source electrode of the scanning transistor ST may be electrically connected to the data line DL, and the source electrode or the drain electrode of the scanning transistor ST may be electrically connected to the second node N2 of the driving transistor DT. The gate electrode of the scanning transistor ST may be electrically connected to the scanning line SCL.

[0119] The storage capacitor Cst can be electrically connected between a first node N1 and a second node N2 of the driving transistor DT. The storage capacitor Cst can include a first capacitor electrode electrically connected to the first node N1 of the driving transistor DT or corresponding to the first node N1 of the driving transistor DT, and a second capacitor electrode electrically connected to the second node N2 of the driving transistor DT or corresponding to the second node N2 of the driving transistor DT.

[0120] The storage capacitor Cst can be an external capacitor intentionally designed outside the driving transistor DT, rather than a parasitic capacitor (e.g., Cgs, Cgd) that can exist as an internal capacitor between the first node N1 and the second node N2 of the driving transistor DT.

[0121] Each of the driving transistor DT and the scanning transistor ST can be an n-type transistor or a p-type transistor.

[0122] The display panel 110 can have a top-emitting structure or a bottom-emitting structure.

[0123] If the display panel 110 has a top-emitting structure, at least a part of the sub-pixel circuit SPC can overlap at least a part of the light-emitting device ED in the vertical direction. Alternatively, if the display panel 110 has a bottom-emitting structure, the sub-pixel circuit SPC can not overlap the light-emitting device ED in the vertical direction.

[0124] As Figure 2 shown, the sub-pixel circuit SPC can have a 2T-1C structure including two transistors T1 and T2 and one capacitor Cst. In some cases, the sub-pixel circuit SPC can further include one or more transistors or one or more capacitors.

[0125] For example, the sub-pixel circuit SPC can have an 8T-1C structure including eight transistors and a single capacitor. Again, for example, the sub-pixel circuit SPC can have a 6T-2C structure including six transistors and two capacitors. Again, for example, the sub-pixel circuit SPC can have a 7T-1C structure including seven transistors and one capacitor.

[0126] According to the structure of the sub-pixel circuit SPC, the type and number of the gate signals and / or gate lines supplied to the sub-pixel SP can be changed.

[0127] In addition, according to the structure of the sub-pixel circuit SPC, the type and number of the common pixel driving voltages supplied to the sub-pixel SP can be changed.

[0128] Since the circuit elements within each sub-pixel SP (in particular, the light-emitting device ED implemented with an organic light-emitting diode (OLED) including an organic material) are vulnerable to external moisture or oxygen, a encapsulation layer 200 may be provided on the display panel 110 to prevent oxygen from penetrating into the circuit elements (in particular, the light-emitting device ED). The encapsulation layer 200 may be configured in various shapes to prevent the light-emitting device ED from coming into contact with moisture or oxygen.

[0129] Figure 3 A display panel 110 according to an exemplary embodiment of the present disclosure is shown.

[0130] The display panel 110 may include a display area DA and a non-display area NDA. The non-display area NDA is an area where an image is not displayed. The non-display area NDA may be an area adjacent to the display area DA. Further, the non-display area NDA may be an area adjacent to and configured to surround the display area DA. However, the present disclosure is not limited thereto.

[0131] The display panel 110 may include two gate driving circuits GIP. The first gate driving circuit GIP1 and the second gate driving circuit GIP2 may be respectively provided on the left and right sides of the display panel 110. However, the present disclosure is not limited thereto. For example, the first gate driving circuit GIP1 and the second gate driving circuit GIP2 may be respectively provided on the upper and lower sides of the display panel 110. Alternatively, the first gate driving circuit GIP1 and the second gate driving circuit GIP2 may be respectively provided on any two sides of the display panel 110. Alternatively, the first gate driving circuit GIP1 and the second gate driving circuit GIP2 together may be provided on any one side of the display panel 110.

[0132] The display panel 110 may be combined with a plurality of source films SF1, SF2, SF3, SF4, and SF5. The plurality of source films may include a first source film SF1, a second source film SF2, a third source film SF3, a fourth source film SF4, and a fifth source film SF5. The first source film SF1, the second source film SF2, the third source film SF3, the fourth source film SF4, and the fifth source film SF5 may respectively include driving integrated circuits DIC1, DIC2, DIC3, DIC4, and DIC5. However, the present disclosure is not limited thereto. For example, each of the first source film SF1, the second source film SF2, the third source film SF3, the fourth source film SF4, and the fifth source film SF5 may include at least one of the driving integrated circuits DIC1, DIC2, DIC3, DIC4, and DIC5.

[0133] Multiple voltage supply lines (not shown) may be provided in each of the multiple source films SF1, SF2, SF3, SF4, and SF5. The multiple voltage supply lines may supply voltages required for driving, such as data voltages, driving voltages, and base voltages.

[0134] Two adjacent source films may share a base voltage pad SPAD. The base voltage pad SPAD may be a pad to which a base voltage is supplied. Refer to Figure 3 , the first source film SF1 may share a base voltage pad SPAD with the second source film SF2.

[0135] Refer to Figure 3 , a region indicated by I-I’, a region indicated by II-II’, and a third region A3 are shown.

[0136] Refer to Figure 3 , the region indicated by I-I’ may be a cross-sectional region related to the display region DA and the non-display region NDA.

[0137] Refer to Figure 3 , the region indicated by II-II’ may be a cross-sectional region related to the display region DA.

[0138] Refer to Figure 3 , the third region A3 may be a region where the base voltage pad SPAD is provided.

[0139] Hereinafter, the region indicated by I-I’, the region indicated by II-II’, and the third region A3 will be described in detail.

[0140] Figure 4 and Figure 5 are cross-sectional views of the display panel 110 according to an exemplary embodiment of the present disclosure.

[0141] Figure 4 A cross-sectional view of the region indicated by I-I’ shown in Figure 3 is shown.

[0142] The substrate SUB can be disposed at the bottom of the display panel 110. The substrate SUB can include transparent plastic or glass. In some example embodiments, the substrate SUB can be made of a flexible plastic material or a flexible polymer film. For example, the flexible polymer film can be made of any one of polyimide (PI), polyethylene terephthalate (PET), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polycarbonate (PC), polyethersulfone (PES), polyarylate (PAR), polysulfone (PSF), cycloolefin copolymer (COC), triacetyl cellulose (TAC), polyvinyl alcohol (PVA), and polystyrene (PS), and the present disclosure is not limited thereto. Refer to Figure 4 , the substrate SUB is shown as being disposed at the bottom, but the substrate SUB can be disposed under a polarizer, a cover glass, etc., and the present disclosure is not limited thereto.

[0143] The gate driving circuit GIP can be disposed on the substrate SUB corresponding to the non-display area NDA. The gate driving circuit GIP can be an in-panel gate type formed on the display panel 110.

[0144] The gate electrode GAT can be disposed on the substrate SUB. The gate electrode GAT can be disposed to be spaced apart from the gate driving circuit GIP.

[0145] A passivation layer PAS can be disposed to cover the gate driving circuit GIP and the gate electrode GAT.

[0146] The outer coating OC can be disposed on the passivation layer PAS. The outer coating OC can be etched during the process of forming the undercut protrusion UC and can be divided into three parts. The outer coating OC can include a first part corresponding to the display area DA, a second part corresponding to the non-display area NDA, and a third part corresponding to the undercut protrusion.

[0147] The bank layer BNK can be disposed on the outer coating OC. The bank layer BNK can be disposed at the boundaries between the plurality of sub-pixels SP and suppress color mixing of light beams from the plurality of sub-pixels SP. The bank layer BNK can include an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or an organic insulating material such as a benzocyclobutene (BCB)-based resin, an acrylic resin, or a polyimide. For example, the bank layer BNK can be formed of a black resin. However, the present disclosure is not limited thereto. The bank layer BNK can be etched during the process of forming the undercut protrusion UC and can be divided into three parts. The bank layer BNK can include a first part corresponding to the display area DA, a second part corresponding to the non-display area NDA, and a third part corresponding to the undercut protrusion.

[0148] Refer to Figure 4, To form the undercut protrusion UC, a part of each of the passivation layer PAS, the outer coating OC, and the bank layer BNK can be etched and removed.

[0149] The undercut protrusion UC can be provided outside the display panel 110. Assuming the display panel 110 has four sides, the undercut protrusion UC can be provided on three sides of the display panel 110, or can be provided on the outer sides corresponding to the four sides of the display panel 110.

[0150] The undercut protrusion UC can include a gate electrode GAT, a passivation layer PAS, and an outer coating OC. The undercut protrusion UC can be spatula-shaped or mushroom-shaped. However, the present disclosure is not limited thereto.

[0151] After forming the undercut protrusion UC, a light-emitting layer EL can be provided to cover the bank layer BNK and the outer coating OC. The light-emitting layer EL can include a first part corresponding to the display area DA, a second part corresponding to the non-display area NDA, and a third part corresponding to the undercut protrusion.

[0152] In this case, due to the undercut protrusion UC, the light-emitting layer EL can be provided in a partially separated state. The light-emitting layer EL can be provided in contact with the outer coating OC of the undercut protrusion UC, but the light-emitting layer EL can be provided not in contact with the gate electrode GAT of the undercut protrusion UC.

[0153] Refer to Figure 4 , The light-emitting layer EL provided on the undercut protrusion UC can be defined as an undercut light-emitting layer EL. The light-emitting layer EL can be provided on the right side of the undercut protrusion UC and can be defined as a display area light-emitting layer EL. The light-emitting layer EL can be provided on the left side of the undercut protrusion UC and can be referred to as a non-display area light-emitting layer EL. For example, the light-emitting layer EL can be divided into a display area light-emitting layer EL and a non-display area light-emitting layer EL, and the present disclosure is not limited thereto.

[0154] A cathode layer (cathode) CAT can be provided on the light-emitting layer EL. Due to the undercut protrusion UC, the cathode layer CAT can be provided in a partially separated state. The cathode layer CAT can include a first part corresponding to the display area DA, a second part corresponding to the non-display area NDA, and a third part corresponding to the undercut protrusion. The cathode layer CAT can include a non-display area cathode layer provided on the non-display area light-emitting layer EL, an undercut cathode layer CAT_u provided on the undercut light-emitting layer EL, and a display area cathode layer provided on the display area light-emitting layer EL.

[0155] The cover layer CPL can be disposed on the cathode layer CAT. Due to the undercut protrusion UC, the cover layer CPL can be disposed in a partially separated state. The cover layer CPL can include a first portion corresponding to the display area DA, a second portion corresponding to the non-display area NDA, and a third portion corresponding to the undercut protrusion.

[0156] The encapsulation layer EPAS can be disposed on the cover layer CPL. Due to the undercut protrusion UC, the encapsulation layer EPAS can be disposed in a partially separated state. The encapsulation layer EPAS can include a first portion corresponding to the display area DA, a second portion corresponding to the non-display area NDA, and a third portion corresponding to the undercut protrusion.

[0157] The encapsulation layer EPAS has a structure in which an inorganic encapsulation layer and an organic encapsulation layer are alternately stacked, so that the encapsulation layer EPAS can protect the light-emitting element while suppressing the infiltration of moisture or oxygen into the light-emitting element. For example, the encapsulation layer EPAS can have a multi-insulating film structure in which an organic film and an inorganic film are alternately stacked. The inorganic film can block the penetration of moisture or oxygen. The organic film can flatten the surface of the inorganic film. When the organic film and the inorganic film are stacked in multiple layers, the movement path of moisture or oxygen can be longer than that of a single layer, thereby effectively blocking the penetration of moisture and oxygen that affect the light-emitting layer EL. For example, the encapsulation layer EPAS includes a first inorganic encapsulation layer, a first organic encapsulation layer, and a second inorganic encapsulation layer stacked in sequence. For example, the encapsulation layer EPAS includes a first inorganic encapsulation layer, a first organic encapsulation layer, a second inorganic encapsulation layer, a second organic encapsulation layer, and a third inorganic encapsulation layer stacked in sequence. However, the present disclosure is not limited thereto.

[0158] The first inorganic encapsulation layer, the second inorganic encapsulation layer, and the third inorganic encapsulation layer can be used to block the penetration of moisture or oxygen. The first inorganic encapsulation layer, the second inorganic encapsulation layer, and the third inorganic encapsulation layer can be made of an inorganic material, such as an inorganic material such as silicon nitride (SiNx), silicon oxide (SiOx), or aluminum oxide (AlOx). However, the present disclosure is not limited thereto.

[0159] The first organic encapsulation layer is disposed between the first inorganic encapsulation layer and the second inorganic encapsulation layer, and the second organic encapsulation layer is disposed between the second inorganic encapsulation layer and the third inorganic encapsulation layer. The first organic encapsulation layer and the second organic encapsulation layer may each have a greater thickness than each of the first inorganic encapsulation layer, the second inorganic encapsulation layer, and the third inorganic encapsulation layer to adsorb or block particles that may be generated during the manufacturing process of the display device. The first organic encapsulation layer and the second organic encapsulation layer may fill cracks that may form in the first inorganic encapsulation layer and the second inorganic encapsulation layer. The first organic encapsulation layer and the second organic encapsulation layer may flatten the upper portions of the first inorganic encapsulation layer and the second inorganic encapsulation layer by covering particles on the first inorganic encapsulation layer and the second inorganic encapsulation layer, respectively. For example, the first organic encapsulation layer may flatten the upper portion of the first inorganic encapsulation layer by covering particles on the first inorganic encapsulation layer. For example, the second organic encapsulation layer may flatten the upper portion of the second inorganic encapsulation layer by covering particles on the second inorganic encapsulation layer. The first organic encapsulation layer and the second organic encapsulation layer may be made of an organic material, and for example, an epoxy polymer, an acrylic polymer, etc. may be used. However, the present disclosure is not limited thereto.

[0160] In addition, the encapsulation layer EPAS is not limited to three layers or five layers. For example, it may include n layers (where n is an integer greater than 3) in which inorganic encapsulation layers and organic encapsulation layers are alternately stacked.

[0161] The adhesive layer FSP may be disposed on the encapsulation layer EPAS. Since the adhesive layer FSP is deposited on the entire surface, the encapsulation layer EPAS may be disposed in both the display area DA and the non-display area NDA.

[0162] The metal encapsulation layer FSM may be disposed on the adhesive layer FSP. The metal encapsulation layer FSM may be disposed on top of the display panel 110.

[0163] In addition, referring to Figure 4 and Figure 5 , a fourth region A4 is shown, which is an enlarged region around the undercut protrusion UC. Referring to Figure 5 , the display area light-emitting layer EL disposed in the display area DA may be exposed to oxygen or moisture / water through a fifth region A5. If the light-emitting layer EL is exposed to oxygen or moisture / water, defects may occur in the light-emitting layer EL.

[0164] If the cathode layer CAT is disposed on the light-emitting layer EL, the cathode layer CAT may be formed by a physical vapor deposition (PVD) process. The PVD process may be performed by an evaporation method and a sputtering method. If the sputtering method is applied, the cathode layer CAT may be disposed to cover the entire light-emitting layer EL. However, if the evaporation method is applied, the cathode layer CAT may be disposed while exposing the lower end of the light-emitting layer EL.

[0165] The light-emitting layer EL and the cathode layer CAT can be formed by a vapor deposition method. If the vapor deposition method is used, there may be a problem of insufficient step coverage. If the step coverage is insufficient, the deposition thickness on the side portion may be thin. The thickness of the cathode layer CAT may be thinner than the thickness of the light-emitting layer EL. In this case, the step coverage of the cathode layer CAT covering the light-emitting layer EL can be further reduced, and accordingly, the cathode layer CAT can be provided while exposing the lower end of the light-emitting layer EL.

[0166] This can correspond to the arrangement of the cathode layer CAT and the light-emitting layer EL shown in the fifth region A5. Oxygen or moisture / water may flow into the light-emitting layer EL through this region. If the light-emitting layer EL is exposed to oxygen or moisture / water, defects may occur in the light-emitting layer EL.

[0167] Accordingly, an exemplary embodiment of the present disclosure can provide a display device 100 including an insulating film capable of blocking external substances.

[0168] An exemplary embodiment of the present disclosure can provide a display device 100 including an insulating film capable of preventing damage to the light-emitting layer EL.

[0169] An exemplary embodiment of the present disclosure can provide a display device 100 capable of having low power consumption by preventing damage to the light-emitting layer EL. This will be described in detail below.

[0170] Figure 6 and Figure 7 are cross-sectional views of a display panel 110 for a display area DA and a non-display area NDA according to an exemplary embodiment of the present disclosure.

[0171] Refer to Figure 6 and Figure 7 , a cross-sectional view of the region I-I' shown in Figure 3 is shown.

[0172] In Figure 6 and Figure 7 the configuration of the display panel 110 shown, the description of the configuration identical to that of the display panel 110 shown in Figure 5 can be omitted.

[0173] Refer to Figure 6, the substrate SUB may be disposed at the bottom of the display panel 110. The substrate SUB may include transparent plastic or glass. In some example embodiments, the substrate SUB may be made of a flexible plastic material or a flexible polymer film. For example, the flexible polymer film may be made of any one of polyimide (PI), polyethylene terephthalate (PET), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polycarbonate (PC), polyethersulfone (PES), polyarylate (PAR), polysulfone (PSF), cycloolefin copolymer (COC), triacetyl cellulose (TAC), polyvinyl alcohol (PVA), and polystyrene (PS), and the present disclosure is not limited thereto.

[0174] The gate driving circuit GIP may be disposed on the substrate SUB. The gate driving circuit GIP may be an in-panel gate type formed on the display panel 110.

[0175] The gate electrode GAT may be disposed on the substrate SUB and spaced apart from the gate driving circuit GIP.

[0176] The passivation layer PAS may be disposed on the outer coating OC and the gate electrode GAT.

[0177] The outer coating OC may be disposed on the passivation layer PAS. The outer coating OC may be etched during the process of forming the undercut protrusion UC and may be divided into three parts. The outer coating OC may include a first part corresponding to the display area DA, a second part corresponding to the non-display area NDA, and a third part corresponding to the undercut protrusion.

[0178] The bank layer BNK may be disposed on the outer coating OC. The bank layer BNK may be disposed at the boundaries between the plurality of sub-pixels SP and suppress color mixing of the light beams from the plurality of sub-pixels SP. The bank layer BNK may include an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or an organic insulating material such as benzocyclobutene (BCB)-based resin, acrylic resin, or polyimide. For example, the bank layer BNK may be formed of a black resin. However, the present disclosure is not limited thereto. The bank layer BNK may be disposed on the outer coating OC. The bank layer BNK may be etched during the process of forming the undercut protrusion UC and may be divided into three parts. The bank layer BNK may include a first part corresponding to the display area DA, a second part corresponding to the non-display area NDA, and a third part corresponding to the undercut protrusion.

[0179] The undercut protrusion UC may be disposed on the substrate SUB. The undercut protrusion UC may include the gate electrode GAT disposed on the substrate SUB and the passivation layer PAS disposed on the gate electrode GAT.

[0180] The light-emitting layer EL can be disposed on the bank layer BNK and the undercut protrusion UC. The light-emitting layer EL can include a first portion corresponding to the display area DA, a second portion corresponding to the non-display area NDA, and a third portion corresponding to the undercut protrusion. The light-emitting layer EL can include a display area light-emitting layer EL, an undercut light-emitting layer EL, and a non-display area light-emitting layer EL. The thickness of the light-emitting layer EL can be, for example, about 4500 angstroms, however, the present disclosure is not limited thereto.

[0181] The first cathode layer CAT1 can be disposed on the light-emitting layer EL. The first cathode layer CAT1 can include a first portion corresponding to the display area DA, a second portion corresponding to the non-display area NDA, and a third portion corresponding to the undercut protrusion. The first cathode layer CAT1 can include a non-display area cathode layer, an undercut cathode layer CAT1_u, and a display area cathode layer. The thickness of the first cathode layer CAT1 can be, for example, about 1500 angstroms, however, the present disclosure is not limited thereto.

[0182] Reference Figure 6 , the first cover layer CPL1 can be disposed on the first cathode layer CAT1. The first cover layer CPL1 can be disposed to cover the first cathode layer CAT1 and the undercut protrusion UC. The thickness of the first cover layer CPL1 can be, for example, about 5000 angstroms or greater than 5000 angstroms, however, the present disclosure is not limited thereto. Since the first cover layer CPL1 is disposed to be relatively thicker than the light-emitting layer EL and the first cathode layer CAT1, the first cover layer CPL1 can prevent air or moisture from infiltrating into the light-emitting layer EL. If the thicknesses of the light-emitting layer EL and the first cathode layer CAT1 are designed to be different, the thickness of the first cover layer CPL1 can also be designed to change.

[0183] The second cathode layer CAT2 can be disposed on the first cover layer CPL1. The second cathode layer CAT2 can be disposed to contact the first cathode layer CAT1 in the non-display area NDA. The thickness of the second cathode layer CAT2 can be, for example, about 1500 angstroms, however, the present disclosure is not limited thereto. Since the second cathode layer CAT2 is disposed to cover the first cover layer CPL1, the second cathode layer CAT2 can prevent air or moisture from infiltrating into the light-emitting layer EL. In addition, the thickness of the second cathode layer CAT2 can be the same as or different from the thickness of the first cathode layer CAT1.

[0184] The second cover layer CPL2 can be disposed on the second cathode layer CAT2. The second cover layer CPL2 can be disposed to cover the second cathode layer CAT2. The thickness of the second cover layer CPL2 can be, for example, about 300 angstroms, however, the present disclosure is not limited thereto. Since the second cover layer CPL2 is disposed to cover the second cathode layer CAT2, the second cover layer CPL2 can prevent air or moisture from infiltrating into the light-emitting layer EL.

[0185] The encapsulation layer EPAS can be disposed on the second cover layer CPL2. The encapsulation layer EPAS has a structure in which inorganic encapsulation layers and organic encapsulation layers are alternately stacked, so that the encapsulation layer EPAS can protect the light-emitting element and at the same time inhibit the infiltration of moisture or oxygen into the light-emitting element. For example, the encapsulation layer EPAS can have a multi-insulating film structure in which organic films and inorganic films are alternately stacked. The inorganic film can block the penetration of moisture or oxygen. The organic film can flatten the surface of the inorganic film. When the organic film and the inorganic film are stacked in multiple layers, the movement path of moisture or oxygen can be longer than that of a single layer, thereby effectively blocking the penetration of moisture and oxygen that affect the light-emitting layer EL. For example, the encapsulation layer EPAS includes a first inorganic encapsulation layer, a first organic encapsulation layer, and a second inorganic encapsulation layer stacked in sequence. For example, the encapsulation layer EPAS includes a first inorganic encapsulation layer, a first organic encapsulation layer, a second inorganic encapsulation layer, a second organic encapsulation layer, and a third inorganic encapsulation layer stacked in sequence. However, the present disclosure is not limited thereto.

[0186] The first inorganic encapsulation layer, the second inorganic encapsulation layer, and the third inorganic encapsulation layer can be used to block the penetration of moisture or oxygen. The first inorganic encapsulation layer, the second inorganic encapsulation layer, and the third inorganic encapsulation layer can be made of inorganic materials, such as inorganic materials such as silicon nitride (SiNx), silicon oxide (SiOx), or aluminum oxide (AlOx). However, the present disclosure is not limited thereto.

[0187] The first organic encapsulation layer is disposed between the first inorganic encapsulation layer and the second inorganic encapsulation layer, and the second organic encapsulation layer is disposed between the second inorganic encapsulation layer and the third inorganic encapsulation layer. The first organic encapsulation layer and the second organic encapsulation layer can each have a greater thickness than each of the first inorganic encapsulation layer, the second inorganic encapsulation layer, and the third inorganic encapsulation layer, so as to adsorb or block particles that may be generated during the manufacturing process of the display device. The first organic encapsulation layer and the second organic encapsulation layer can fill cracks that may form in the first inorganic encapsulation layer and the second inorganic encapsulation layer. The first organic encapsulation layer and the second organic encapsulation layer can flatten the upper portions of the first inorganic encapsulation layer and the second inorganic encapsulation layer by covering the particles on the first inorganic encapsulation layer and the second inorganic encapsulation layer, respectively. For example, the first organic encapsulation layer can flatten the upper portion of the first inorganic encapsulation layer by covering the particles on the first inorganic encapsulation layer. For example, the second organic encapsulation layer can flatten the upper portion of the second inorganic encapsulation layer by covering the particles on the second inorganic encapsulation layer. The first organic encapsulation layer and the second organic encapsulation layer can be made of organic materials, and for example, epoxy polymers, acrylic polymers, etc. can be used. However, the present disclosure is not limited thereto.

[0188] In addition, the encapsulation layer EPAS is not limited to three layers or five layers. For example, it can include n layers (where n is an integer greater than 3) in which inorganic encapsulation layers and organic encapsulation layers are alternately stacked.

[0189] The adhesive layer FSP can be disposed on the encapsulation layer EPAS, and the metal encapsulation layer FSM can be disposed on the adhesive layer FSP. The thickness of the encapsulation layer EPAS can be, for example, about 7000 angstroms, however, the present disclosure is not limited thereto. Since the encapsulation layer EPAS is disposed to cover the second cover layer CPL2, the encapsulation layer EPAS can prevent air or moisture from penetrating into the light-emitting layer EL.

[0190] Referring Figure 6 , the first cover layer CPL1 can be disposed between the passivation layer PAS and the light-emitting layer EL. Since the first cover layer CPL1 is disposed between the passivation layer PAS and the light-emitting layer EL, external substances can be prevented from penetrating into the light-emitting layer EL in the display area.

[0191] Referring Figure 6 , the first cover layer CPL1 can be disposed outside the light-emitting layer EL corresponding to the display area DA. Since the first cover layer CPL1 is disposed outside the light-emitting layer EL corresponding to the display area DA, external substances can be prevented from penetrating into the light-emitting layer EL in the display area.

[0192] Referring Figure 6 , the substrate SUB can include a first region A1 where the passivation layer PAS overlaps with the electrode and a second region A2 where the passivation layer PAS does not overlap with the electrode. That is, there can be an empty space between the substrate SUB and the passivation layer PAS. However, this space can be filled with the first cover layer CPLD.

[0193] Referring Figure 6 , the first cover layer CPL1 can be disposed to surround the second region A2. Since the first cover layer CPL1 is disposed to surround the second region A2, external substances can be prevented from penetrating into the light-emitting layer EL in the display area.

[0194] Since the first cover layer CPL1 is disposed to cover the undercut protrusion UC and the cathode layer in the display area, external substances can be prevented from penetrating into the light-emitting layer EL in the display area. In addition, since the second cathode layer CAT2 and the second cover layer CPL2 are provided, the penetration of external substances can be further prevented.

[0195] Referring Figure 7 , the structure of another display panel 110 capable of preventing external substances from penetrating into the light-emitting layer EL in the display area is shown.

[0196] Referring Figure 7, the substrate SUB can be disposed at the bottom of the display panel 110. The substrate SUB can include transparent plastic or glass. In some example embodiments, the substrate SUB can be made of a flexible plastic material or a flexible polymer film. For example, the flexible polymer film can be made of any one of polyimide (PI), polyethylene terephthalate (PET), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polycarbonate (PC), polyethersulfone (PES), polyarylate (PAR), polysulfone (PSF), cycloolefin copolymer (COC), triacetyl cellulose (TAC), polyvinyl alcohol (PVA), and polystyrene (PS), and the present disclosure is not limited thereto.

[0197] The gate driving circuit GIP can be disposed on the substrate SUB. The gate driving circuit GIP can be an in-panel gate type formed on the display panel 110.

[0198] The gate electrode GAT can be disposed on the substrate SUB and can be spaced apart from the gate driving circuit GIP.

[0199] The passivation layer PAS can be disposed on the outer coating OC and the gate electrode GAT.

[0200] The outer coating OC can be disposed on the passivation layer PAS.

[0201] The bank layer BNK can be disposed on the outer coating OC. The bank layer BNK can be disposed at the boundaries between the plurality of sub-pixels SP and suppress color mixing of the light beams from the plurality of sub-pixels SP. The bank layer BNK can include an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or an organic insulating material such as benzocyclobutene (BCB)-based resin, acrylic resin, or polyimide. For example, the bank layer BNK can be formed of a black resin. However, the present disclosure is not limited thereto.

[0202] The undercut protrusion UC can be disposed on the substrate SUB. The undercut protrusion UC can include the gate electrode GAT disposed on the substrate SUB and the passivation layer PAS disposed on the gate electrode GAT.

[0203] The light-emitting layer EL can be disposed on the bank layer BNK and the undercut protrusion UC. The light-emitting layer EL can include a first portion corresponding to the display area DA, a second portion corresponding to the non-display area NDA, and a third portion corresponding to the undercut protrusion. The light-emitting layer EL can include a display area light-emitting layer EL, an undercut light-emitting layer EL, and a non-display area light-emitting layer EL.

[0204] The first cathode layer CAT1 can be disposed on the light-emitting layer EL. The cathode layer CAT can include a first portion corresponding to the display area DA, a second portion corresponding to the non-display area NDA, and a third portion corresponding to the undercut protrusion. The first cathode layer CAT1 can include a non-display area cathode layer, an undercut cathode layer CAT1_u, and a display area cathode layer.

[0205] Reference Figure 7 , a first insulating layer IN1 can be disposed to cover the first cathode layer CAT1 and the undercut protrusion UC. The first insulating layer IN1 can be a layer capable of blocking oxygen and moisture. The first insulating layer IN1 can include an inorganic insulating material. For example, the first insulating layer IN1 can be configured as a single layer or multiple layers made of silicon nitride (SiNx) or silicon oxide (SiOx). For example, the first insulating layer IN1 can be formed by a single layer or multiple layers of inorganic films. For example, the single layer of inorganic film can be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multiple layers of inorganic films can be formed by alternately laminating one or more layers of silicon oxide (SiOx) films, one or more layers of silicon nitride (SiNx) films, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0206] A cover layer CPL can be disposed on the first insulating layer IN1. The cover layer CPL can be disposed to contact the first cathode layer CAT1 in the non-display area NDA.

[0207] A second insulating layer IN2 can be disposed on the cover layer CPL. The second insulating layer IN2 can be disposed to cover the cover layer CPL. The second insulating layer IN2 can include an inorganic insulating material. For example, the second insulating layer IN2 can be configured as a single layer or multiple layers made of silicon nitride (SiNx) or silicon oxide (SiOx). For example, the second insulating layer IN2 can be formed by a single layer or multiple layers of inorganic films. For example, the single layer of inorganic film can be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multiple layers of inorganic films can be formed by alternately laminating one or more layers of silicon oxide (SiOx) films, one or more layers of silicon nitride (SiNx) films, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0208] In addition, the inorganic insulating materials included in the first insulating layer IN1 and the second insulating layer IN2 may be as follows. For example, the first insulating layer IN1 and the second insulating layer IN2 may include Al2O3, Al:HfO2, Al:ZnO, AlGaN, Box, BiFeO3, CeO2, Co3O4, CoFe2O4, Er2O3, Fe2O3, Fe3O4, FePO4, Ga2O3, HfO2, HfSiON, In2O3, ITO, La2O3, Li2O, Li3PO4, LiPON, LiFePO4, Li2MNo4, Li5TaO z , any one of MgO, MnO2, MoO3, NaTiO, Nb2O5, NiFe2O4, NiO, Po4, SiO2, SnO2, SrO, SrTiO3, Ta2O5, TiO2, V2O5, WO3, Y2O3, YSZ, ZNal2O4, ZnO, ZnMgO, ZNoS, and ZrO2.

[0209] The encapsulation layer EPAS may be disposed on the second insulating layer IN2. The encapsulation layer EPAS has a structure in which an inorganic encapsulation layer and an organic encapsulation layer are alternately stacked, so that the encapsulation layer EPAS can protect the light-emitting element while suppressing the infiltration of moisture or oxygen into the light-emitting element. For example, the encapsulation layer EPAS may have a multi-insulating film structure in which an organic film and an inorganic film are alternately stacked. The inorganic film can block the penetration of moisture or oxygen. The organic film can planarize the surface of the inorganic film. When the organic film and the inorganic film are stacked in multiple layers, the movement path of moisture or oxygen can be longer than that of a single layer, thereby effectively blocking the penetration of moisture and oxygen that affect the light-emitting layer EL. For example, the encapsulation layer EPAS includes a first inorganic encapsulation layer, a first organic encapsulation layer, and a second inorganic encapsulation layer stacked in sequence. For example, the encapsulation layer EPAS includes a first inorganic encapsulation layer, a first organic encapsulation layer, a second inorganic encapsulation layer, a second organic encapsulation layer, and a third inorganic encapsulation layer stacked in sequence. However, the present disclosure is not limited thereto.

[0210] The first inorganic encapsulation layer, the second inorganic encapsulation layer, and the third inorganic encapsulation layer can be used to block the penetration of moisture or oxygen. The first inorganic encapsulation layer, the second inorganic encapsulation layer, and the third inorganic encapsulation layer may be made of an inorganic material, such as an inorganic material such as silicon nitride (SiNx), silicon oxide (SiOx), or aluminum oxide (AlOx). However, the present disclosure is not limited thereto.

[0211] The first organic encapsulation layer is disposed between the first inorganic encapsulation layer and the second inorganic encapsulation layer, and the second organic encapsulation layer is disposed between the second inorganic encapsulation layer and the third inorganic encapsulation layer. The first organic encapsulation layer and the second organic encapsulation layer may each have a greater thickness than each of the first inorganic encapsulation layer, the second inorganic encapsulation layer, and the third inorganic encapsulation layer, so as to adsorb or block particles that may be generated during the manufacturing process of the display device. The first organic encapsulation layer and the second organic encapsulation layer may fill cracks that may form in the first inorganic encapsulation layer and the second inorganic encapsulation layer. The first organic encapsulation layer and the second organic encapsulation layer may flatten the upper portions of the first inorganic encapsulation layer and the second inorganic encapsulation layer by covering particles on the first inorganic encapsulation layer and the second inorganic encapsulation layer, respectively. For example, the first organic encapsulation layer may flatten the upper portion of the first inorganic encapsulation layer by covering particles on the first inorganic encapsulation layer. For example, the second organic encapsulation layer may flatten the upper portion of the second inorganic encapsulation layer by covering particles on the second inorganic encapsulation layer. The first organic encapsulation layer and the second organic encapsulation layer may be made of an organic material, and for example, epoxy polymers, acrylic polymers, etc. may be used. However, the present disclosure is not limited thereto.

[0212] In addition, the encapsulation layer EPAS is not limited to three layers or five layers. For example, it may include n layers (where n is an integer greater than 3) in which inorganic encapsulation layers and organic encapsulation layers are alternately stacked.

[0213] The adhesive layer FSP may be disposed on the encapsulation layer EPAS, and the metal encapsulation layer FSM may be disposed on the adhesive layer FSP.

[0214] Since the first insulating layer IN1 is disposed to cover the undercut protrusion UC and the cathode of the display region, external substances can be prevented from infiltrating into the light-emitting layer EL of the display region. In addition, since the cover layer CPL and the second insulating layer IN2 are provided, the infiltration of external substances can be further prevented.

[0215] Referring to Figure 7 , the first insulating layer IN1 may be disposed between the passivation layer PAS and the light-emitting layer EL. Since the first insulating layer IN1 is disposed between the passivation layer PAS and the light-emitting layer EL, external substances can be prevented from infiltrating into the light-emitting layer EL of the display region.

[0216] Referring to Figure 7 , the first insulating layer IN1 may be disposed outside the light-emitting layer EL corresponding to the display region DA. Since the first insulating layer IN1 is disposed outside the light-emitting layer EL corresponding to the display region DA, external substances can be prevented from infiltrating into the light-emitting layer EL of the display region.

[0217] Referring to Figure 7, the substrate SUB may include a first region A1 where the passivation layer PAS overlaps with the electrode and a second region A2 where the passivation layer PAS does not overlap with the electrode. That is, there may be an empty space between the substrate SUB and the passivation layer PAS. However, this space may be filled with the first insulating layer IN1.

[0218] Referring to Figure 7 , the first insulating layer IN1 may be arranged to surround the second region A2. Since the first insulating layer IN1 is arranged to surround the second region A2, external substances can be prevented from infiltrating into the light-emitting layer EL in the display area.

[0219] Referring to Figure 6 and Figure 7 , the display device 100 may include a passivation layer PAS provided on the substrate SUB, an outer coating OC provided on the passivation layer PAS in the display area DA, a bank layer BNK provided on the outer coating OC, a display area light-emitting layer EL provided on the bank layer BNK and in the display area DA, and a cathode layer (display area cathode layer) CAT provided on the display area light-emitting layer EL.

[0220] Figure 8 and Figure 9 are cross-sectional views of a display panel for the display area DA according to an exemplary embodiment of the present disclosure.

[0221] Referring to Figure 8 and Figure 9 , shows Figure 3 a cross-sectional view of the region I-I' shown in

[0222] Referring to Figure 8 and Figure 9 , the substrate SUB may be provided at the bottom of the display panel 110.

[0223] A buffer layer BUF may be provided on the substrate SUB. The buffer layer BUF may be made of an insulating material. For example, the buffer layer BUF may be configured as a single layer or multiple layers made of at least one of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON). For example, the buffer layer BUF may be formed by a single layer or multiple layers of inorganic films. For example, the single-layer inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multiple-layer inorganic film may be formed by alternately laminating one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto. However, depending on the structure or characteristics of the display device, the buffer layer BUF may not be included.

[0224] The light blocking layer LS may be disposed on a part of the buffer layer BUF. The light blocking layer LS may block external light and prevent the characteristics of components disposed inside the display panel 110 from being changed due to the external light. Additionally, the light blocking layer LS may include a metal material and may transmit an electrical signal.

[0225] The first interlayer dielectric layer ILD1 may be disposed to cover the light blocking layer LS. The first interlayer dielectric layer ILD1 may be configured as a single layer or multiple layers made of silicon nitride (SiNx) or silicon oxide (SiOx). For example, the first interlayer dielectric layer ILD1 may be formed of a single layer or multiple layers of an inorganic film. For example, the single layer of the inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multiple layers of the inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto. Contact holes may be formed in a part of the first interlayer dielectric layer ILD1.

[0226] The active layer ACT may be disposed on the first interlayer dielectric layer ILD1.

[0227] The second interlayer dielectric layer ILD2 may be disposed to cover the active layer ACT and the first interlayer dielectric layer ILD1. The second interlayer dielectric layer ILD2 may be configured as a single layer or multiple layers made of silicon nitride (SiNx) or silicon oxide (SiOx). For example, the second interlayer dielectric layer ILD2 may be formed of a single layer or multiple layers of an inorganic film. For example, the single layer of the inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multiple layers of the inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0228] The electrodes SDE and GE for driving the transistor may be disposed on the second interlayer dielectric layer ILD2. To this end, contact holes may be formed in a part of the second interlayer dielectric layer ILD2. The electrodes SDE and GE for driving the transistor may include a gate electrode GAT and two source-drain electrodes SDE. One source-drain electrode SDE may be electrically connected to the light blocking layer LS.

[0229] The capacitor electrode pattern CP may be disposed on the first interlayer dielectric layer ILD1.

[0230] A passivation layer PAS may be disposed to cover the electrodes SDE and GE for driving the transistor and the second interlayer dielectric layer ILD2.

[0231] The color filter CF may be disposed on the passivation layer PAS.

[0232] An outer coating OC may be provided to cover the color filter CF and the passivation layer PAS.

[0233] The pixel electrode PXL may be provided on the outer coating OC. The pixel electrode PXL may be electrically connected to the source-drain electrode SDE through a contact hole formed in the outer coating OC.

[0234] The bank layer BNK may be provided on the pixel electrode PXL and the outer coating OC.

[0235] The light-emitting layer EL may be provided on the bank layer BNK. The light-emitting layer EL may be electrically connected to the pixel electrode PXL through a contact hole formed in the bank layer BNK.

[0236] Reference Figure 8 ,a first cover layer CPL1 may be provided on the first cathode layer CAT1.

[0237] Reference Figure 8 ,a second cathode layer CAT2 may be provided on the first cover layer CPL1. The second cathode layer CAT2 may be provided to be spaced apart from the first cathode layer CAT1 in the display area DA.

[0238] Reference Figure 8 ,a second cover layer CPL2 may be provided on the second cathode layer CAT2.

[0239] Reference Figure 8 ,an encapsulation layer EPAS may be provided on the second cover layer CPL2.

[0240] Reference Figure 9 ,a first insulating layer IN1 may be provided on the first cathode layer CAT1.

[0241] Reference Figure 9 ,a cover layer CPL may be provided on the first insulating layer IN1.

[0242] Reference Figure 9 ,a second insulating layer IN2 may be provided on the cover layer CPL.

[0243] Figure 10 Shows the base voltage pad SPAD provided on the display panel 110 according to an exemplary embodiment of the present disclosure.

[0244] Figure 11 Is a cross-sectional view of the base voltage pad SPAD according to an exemplary embodiment of the present disclosure.

[0245] Reference Figure 10 ,shows Figure 3 the third region A3 shown in

[0246] Reference Figure 10, the display panel 110 can be electrically connected to the first source film SF1 and the second source film SF2.

[0247] Reference Figure 10 , the first source film SF1 and the second source film SF2 can be connected to the base voltage pad SPAD.

[0248] Reference Figure 10 , the base voltage pad SPAD can be electrically connected to the cathode layer CAT. The base voltage pad SPAD can be in physical contact with the cathode layer CAT.

[0249] Reference Figure 10 , for ease of explanation, the cathode layer CAT is shown in the area where the base voltage pad SPAD is provided. Reference Figure 11 , the cross-sectional structures of the cathode layer CAT and the base voltage pad SPAD will be described in detail.

[0250] Reference Figure 11 , a partial cross-sectional area of the base voltage pad SPAD is shown. Reference Figure 11 , the cathode layer CAT can be provided to contact the pixel electrode PXL. Figure 10 The base voltage pad SPAD shown in can include the pixel electrode PXL, the gate electrode GATE, and the light blocking layer LS.

[0251] Refer to Figure 11 , the substrate SUB can be provided at the bottom of the display panel 110.

[0252] The light blocking layer LS can be provided on the substrate SUB.

[0253] The first interlayer dielectric layer ILD1 can be provided on the light blocking layer LS.

[0254] The second interlayer dielectric layer ILD2 can be provided on the first interlayer dielectric layer ILD1.

[0255] The gate layer (gate electrode) GAT can be provided on the second interlayer dielectric layer ILD2. The gate layer GAT can be electrically connected to the light blocking layer LS through a contact hole formed in the first interlayer dielectric layer ILD1 and the second interlayer dielectric layer ILD2.

[0256] The pixel electrode PXL can be provided on the gate layer GAT.

[0257] The cathode layer CAT can be provided on the pixel electrode PXL.

[0258] The cover layer CPL can be provided on the cathode layer CAT.

[0259] The encapsulation layer EPAS can be provided on the cover layer CPL.

[0260] Since Figure 11The display panel 110 shown is the same as Figure 4 and Figure 5 the display panel 110 shown, so that penetration of external substances into the light-emitting layer EL can be prevented.

[0261] Figure 12 A base voltage pad SPAD provided on the display panel 110 according to an exemplary embodiment of the present disclosure is shown.

[0262] Figure 13 and Figure 14 are cross-sectional views of the base voltage pad SPAD according to an exemplary embodiment of the present disclosure.

[0263] Referring to Figure 12 , for ease of explanation, a second cathode layer CAT2 is shown provided in the region where the base voltage pad SPAD is provided. Figure 13 and Figure 14 show the cross-sectional structure of the second cathode layer CAT2 and the base voltage pad SPAD.

[0264] Referring to Figure 12 , the base voltage pad SPAD can be electrically connected to the first cathode layer CAT1 (not shown as it is covered by the second cathode layer CAT2). A part of the first cathode layer CAT1 can be arranged to overlap a part of the upper surface of the base voltage pad SPAD. At the position where the first cathode layer CAT1 and the base voltage pad SPAD overlap, the base voltage pad SPAD can be in physical contact with the first cathode layer CAT1.

[0265] The second cathode layer CAT2 can be provided on the first cathode layer CAT1. Since the second cathode layer CAT2 is provided to cover the first cathode layer CAT1, the upper end of the second cathode layer CAT2 can be arranged to be higher than the upper end of the first cathode layer CAT1. Referring to Figure 12 , the second cathode layer CAT2 and the base voltage pad SPAD are shown, and a part of the second cathode layer CAT2 can be arranged to overlap the base voltage pad SPAD. At the position where the second cathode layer CAT2 and the base voltage pad SPAD overlap, the base voltage pad SPAD can be in physical contact with the second cathode layer CAT2.

[0266] Referring to Figure 12 , a first cross-sectional area IV-IV' and a second cross-sectional area V-V' shown in the second cathode layer CAT2 are shown.

[0267] Figure 13 A cross-sectional view of the first cross-sectional area IV-IV' is shown, and Figure 14 a cross-sectional view of the second cross-sectional area V-V' is shown.

[0268] In Figure 12In the region IV-IV' shown, the first cover layer CPL1 can be disposed between the second cathode layer CAT2 and the first cathode layer CAT1. Figure 12 The region V-V' shown can be a region where the first cover layer CPL1 is not disposed.

[0269] Referring to Figure 13 and Figure 14 , the first cathode layer CAT1 can be disposed to contact the pixel electrode PXL. Figure 12 The base voltage pad SPAD shown in may include the pixel electrode PXL, the gate electrode GATE, and the light blocking layer LS. That is, the base voltage pad SPAD may include a plurality of electrodes.

[0270] Referring to Figure 13 , the first cathode layer CAT1 can be disposed on the pixel electrode PXL. The first cover layer CPL1 can be disposed on the first cathode layer CAT1. The second cathode layer CAT2 can be disposed on the first cover layer CPL1. The encapsulation layer EPAS can be disposed on the second cathode layer CAT2. That is, the first cover layer CPL1 can be disposed in Figure 12 the region IV-IV' shown, and the second cathode layer CAT2 can be disposed to be spaced apart from the first cathode layer CAT1.

[0271] Referring to Figure 14 , the first cathode layer CAT1 can be disposed on the pixel electrode PXL. The second cathode layer CAT2 can be disposed on the first cathode layer CAT1. The encapsulation layer EPAS can be disposed on the second cathode layer CAT2. That is, the first cover layer CPL1 can not be disposed in Figure 12 the region V-V' shown, and the second cathode layer CAT2 can be disposed to contact the first cathode layer CAT1. A base voltage can be supplied to the first cathode layer CAT1. The base voltage supplied to the first cathode layer CAT1 can also be supplied to the second cathode layer CAT2. Therefore, the phenomenon of current concentration on the base voltage pad SPAD can be alleviated.

[0272] Referring to Figure 13 and Figure 14, the first cover layer CPL1 can be disposed between the first cathode layer CAT1 and the second cathode layer CAT2 in the first cross-sectional region IV-IV', however, it may not be disposed between the first cathode layer CAT1 and the second cathode layer CAT2 in the second cross-sectional region V-V'. For example, in order to make the first cathode layer CAT1 and the second cathode layer CAT2 contact each other in the second cross-sectional region V-V', the first cover layer CPL1 can be disposed only in the first cross-sectional region IV-IV'. For example, in order to make the first cathode layer CAT1 and the second cathode layer CAT2 contact each other in the second cross-sectional region V-V' but not contact each other in the first cross-sectional region IV-IV', the first cover layer CPL1 can be disposed only in the first cross-sectional region IV-IV' but not in the second cross-sectional region V-V'.

[0273] Reference Figure 12 , based on the first cross-sectional region IV-IV', the relationship between the lengths of the first cathode layer CAT1, the first cover layer CPL1, and the second cathode layer CAT2 can be as follows. The second cathode layer CAT2 can be set to be the longest upward relative to the first cross-sectional region IV-IV', and the first cover layer CPL1 can be set to be the shortest upward relative to the first cross-sectional region IV-IV'. Therefore, the first cover layer CPL1 is shown in Figure 13 but not shown in Figure 14 .

[0274] However, different from the above description, the first cover layer CPL1 can be set shorter, and in this case, the first cover layer CPL1 may not be disposed in the first cross-sectional region IV-IV'. The first cathode layer CAT1 and the second cathode layer CAT2 can be set to contact each other in the first cross-sectional region IV-IV'. However, the present disclosure is not limited thereto.

[0275] A simple description of the above exemplary embodiments of the present disclosure is given below.

[0276] A display device according to an exemplary embodiment of the present disclosure may include: a substrate including a display area and a non-display area; an undercut protrusion disposed on the substrate and in the non-display area; a light-emitting layer including an undercut light-emitting layer separated on the undercut protrusion; a first cathode layer disposed on the light-emitting layer and including an undercut cathode layer separated on the undercut protrusion; and a first insulating layer disposed to cover the first cathode layer.

[0277] A display device according to an exemplary embodiment of the present disclosure may further include a second cathode layer disposed on the first cover layer as the first insulating layer, a second cover layer disposed on the second cathode layer, and a packaging layer disposed on the second cover layer.

[0278] The second cathode layer may be disposed in contact with the first cathode layer in a non-display area.

[0279] The second cathode layer may be disposed in contact with the first cathode layer in a non-display area, and the second cathode layer may be disposed to be spaced apart from the first cathode layer by a first cover layer in a display area.

[0280] The second cathode layer may be disposed spaced apart from the first cathode layer in a display area.

[0281] The second cathode layer may be disposed to be spaced apart from the first cathode layer by a first cover layer in a display area.

[0282] The substrate may further include a base voltage pad to which a base voltage is supplied. The base voltage pad may include a first region and a second region. In the first region, the second cathode layer is disposed to be spaced apart from the first cathode layer, and in the second region, the second cathode layer is disposed in contact with the first cathode layer.

[0283] A part of the first cathode layer may be disposed to overlap with a part of the upper surface of the base voltage pad.

[0284] At a position where the first cathode layer and the base voltage pad overlap, the base voltage pad may be in contact with the first cathode layer.

[0285] A part of the second cathode layer may be disposed to overlap with the base voltage pad.

[0286] At a position where the second cathode layer and the base voltage pad overlap, the base voltage pad may be in contact with the second cathode layer.

[0287] The second cathode layer may be disposed to cover the first cathode layer and include a portion that does not overlap with the first cathode layer.

[0288] The first region may be a region where the first cover layer is disposed between the second cathode layer and the first cathode layer, and the second region may be a region where the first cover layer is not disposed.

[0289] The base voltage supplied to the first cathode layer may also be supplied to the second cathode layer.

[0290] The display device according to an exemplary embodiment of the present disclosure may further include a cover layer disposed on the first insulating layer and a second insulating layer disposed on the cover layer.

[0291] The first insulating layer and the second insulating layer may be inorganic layers.

[0292] The undercut protrusion may include an electrode disposed on the substrate and a passivation layer disposed on the electrode.

[0293] The first insulating layer may be disposed between the passivation layer and the light-emitting layer.

[0294] The first insulating layer may be disposed outside the light-emitting layer corresponding to the display area.

[0295] The substrate may include a first region where the passivation layer overlaps with the electrode and a second region where the passivation layer does not overlap with the electrode.

[0296] The first insulating layer may be disposed to surround the second region.

[0297] The display device according to an exemplary embodiment of the present disclosure may further include a passivation layer disposed on the substrate in the display area, an outer coating disposed on the passivation layer, a bank layer disposed on the outer coating, a display area light-emitting layer in the display area disposed on the bank layer, and a display area cathode layer disposed between the first insulating layer and the display area light-emitting layer.

[0298] The above description and the drawings provide examples of the technical concept of the present disclosure for illustrative purposes only. Various modifications, additions, and substitutions to the described exemplary embodiments will be apparent to those skilled in the art without departing from the spirit and scope of the present disclosure. Additionally, the disclosed exemplary embodiments are intended to illustrate the scope of the technical concept of the present disclosure. Therefore, the scope of the present disclosure is not limited to the illustrated exemplary embodiments.

[0299] Cross-reference to related applications

[0300] This application claims the priority benefit of Korean Patent Application No. 10-2024-0007364, filed on January 17, 2024, the entire contents of which are hereby expressly incorporated herein for all purposes.

Claims

1. A display device, the display device comprising: A substrate, the substrate comprising a display area and a non-display area; An undercut protrusion, the undercut protrusion being provided on the substrate and being provided in the non-display area; A light-emitting layer, the light-emitting layer comprising an undercut light-emitting layer separated on the undercut protrusion; A first cathode layer, the first cathode layer being provided on the light-emitting layer and comprising an undercut cathode layer separated on the undercut protrusion; And A first insulating layer, the first insulating layer being provided to cover the first cathode layer.

2. The display device according to claim 1, the display device further comprising: A second cathode layer, the second cathode layer being provided on a first cover layer that is the first insulating layer; A second cover layer, the second cover layer being provided on the second cathode layer; And A encapsulation layer, the encapsulation layer being provided on the second cover layer.

3. The display device according to claim 2, wherein, The second cathode layer is provided to be in contact with the first cathode layer in the non-display area.

4. The display device according to claim 2, wherein The second cathode layer is provided to be spaced apart from the first cathode layer in the display area.

5. The display device according to claim 4, wherein, The second cathode layer is provided to be spaced apart from the first cathode layer by the first cover layer in the display area.

6. The display device according to claim 2, wherein, The substrate further comprises a base voltage pad, a base voltage being supplied to the base voltage pad, wherein, the base voltage pad comprises a first area and a second area, in the first area the second cathode layer is provided to be spaced apart from the first cathode layer, and in the second area the second cathode layer is provided to be in contact with the first cathode layer.

7. The display device according to claim 6, wherein, A part of the first cathode layer is provided to overlap with a part of the upper surface of the base voltage pad.

8. The display device according to claim 7, wherein, At a position where the first cathode layer and the base voltage pad overlap, the base voltage pad is in contact with the first cathode layer.

9. The display device according to claim 6, wherein, A part of the second cathode layer is provided to overlap with the base voltage pad.

10. The display device according to claim 9, wherein, At a position where the second cathode layer and the base voltage pad overlap, the base voltage pad is in contact with the second cathode layer.

11. The display device according to claim 6, wherein, The second cathode layer is provided to cover the first cathode layer and comprises a part that does not overlap with the first cathode layer.

12. The display device according to claim 6, wherein, The first area is an area where the first cover layer is provided between the second cathode layer and the first cathode layer, and the second area is an area where the first cover layer is not provided.

13. The display device according to claim 6, wherein, The base voltage supplied to the first cathode layer is also supplied to the second cathode layer.

14. The display device according to claim 1, the display device further comprising: A cover layer, the cover layer being provided on the first insulating layer; And A second insulating layer, the second insulating layer being provided on the cover layer.

15. The display device according to claim 1, wherein, The undercut protrusion comprises an electrode provided on the substrate and a passivation layer provided on the electrode.

16. The display device according to claim 15, wherein, The first insulating layer is provided between the passivation layer and the light-emitting layer.

17. The display device according to claim 1, wherein, The first insulating layer is provided outside the light-emitting layer corresponding to the display area.

18. The display device according to claim 15, wherein, The substrate comprises: A first area where the passivation layer overlaps with the electrode; and A second area where the passivation layer does not overlap with the electrode.

19. The display device according to claim 18, wherein, The first insulating layer is provided to surround the second area.

20. The display device according to claim 1, further comprising: a passivation layer disposed on the substrate in the display area; an outer coating disposed on the passivation layer; a bank layer disposed on the outer coating; a display area light-emitting layer disposed on the bank layer and in the display area; and a display area cathode layer disposed between the first insulating layer and the display area light-emitting layer.

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