Display device and display panel

Abstract

The invention relates to a display device and a display panel. A display device according to an embodiment of the present disclosure may include a first lower metal directly connected to a first pixel electrode or a first source electrode in a first sub-pixel and overlapping a first active layer; a second lower metal directly connected to a second pixel electrode or a second source electrode in the second sub-pixel and overlapping the second active layer; and an overlapping pattern in which one side of the overlapping pattern overlaps at least a portion of the first lower metal and the other side of the overlapping pattern overlaps at least a portion of the second lower metal.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2024 - 0007763, filed on January 18, 2024, which is hereby incorporated by reference in its entirety for all purposes as if fully set forth herein. Technical field

[0003] Embodiments of the present disclosure relate to a display device and a display panel. Background art

[0004] When manufacturing a display panel, due to various reasons such as foreign substances appearing at various positions within a sub - pixel, defects such as bright spots or dark spots may occur in the sub - pixel. For example, drive transistors within each sub - pixel are formed through many processes, and minute process - related foreign substances may appear in the drive transistors. If a foreign substance appears in the drive transistor, a short - circuit or disconnection phenomenon may occur due to the foreign substance. Due to this phenomenon, the corresponding sub - pixel may become a defective sub - pixel that emits light abnormally. As a result, the yield of the display panel may be reduced. Summary of the invention

[0005] Embodiments of the present disclosure may provide a display device and a display panel having a repair structure capable of repairing defective sub - pixels.

[0006] Embodiments of the present disclosure may provide a display device and a display panel having a repair structure with high repair performance or a high probability of repair success.

[0007] Embodiments of the present disclosure may provide a display device and a display panel having a repair structure that does not cause a reduction in the aperture ratio.

[0008] Embodiments of the present disclosure may provide a display device and a display panel having a repair structure that occupies a small space.

[0009] Embodiments of the present disclosure may provide a display device and a display panel having a repair structure suitable for high - resolution embodiments.

[0010] A display device according to an embodiment of the present disclosure may include: a first driving transistor including a first active layer, a first drain electrode, and a first gate electrode; a first pixel electrode directly connected to a part of the first active layer or electrically connected to a part of the first active layer through an additional first source electrode; a second driving transistor including a second active layer, a second drain electrode, and a second gate electrode; a second pixel electrode directly connected to a part of the second active layer or electrically connected to a part of the second active layer through an additional second source electrode; a first lower metal directly connected to the first pixel electrode or directly connected to the first source electrode and overlapping with the first active layer; a second lower metal directly connected to the second pixel electrode or directly connected to the second source electrode and overlapping with the second active layer; a first buffer layer disposed on the first lower metal and the second lower metal; an overlapping pattern disposed on the first buffer layer and including a first part overlapping at least a part of the first lower metal, a second part overlapping at least a part of the second lower metal, and a third part between the first part and the second part; and a second buffer layer disposed on the overlapping pattern and under the first active layer and the second active layer.

[0011] A display panel according to an embodiment of the present disclosure may include: a first sub-pixel including a first sub-pixel circuit and a first light-emitting device; a second sub-pixel including a second sub-pixel circuit and a second light-emitting device; a first lower metal connected to the first sub-pixel circuit; a second lower metal connected to the second sub-pixel circuit; an overlapping pattern including a first part overlapping a part of the first lower metal, a second part overlapping a part of the second lower metal, and a third part between the first part and the second part; and a first buffer layer disposed between the first lower metal, the second lower metal, and the overlapping pattern.

[0012] According to an embodiment of the present disclosure, a display device and a display panel having a repair structure capable of repairing defective sub-pixels may be provided.

[0013] According to an embodiment of the present disclosure, a display device and a display panel having a repair structure that does not cause a reduction in aperture ratio may be provided.

[0014] According to an embodiment of the present disclosure, a display device and a display panel having a repair structure that occupies a small space may be provided.

[0015] According to an embodiment of the present disclosure, a display device and a display panel having a repair structure suitable for a high-resolution implementation can be provided.

[0016] According to an embodiment of the present disclosure, a display device and a display panel having a repair structure with high repair performance or a high probability of repair success can be provided, thereby optimizing the process by reducing production energy consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a system configuration diagram of a display device according to an embodiment of the present disclosure.

[0018] Figure 2 is an equivalent circuit of a sub-pixel in a display panel according to an embodiment of the present disclosure.

[0019] Figure 3 is a schematic plan view of a sub-pixel of a display device according to an embodiment of the present disclosure.

[0020] Figure 4 is an equivalent circuit of a first sub-pixel and a second sub-pixel adjacent to each other in a column direction in a display device according to an embodiment of the present disclosure.

[0021] Figure 5 and Figure 6 show a symmetric structure of a first sub-pixel and a second sub-pixel adjacent to each other in a column direction in a display device according to an embodiment of the present disclosure.

[0022] Figure 7 shows a case where a defect occurs in a second sub-pixel among a first sub-pixel and a second sub-pixel adjacent to each other in a column direction in a display device according to an embodiment of the present disclosure.

[0023] Figure 8 and Figure 9 show a repair structure of a display device according to an embodiment of the present disclosure.

[0024] Figure 10 and Figure 11 show a soldering repair process when a defect occurs in a second sub-pixel circuit in a second sub-pixel among a first sub-pixel and a second sub-pixel adjacent to each other in a column direction in a display device according to an embodiment of the present disclosure.

[0025] Figure 12 shows an equivalent circuit showing a cutting point for disabling a second sub-pixel circuit in a second sub-pixel when a defect occurs in the second sub-pixel circuit in a second sub-pixel among a first sub-pixel and a second sub-pixel adjacent to each other in a column direction in a display device according to an embodiment of the present disclosure.

[0026] Figure 13 Shows the first to eighth sub-pixels in a display panel according to an embodiment of the present disclosure.

[0027] Figure 14 Is Figure 13 A plan view of the circuit cluster area.

[0028] Figure 15 Is a plan view of a display panel according to an embodiment of the present disclosure.

[0029] Figure 16 Is Figure 15 An enlarged plan view of a part of

[0030] Figure 17 Is along Figure 16 A cross-sectional view taken along line A-A' of

[0031] Figure 18 Is a cross-sectional view of a first sub-pixel and a second sub-pixel adjacent to each other in the column direction in a display device according to an embodiment of the present disclosure.

[0032] Figure 19 Is a plan view of a display panel on which a repair process has been performed.

[0033] Figure 20 Is Figure 15 An enlarged plan view of a part of

[0034] Figure 21 Is a cross-sectional view of a first sub-pixel and a second sub-pixel adjacent to each other in the column direction in a display device according to an embodiment of the present disclosure.

[0035] Figure 22 Is a plan view of a display panel according to an embodiment of the present disclosure.

[0036] Figure 23 Is an enlarged Figure 22 A plan view of a part of the area in

[0037] Figure 24 Is along Figure 23 A cross-sectional view taken along line B-B' of

[0038] Figure 25 Is a cross-sectional view of a first sub-pixel and a second sub-pixel adjacent to each other in the column direction in a display device according to an embodiment of the present disclosure.

[0039] Figure 26 Is a plan view of a display panel on which a repair process has been performed.

[0040] Figure 27Shows the current supply situation after the repair process when a defect occurs in the second sub-pixel among the first to fourth sub-pixels arranged in the column direction in the display panel according to an embodiment of the present disclosure.

[0041] Figure 28 Shows the current supply situation after the repair process when a defect occurs in the first sub-pixel among the first to fourth sub-pixels arranged in the column direction in the display panel according to an embodiment of the present disclosure. Detailed implementation

[0042] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. When assigning reference numerals to the components of each drawing, even if the same components are shown in different drawings, the same reference numerals can be assigned to these same components. When it is determined that details of known technologies or functions will make the subject matter of the present disclosure unclear, these known technologies or function details can be skipped. As used herein, when a component "includes" or "has" another component or "is constituted of" another component, the component can also add other components, unless the component "only" includes or "has" "another component" or "is only constituted of" "another component". As used herein, the singular forms "a", "an", and "the" are intended to also include the plural forms, unless the context clearly indicates otherwise.

[0043] Labels such as "first", "second", "A", "B", "(a)", and "(b)" can be used to describe the components of the present disclosure. These labels are provided only to distinguish one component from another, and the nature, order, or quantity of the components are not limited by the labels.

[0044] When describing the positional relationship between components, when two or more components are described as "connected", "coupled", or "linked", the two or more components can be directly "connected", "coupled", or "linked", or another component can intervene therebetween. Here, the other component can be included in one or more of the two or more components that are "connected", "coupled", or "linked" to each other.

[0045] When using terms such as "after", "then", and "before" to describe the temporal flow relationship related to components, operation methods, and manufacturing methods, it can include a non-consecutive relationship, unless the term is used together with "immediately" or "directly".

[0046] When a component is specified to have a value or its corresponding information (e.g., level), the value or corresponding information can be interpreted as including tolerances that may be caused by various factors (e.g., process factors, internal or external influences, or noise).

[0047] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0048] Figure 1 is a system configuration diagram of a display device 100 according to an embodiment of the present disclosure.

[0049] Referring to Figure 1 , according to an embodiment of the present disclosure, the display device 100 may include a display panel 110 and a driving circuit. The display panel 110 includes a plurality of sub-pixels SP, and the driving circuit is configured to drive the plurality of sub-pixels SP included in the display panel 110.

[0050] The driving circuit may include a data driving circuit 120 and a gate driving circuit 130, and may further include a controller 140 for controlling the data driving circuit 120 and the gate driving circuit 130.

[0051] The display panel 110 may include a substrate SUB and signal lines provided on the substrate SUB, such as a plurality of data lines DL and a plurality of gate lines GL. The plurality of data lines DL and the plurality of gate lines GL may be connected to the plurality of sub-pixels SP.

[0052] The display panel 110 may include a display area DA for displaying an image and a non-display area NDA for not displaying an image. In the display panel 110, the plurality of sub-pixels SP for displaying an image may be provided in the display area DA, and the driving circuits 120, 130 and the controller 140 may be electrically connected to the non-display area NDA, or may be mounted on the non-display area NDA. Alternatively, a pad portion connected to an integrated circuit or a printed circuit may be provided in the non-display area NDA.

[0053] The data driving circuit 120 may be a circuit for driving the plurality of data lines DL, and may provide data signals to the plurality of data lines DL.

[0054] The gate driving circuit 130 may be a circuit for driving the plurality of gate lines GL, and may provide gate signals to the plurality of gate lines GL.

[0055] The controller 140 may provide a data driving control signal DCS to the data driving circuit 120 to control the data driving circuit 120, and may provide a gate driving control signal GCS to the gate driving circuit 130 to control the gate driving circuit 130.

[0056] The controller 140 may start scanning according to the timing implemented in each frame, and convert the input image data input from the outside to a data signal format suitable for use in the data driving circuit 120, thereby obtaining the converted image data and providing the converted image data to the data driving circuit 120, and may control the data driving at an appropriate time according to the scanning.

[0057] The controller 140 may receive various timing signals from the outside (e.g., the host system 150), such as a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, an input data enable signal DE, a clock signal CLK, and input image data.

[0058] To control the data driving circuit 120 and the gate driving circuit 130, the controller 140 may receive various timing signals, such as a vertical synchronization signal VSYNC, a horizontal synchronization signal VSYNC, an input data enable signal DE, a clock signal CLK, and may generate various control signals DCS and GCS and output them to the data driving circuit 120 and the gate driving circuit 130.

[0059] For example, the controller 140 may output various gate control signals GCS including a gate start pulse GSP, a gate shift clock GSC, and a gate output enable GOE signal to control the gate driving circuit 130.

[0060] In addition, to control the data driving circuit 120, the controller 140 may output various data control signals DCS including a source start pulse SSP, a source sampling clock SSC, and a source output enable SOE signal.

[0061] The controller 140 may be implemented as a component separate from the data driving circuit 120, or may be integrated with the data driving circuit 120 and implemented as an integrated circuit.

[0062] The data driving circuit 120 may receive image data Data from the controller 140 and provide data voltages to a plurality of data lines DL, thereby driving the plurality of data lines DL. Here, the data driving circuit 120 may also be referred to as a source driving circuit.

[0063] The data driving circuit 120 may include one or more source driver integrated circuits SDICs.

[0064] Each source driver integrated circuit SDIC may include a shift register, a latch circuit, a digital-to-analog converter DAC, and an output buffer. In some cases, each source driver integrated circuit SDIC may further include an analog-to-digital converter ADC.

[0065] For example, each source driver integrated circuit SDIC may be connected to the display panel 110 using a tape automated bonding (TAB) method, or may be connected to the bonding pads of the display panel 110 using a chip-on-glass (COG) or chip-on-panel (COP) method, or may be implemented and connected to the display panel 110 using a chip-on-film (COF) method.

[0066] The gate driving circuit 130 can output a gate signal with a conductive level voltage or a gate signal with a cut-off level voltage according to the control of the controller 140. The gate driving circuit 130 can sequentially drive a plurality of gate lines GL by sequentially supplying gate signals with a conductive level voltage to the plurality of gate lines GL.

[0067] The gate driving circuit 130 can be connected to the display panel 110 using the tape automated bonding (TAB) method, or can be connected to the bonding pads of the display panel 110 using the chip on glass (COG) or chip on panel (COP) method, or can be connected to the display panel 110 according to the chip on film (COF) method. Alternatively, the gate driving circuit 130 can be of the gate in panel (GIP) type and can be formed in the non-display area NDA of the display panel 110. The gate driving circuit 130 can be disposed on the substrate SUB or connected to the substrate SUB. That is, if the gate driving circuit 130 is of the GIP type, it can be disposed in the non-display area NDA of the substrate SUB. In the case of the chip on glass (COG) type, the chip on film (COF) type, etc., the gate driving circuit 130 can be connected to the substrate SUB.

[0068] Meanwhile, at least one of the data driving circuit 120 and the gate driving circuit 130 can be disposed in the display area DA. For example, at least one of the data driving circuit 120 and the gate driving circuit 130 can be arranged not to overlap with the sub-pixels SP, or can be arranged to partially or completely overlap with the sub-pixels SP.

[0069] When the gate driving circuit 130 selects a specific gate line GL, the data driving circuit 120 can convert the image data Data received from the controller 140 into an analog data voltage and can supply the analog data voltage to the plurality of data lines DL.

[0070] The data driving circuit 120 can be connected to one side (e.g., the upper side or the lower side) of the display panel 110. According to the driving method or the panel design method, the data driving circuit 120 can be connected to both sides (e.g., the upper side and the lower side) of the display panel 110, or can be connected to two or more of the four sides of the display panel 110.

[0071] The gate driving circuit 130 can be connected to one side (e.g., the left side or the right side) of the display panel 110. According to the driving method or the panel design method, the gate driving circuit 130 can be connected to both sides (e.g., the left side and the right side) of the display panel 110, or can be connected to two or more of the four sides of the display panel 110.

[0072] The controller 140 may be a timing controller used in typical display technologies, or may be a control device including a timing controller capable of further performing other control functions, or may be a control device different from the timing controller, or may be a control device in addition to the timing controller, or may be a circuit within the control device. The controller 140 may be implemented using various circuits or electronic components, such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), or processors.

[0073] The controller 140 may be mounted on a printed circuit board, a flexible printed circuit, etc., and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through the printed circuit board or the flexible printed circuit.

[0074] The controller 140 may transmit and receive signals to and from the data driving circuit 120 according to one or more predetermined interfaces. For example, the interface may include a low-voltage differential signaling (LVDS) interface, an embedded clock point-to-point interface (EPI) interface, or a serial peripheral interface (SPI).

[0075] The controller 140 may include a storage medium, such as one or more registers.

[0076] The display device 100 according to the present embodiment may be a display including a backlight unit, such as a liquid crystal display device, or may be a self-emitting display, such as an organic light-emitting display device, a quantum dot display device, and an inorganic light-emitting display device.

[0077] If the display device 100 according to the present embodiment is an organic light-emitting display device, each sub-pixel SP may include a light-emitting organic light-emitting diode (OLED) as a light-emitting device.

[0078] If the display device 100 according to the present embodiment is a quantum dot display device, each sub-pixel SP may include a light-emitting device made of quantum dots, which are self-luminous semiconductor crystals.

[0079] If the display device 100 according to the present embodiment is an inorganic light-emitting display device, each sub-pixel SP may include an inorganic light-emitting device as a light-emitting device, which is self-luminous and made based on inorganic materials. For example, the inorganic light-emitting device may also be referred to as a microscale or nanoscale light-emitting diode (LED), and the inorganic light-emitting display may also be referred to as a micro-LED display or a nano-LED display.

[0080] Figure 2 is an equivalent circuit of a sub-pixel in the display panel 110 according to an embodiment of the present disclosure.

[0081] Reference Figure 2, each of the plurality of sub-pixels SP provided on the display panel 110 according to an embodiment of the present disclosure may include a light-emitting device ED and a sub-pixel circuit SPC for driving the light-emitting device ED.

[0082] The sub-pixel circuit SPC of each sub-pixel SP may include a driving transistor DRT, a scanning transistor SCT, a sensing transistor SENT, and a storage capacitor Cst. In this case, the sub-pixel circuit SPC of each sub-pixel SP may include three transistors (DRT, SCT, SENT) and one capacitor (Cst), and thus it may be referred to as a 3T-1C structure.

[0083] Reference Figure 2 , the light-emitting device ED may include a pixel electrode PE, a common electrode CE, and an emission layer EL located between the pixel electrode PE and the common electrode CE.

[0084] The pixel electrode PE may be an electrode connected to a transistor such as the driving transistor DRT, and may be an electrode provided in each sub-pixel SP. The common electrode CE may be an electrode to which a common voltage is applied, and is an electrode commonly provided in all sub-pixels SP. For example, the common voltage may be a driving voltage EVDD as a high-level common voltage, or a reference voltage (base voltage) EVSS as a low-level common voltage.

[0085] When the reference voltage EVSS is applied to the common electrode CE, the common electrode CE may receive the reference voltage EVSS through a reference voltage line BVL.

[0086] According to Figure 2 's example, the pixel electrode PE may be an anode electrode, and the common electrode CE may be a cathode electrode. Alternatively, the pixel electrode PE may be a cathode electrode, and the common electrode CE may be an anode electrode.

[0087] For example, the light-emitting device ED may be an organic light-emitting diode (OLED), an inorganic light-emitting diode (LED), or a quantum dot light-emitting device.

[0088] Reference Figure 2 , the driving transistor DRT is a transistor for driving the light-emitting device ED, and may include a first node N1, a second node N2, and a third node N3.

[0089] The first node N1 of the driving transistor DRT may be a source node or a drain node of the driving transistor DRT, may be electrically connected to the source node or the drain node of the sensing transistor SENT, and may also be electrically connected to the pixel electrode PE of the light-emitting device ED.

[0090] The second node N2 of the driving transistor DRT can be the gate node of the driving transistor DRT and can be electrically connected to the source node or the drain node of the scanning transistor SCT.

[0091] The third node N3 of the driving transistor DRT can be electrically connected to the driving voltage line DVL that provides the driving voltage EVDD.

[0092] Reference Figure 2 , the scanning transistor SCT can be controlled by the scanning signal SC which is a type of gate signal and can be connected between the second node N2 of the driving transistor DRT and the data line DL. That is, the scanning transistor SCT can be turned on or off according to the scanning signal SC provided by the scanning signal line SCL which is a type of gate line GL, and can control the connection between the second node N2 of the driving transistor DRT and the data line DL.

[0093] The scanning transistor SCT can be turned on by the scanning signal SC having a conductive level voltage and can transfer the data voltage Vdata provided from the data line DL to the second node N2 of the driving transistor DRT.

[0094] Here, if the scanning transistor SCT is an n-type transistor, the conductive level voltage of the scanning signal SC can be a high-level voltage. If the scanning transistor SCT is a p-type transistor, the conductive level voltage of the scanning signal SC can be a low-level voltage. Hereinafter, the scanning transistor SCT is exemplified as an n-type transistor. Therefore, the conductive level voltage is exemplified as a high-level voltage.

[0095] Reference Figure 2 , the sensing transistor SENT can be controlled by the sensing signal SE which is a type of gate signal and can be connected between the first node N1 of the driving transistor DRT and the reference voltage line RVL. That is, the sensing transistor SENT can be turned on or off according to the sensing signal SE provided by the sensing signal line SENL which is a type of gate line GL, and can control the connection between the reference voltage line RVL and the first node N1 of the driving transistor DRT.

[0096] The sensing transistor SENT can be turned on by the sensing signal SE having a conductive level voltage and can transfer the reference voltage Vref provided from the reference voltage line RVL to the first node N1 of the driving transistor DRT. Here, the sensing signal SE can be regarded as a second scanning signal different from the scanning signal SC.

[0097] In addition, the sensing transistor SENT can be turned on by the sensing signal SE having a conductive level voltage and can transfer the voltage of the first node N1 of the driving transistor DRT to the reference voltage line RVL.

[0098] Here, if the sensing transistor SENT is an n-type transistor, the conduction level voltage of the sensing signal SE can be a high-level voltage. If the sensing transistor SENT is a p-type transistor, the conduction level voltage of the sensing signal SE can be a low-level voltage. Hereinafter, an example is given where the sensing transistor SENT is an n-type transistor. Therefore, the conduction level voltage is exemplified as a high-level voltage.

[0099] When driving to sense the characteristic value of the sub-pixel SP, the function of the sensing transistor SENT to transfer the voltage of the first node N1 of the driving transistor DRT to the reference voltage line RVL can be used. In this case, the voltage transmitted to the reference voltage line RVL can be a voltage for calculating the characteristic value of the sub-pixel SP or a voltage reflecting the characteristic value of the sub-pixel SP.

[0100] In the present disclosure, the characteristic value of the sub-pixel SP can be the characteristic value of the driving transistor DRT or the light-emitting device ED. For example, the characteristic values of the driving transistor DRT can include the threshold voltage and mobility of the driving transistor DRT. The characteristic values of the light-emitting device ED can include the threshold voltage of the light-emitting device ED.

[0101] Reference Figure 2 , the storage capacitor Cst can be connected between the second node N2 and the first node N1 of the driving transistor DRT. The storage capacitor Cst can be charged with charges corresponding to the voltage difference between the two ends, and can be used to maintain the voltage difference between the two ends for a set frame time. Therefore, the corresponding sub-pixel SP can emit light during the set frame time.

[0102] In the present disclosure, the source nodes, drain nodes, and gate nodes of various transistors DRT, SCT, and SENT can also be referred to as source electrodes, drain electrodes, and gate electrodes.

[0103] Reference Figure 2 , the driving transistor DRT, the scanning transistor SCT, and the sensing transistor SENT can each be an n-type transistor or a p-type transistor. In the present disclosure, for ease of explanation, as an example, it is exemplified that the driving transistor DRT, the scanning transistor SCT, and the sensing transistor SENT are each n-type.

[0104] The storage capacitor Cst can be an external capacitor intentionally designed outside the driving transistor DT, rather than a parasitic capacitor (e.g., Cgs, Cgd) that can exist as an internal capacitor between the first node N1 and the second node N2 of the driving transistor DRT.

[0105] Figure 2The sub-pixel SP shown is only an example and can be modified in various ways by including one or more transistors or one or more capacitors.

[0106] Reference Figure 2 , for example, the gate nodes of the scan transistor SCT and the sense transistor SENT may not be connected. That is, the gate nodes of the scan transistor SCT and the sense transistor SENT may be connected to different gate lines GL.

[0107] In this case, the on / off states of the scan transistor SCT and the sense transistor SENT can be controlled independently.

[0108] Reference Figure 2 , as another example, the gate nodes of the scan transistor SCT and the sense transistor SENT may be electrically connected to each other. That is, the gate nodes of the scan transistor SCT and the sense transistor SENT may be commonly connected to one gate line GL.

[0109] In this case, the on / off states of the scan transistor SCT and the sense transistor SENT can be controlled simultaneously.

[0110] The display panel 110 according to an embodiment of the present disclosure may have a top emission structure or may have a bottom emission structure. In the top emission structure, the light emitted from the light-emitting device ED is emitted in a direction opposite to the substrate SUB. In the bottom emission structure, the light emitted from the light-emitting device ED is emitted in the direction of the substrate SUB. Hereinafter, for ease of explanation, an example in which the display panel 110 according to an embodiment of the present disclosure has a bottom emission structure is illustrated.

[0111] Figure 3 is a schematic plan view of a sub-pixel SP of the display device 100 according to an embodiment of the present disclosure.

[0112] Reference Figure 3 , each sub-pixel SP may include an emission region EA and a sub-pixel circuit SPC.

[0113] Reference Figure 3 , the pixel electrode PE may be disposed in the emission region EA.

[0114] Reference Figure 3 , a part of the pixel electrode PE may extend to the region where the sub-pixel circuit SPC is disposed and may be electrically connected to an electrode (e.g., a source electrode or a drain electrode) corresponding to the first node N1 of the driving transistor DRT in the sub-pixel circuit SPC through a contact hole CNT.

[0115] Figure 4It is an equivalent circuit of a first sub-pixel SP1 and a second sub-pixel SP2 adjacent to each other in the column direction in a display device 100 according to an embodiment of the present disclosure.

[0116] Each of the first sub-pixel SP1 and the second sub-pixel SP2 may have the same structure (i.e., equivalent circuit) as the sub-pixel SP Figure 2 in.

[0117] The first sub-pixel SP1 and the second sub-pixel SP2 may be arranged adjacent to each other in the column direction. Here, the column direction may refer to the direction in which the data line DL extends.

[0118] The first sub-pixel SP1 may include a first light-emitting device ED1 and a first sub-pixel circuit SPC1 for driving the first light-emitting device ED1.

[0119] The first sub-pixel circuit SPC1 may include a first driving transistor DRT1, a first scanning transistor SCT1, a first sensing transistor SENT1, and a first storage capacitor Cst1.

[0120] The first driving transistor DRT1 may include a first node N1, a second node N2, and a third node N3. Hereinafter, for ease of explanation, the first node N1, the second node N2, and the third node N3 of the first driving transistor DRT1 are respectively referred to as a first source electrode S1, a first gate electrode G1, and a first drain electrode D1.

[0121] The first scanning transistor SCT1 may control the connection between the data line DL and the first gate electrode G1 of the first driving transistor DRT1 according to the first scanning signal SC1.

[0122] The first sensing transistor SENT1 may control the connection between the reference voltage line RLV and the first source electrode S1 of the first driving transistor DRT1 according to the first sensing signal SE1.

[0123] The first storage capacitor Cst1 may be formed between the first gate electrode G1 and the first source electrode S1 of the first driving transistor DRT1.

[0124] The first light-emitting device ED1 may include a first pixel electrode PE1, an emission layer EL, and a common electrode CE.

[0125] The second sub-pixel SP1 may include a second light-emitting device ED2 and a second sub-pixel circuit SPC2 for driving the second light-emitting device ED2.

[0126] The second sub-pixel circuit SPC2 may include a second driving transistor DRT2, a second scanning transistor SCT2, a second sensing transistor SENT2, and a second storage capacitor Cst2.

[0127] The second driving transistor DRT2 may include a first node N1, a second node N2, and a third node N3. Hereinafter, for ease of explanation, the first node N1, the second node N2, and the third node N3 of the second driving transistor DRT2 are respectively referred to as a second source electrode S2, a second gate electrode G2, and a second drain electrode D2.

[0128] The second scanning transistor SCT2 may control the connection between the data line DL and the second gate electrode G2 of the second driving transistor DRT2 in accordance with a second scanning signal SC2.

[0129] The second sensing transistor SENT2 may control the connection between the reference voltage line RLV and the second source electrode S2 of the second driving transistor DRT2 in accordance with a second sensing signal SE2.

[0130] The second storage capacitor Cst2 may be formed between the second gate electrode G2 and the second source electrode S2 of the second driving transistor DRT2.

[0131] The second light-emitting device ED2 may include a second pixel electrode PE2, an emission layer EL, and a common electrode CE.

[0132] Meanwhile, the display device 100 according to an embodiment of the present disclosure may include a repair structure that helps to repair and normalize and increase the aperture ratio when a defect occurs in the sub-pixel circuit SPC within the sub-pixel SP during the panel manufacturing process.

[0133] Figure 5 and Figure 6 shows a symmetric structure of a first sub-pixel SP1 and a second sub-pixel SP2 adjacent to each other in the column direction in the display device 100 according to an embodiment of the present disclosure. In the following description, reference is also made to Figure 4 .

[0134] Reference Figure 5 and Figure 6 , the first sub-pixel SP1 and the second sub-pixel SP2 may be disposed adjacent to each other in the column direction.

[0135] The first sub-pixel SP1 may include a first emission region EA1 and a first sub-pixel circuit SPC1.

[0136] The first pixel electrode PE1 may be disposed in the first emission region EA1, and a part of the first pixel electrode PE1 may extend to the region where the first sub-pixel circuit SPC1 is disposed, and may be electrically connected to a point (e.g., the first source electrode S1 of the first driving transistor DRT1) in the first sub-pixel circuit SPC1 through a first contact hole CNT1.

[0137] The second sub-pixel SP2 may include a second emission region EA2 and a second sub-pixel circuit SPC2.

[0138] A second pixel electrode PE2 may be disposed in the second emission region EA2, and a part of the second pixel electrode PE2 may extend to a region where the second sub-pixel circuit SPC2 is disposed and may be electrically connected to a point (e.g., a second source electrode S2 of the second driving transistor DRT2) in the second sub-pixel circuit SPC2 through a second contact hole CNT2.

[0139] Reference Figure 5 and Figure 6 , the first sub-pixel SP1 and the second sub-pixel SP2 may have a symmetric structure based on a boundary between the first sub-pixel SP1 and the second sub-pixel SP2.

[0140] Reference Figure 5 and Figure 6 , according to the symmetric structure of the first sub-pixel SP1 and the second sub-pixel SP2, the first sub-pixel circuit SPC1 may be disposed closer to the second sub-pixel circuit SPC2 among the second emission region EA2 and the second sub-pixel circuit SPC2.

[0141] Reference Figure 6 , according to the symmetric structure of the first sub-pixel SP1 and the second sub-pixel SP2, the first source electrode S1 may be disposed closer to the second source electrode S2 among the second source electrode S2 and the second pixel electrode PE2.

[0142] Reference Figure 5 and Figure 6 , if each of the first sub-pixel SP1 and the second sub-pixel SP2 is a normal sub-pixel SP, the first sub-pixel circuit SPC1 may supply a first current I1 to a first light-emitting device ED1, and the second sub-pixel circuit SPC2 may supply a second current I2 to a second light-emitting device ED2.

[0143] Accordingly, the first current I1 may flow from the first source electrode S1 of the first driving transistor DRT1 to the first pixel electrode PE1, and the second current I2 may flow from the second source electrode S2 of the driving transistor DRT2 to the second pixel electrode PE2.

[0144] Figure 7 Illustrated is a case where a defect occurs in the second sub-pixel SP2 among the first sub-pixel SP1 and the second sub-pixel SP2 adjacent in a column direction in a display device 100 according to an embodiment of the present disclosure. In the following description, reference is also made to Figures 4 to 6 .

[0145] Reference Figure 7, during the panel manufacturing process, defects may occur in the second sub-pixel circuit SPC2 in the second sub-pixel SP2 among the first sub-pixel SP1 and the second sub-pixel SP2. In this case, the second sub-pixel SP2 may not emit light normally, which may lead to deterioration of image quality.

[0146] For example, if a defect (such as a circuit break, etc.) occurs in the second sub-pixel circuit SPC2, then current is not supplied from the second sub-pixel circuit SPC2 to the second light-emitting device ED2. As a result, the second light-emitting device ED2 may not emit light. In this case, the second sub-pixel SP2 may appear as a dark spot, which may cause image anomalies.

[0147] For example, the defect that occurs in the second sub-pixel circuit SPC2 may be a defect in the second driving transistor DRT2 within the second sub-pixel circuit SPC2. For example, if at least one of the second source electrode S2, the second drain electrode D2, and the second gate electrode G2 of the second driving transistor DRT2 is disconnected or damaged due to foreign matter generated during the process, a defect may occur in the second driving transistor DRT2.

[0148] In the present disclosure, the sub-pixel SP in which a defect occurs may be referred to as a defective sub-pixel, and the sub-pixel SP in which no defect occurs may be referred to as a normal sub-pixel.

[0149] Figure 8 A repair structure of the display device 100 according to an embodiment of the present disclosure is shown, and Figure 9 is a cross-sectional view along the Figure 8 line X-X'. However, it is assumed that Figure 8 and Figure 9 each of the first sub-pixel SP1 and the second sub-pixel SP2 shown is a normal sub-pixel.

[0150] Referring to Figure 8 , the first sub-pixel SP1 may include a first pixel electrode PE1 and a first source electrode S1, and the second sub-pixel SP2 may include a second pixel electrode PE2 and a second source electrode S2.

[0151] Each of the first source electrode S1 and the second source electrode S2 may be formed of a single metal layer. Alternatively, each of the first source electrode S1 and the second source electrode S2 may be formed of multiple metal layers. Alternatively, each of the first source electrode S1 and the second source electrode S2 may include multiple electrodes electrically connected to each other.

[0152] If the first sub-pixel SP1 is a normal sub-pixel, the first current I1 can flow from the first source electrode S1 to the first pixel electrode PE1. If the second sub-pixel SP2 is a normal sub-pixel, the second current I2 can flow from the second source electrode S2 to the second pixel electrode PE2.

[0153] Reference Figure 8 and Figure 9 , if a defect occurs in one of the first sub-pixel SP1 and the second sub-pixel SP2, the display device 100 according to an embodiment of the present disclosure may include a repair structure to repair the defect.

[0154] Reference Figure 8 and Figure 9 , the repair structure of the display device 100 according to an embodiment of the present disclosure may include an overlapping pattern OP that overlaps at least one of the first source electrode S1 and the second source electrode S2 in a vertical direction.

[0155] Reference Figure 8 and Figure 9 , the repair structure of the display device 100 according to an embodiment of the present disclosure may include a first lower metal LM1 connected to the first source electrode S1 and a second lower metal LM2 connected to the second source electrode S2.

[0156] Reference Figure 8 and Figure 9 , the first lower metal LM1 may be disposed in the region of the first sub-pixel SP1, and the second lower metal LM2 may be disposed in the region of the second sub-pixel SP2.

[0157] In this case, as Figure 9 shown, by way of example, the overlapping pattern OP may include a first portion PART1 that overlaps a part of the first lower metal LM1, a second portion PART2 that overlaps a part of the second lower metal LM2, and a third portion PART3 between the first portion PART1 and the second portion PART2.

[0158] Reference Figure 9 , the first lower metal LM1 and the second lower metal LM2 may be disposed on the substrate SUB, a first buffer layer BUF1 may be disposed on the first lower metal LM1 and the second lower metal LM2, and the overlapping pattern OP may be disposed on the first buffer layer BUF1.

[0159] Accordingly, the first lower metal LM1 and the second lower metal LM2 may be spaced apart from the overlapping pattern OP by the first buffer layer BUF1.

[0160] The first lower metal LM1 and the second lower metal LM2 may be formed as the lowest metal layer closest to the substrate SUB in the display panel 110. The overlapping pattern OP may be formed of the second closest and second lowest metal layer to the substrate SUB in the display panel 110.

[0161] The first lower metal LM1 may overlap with the first driving transistor DRT1, and the second lower metal LM2 may overlap with the second driving transistor DRT2. For example, the first lower metal LM1 may overlap with the first active layer ACT1 of the first driving transistor DRT1, and the second lower metal LM2 may overlap with the second active layer ACT2 of the second driving transistor DRT2.

[0162] Figure 10 Shown is a soldering repair process when a defect occurs in the second sub-pixel circuit SPC2 within the second sub-pixel SP2 among the first sub-pixel SP1 and the second sub-pixel SP2 adjacent in the column direction in the display device 100 according to an embodiment of the present disclosure. Figure 11 is a cross-sectional view taken along Figure 10 the line X-X' of.

[0163] Refer to Figure 10 and Figure 11 The first lower metal LM1 may be connected to the first source electrode S1 of the first driving transistor DRT1, and the second lower metal LM2 may be connected to the second source electrode S2 of the second driving transistor DRT2.

[0164] Refer to Figure 10 and Figure 11 Before the soldering repair process, the first part PART1 of the overlapping pattern OP and the first lower metal LM1 may be not only arranged to be spaced apart from each other but also electrically isolated from each other. The second part PART2 of the overlapping pattern OP and the second lower metal LM2 may be not only arranged to be spaced apart from each other but also electrically isolated from each other.

[0165] Refer to Figure 10 and Figure 11 If a defect occurs in the second sub-pixel circuit SPC2 in the second sub-pixel SP2 among the first sub-pixel SP1 and the second sub-pixel SP2 adjacent in the column direction, the first part PART1 of the overlapping pattern OP and the first lower metal LM1 may be electrically connected by laser soldering, and the second part PART2 of the overlapping pattern OP and the second lower metal LM2 may be electrically connected by laser soldering.

[0166] By performing laser welding, a first welding pattern WPTN1 can be formed between a first part PART1 of the overlapping pattern OP and a first lower metal LM1, and a second welding pattern WPTN2 can be formed between a second part PART2 of the overlapping pattern OP and a second lower metal LM2.

[0167] The first welding pattern WPTN1 can be formed by welding to at least one of the first part PART1 of the overlapping pattern OP and the first lower metal LM1, or the first welding pattern WPTN1 can be a pattern made of a material different from the first part PART1 of the overlapping pattern OP and the first lower metal LM1.

[0168] The second welding pattern WPTN2 can be formed by welding to at least one of the second part PART2 of the overlapping pattern OP and the second lower metal LM2, or the second welding pattern WPTN2 can be a pattern made of a material different from the second part PART2 of the overlapping pattern OP and the second lower metal LM2.

[0169] Therefore, the first driving transistor DRT1 can supply not only the first current I1 to the first pixel electrode PE1 but also the first current I1 to the second pixel electrode PE2. As a result, the first light-emitting device ED1 of the first sub-pixel SP1 can emit light, and the second light-emitting device ED2 of the second sub-pixel SP2 can emit light.

[0170] Even if a defect occurs in the second sub-pixel circuit SPC2 of the second sub-pixel SP2, the second light-emitting device ED2 can emit light normally through the first driving transistor DRT1 of the first sub-pixel SP1, thereby normalizing the second sub-pixel SP2.

[0171] Figure 12 An equivalent circuit is shown, which shows cut points CP1, CP2, and CP3 for disabling the second sub-pixel circuit SPC2 in the second sub-pixel SP2 when a defect occurs in the second sub-pixel circuit SPC2 among the first sub-pixel SP1 and the second sub-pixel SP2 adjacent in the column direction in the display device 100 according to an embodiment of the present disclosure.

[0172] Reference Figure 12 According to an embodiment of the present disclosure, the display panel 110 may include a driving voltage line DVL for transmitting a driving voltage EVDD to a first drain electrode D1 of the first driving transistor DRT1 and a second drain electrode D2 of the second driving transistor DRT2.

[0173] Reference Figure 12, the display panel 110 according to an embodiment of the present disclosure may include a data line DL for transmitting a data voltage Vdata, a first scanning transistor SCT1 for controlling the connection between the data line DL and a first gate electrode G1 of the first driving transistor DRT1, and a second scanning transistor SCT2 for controlling the connection between the data line DL and a second gate electrode G2 of the second driving transistor DRT2.

[0174] Reference Figure 12 , the display panel 110 according to an embodiment of the present disclosure may include a reference voltage line RVL for transmitting a reference voltage, a first sensing transistor SENT1 for controlling the connection between the reference voltage line RVL and a first source electrode S1 of the first driving transistor DRT1, and a second sensing transistor SENT2 for controlling the connection between the reference voltage line RVL and a second source electrode S2 of the second driving transistor DRT2.

[0175] Reference Figure 12 , if a defect occurs in the second sub-pixel circuit SPC2 in the second sub-pixel SP2 among the first sub-pixel SP1 and the second sub-pixel SP2 adjacent in the column direction, in order to disable the second sub-pixel circuit SPC2 in the sub-pixel SP2, it is necessary not to supply at least one of the driving voltage EVDD, the data voltage Vdata, and the reference voltage Vref to the second sub-pixel circuit SPC2.

[0176] Reference Figure 12 , the cut-off points for disabling the second sub-pixel circuit SPC2 in the second sub-pixel SP2 may include a first cut-off point CP1 for blocking the supply of the driving voltage EVDD, a second cut-off point CP2 for blocking the supply of the data voltage Vdata, and a third cut-off point CP3 for blocking the supply of the reference voltage Vref.

[0177] Reference Figure 12 , the first cut-off point CP1 may be a connection point between the driving voltage line DVL and the second sub-pixel circuit SPC2, the second cut-off point CP2 may be a connection point between the data line DL and the second sub-pixel circuit SPC2, and the third cut-off point CP3 may be a connection point between the reference voltage line RVL and the second sub-pixel circuit SPC2.

[0178] Reference Figure 12, if both the first sub-pixel circuit SPC1 and the second sub-pixel circuit SPC2 are normal, a first current I1 can be provided from the first driving transistor DRT1 to the first pixel electrode PE1, and a second current I2 can be provided from the second driving transistor DRT2 to the second pixel electrode PE2. In this case, the driving voltage line DVL and the first drain electrode D1 can be electrically connected, and the driving voltage line DVL and the second drain electrode D2 can be electrically connected.

[0179] Reference Figure 12 , if the second sub-pixel circuit SPC2 among the first sub-pixel circuit SPC1 and the second sub-pixel circuit SPC2 is defective, a first current I1 can be provided from the first driving transistor DRT1 to both the first pixel electrode PE1 and the second pixel electrode PE2. In this case, the driving voltage line DVL and the first drain electrode D1 can be electrically connected, but the driving voltage line DVL and the second drain electrode D2 can be electrically disconnected.

[0180] Reference Figure 12 , if both the first sub-pixel circuit SPC1 and the second sub-pixel circuit SPC2 are normal, a first current I1 can be provided from the first driving transistor DRT1 to the first pixel electrode PE1, and a second current I2 can be provided from the second driving transistor DRT2 to the second pixel electrode PE2. In this case, the data line DL and the first scanning transistor SCT1 can be connected, and the data line DL and the second scanning transistor SCT2 can be connected.

[0181] Reference Figure 12 , if the second sub-pixel circuit SPC2 among the first sub-pixel circuit SPC1 and the second sub-pixel circuit SPC2 is defective, a first current I1 can be provided from the first driving transistor DRT1 to both the first pixel electrode PE1 and the second pixel electrode PE2. In this case, the data line DL and the first scanning transistor SCT1 can be connected, but the data line DL and the second scanning transistor SCT2 can be disconnected.

[0182] Reference Figure 12 , if both the first sub-pixel circuit SPC1 and the second sub-pixel circuit SPC2 are normal, a first current I1 can be provided from the first driving transistor DRT1 to the first pixel electrode PE1, and a second current I2 can be provided from the second driving transistor DRT2 to the second pixel electrode PE2. In this case, the reference voltage line RVL and the first sensing transistor SENT1 can be connected, and the reference voltage line RVL and the second sensing transistor SENT2 can be connected.

[0183] Reference Figure 12, if the second sub-pixel circuit SPC2 among the first sub-pixel circuit SPC1 and the second sub-pixel circuit SPC2 is defective, the first current I1 can be supplied from the first driving transistor DRT1 to the first pixel electrode PE1 and the second pixel electrode PE2. In this case, the reference voltage line RVL and the first sensing transistor SENT1 can be connected, but the reference voltage line RVL and the second sensing transistor SENT2 can be disconnected.

[0184] Figure 13 The first sub-pixel SP1 to the eighth sub-pixel SP8 in the display panel 110 according to an embodiment of the present disclosure are shown. Figure 14 is Figure 13 A plan view of the circuit cluster region 1500 of.

[0185] Reference Figure 13 , the first sub-pixel SP1, the third sub-pixel SP3, the fifth sub-pixel SP5, and the seventh sub-pixel SP7 can be set in the first sub-pixel row ROW1 and can be arranged in the row direction. The second sub-pixel SP2, the fourth sub-pixel SP4, the sixth sub-pixel SP6, and the eighth sub-pixel SP8 can be set in the second sub-pixel row ROW2 and can be arranged in the row direction.

[0186] Reference Figure 13 , the first sub-pixel SP1 and the second sub-pixel SP2 can be set in the first sub-pixel column COL1 and be adjacent to each other in the column direction. The third sub-pixel SP3 and the fourth sub-pixel SP4 can be set in the second sub-pixel column COL2 and be adjacent to each other in the column direction. The fifth sub-pixel SP5 and the sixth sub-pixel SP6 can be set in the third sub-pixel column COL3 and be adjacent to each other in the column direction. The seventh sub-pixel SP7 and the eighth sub-pixel SP8 can be set in the fourth sub-pixel column COL4 and be adjacent to each other in the column direction.

[0187] Reference Figure 13 , the first sub-pixel SP1 can include a first emission region EA1 and a first sub-pixel circuit SPC1. The second sub-pixel SP2 can include a second emission region EA2 and a second sub-pixel circuit SPC2. The third sub-pixel SP3 can include a third emission region EA3 and a third sub-pixel circuit SPC3. The fourth sub-pixel SP4 can include a fourth emission region EA4 and a fourth sub-pixel circuit SPC4. The fifth sub-pixel SP5 can include a fifth emission region EA5 and a fifth sub-pixel circuit SPC5. The sixth sub-pixel SP6 can include a sixth emission region EA6 and a sixth sub-pixel circuit SPC6. The seventh sub-pixel SP7 can include a seventh emission region EA7 and a seventh sub-pixel circuit SPC7. The eighth sub-pixel SP8 can include an eighth emission region EA8 and an eighth sub-pixel circuit SPC8.

[0188] Reference Figure 13 As shown in the reference, the first sub-pixel SP1 and the second sub-pixel SP2 adjacent to each other in the column direction may have a structure symmetric about the boundary. Therefore, the first sub-pixel circuit SPC1 and the second sub-pixel circuit SPC2 may be disposed between the first emission region EA1 and the second emission region EA2, and the first sub-pixel circuit SPC1 and the second sub-pixel circuit SPC2 may be disposed adjacent to each other.

[0189] Reference Figure 13 As shown in the reference, the third sub-pixel SP3 and the fourth sub-pixel SP4 adjacent to each other in the column direction may have a structure symmetric about the boundary. Therefore, the third sub-pixel circuit SPC3 and the fourth sub-pixel circuit SPC4 may be disposed between the third emission region EA3 and the fourth emission region EA4, and the third sub-pixel circuit SPC3 and the fourth sub-pixel circuit SPC4 may be disposed adjacent to each other.

[0190] Reference Figure 13 As shown in the reference, the fifth sub-pixel SP5 and the sixth sub-pixel SP6 adjacent to each other in the column direction may have a structure symmetric about the boundary. Therefore, the fifth sub-pixel circuit SPC5 and the sixth sub-pixel circuit SPC6 may be disposed between the fifth emission region EA5 and the sixth emission region EA6, and the fifth sub-pixel circuit SPC5 and the sixth sub-pixel circuit SPC6 may be disposed adjacent to each other.

[0191] Reference Figure 13 As shown in the reference, the seventh sub-pixel SP7 and the eighth sub-pixel SP8 adjacent to each other in the column direction may have a structure symmetric about the boundary. Therefore, the seventh sub-pixel circuit SPC7 and the eighth sub-pixel circuit SPC8 may be disposed between the seventh emission region EA7 and the eighth emission region EA8, and the seventh sub-pixel circuit SPC7 and the eighth sub-pixel circuit SPC8 may be disposed adjacent to each other.

[0192] Hereinafter, the symmetric structure of two sub-pixels SP adjacent to each other in the column direction may be referred to as a "vertical symmetric structure".

[0193] Reference Figure 13 will refer to Figure 14 describe the schematic planar structure of the circuit cluster region 1500 in which the first sub-pixel circuit SPC1 to the eighth sub-pixel circuit SPC8 are aggregated.

[0194] Reference Figure 14, the first sub-pixel circuit SPC1 may include a first driving transistor DRT1, a first scanning transistor SCT1, a first sensing transistor SENT1, and a first storage capacitor Cst1. The second sub-pixel circuit SPC2 may include a second driving transistor DRT2, a second scanning transistor SCT2, a second sensing transistor SENT2, and a second storage capacitor Cst2. The third sub-pixel circuit SPC3 may include a third driving transistor DRT3, a third scanning transistor SCT3, a third sensing transistor SENT3, and a third storage capacitor Cst3. The fourth sub-pixel circuit SPC4 may include a fourth driving transistor DRT4, a fourth scanning transistor SCT4, a fourth sensing transistor SENT4, and a fourth storage capacitor Cst4. The fifth sub-pixel circuit SPC5 may include a fifth driving transistor DRT5, a fifth scanning transistor SCT5, a fifth sensing transistor SENT5, and a fifth storage capacitor Cst5. The sixth sub-pixel circuit SPC6 may include a sixth driving transistor DRT6, a sixth scanning transistor SCT6, a sixth sensing transistor SENT6, and a sixth storage capacitor Cst6. The seventh sub-pixel circuit SPC7 may include a seventh driving transistor DRT7, a seventh scanning transistor SCT7, a seventh sensing transistor SENT7, and a seventh storage capacitor Cst7, and the eighth sub-pixel circuit SPC8 may include an eighth driving transistor DRT8, an eighth scanning transistor SCT8, an eighth sensing transistor SENT8, and an eighth storage capacitor Cst8.

[0195] Reference will be made to Figure 14 describe the arrangement structures of the column lines DL1 to DL4, DVL, and RVL.

[0196] Reference Figure 14 , the first data line DL1 and the second data line DL2 may be disposed between the first sub-pixel column COL1 and the second sub-pixel column COL2. The third data line DL3 and the fourth data line DL4 may be disposed between the third sub-pixel column COL3 and the fourth sub-pixel column COL4.

[0197] The first data line DL1 may supply a first data voltage Vdata1 to the first sub-pixel circuit SPC1 and the second sub-pixel circuit SPC2 disposed in the first sub-pixel column COL1. The first data line DL1 may be connected to the first scanning transistor SCT1 in the first sub-pixel circuit SPC1 and the second scanning transistor SCT2 in the second sub-pixel circuit SPC2.

[0198] The second data line DL2 can supply a second data voltage Vdata2 to a third sub-pixel circuit SPC3 and a fourth sub-pixel circuit SPC4 disposed in a second sub-pixel column COL2. The second data line DL2 can be connected to a third scanning transistor SCT3 in the third sub-pixel circuit SPC3 and a fourth scanning transistor SCT4 in the fourth sub-pixel circuit SPC4.

[0199] The third data line DL3 can supply a third data voltage Vdata3 to a fifth sub-pixel circuit SPC5 and a sixth sub-pixel circuit SPC6 disposed in a third sub-pixel column COL3. The third data line DL3 can be connected to a fifth scanning transistor SCT5 in the fifth sub-pixel circuit SPC5 and a sixth scanning transistor SCT6 in the sixth sub-pixel circuit SPC6.

[0200] The fourth data line DL4 can supply a fourth data voltage Vdata4 to a seventh sub-pixel circuit SPC7 and an eighth sub-pixel circuit SPC8 disposed in a fourth sub-pixel column COL4. The fourth data line DL4 can be connected to a seventh scanning transistor SCT7 in the seventh sub-pixel circuit SPC7 and an eighth scanning transistor SCT8 in the eighth sub-pixel circuit SPC8.

[0201] Reference Figure 14 , a reference voltage line RVL can be disposed between the second sub-pixel column COL2 and the third sub-pixel column COL3.

[0202] The reference voltage line RVL can be connected to first sub-pixel circuits SPC1 to eighth sub-pixel circuits SPC8 disposed in the first sub-pixel column COL1 to the fourth sub-pixel column COL4. The reference voltage line RVL can be connected to first sub-pixel circuits SPC1 to eighth sub-pixel circuits SPC8 disposed in the first sub-pixel column COL1 to the fourth sub-pixel column COL4 through a reference connection pattern CPTN_RVL.

[0203] The reference voltage line RVL can supply a reference voltage Vref to drain nodes or source nodes of first sensing transistors SENT1 to eighth sensing transistors SENT8 in first sub-pixel circuits SPC1 to eighth sub-pixel circuits SPC8 disposed in the first sub-pixel column COL1 to the fourth sub-pixel column COL4.

[0204] Reference Figure 14 , a driving voltage line DVL can be disposed on one side of the first sub-pixel column COL1 and on the other side of the fourth sub-pixel column COL4.

[0205] The driving voltage line DVL disposed on one side of the first sub-pixel column COL1 can be connected to the first to fourth sub-pixel circuits SPC1 to SPC4 disposed in the first sub-pixel column COL1 and the second sub-pixel column COL2. The driving voltage line DVL disposed on one side of the first sub-pixel column COL1 can be connected to the first to fourth sub-pixel circuits SPC1 to SPC4 disposed in the first sub-pixel column COL1 and the second sub-pixel column COL2 through the driving connection pattern CPTN_DVL.

[0206] The driving voltage line DVL disposed on one side of the first sub-pixel column COL1 can supply the driving voltage EVDD to the drain nodes or source nodes of the first to fourth scanning transistors SCT1 to SCT4 in the first to fourth sub-pixel circuits SPC1 to SPC4 disposed in the first sub-pixel column COL1 and the second sub-pixel column COL2.

[0207] The driving voltage line DVL disposed on the other side of the fourth sub-pixel column COL4 can be connected to the fifth to eighth sub-pixel circuits SPC5 to SPC8 disposed in the third sub-pixel column COL3 and the fourth sub-pixel column COL4. The driving voltage line DVL disposed on the other side of the fourth sub-pixel column COL4 can be connected to the fifth to eighth sub-pixel circuits SPC5 to SPC8 disposed in the third sub-pixel column COL3 and the fourth sub-pixel column COL4 through the driving connection pattern CPTN_DVL.

[0208] The driving voltage line DVL disposed on the other side of the fourth sub-pixel column COL4 can supply the driving voltage EVDD to the drain nodes or source nodes of the fifth to eighth scanning transistors SCT5 to SCT8 in the fifth to eighth sub-pixel circuits SPC5 to SPC8 disposed in the third sub-pixel column COL3 and the fourth sub-pixel column COL4.

[0209] Reference Figure 14 , since the first sub-pixel SP1 and the second sub-pixel SP2 have a vertically symmetric structure, the first sub-pixel circuit SPC1 and the second sub-pixel circuit SPC2 can also have a vertically symmetric structure.

[0210] Reference Figure 14 , since the third sub-pixel SP3 and the fourth sub-pixel SP4 have a vertically symmetric structure, the third sub-pixel circuit SPC3 and the fourth sub-pixel circuit SPC4 can also have a vertically symmetric structure.

[0211] Reference Figure 14, since the fifth sub-pixel SP5 and the sixth sub-pixel SP6 have a vertically symmetric structure, the fifth sub-pixel circuit SPC5 and the sixth sub-pixel circuit SPC6 can also have a vertically symmetric structure.

[0212] Reference Figure 14 , since the seventh sub-pixel SP7 and the eighth sub-pixel SP8 have a vertically symmetric structure, the seventh sub-pixel circuit SPC7 and the eighth sub-pixel circuit SPC8 can also have a vertically symmetric structure.

[0213] In the following, a repair structure according to an embodiment of the present disclosure that helps to repair and improve the aperture ratio in the display panel 110 will be described.

[0214] Figure 15 is Figure 14 a plan view of a local area 1600 of Figure 16 is Figure 15 an enlarged plan view of a local area 1700 of

[0215] Figure 17 is a cross-sectional view taken along Figure 16 line A-A' of Figure 18 and is a cross-sectional view of a first sub-pixel SP1 and a second sub-pixel SP2 adjacent to each other in the column direction in the display device 100 according to an embodiment of the present disclosure. Figure 19 is Figure 14 a plan view of a local area 1600 of

[0216] Reference Figure 15 , the first sub-pixel circuit SPC1 and the second sub-pixel circuit SPC2 are adjacent to each other in the column direction and can have a vertically symmetric structure. The third sub-pixel circuit SPC3 and the fourth sub-pixel circuit SPC4 are adjacent to each other in the column direction and can have a vertically symmetric structure. The fifth sub-pixel circuit SPC5 and the sixth sub-pixel circuit SPC6 are adjacent to each other in the column direction and can have a vertically symmetric structure. The seventh sub-pixel circuit SPC7 and the eighth sub-pixel circuit SPC8 are adjacent to each other in the column direction and can have a vertically symmetric structure.

[0217] Reference Figure 15, the repair structure of the display panel 110 according to an embodiment of the present disclosure may include lower metals LM1 and LM2, LM3 and LM4, LM5 and LM6, LM7 and LM8 provided on each of the sub-pixel circuits SPC1 and SPC2, SPC3 and SPC4, SPC5 and SPC6, SPC7 and SPC8 having a vertical symmetry structure, and an overlapping pattern OP overlapping with the lower metals LM1 and LM2, LM3 and LM4, LM5 and LM6, LM7 and LM8 provided on each of the sub-pixel circuits SPC1 and SPC2, SPC3 and SPC4, SPC5 and SPC6, SPC7 and SPC8 having a vertical symmetry structure.

[0218] Before the repair process, the lower metals LM1 and LM2, LM3 and LM4, LM5 and LM6, LM7 and LM8 may be connected to adjacent power supply lines (e.g., driving voltage line DVL, reference voltage line RVL, etc.).

[0219] The connection points between the lower metals LM1 and LM2, LM3 and LM4, LM5 and LM6, LM7 and LM8 and the power supply lines (e.g., driving voltage line DVL, reference voltage line RVL, etc.) may be cut off during the repair process. For example, the connection points between the lower metals LM1 and LM2, LM3 and LM4, LM5 and LM6, LM7 and LM8 and the constant voltage lines (e.g., driving voltage line DVL, reference voltage line RVL, etc.) may become the cutting points CP where cutting is performed during the repair process.

[0220] In addition, during the repair process, as Figure 12 shown, a cutting process may also be performed to disable the sub-pixel circuit. The cutting points CP1, CP2, and CP3 for disabling the sub-pixel circuit may be the connection points between the sub-pixel circuit to be disabled and the signal lines (e.g., DL, DVL, RVL).

[0221] Hereinafter, the repair structure will be described in more detail with reference to the first sub-pixel SP1 and the second sub-pixel SP2.

[0222] Referring to Figures 15 to 17 , in the first sub-pixel circuit SPC1 and the second sub-pixel circuit SPC2 having a vertical symmetry structure, a first lower metal LM1 may be provided in the first sub-pixel circuit SPC1, a second lower metal LM2 may be provided in the second sub-pixel circuit SPC2, and the overlapping pattern OP may overlap at least a part of the first lower metal LM1 and may overlap at least a part of the second lower metal LM2.

[0223] As Figure 17As shown, in the first state, the overlapping pattern OP may not be electrically connected to the first lower metal LM1 and the second lower metal LM2.

[0224] Alternatively, in the first state, the overlapping pattern OP may be electrically connected to one of the first lower metal LM1 and the second lower metal LM2 and may not be electrically connected to the other.

[0225] In a second state different from the first state, the overlapping pattern OP may be electrically connected to both the first lower metal LM1 and the second lower metal LM2.

[0226] The first state may represent a state in which both the first sub-pixel SP1 and the second sub-pixel SP2 are normal sub-pixels. In the first state, the first sub-pixel circuit SPC1 may supply a first current to the first light-emitting device ED1, and the second sub-pixel circuit SPC2 may supply a second current to the second light-emitting device ED2.

[0227] The second state may represent a situation where, when one of the first sub-pixel SP1 and the second sub-pixel SP2 is a normal sub-pixel and the other is a defective sub-pixel (i.e., an abnormal sub-pixel), the defective sub-pixel has been repaired.

[0228] For example, among the first sub-pixel SP1 and the second sub-pixel SP2, if the first sub-pixel SP1 is a normal sub-pixel and the second sub-pixel SP2 is a defective sub-pixel (i.e., an abnormal sub-pixel), the second state may be a state in which a repair process has been performed on the second sub-pixel SP2 and the second sub-pixel SP2 has been normalized.

[0229] In the second state, the first sub-pixel circuit SPC1 may not only supply a first current to the first light-emitting device ED1 but also supply a first current to the second light-emitting device ED2. The second sub-pixel circuit SPC2 may be disabled and may not be able to supply current to the second light-emitting device ED2.

[0230] The repair process may include a soldering process (e.g., a soldering repair process) and a cutting process (e.g., a cutting repair process).

[0231] The soldering point WP (which is a point for the soldering process) may include a point corresponding to the first part PART1 of the overlapping pattern OP and a point corresponding to the second part PART2 of the overlapping pattern OP.

[0232] Reference Figure 17 and Figure 18 will describe the vertical structure of the display panel 110 including the repair structure.

[0233] Reference Figure 17 and Figure 18, a first lower metal LM1 and a second lower metal LM2 may be provided on a substrate SUB. The first lower metal LM1 may be provided in a region of a first sub-pixel circuit SPC1, and the second lower metal LM2 may be provided in a region of a second sub-pixel circuit SPC2.

[0234] Reference Figure 17 and Figure 18 , a first buffer layer BUF1 may be provided on the first lower metal LM1 and the second lower metal LM2, and an overlap pattern OP may be provided on the first buffer layer BUF1.

[0235] Reference Figure 17 and Figure 18 , a plate PLT of the first sub-pixel circuit SPC1 and the second sub-pixel circuit SPC2 may be provided on the first buffer layer BUF1 together with the overlap pattern OP. The plate PLT of the first sub-pixel circuit SPC1 and the second sub-pixel circuit SPC2 and the overlap pattern OP may be in the same layer and include the same material.

[0236] Reference Figure 17 and Figure 18 , a second buffer layer BUF2 may be provided on the plate PLT and the overlap pattern OP.

[0237] Reference Figure 17 and Figure 18 , an active layer pattern may be provided on the second buffer layer BUF2.

[0238] For example, the active layer pattern may include an active layer pattern AP_SCT1 for forming a first active layer ACT1 of a first driving transistor DRT1 and an active layer of a first scanning transistor SCT1, an active layer pattern AP_SENT1 for forming an active layer of a first sensing transistor SENT1, a second active layer ACT2 for forming a second driving transistor DRT2 and an active layer pattern AP_SCT2 of an active layer of a second scanning transistor SCT2, and an active layer pattern AP_SENT2 for forming an active layer of a second sensing transistor SENT2.

[0239] For example, the active layer pattern may further include a driving connection pattern CPTN_DVL for connecting a driving voltage line DVL to a first drain electrode D1 of the first driving transistor DRT1 and a second drain electrode D2 of the second driving transistor DRT2.

[0240] For example, the active layer pattern may include an oxide semiconductor material.

[0241] Reference Figure 17 and Figure 18, a gate insulating layer GI may be disposed on the active layer patterns ACT1, AP_SCT1, AP_SENT1, ACT2, AP_SCT2, AP_SENT2, and CPTN_DVL.

[0242] Reference Figure 16 , Figure 17 and Figure 18 , a first gate electrode G1 and a first source electrode S1 of the first driving transistor DRT1 may be disposed on the gate insulating layer GI. A second gate electrode G2 and a second source electrode S2 of the second driving transistor DRT2 may be disposed on the gate insulating layer GI.

[0243] The first source electrode S1 may be connected to a first lower metal LM1 through holes in the gate insulating layer GI, the second buffer layer BUF2, and the first buffer layer BUF1.

[0244] The second source electrode S2 may be connected to a second lower metal LM2 through holes (GI holes) in the gate insulating layer GI, the second buffer layer BUF2, and the first buffer layer BUF1.

[0245] Reference Figure 17 and Figure 18 , a passivation layer PAS may be disposed on the first gate electrode G1, the first source electrode S1, the second gate electrode G2, and the second source electrode S2.

[0246] Reference Figure 17 and Figure 18 , an overcoat layer OC may be disposed on the passivation layer PAS.

[0247] Reference Figure 16 , Figure 17 and Figure 18 , a first pixel electrode PE1 and a second pixel electrode PE2 may be disposed on the overcoat layer OC. The first pixel electrode PE1 may be connected to the first source electrode S1 through a hole (OC hole) in the overcoat layer OC and a hole (PAS hole) in the passivation layer PAS. The second pixel electrode PE2 may be connected to the second source electrode S2 through a hole (OC hole) in the overcoat layer OC and a hole (PAS hole) in the passivation layer PAS.

[0248] Reference Figure 16 , Figure 17 and Figure 18 , the hole (OC hole) of the overcoat layer OC and the hole (PAS hole) of the passivation layer PAS may overlap each other. The hole (OC hole) of the overcoat layer OC may be larger than the hole (PAS hole) of the passivation layer PAS.

[0249] Reference Figure 16 , Figure 17 and Figure 18, the positions of the holes in the outer coating OC (OC holes) and the holes in the passivation layer PAS (PAS holes) may be different from the positions of the holes in the gate insulating layer GI (GI holes).

[0250] Reference Figure 17 and Figure 18 , a partition bank BK may be provided on the first pixel electrode PE1 and the second pixel electrode PE2. The partition bank BK may include a first opening (not shown) corresponding to the first emission region EA1 (or overlapping with the first emission region EA1) and a second opening (not shown) corresponding to the second emission region EA2 (or overlapping with the second emission region EA2). A part of the first pixel electrode PE1 may be exposed through the first opening of the partition bank BK, and a part of the second pixel electrode PE2 may be exposed through the second opening of the partition bank BK.

[0251] The repair structure of the display device 100 according to an embodiment of the present disclosure will be described again from the perspective of the first sub-pixel SP1 and the second sub-pixel SP2 adjacent in the column direction.

[0252] In the display device 100 according to an embodiment of the present disclosure, if the first sub-pixel SP1 and the second sub-pixel SP2 have a vertically symmetric structure and are a set for repair processing, the distance between the first source electrode S1 of the first driving transistor DRT1 and the second source electrode S2 of the second driving transistor DRT2 may be less than the distance between the first emission region EA1 of the first light-emitting device ED1 and the second emission region EA2 of the second light-emitting device ED2.

[0253] The display device 100 according to an embodiment of the present disclosure may include: a first sub-pixel SP1 including a first driving transistor DRT1 and a first light-emitting device ED1, a second sub-pixel SP2 including a second driving transistor DRT2 and a second light-emitting device ED2, a first lower metal LM1 connected to the first source electrode S1 of the first driving transistor DRT1, a second lower metal LM2 connected to the second source electrode S2 of the second driving transistor DRT2, an overlapping pattern OP including a first part PART1 overlapping a part of the first lower metal LM1, a second part PART2 overlapping a part of the second lower metal LM2, and a third part PART3 between the first part PART1 and the second part PART2, and a first buffer layer BUF1 provided between the first lower metal LM1 and the second lower metal LM2 and the overlapping pattern OP.

[0254] In the display device 100 according to an embodiment of the present disclosure, a first lower metal LM1 may be disposed under a first active layer ACT1 of a first driving transistor DRT1, and a second lower metal LM2 may be disposed under the first active layer ACT1 of a second driving transistor DRT2, and an overlap pattern OP may be disposed under the first lower metal LM1 and the second lower metal LM2.

[0255] If it is recognized during processing that the first sub-pixel SP1 and the second sub-pixel SP2 are normal sub-pixels, the repair process may not be performed during processing. In this case, in a first state of the display panel 110, a first current I1 may be provided from the first driving transistor DRT1 to the first pixel electrode PE1, and a second current I2 may be provided from the second driving transistor DRT2 to the second pixel electrode PE2.

[0256] In this first state, a first portion PART1 of the overlap pattern OP and the first lower metal LM1 may be spaced apart from each other, and a second portion PART2 of the overlap pattern OP and the second lower metal LM2 may be spaced apart from each other.

[0257] In addition, in the first state, the overlap pattern OP may be electrically connected to a common power supply line. For example, the common power supply line may include one or more of a driving voltage line DVL, a reference voltage line RVL, and a reference voltage line BVL.

[0258] In the first state, if the overlap pattern OP is floating and not electrically connected to the common power supply line, foreign substances may be generated around the overlap pattern OP, which may cause defects in the repair structure. Therefore, in the first state, defects caused by the repair structure may be prevented by electrically connecting the overlap pattern OP to an adjacent common power supply line, thereby improving performance and the possibility of repair success.

[0259] If it is recognized during processing that the first sub-pixel SP1 is a normal sub-pixel and the second sub-pixel SP2 is a defective sub-pixel, a repair process for normalizing the second sub-pixel SP2 (i.e., a repair process for causing the second light-emitting device ED2 to emit light) may be performed during processing. In this case, in a second state of the display panel 110, a first current I1 may be provided from the first driving transistor DRT1 to the first pixel electrode PE1 and the second pixel electrode PE2.

[0260] In the second state, a first portion PART1 of the overlap pattern OP and the first lower metal LM1 may be connected, and a second portion PART2 of the overlap pattern OP and the second lower metal LM2 may be connected.

[0261] In addition, in the second state, the overlapping pattern OP may be electrically disconnected from the common power supply line. For example, the common power supply line may include one or more of a driving voltage line DVL, a reference voltage line RVL, and a reference voltage line BVL.

[0262] The display device 100 according to an embodiment of the present disclosure may include: a first driving transistor DRT1 including a first active layer ACT1, a first source electrode S1, a first drain electrode D1, and a first gate electrode G1; a first pixel electrode PE1 electrically connected to the first source electrode S1; a second driving transistor DRT2 including a second active layer ACT2, a second source electrode S2, a second drain electrode D2, and a second gate electrode G2; and a second pixel electrode PE2 electrically connected to the second source electrode S2.

[0263] The display device 100 according to an embodiment of the present disclosure may include a first lower metal LM1 electrically connected to the first source electrode S1 and overlapping the first active layer ACT1; a second lower metal LM2 electrically connected to the second source electrode S2 and overlapping the second active layer ACT2; a first buffer layer BUF1 disposed on the first lower metal LM1 and the second lower metal LM2; an overlapping pattern OP disposed on the first buffer layer BUF1 and including a first part PART1 overlapping a part of the first lower metal LM1, a second part PART2 overlapping a part of the second lower metal LM2, and a third part PART3 between the first part PART1 and the second part PART2; and a second buffer layer BUF2 disposed on the overlapping pattern OP and below the first active layer ACT1 and the second active layer ACT2.

[0264] The distance between the first source electrode S1 and the second source electrode S2 may be less than the distance between a first emission region EA1 formed by the first pixel electrode PE1 and a second emission region EA2 formed by the second pixel electrode PE2.

[0265] The display device 100 according to an embodiment of the present disclosure may further include a gate insulating layer GI disposed on the first active layer ACT1 and the second active layer ACT2.

[0266] The first source electrode S1 may be disposed on the gate insulating layer GI and may be connected to the first lower metal LM1 through a hole (GI hole) in the gate insulating layer GI, the second buffer layer BUF2, and the first buffer layer BUF1.

[0267] The second source electrode S2 may be disposed on the gate insulating layer GI and may be connected to the second lower metal LM2 through a hole (GI hole) in the gate insulating layer GI, the second buffer layer BUF2, and the first buffer layer BUF1.

[0268] The display device 100 according to an embodiment of the present disclosure may further include a passivation layer PAS disposed on the first source electrode S1, the first gate electrode G1, the second source electrode S2, and the second gate electrode G2, and an outer coating OC disposed on the passivation layer PAS.

[0269] The first pixel electrode PE1 may be disposed on the outer coating OC and may be connected to the first source electrode S1 through holes (OC holes) in the outer coating OC and holes (PAS holes) in the passivation layer PAS. The second pixel electrode PE2 may be disposed on the outer coating OC and may be connected to the second source electrode S2 through holes (OC holes) in the outer coating OC and holes (PAS holes) in the passivation layer PAS.

[0270] The first source electrode S1 and the second source electrode S2 may include the same electrode material as the electrode material (also referred to as the gate electrode material or gate material) included in the first gate electrode G1 and the second gate electrode G2, and may be disposed in the same layer as the first gate electrode G1 and the second gate electrode G2.

[0271] The first gate electrode G1 may be disposed on the first active layer ACT1, and the second gate electrode G2 may be disposed on the second active layer ACT2.

[0272] Reference Figures 15 to 18 , the display device 100 according to an embodiment of the present disclosure may further include a first storage capacitor Cst1 formed between the first source electrode S1 and the first gate electrode G1, and a second storage capacitor Cst2 formed between the second source electrode S2 and the second gate electrode G2.

[0273] The first storage capacitor Cst1 may include a first upper capacitor Cu1 and a first lower capacitor Cd1.

[0274] The first upper capacitor Cu1 may include a first capacitor electrode corresponding to the first source electrode S1 and a second capacitor electrode AP_SCT1 (e.g., an active layer pattern) including the same material as the first active layer ACT1.

[0275] The first lower capacitor Cd1 may include a third capacitor electrode PLT including the same material as the overlapping pattern OP and a fourth capacitor electrode corresponding to the first lower metal LM1.

[0276] The first capacitor electrode and the fourth capacitor electrode may be at the same potential as the first source electrode S1, and the second capacitor electrode and the third capacitor electrode may be at the same potential as the first gate electrode G1.

[0277] Therefore, the first upper capacitor Cu1 and the first lower capacitor Cd1 may be connected in parallel. Therefore, the capacitance of the first storage capacitor Cst1 may be increased.

[0278] The second storage capacitor Cst2 may include a second upper capacitor Cu2 and a second lower capacitor Cd2.

[0279] The second upper capacitor Cu2 may include a fifth capacitor electrode corresponding to the second source electrode S2 and a sixth capacitor electrode AP_SCT2 (e.g., an active layer pattern) including the same material as the second active layer ACT2.

[0280] The second lower capacitor Cd2 may include a seventh capacitor electrode PLT including the same material as the overlapping pattern OP and an eighth capacitor electrode corresponding to the second lower metal LM2.

[0281] The fifth capacitor electrode and the eighth capacitor electrode may be at the same potential as the second source electrode S2, and the sixth capacitor electrode and the seventh capacitor electrode may be at the same potential as the second gate electrode G2.

[0282] Therefore, the second upper capacitor Cu2 and the second lower capacitor Cd2 may be connected in parallel. Accordingly, the capacitance of the second storage capacitor Cst2 may be increased.

[0283] If it is recognized during processing that the first sub-pixel SP1 and the second sub-pixel SP2 are normal sub-pixels, no repair process is performed during processing. In this case, in the first state of the display panel 110, a first current I1 may be provided from the first driving transistor DRT1 to the first pixel electrode PE1, and a second current I2 may be provided from the second driving transistor DRT2 to the second pixel electrode PE2.

[0284] In the first state, as Figure 17 and Figure 18 shown, a first portion PART1 of the overlapping pattern OP and the first lower metal LM1 may be spaced apart, and a second portion PART2 of the overlapping pattern OP and the second lower metal LM2 may be spaced apart.

[0285] In addition, in the first state, as Figure 15 shown, the overlapping pattern OP may be electrically connected to a common power supply line. For example, the common power supply line may include one or more of a driving voltage line DVL, a reference voltage line RVL, and a reference voltage line BVL.

[0286] As Figure 15 shown, for example, in the first state, the driving voltage line DVL may be a common power supply line for transmitting a driving voltage EVDD to the first drain electrode D1 and the second drain electrode D2, and may be connected to at least one of the two ends of the overlapping pattern OP.

[0287] The repair structure for the third sub-pixel circuit SPC3 and the fourth sub-pixel circuit SPC4 may include a third lower metal LM3 connected to the source electrode of the third driving transistor DRT3 in the third sub-pixel circuit SPC3, a fourth lower metal LM4 connected to the source electrode of the fourth driving transistor DRT4 in the fourth sub-pixel circuit SPC4, and an overlap pattern OP that overlaps at least a part of the third lower metal LM3 and at least a part of the fourth lower metal LM4. Here, the overlap pattern OP may include a first part PART1 that overlaps at least a part of the third lower metal LM3, a second part PART2 that overlaps at least a part of the fourth lower metal LM4, and a third part PART3 between the first part PART1 and the second part PART2.

[0288] In addition, in a first state where the third sub-pixel SP3 and the fourth sub-pixel SP4 are recognized as normal sub-pixels and the third sub-pixel SP3 and the fourth sub-pixel SP4 are in a non-repaired state, as Figure 15 shown, at least one of the two ends of the overlap pattern OP may be connected to a reference voltage line RVL that is the nearest common power supply line.

[0289] If it is recognized during processing that the first sub-pixel SP1 is a normal sub-pixel and the second sub-pixel SP is a defective sub-pixel, a repair process may be performed during processing to normalize the second sub-pixel SP2 (i.e., a repair process for causing the second light-emitting device ED2 to emit light). In this case, in a second state of the display panel 110, a first current I1 may be provided from the first driving transistor DRT1 to the first pixel electrode PE1 and the second pixel electrode PE2.

[0290] As Figure 11 and Figure 18 shown, in the second state, the first part PART1 of the overlap pattern OP and the first lower metal LM1 may be connected, and the second part PART2 of the overlap pattern OP and the second lower metal LM2 may be connected. Therefore, a first welding pattern WPTN1 may be formed between the first part PART1 of the overlap pattern OP and the first lower metal LM1, and a second welding pattern WPTN2 may be formed between the second part PART2 of the overlap pattern OP and the second lower metal LM2.

[0291] In addition, as Figure 19 shown, in the second state, the overlap pattern OP may be electrically disconnected from the common power supply line. For example, the common power supply line may include one or more of a driving voltage line DVL, a reference voltage line RVL, and a reference voltage line BVL.

[0292] For example, the overlapping pattern OP can be connected to the driving voltage line DVL and then can be cut (i.e., the first cut) during the repair process.

[0293] As Figure 19 shown, in the second state, the display device can further include a driving voltage line DVL for transmitting the driving voltage EVDD to the first drain electrode D1 and the second drain electrode D2. In addition, both ends of the overlapping pattern OP can be electrically disconnected from the driving voltage line DVL.

[0294] Meanwhile, in the second state where it is recognized that the fourth sub-pixel SP4 among the third sub-pixel SP3 and the fourth sub-pixel SP4 is a defective sub-pixel and the repair process has been performed to normalize the fourth sub-pixel SP4, the connection between at least one of the two ends of the overlapping pattern OP and the reference voltage line RVL can be disconnected by a cutting process.

[0295] In addition, as Figure 19 shown, in the second state, in order to disable the second driving transistor DRT2, for example, the connection point between the second driving transistor DRT2 and the driving voltage line DVL can be cut off (i.e., the second cut).

[0296] As described above, the repair structure described with reference to Figures 15 to 19 may require two welding processes (i.e., the welding processes at the two welding points WP1 and WP2) and two cutting processes (i.e., the first cut and the second cut).

[0297] Figure 20 is Figure 15 an enlarged plan view of a partial region 1700. Figure 21 is a cross-sectional view of a first sub-pixel and a second sub-pixel adjacent to each other in the column direction in a display device according to an embodiment of the present disclosure. Figure 21 The cross-sectional view of Figure 20 may include a portion along the line C-C' of

[0298] Figure 20 The plan view of Figure 16 and the plan view of Figure 15 are plan views that more detailedly and enlargedly show the same partial region 1700 of Figure 20 Therefore, the plan view of Figure 16 can be almost the same as the plan view of Figure 21 In addition, the cross-sectional view of Figure 18 and the cross-sectional view of Figure 21 are cross-sectional views of the same region. Therefore, the cross-sectional view of Figure 20 and the cross-sectional view of 18 can also almost correspond to each other. However, Figure 21 and Figure 16 and Figure 18There is only a slight difference. Therefore, in the following text, the description of the same configuration will be omitted, and the differences will be mainly explained.

[0299] Figure 20 and Figure 21 the positions of the holes (PAS holes) in the passivation layer PAS in Figure 16 and Figure 18 can be different from the positions of the holes (PAS holes) in the passivation layer PAS in Figure 20 and Figure 21 and the positions of the holes (GI holes) in the gate insulating layer GI in Figure 16 and Figure 18 can be different from the positions of the holes (GI holes) in the gate insulating layer GI in

[0300] This difference may be due to the absence of Figure 20 and Figure 21 the first source electrode S1 and the second source electrode S2 in Figure 16 and Figure 18 .

[0301] In Figure 16 and Figure 18 , the first pixel electrode PE1 and the first lower metal LM1 may not be directly connected, but may be electrically connected through the first source electrode S1, and the second pixel electrode PE2 and the second lower metal LM2 may not be directly connected, but may be electrically connected through the second source electrode S2.

[0302] In contrast, in Figure 20 and Figure 21 , the first pixel electrode PE1 may be directly connected to the first lower metal LM1, and the second pixel electrode PE2 may be directly connected to the second lower metal LM2.

[0303] The first pixel electrode PE1 may be directly connected to the first lower metal LM1 through the holes that penetrate all of the outer coating OC, the passivation layer PAS, the second buffer layer BUF2, and the first buffer layer BUF1.

[0304] The second pixel electrode PE2 may be directly connected to the second lower metal LM2 through the holes that penetrate all of the outer coating OC, the passivation layer PAS, the second buffer layer BUF2, and the first buffer layer BUF1.

[0305] Referring to Figure 20 and Figure 21 , the holes that penetrate all of the outer coating OC, the passivation layer PAS, the second buffer layer BUF2, and the first buffer layer BUF1 may include the holes (PAS holes) in the passivation layer PAS.

[0306] In Figure 20 and Figure 21In [description], the active layer pattern AP_SENT1 for forming the active layer of the first sensing transistor SENT1 can be used as the first source electrode S1, and the first pixel electrode PE1 can also be used as the first source electrode S1.

[0307] In Figure 20 and Figure 21 In [description], the active layer pattern AP_SENT2 for forming the active layer of the second sensing transistor SENT2 can be used as the second source electrode S2, and the second pixel electrode PE2 can also be used as the second source electrode S2.

[0308] Since there are no Figure 20 and Figure 21 first source electrode S1 and second source electrode S2 in Figure 16 and Figure 18 , the storage capacitor structures in Figure 20 and Figure 21 can be different.

[0309] Referring to Figure 21 , the first storage capacitor Cst1 can include a first upper capacitor Cu1 and a first lower capacitor Cd1.

[0310] The first upper capacitor Cu1 can include a first capacitor electrode AP_SCT1 (e.g., active layer pattern) including the same material as the first active layer ACT1 and a second capacitor electrode PLT including the same material as the overlapping pattern OP. Here, the first capacitor electrode AP_SCT1 (e.g., active layer pattern) including the same material as the first active layer ACT1 can be electrically connected to the first pixel electrode PE1. Therefore, the first capacitor electrode AP_SCT1 can be regarded as the first pixel electrode PE1.

[0311] The first lower capacitor Cd1 can include: a second capacitor electrode PLT including the same material as the overlapping pattern OP, and a third capacitor electrode corresponding to the first lower metal LM1.

[0312] The first capacitor electrode and the third capacitor electrode can be at the same potential as the first source electrode S1, and the second capacitor electrode can be at the same potential as the first gate electrode G1. Therefore, the first upper capacitor Cu1 and the first lower capacitor Cd1 can be connected in parallel. Therefore, the capacitance of the first storage capacitor Cst1 can be increased.

[0313] Referring to Figure 21 , the second storage capacitor Cst2 can include a second upper capacitor Cu2 and a second lower capacitor Cd2.

[0314] The second upper capacitor Cu2 may include: a fourth capacitor electrode AP_SCT2 (e.g., an active layer pattern) including the same material as the second active layer ACT2, and a fifth capacitor electrode PLT including the same material as the overlapping pattern OP. Here, the fourth capacitor electrode AP_SCT2 (e.g., an active layer pattern) including the same material as the second active layer ACT2 may be electrically connected to the second pixel electrode PE2. Accordingly, the fourth capacitor electrode AP_SCT2 may be regarded as the second pixel electrode PE2.

[0315] The second lower capacitor Cd2 may include: a fifth capacitor electrode PLT including the same material as the overlapping pattern OP, and a sixth capacitor electrode corresponding to the second lower metal LM2.

[0316] The fourth capacitor electrode and the sixth capacitor electrode may be at the same potential as the second source electrode S2, and the fifth capacitor electrode may be at the same potential as the second gate electrode G2. Accordingly, the second upper capacitor Cu2 and the second lower capacitor Cd2 may be connected in parallel. Accordingly, the capacitance of the second storage capacitor Cst2 may increase.

[0317] Hereinafter, a repair structure capable of reducing two welding processes to one welding process and reducing two cutting processes to one cutting process will be described with reference to Figures 22 to 26 FIG.

[0318] Figure 22 is a plan view of a local region 1600 in Figure 14 FIG. Figure 23 is an enlarged plan view of a local region 2200 in Figure 22 FIG. Figure 24 is a cross-sectional view taken along line B-B' of Figure 23 FIG. Figure 25 is a cross-sectional view of a first sub-pixel SP1 and a second sub-pixel SP2 adjacent to each other in a column direction in a display device 100 according to an embodiment of the present disclosure. Figure 26 is Figure 14 a plan view of the local region 1600 in

[0319] Except for differences in the repair structure, Figures 22 to 26 may correspond to Figures 15 to 19 FIG. Figures 22 to 26 Accordingly, when describing with reference to Figures 15 to 19 FIG.

[0320] Reference is made to Figures 22 to 26, before the repair process, the second part PART2 of the overlapping pattern OP may not be electrically connected to the second lower metal LM2, but the first part PART1 of the overlapping pattern OP may be electrically connected to the first lower metal LM1 through the connection pattern CPTN_OP.

[0321] Meanwhile, before the repair process, the first part PART1 of the overlapping pattern OP may not be electrically connected to the first lower metal LM1, but the second part PART2 of the overlapping pattern OP may be electrically connected to the second lower metal LM2 through the connection pattern CPTN_OP.

[0322] That is, the repair structure according to an embodiment of the present disclosure may further include a connection pattern CPTN_OP that connects the first part PART1 of the overlapping pattern OP and the first lower metal LM1 or connects the second part PART2 of the overlapping pattern OP and the second lower metal LM2.

[0323] The connection pattern CPTN_OP may include the same material as the first source electrode S1 and the second source electrode S2, and may be disposed in the layer where the first source electrode S1 and the second source electrode S2 are disposed.

[0324] Reference Figures 22 to 26 , before the repair process, the overlapping pattern OP may not be connected to an adjacent common power supply line (e.g., a driving voltage line (DVL), a reference voltage line RVL).

[0325] Reference Figures 22 to 26 , if a defect is identified in the second sub-pixel circuit SPC2 among the first sub-pixel circuit SPC1 and the second sub-pixel circuit SPC2, only one soldering process and one cutting process are required to perform the repair process to normalize the second sub-pixel circuit SPC2.

[0326] The first soldering process may be a soldering process that electrically connects an end of the overlapping pattern OP that is not connected to the connection pattern CPTN_OP to the corresponding lower metal. That is, through one soldering process, a soldering pattern WPTN may be formed between an end of the overlapping pattern OP that is not connected to the connection pattern CPTN_OP and the corresponding lower metal.

[0327] For example, the second part PART2 of the overlapping pattern OP may be electrically connected to the second lower metal LM2 through one soldering process. That is, through one soldering process, a soldering pattern WPTN may be formed between the second part PART2 of the overlapping pattern OP and the second lower metal LM2.

[0328] The first cutting process may be a cutting process (e.g., a second cutting) for disabling the second sub-pixel circuit SPC2. For example, as Figure 26As shown, the connection between the second driving transistor DRT2 in the second sub-pixel circuit SPC2 and the driving voltage line DVL can be disconnected through a cutting process.

[0329] Figure 27 Illustrated is the current supply situation after a repair process when a defect occurs in the second sub-pixel SP2 among the first sub-pixel to the fourth sub-pixel arranged in the column direction in the display panel 110 according to an embodiment of the present disclosure. Figure 28 Illustrated is the current supply situation after a repair process when a defect occurs in the first sub-pixel SP1 among the first sub-pixel to the fourth sub-pixel arranged in the column direction in the display panel 110 according to an embodiment of the present disclosure.

[0330] Reference Figure 27 and Figure 28 , an example of the arrangement of the first sub-pixel SP1 to the fourth sub-pixel SP4 in the column direction is illustrated.

[0331] Reference Figure 27 and Figure 28 , the first sub-pixel SP1 may include the first pixel electrode PE1 of the first light-emitting device ED1 in the first sub-pixel circuit SPC1 and the first source electrode S1 of the first driving transistor DRT1. The second sub-pixel SP2 may include the second pixel electrode PE2 of the second light-emitting device ED2 in the second sub-pixel circuit SPC2 and the second source electrode S2 of the second driving transistor DRT2. The third sub-pixel SP3 may include the third pixel electrode PE3 of the third light-emitting device ED3 in the third sub-pixel circuit SPC3 and the third source electrode S3 of the third driving transistor DRT3. The fourth sub-pixel SP4 may include the fourth pixel electrode PE4 of the fourth light-emitting device ED4 in the fourth sub-pixel circuit SPC4 and the fourth source electrode S4 of the fourth driving transistor DRT4.

[0332] The first pixel electrode PE1 to the fourth pixel electrode PE4 may be electrically connected to the first source electrode S1 to the fourth source electrode S4 through contact holes CNT in an insulating layer (e.g., outer coating OC, passivation layer PAS).

[0333] Reference Figure 27 and Figure 28 , the first sub-pixel SP1 and the second sub-pixel SP2 may have a vertically symmetric structure and may be a set for repair processing, and the third sub-pixel SP3 and the fourth sub-pixel SP4 may have a vertically symmetric structure and may be a set for repair processing.

[0334] Reference Figure 27 and Figure 28, according to the vertical symmetry structure of the first sub-pixel SP1 and the second sub-pixel SP2, the first sub-pixel circuit SPC1 and the second sub-pixel circuit SPC2 can be arranged adjacent to each other. According to the vertical symmetry structure of the third sub-pixel SP3 and the fourth sub-pixel SP4, the third sub-pixel circuit SPC3 and the fourth sub-pixel circuit SPC4 can be arranged adjacent to each other. According to this vertical symmetry structure, the second light-emitting device ED2 and the third light-emitting device ED3 can be arranged adjacent to each other.

[0335] Reference Figure 27 and Figure 28 , the repair structure for the first sub-pixel SP1 and the second sub-pixel SP2 may include a first lower metal connected to the first source electrode S1, a second lower metal connected to the second source electrode S2, and an overlapping pattern OP that overlaps at least a part of the first lower metal and at least a part of the second lower metal.

[0336] Reference Figure 27 and Figure 28 , the repair structure for the third sub-pixel SP3 and the fourth sub-pixel SP4 may include a third lower metal connected to the third source electrode S3, a fourth lower metal connected to the fourth source electrode S4, and an overlapping pattern OP that overlaps at least a part of the third lower metal and at least a part of the fourth lower metal.

[0337] Reference Figure 27 , if a defect occurs in the second sub-pixel circuit SPC2, the first lower metal connected to the first source electrode S1 and the second lower metal connected to the second source electrode S2 can be connected to the overlapping pattern OP through a repair process to normalize the second sub-pixel SP2. Therefore, a first welding pattern WPTN1 can be formed between the overlapping pattern OP and the first lower metal, and a second welding pattern WPTN2 can be formed between the overlapping pattern OP and the second lower metal.

[0338] In addition, the second sub-pixel circuit SPC2 can be disabled through a repair process to normalize the second sub-pixel SP2.

[0339] Reference Figure 27 , through the repair process of normalizing the second sub-pixel SP2, the first current I1 output from the first source electrode S1 of the first driving transistor DRT1 in the normal first sub-pixel circuit SPC1 can be provided to the first pixel electrode PE1 and the second pixel electrode PE2. Therefore, the second light-emitting device ED2 can emit light normally.

[0340] Reference Figure 28, if a defect occurs in the first sub-pixel circuit SPC1, the first lower metal connected to the first source electrode S1 and the second lower metal connected to the second source electrode S2 can be connected to the overlapping pattern OP through a repair process to normalize the first sub-pixel SP1. Therefore, a first welding pattern WPTN1 can be formed between the overlapping pattern OP and the first lower metal, and a second welding pattern WPTN2 can be formed between the overlapping pattern OP and the second lower metal.

[0341] In addition, the first sub-pixel circuit SPC1 can be disabled through a repair process to normalize the first sub-pixel SP1.

[0342] Reference Figure 28 , through the repair process of normalizing the first sub-pixel SP1, the second current I2 output from the second source electrode S2 of the second driving transistor DRT2 in the normal second sub-pixel circuit SPC2 can be supplied to the second pixel electrode PE2 and the first pixel electrode PE1. Therefore, the first light-emitting device ED1 can emit light normally.

[0343] Embodiments of the above-described present disclosure will be briefly described below.

[0344] A display device according to an embodiment of the present disclosure may include: a first lower metal directly connected to a first pixel electrode or a first source electrode in a first sub-pixel and overlapping with a first active layer; a second lower metal directly connected to a second pixel electrode or a second source electrode in a second sub-pixel and overlapping with a second active layer; and an overlapping pattern, wherein one side of the overlapping pattern overlaps at least a part of the first lower metal, and the other side of the overlapping pattern overlaps at least a part of the second lower metal.

[0345] A display device according to an embodiment of the present disclosure may include: a first driving transistor including a first active layer, a first drain electrode, and a first gate electrode; a first pixel electrode directly connected to a part of the first active layer or electrically connected to a part of the first active layer through an additional first source electrode; a second driving transistor including a second active layer, a second drain electrode, and a second gate electrode; a second pixel electrode directly connected to a part of the second active layer or electrically connected to a part of the second active layer through an additional second source electrode; a first lower metal directly connected to the first pixel electrode or directly connected to the first source electrode and overlapping with the first active layer; a second lower metal directly connected to the second pixel electrode or directly connected to the second source electrode and overlapping with the second active layer; a first buffer layer disposed on the first lower metal and the second lower metal; an overlapping pattern disposed on the first buffer layer and including a first part overlapping at least a part of the first lower metal, a second part overlapping at least a part of the second lower metal, and a third part between the first part and the second part; and a second buffer layer disposed on the overlapping pattern and disposed below the first active layer and the second active layer.

[0346] The distance between the first source electrode and the second source electrode may be less than the distance between a first emission region formed by the first pixel electrode and a second emission region formed by the second pixel electrode.

[0347] A display device according to an embodiment of the present disclosure may further include a gate insulating layer disposed on the first active layer and the second active layer.

[0348] The first source electrode may be disposed on the gate insulating layer and may be connected to the first lower metal through a hole in the gate insulating layer, the second buffer layer, and the first buffer layer.

[0349] The second source electrode may be disposed on the gate insulating layer and may be connected to the second lower metal through a hole in the gate insulating layer, the second buffer layer, and the first buffer layer.

[0350] A display device according to an embodiment of the present disclosure may further include: a passivation layer disposed on the first source electrode, the first gate electrode, the second source electrode, and the second gate electrode; and an outer coating layer disposed on the passivation layer.

[0351] The first pixel electrode may be disposed on the outer coating layer and may be connected to the first source electrode through a hole in the outer coating layer and the passivation layer. The second pixel electrode may be disposed on the outer coating layer and may be connected to the second source electrode through a hole in the outer coating layer and the passivation layer.

[0352] The first gate electrode may be disposed on the first active layer, and the second gate electrode may be disposed on the second active layer.

[0353] The first source electrode and the second source electrode may include the same electrode material as that included in the first gate electrode and the second gate electrode.

[0354] The display device according to an embodiment of the present disclosure may further include a first storage capacitor formed between the first source electrode and the first gate electrode, and a second storage capacitor formed between the second source electrode and the second gate electrode, as an example of a storage capacitor structure.

[0355] The first storage capacitor may include a first upper capacitor and a first lower capacitor. The first upper capacitor and the first lower capacitor may be connected in parallel to form the first storage capacitor.

[0356] The second storage capacitor may include a second upper capacitor and a second lower capacitor. The second upper capacitor and the second lower capacitor may be connected in parallel to form the second storage capacitor.

[0357] The first upper capacitor may include a first capacitor electrode corresponding to the first source electrode and a second capacitor electrode including the same material as the first active layer.

[0358] The first lower capacitor may include a third capacitor electrode including the same material as the overlapping pattern and a fourth capacitor electrode corresponding to the first lower metal.

[0359] The second upper capacitor may include a fifth capacitor electrode corresponding to the second source electrode and a sixth capacitor electrode including the same material as the second active layer.

[0360] The second lower capacitor may include a seventh capacitor electrode including the same material as the overlapping pattern and an eighth capacitor electrode corresponding to the second lower metal.

[0361] The display device according to an embodiment of the present disclosure may further include a first storage capacitor formed between the first pixel electrode and the first gate electrode, and a second storage capacitor formed between the second pixel electrode and the second gate electrode, as another example of a storage capacitor structure.

[0362] The first storage capacitor may include a first upper capacitor and a first lower capacitor, and the second storage capacitor may include a second upper capacitor and a second lower capacitor.

[0363] The first upper capacitor and the first lower capacitor may be connected in parallel to form the first storage capacitor.

[0364] The first upper capacitor may include: a first capacitor electrode including the same material as the first active layer, and a second capacitor electrode including the same material as the overlapping pattern.

[0365] The first lower capacitor may include the second capacitor electrode and a third capacitor electrode corresponding to the first lower metal.

[0366] The second upper capacitor and the second lower capacitor may be connected in parallel to form a second storage capacitor.

[0367] The second upper capacitor may include: a fourth capacitor electrode including the same material as the second active layer, and a fifth capacitor electrode including the same material as the overlapping pattern.

[0368] The second lower capacitor may include the fifth capacitor electrode and a sixth capacitor electrode corresponding to the first lower metal.

[0369] When a first current is provided from the first driving transistor to the first pixel electrode and a second current is provided from the second driving transistor to the second pixel electrode (e.g., when it is recognized that both the first sub-pixel and the second sub-pixel are normal sub-pixels and no repair process is performed), the first part and the first lower metal may be spaced apart, or the second part and the second lower metal may be spaced apart.

[0370] When a first current is provided from the first driving transistor to the first pixel electrode and a second current is provided from the second driving transistor to the second pixel electrode, at least one of the first lower metal and the second lower metal may be electrically isolated from the overlapping pattern.

[0371] The display device according to an embodiment of the present disclosure may further include a connection pattern connecting the first part and the first lower metal or connecting the second part and the second lower metal. Here, the connection pattern may include the same material as the first source electrode and the second source electrode.

[0372] When a first current is provided from the first driving transistor to the first pixel electrode and the second pixel electrode, the first part and the first lower metal may be connected, and the second part and the second lower metal may be connected.

[0373] The display device according to an embodiment of the present disclosure may further include a driving voltage line for transmitting a driving voltage to the first drain electrode and the second drain electrode.

[0374] When a first current is provided from the first driving transistor to the first pixel electrode and a second current is provided from the second driving transistor to the second pixel electrode, at least one of the two ends of the overlapping pattern may be connected to the driving voltage line.

[0375] When a first current is supplied from the first driving transistor to the first pixel electrode and the second pixel electrode (e.g., when it is recognized that the first sub-pixel is a normal sub-pixel and the second sub-pixel is a defective sub-pixel and a repair process has been performed), both ends of the overlapping pattern can be electrically disconnected from the driving voltage line.

[0376] When a first current is supplied from the first driving transistor to the first pixel electrode and a second current is supplied from the second driving transistor to the second pixel electrode, the driving voltage line and the first drain electrode can be electrically connected, and the driving voltage line and the second drain electrode can be electrically connected.

[0377] When a first current is supplied from the first driving transistor to the first pixel electrode and the second pixel electrode, the driving voltage line and the first drain electrode can be electrically connected, and the driving voltage line and the second drain electrode can be electrically disconnected.

[0378] The display device according to an embodiment of the present disclosure may further include a data line for transmitting a data voltage, a first scanning transistor for controlling the connection between the data line and the first gate electrode, and a second scanning transistor for controlling the connection between the data line and the second gate electrode.

[0379] When a first current is supplied from the first driving transistor to the first pixel electrode and a second current is supplied from the second driving transistor to the second pixel electrode, the data line and the first scanning transistor can be connected, and the data line and the second scanning transistor can be connected.

[0380] When a first current is supplied from the first driving transistor to the first pixel electrode and the second pixel electrode, the data line and the first scanning transistor can be connected, and the data line and the second scanning transistor can be disconnected.

[0381] The display device according to an embodiment of the present disclosure may further include a reference voltage line for transmitting a reference voltage, a first sensing transistor for controlling the connection between the reference voltage line and the first source electrode, and a second sensing transistor for controlling the connection between the reference voltage line and the second source electrode.

[0382] When a first current is supplied from the first driving transistor to the first pixel electrode and a second current is supplied from the second driving transistor to the second pixel electrode, the reference voltage line and the first sensing transistor can be connected, and the reference voltage line and the second sensing transistor can be connected.

[0383] When a first current is supplied from the first driving transistor to the first pixel electrode and the second pixel electrode, the reference voltage line and the first sensing transistor can be connected, and the reference voltage line and the second sensing transistor can be disconnected.

[0384] A display device according to an embodiment of the present disclosure may include: a first sub-pixel including a first driving transistor and a first light-emitting device; a second sub-pixel including a second driving transistor and a second light-emitting device; a first lower metal connected to a first source electrode of the first driving transistor; a second lower metal connected to a second source electrode of the second driving transistor; an overlapping pattern including a first portion overlapping a part of the first lower metal, a second portion overlapping a part of the second lower metal, and a third portion between the first portion and the second portion; and a first buffer layer disposed between the first lower metal and the second lower metal and the overlapping pattern.

[0385] The first lower metal may be disposed under a first active layer of the first driving transistor, the second lower metal may be disposed under a second active layer of the second driving transistor, and the overlapping pattern may be disposed under the first lower metal and the second lower metal.

[0386] When a first current is provided from the first driving transistor to a first pixel electrode and a second current is provided from the second driving transistor to a second pixel electrode, the first portion and the first lower metal may be spaced apart, or the second portion and the second lower metal may be spaced apart.

[0387] When a first current is provided from the first driving transistor to the first pixel electrode and the second pixel electrode, the first portion and the first lower metal may be connected, and the second portion and the second lower metal may be connected.

[0388] The distance between the first source electrode and the second source electrode may be less than the distance between a first emission region of the first light-emitting device and a second emission region of the second light-emitting device.

[0389] When a first current is provided from the first driving transistor to the first pixel electrode and a second current is provided from the second driving transistor to the second pixel electrode, the overlapping pattern may be electrically connected to a common power line.

[0390] When a first current is provided from the first driving transistor to the first pixel electrode and the second pixel electrode, the overlapping pattern may be electrically disconnected from the common power line.

[0391] A display panel according to an embodiment of the present disclosure may include: a first sub-pixel including a first sub-pixel circuit and a first light-emitting device; a second sub-pixel including a second sub-pixel circuit and a second light-emitting device; a first lower metal connected to the first sub-pixel circuit; a second lower metal connected to the second sub-pixel circuit; an overlapping pattern including a first portion overlapping a part of the first lower metal, a second portion overlapping a part of the second lower metal, and a third portion between the first portion and the second portion; and a first buffer layer disposed between the first lower metal, the second lower metal, and the overlapping pattern.

[0392] When a first current is provided from the first sub-pixel circuit to the first light-emitting device and a second current is provided from the second sub-pixel circuit to the second light-emitting device, the first portion and the first lower metal may be spaced apart, or the second portion and the second lower metal may be spaced apart.

[0393] When a first current is provided from the first sub-pixel circuit to the first light-emitting device and the second light-emitting device, the first portion and the first lower metal may be connected, and the second portion and the second lower metal may be connected.

[0394] The distance between the first sub-pixel circuit and the second sub-pixel circuit is less than the distance between the first emission region of the first light-emitting device and the second emission region of the second light-emitting device.

[0395] The display panel according to an embodiment of the present disclosure may further include a common power supply line adjacent to the overlapping pattern. For example, the common power supply line may include at least one of a driving voltage line, a reference voltage line, and a reference voltage line. For example, the common power supply line may be a constant voltage line whose voltage level does not change over time.

[0396] When a first current is provided from the first sub-pixel circuit to the first light-emitting device and a second current is provided from the second sub-pixel circuit to the second light-emitting device, the overlapping pattern may be electrically connected to the common power supply line.

[0397] When a first current is provided from the first sub-pixel circuit to the first light-emitting device and the second light-emitting device, the overlapping pattern may be electrically disconnected from the common power supply line.

[0398] The display panel according to an embodiment of the present disclosure may further include a substrate, a first active layer disposed in the first sub-pixel circuit, and a second active layer disposed in the second sub-pixel circuit.

[0399] The first lower metal may be disposed below the first active layer and overlap with the first active layer. The second lower metal may be disposed below the second active layer and overlap with the second active layer.

[0400] An overlapping pattern may be provided in a metal layer between the first lower metal and the second lower metal and the substrate.

[0401] According to an embodiment of the present disclosure as described above, a display device and a display panel having a repair structure capable of repairing defective sub-pixels can be provided.

[0402] According to an embodiment of the present disclosure, a display device and a display panel having a repair structure that does not cause a reduction in aperture ratio can be provided.

[0403] According to an embodiment of the present disclosure, a display device and a display panel having a repair structure that occupies a small space can be provided.

[0404] According to an embodiment of the present disclosure, a display device and a display panel having a repair structure suitable for a high-resolution implementation can be provided.

[0405] According to an embodiment of the present disclosure, a display device and a display panel having a repair structure with high repair performance or a high probability of repair success can be provided, thereby optimizing the process by reducing production energy consumption.

[0406] The above description and the drawings provide examples of the technical concept of the present disclosure for illustrative purposes only. Various modifications, additions, and substitutions to the described embodiments will be extremely obvious to those skilled in the art without departing from the spirit and scope of the present disclosure. Additionally, the disclosed embodiments are intended to illustrate the scope of the technical concept of the present disclosure. Therefore, the scope of the present disclosure is not limited to the illustrated embodiments.

Claims

1. A display device, comprising: A first driving transistor, the first driving transistor including a first active layer, a first drain electrode, and a first gate electrode; A first pixel electrode, the first pixel electrode being directly connected to a part of the first active layer or being electrically connected to a part of the first active layer through an additional first source electrode; A second driving transistor, the second driving transistor including a second active layer, a second drain electrode, and a second gate electrode; A second pixel electrode, the second pixel electrode being directly connected to a part of the second active layer or being electrically connected to a part of the second active layer through an additional second source electrode; A first lower metal, the first lower metal being directly connected to the first pixel electrode or directly connected to the first source electrode, and the first lower metal overlapping with the first active layer; A second lower metal, the second lower metal being directly connected to the second pixel electrode or directly connected to the second source electrode, and the second lower metal overlapping with the second active layer; A first buffer layer, the first buffer layer being disposed on the first lower metal and the second lower metal; An overlapping pattern, the overlapping pattern being disposed on the first buffer layer, and including a first part overlapping with at least a part of the first lower metal, a second part overlapping with at least a part of the second lower metal, and a third part between the first part and the second part; And A second buffer layer, the second buffer layer being disposed on the overlapping pattern and below the first active layer and the second active layer.

2. The display device according to claim 1, wherein, The distance between the first source electrode and the second source electrode is less than the distance between a first emission region formed by the first pixel electrode and a second emission region formed by the second pixel electrode.

3. The display device according to claim 1, further comprising a gate insulating layer, the gate insulating layer being disposed on the first active layer and the second active layer, Among them, The first source electrode is disposed on the gate insulating layer and is connected to the first lower metal through holes in the gate insulating layer, the second buffer layer, and the first buffer layer, and wherein, the second source electrode is disposed on the gate insulating layer and is connected to the second lower metal through holes in the gate insulating layer, the second buffer layer, and the first buffer layer.

4. The display device according to claim 1, further comprising: A passivation layer, the passivation layer being disposed on the first source electrode, the first gate electrode, the second source electrode, and the second gate electrode; And An outer coating layer, the outer coating layer being disposed on the passivation layer, wherein, the first pixel electrode is disposed on the outer coating layer and is connected to the first source electrode through holes in the outer coating layer and the passivation layer, and wherein, the second pixel electrode is disposed on the outer coating layer and is connected to the second source electrode through holes in the outer coating layer and the passivation layer.

5. The display device according to claim 1, wherein, The first gate electrode is disposed on the first active layer, and the second gate electrode is disposed on the second active layer; And Among them, the first source electrode and the second source electrode include the same electrode material as the electrode materials included in the first gate electrode and the second gate electrode.

6. The display device according to claim 1, further comprising: A first upper capacitor, the first upper capacitor including: a first capacitor electrode corresponding to the first source electrode, and a second capacitor electrode including the same material as the first active layer; A first lower capacitor, the first lower capacitor including: a third capacitor electrode including the same material as the overlapping pattern, and a fourth capacitor electrode corresponding to the first lower metal; A second upper capacitor, the second upper capacitor including: a fifth capacitor electrode corresponding to the second source electrode, and a sixth capacitor electrode including the same material as the second active layer; and A second lower capacitor, the second lower capacitor including: a seventh capacitor electrode including the same material as the overlapping pattern, and an eighth capacitor electrode corresponding to the second lower metal, wherein the first upper capacitor and the first lower capacitor are connected in parallel to form a first storage capacitor, and wherein the second upper capacitor and the second lower capacitor are connected in parallel to form a second storage capacitor.

7. The display device according to claim 1, further comprising: A first upper capacitor, the first upper capacitor including: a first capacitor electrode including the same material as the first active layer, and a second capacitor electrode including the same material as the overlapping pattern; A first lower capacitor, the first lower capacitor including: the second capacitor electrode, and a third capacitor electrode corresponding to the first lower metal; A second upper capacitor, the second upper capacitor including: a fourth capacitor electrode including the same material as the second active layer, and a fifth capacitor electrode including the same material as the overlapping pattern; and A second lower capacitor, the second lower capacitor including the fifth capacitor electrode, and a sixth capacitor electrode corresponding to the first lower metal, wherein the first upper capacitor and the first lower capacitor are connected in parallel to form a first storage capacitor, and wherein the second upper capacitor and the second lower capacitor are connected in parallel to form a second storage capacitor.

8. The display device according to claim 1, wherein, When a first current is provided from the first driving transistor to the first pixel electrode and a second current is provided from the second driving transistor to the second pixel electrode, the first portion and the first lower metal are spaced apart or the second portion and the second lower metal are spaced apart, and at least one of the first lower metal and the second lower metal is electrically isolated from the overlapping pattern.

9. The display device according to claim 8, further comprising: A connection pattern, the connection pattern connecting the first portion and the first lower metal or connecting the second portion and the second lower metal, wherein the connection pattern includes the same material as the first source electrode and the second source electrode.

10. The display device according to claim 1, wherein, When a first current is provided from the first driving transistor to the first pixel electrode and the second pixel electrode, the first portion is connected to the first lower metal, and the second portion is connected to the second lower metal.

11. The display device according to claim 1, further comprising a driving voltage line configured to transmit a driving voltage to the first drain electrode and the second drain electrode, Among them, When a first current is provided from the first driving transistor to the first pixel electrode and a second current is provided from the second driving transistor to the second pixel electrode, at least one end of the overlapping pattern is connected to the driving voltage line.

12. The display device according to claim 1, further comprising a driving voltage line configured to transmit a driving voltage to the first drain electrode and the second drain electrode, Among them, When a first current is provided from the first driving transistor to the first pixel electrode and the second pixel electrode, the end of the overlapping pattern is electrically disconnected from the driving voltage line.

13. The display device according to claim 1, further comprising a driving voltage line configured to transmit a driving voltage to the first drain electrode and the second drain electrode, Among them, When a first current is provided from the first driving transistor to the first pixel electrode and a second current is provided from the second driving transistor to the second pixel electrode, the driving voltage line is electrically connected to the first drain electrode, and the driving voltage line is electrically connected to the second drain electrode, and wherein, when a first current is provided from the first driving transistor to the first pixel electrode and the second pixel electrode, the driving voltage line is electrically connected to the first drain electrode, and the driving voltage line is electrically disconnected from the second drain electrode.

14. The display device according to claim 1, further comprising: a data line configured to transmit a data voltage; a first scanning transistor configured to control the connection between the data line and the first gate electrode; and a second scanning transistor configured to control the connection between the data line and the second gate electrode, wherein, when a first current is provided from the first driving transistor to the first pixel electrode and a second current is provided from the second driving transistor to the second pixel electrode, the data line is connected to the first scanning transistor, and the data line is connected to the second scanning transistor, and wherein, when a first current is provided from the first driving transistor to the first pixel electrode and the second pixel electrode, the data line is connected to the first scanning transistor, and the data line is disconnected from the second scanning transistor.

15. The display device according to claim 1, further comprising: a reference voltage line configured to transmit a reference voltage; a first sensing transistor configured to control the connection between the reference voltage line and the first source electrode; and a second sensing transistor configured to control the connection between the reference voltage line and the second source electrode, Wherein, when a first current is provided from the first driving transistor to the first pixel electrode and a second current is provided from the second driving transistor to the second pixel electrode, the reference voltage line is connected to the first sensing transistor, and the reference voltage line is connected to the second sensing transistor, and Wherein, when a first current is provided from the first driving transistor to the first pixel electrode and the second pixel electrode, the reference voltage line is connected to the first sensing transistor, and the reference voltage line is disconnected from the second sensing transistor.

16. A display panel, comprising: A first sub-pixel, the first sub-pixel including a first sub-pixel circuit and a first light-emitting device; A second sub-pixel, the second sub-pixel including a second sub-pixel circuit and a second light-emitting device; A first lower metal, the first lower metal being connected to the first sub-pixel circuit; A second lower metal, the second lower metal being connected to the second sub-pixel circuit; An overlapping pattern, the overlapping pattern including a first part overlapping a part of the first lower metal, a second part overlapping a part of the second lower metal, and a third part between the first part and the second part; And A first buffer layer, the first buffer layer being disposed between the first lower metal, the second lower metal and the overlapping pattern.

17. The display panel according to claim 16, further comprising: A substrate; A first active layer, the first active layer being disposed within the first sub-pixel circuit; And A second active layer, the second active layer being disposed within the second sub-pixel circuit, Wherein, the first lower metal is disposed below the first active layer and overlaps with the first active layer, Wherein, the second lower metal is disposed below the second active layer and overlaps with the second active layer, and Wherein, the overlapping pattern is disposed in a metal layer between the first lower metal and the second lower metal and the substrate.

18. The display panel according to claim 16, wherein, The distance between the first sub-pixel circuit and the second sub-pixel circuit is less than the distance between the first emission region of the first light-emitting device and the second emission region of the second light-emitting device.

19. The display panel according to claim 16, wherein, When a first current is provided from the first sub-pixel circuit to the first light-emitting device and a second current is provided from the second sub-pixel circuit to the second light-emitting device, the first part and the first lower metal are spaced apart, or the second part and the second lower metal are spaced apart, and Wherein, when a first current is provided from the first sub-pixel circuit to the first light-emitting device and the second light-emitting device, the first part and the first lower metal are connected, and the second part and the second lower metal are connected.

20. The display panel according to claim 16, further comprising a common power supply line adjacent to the overlapping pattern, Among them, When a first current is provided from the first sub-pixel circuit to the first light-emitting device and a second current is provided from the second sub-pixel circuit to the second light-emitting device, the overlapping pattern is electrically connected to the common power supply line. Wherein, when a first current is supplied from the first sub-pixel circuit to the first light-emitting device and the second light-emitting device, the overlapping pattern is electrically disconnected from the common power supply line.

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