Display device and method of providing display device

Abstract

The invention relates to a display device and a method of providing the same. A display device includes a substrate including a display area including an emission area and a non-emission area, and a non-display area adjacent to the display area. The non-emission region includes a pixel defining layer, and first and second bank structures each including a first bank layer including a side surface facing the emission region and a second bank layer on the first bank layer and including a tip protruding beyond the side surface of the first bank layer. The emission region includes a light emitting layer in contact with a side surface of the first bank layer, a cathode electrode on the light emitting layer and in contact with the side surface of the first bank layer, and an auxiliary electrode on the cathode electrode and in contact with the side surface of the first bank layer and a tip of the second bank layer, and a first encapsulation layer on the second bank structure and the auxiliary electrode.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2024-0006643, filed on January 16, 2024, the entire content of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device and a method of providing (or manufacturing) a display device. Background Art

[0004] With the development of an information-oriented society, more and more requirements have been put forward for display devices for displaying images in various ways. For example, display devices are used in various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs. The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, and an organic light emitting display device. Among flat panel display devices, in a light emitting display device, since each of a plurality of pixels of a display panel includes a light emitting element capable of self-emitting light, an image can be displayed without a backlight unit providing light to the display panel.

[0005] With the development of various electronic devices, the demand for high-resolution display devices is increasing. Since a high-resolution display device requires a high pixel integration density, the interval between light emitting elements overlapping each emission region may become narrow. Therefore, a high-resolution display device can be formed by a patterning process for forming a single pixel rather than a mask process. Summary of the Invention

[0006] Aspects of the present disclosure provide a high-resolution display device by forming (or providing) a light emitting element via a light patterning process without a mask, and also provide a display device in which moisture penetration defects caused by moisture and oxygen are solved.

[0007] However, aspects of the present disclosure are not limited to one aspect set forth herein. By referring to the detailed description of the present disclosure provided later, the above aspects and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains.

[0008] However, the effects according to embodiments of the present disclosure are not limited to those exemplified above, and various other effects are also included herein.

[0009] In an embodiment of the present disclosure, a display device may include: a substrate including a display area including an emission area and a non-emission area, and a non-display area adjacent to the display area; the non-emission area includes: a pixel definition layer; a first bank structure on the pixel definition layer, the first bank structure including a first bank layer and a second bank layer, the first bank layer including a side surface facing the emission area, the second bank layer on the first bank layer and including a first tip protruding from the side surface of the first bank layer; and a second bank structure on the first bank structure, the second bank structure including a third bank layer and a fourth bank layer, the third bank layer including a side surface facing the emission area, the fourth bank layer on the third bank layer and including a second tip protruding from the side surface of the third bank layer; the emission area includes: a light-emitting layer of a light-emitting element in contact with the side surface of the first bank layer; a cathode electrode of the light-emitting element on the light-emitting layer and in contact with the side surface of the first bank layer; and an auxiliary electrode on the cathode electrode and in contact with the side surface of the first bank layer and the first tip of the second bank layer; and a first encapsulation layer on the second bank structure and the auxiliary electrode.

[0010] In an embodiment, the display device may further include: an organic layer including a light-emitting layer and an organic pattern on the first tip and disconnected from the light-emitting layer; a cathode electrode layer including a cathode electrode and an electrode pattern on the organic pattern and disconnected from the cathode electrode; and an auxiliary electrode layer including an auxiliary electrode and an auxiliary electrode pattern on the electrode pattern and disconnected from the auxiliary electrode.

[0011] In an embodiment, along the first tip: the electrode pattern may completely cover the organic pattern, and the auxiliary electrode pattern may completely cover the electrode pattern.

[0012] In an embodiment, within the first bank structure: the second bank layer may include a side surface facing the emission area, and the side surface of the second bank layer may include a first portion in contact with the organic pattern, a second portion in contact with the electrode pattern, and a third portion in contact with the auxiliary electrode pattern.

[0013] In an embodiment, along the side surface of the second bank layer, the second portion may be between the first portion and the third portion.

[0014] In an embodiment, the organic pattern, the electrode pattern, and the auxiliary electrode pattern may overlap each other along the thickness direction of the substrate.

[0015] In an embodiment, within the first bank structure: the second bank layer may include a first surface facing the first bank layer, the first surface of the second bank layer may include a first portion in contact with the first bank layer, a second portion in contact with the auxiliary electrode, and a third portion in contact with the first encapsulation layer, and the second portion may be between the first portion and the third portion.

[0016] In an embodiment, the first surface of the second bank layer may be completely covered by the first bank layer, the auxiliary electrode, and the first encapsulation layer.

[0017] In an embodiment, within the second dike structure: the fourth dike layer may include a side surface facing the emission region and an upper surface positioned in a direction opposite to the direction in which the third dike layer is positioned, and the side surface of the fourth dike layer may be in complete contact with the first encapsulation layer.

[0018] In an embodiment, the display device may further include a second encapsulation layer on the first encapsulation layer, wherein the upper surface of the fourth dike layer and the first encapsulation layer may be spaced apart from each other and a gap is located between the upper surface of the fourth dike layer and the first encapsulation layer, and the second encapsulation layer may extend into the gap between the upper surface of the fourth dike layer and the first encapsulation layer.

[0019] In an embodiment, the upper surface of the fourth dike layer may be in complete contact with the second encapsulation layer.

[0020] In an embodiment, the first encapsulation layer may extend from the emission region to overlap a portion of the upper surface of the fourth dike layer adjacent to the emission region.

[0021] In an embodiment, the display device may further include a residual pattern in the emission region and overlapping the first tip and the second tip, wherein, within the emission region: the anode electrode of the light-emitting element and the pixel defining layer may be spaced apart from each other and a gap is located between the anode electrode of the light-emitting element and the pixel defining layer, and the residual pattern may be in the gap between the anode electrode and the pixel defining layer.

[0022] In an embodiment, the residual pattern may overlap with the organic pattern, the electrode pattern, and the auxiliary electrode pattern.

[0023] In an embodiment, the display device may further include a third dike structure between the first dike structure and the second dike structure along the thickness direction of the substrate, wherein the third dike structure may include a fifth dike layer and a sixth dike layer, the fifth dike layer includes a side surface facing the emission region, the sixth dike layer is on the fifth dike layer and includes a third tip protruding from the side surface of the fifth dike layer, and the organic pattern, the electrode pattern, and the auxiliary electrode pattern may also be on the third tip.

[0024] In an embodiment, the organic pattern, the electrode pattern, and the auxiliary electrode pattern on the first tip and the organic pattern, the electrode pattern, and the auxiliary electrode pattern on the third tip may overlap each other along the thickness direction of the substrate.

[0025] In an embodiment, the first encapsulation layer may completely cover the first tip, the second tip, and the third tip, and the side surfaces of the third dike layer and the fifth dike layer may be in contact with the first encapsulation layer.

[0026] In an embodiment, the display device may further include a fourth bank structure between the second bank structure and the third bank structure along the thickness direction of the substrate. The fourth bank structure may include a seventh bank layer and an eighth bank layer. The seventh bank layer includes a side surface facing the emission region. The eighth bank layer is on the seventh bank layer and includes a fourth tip protruding from the side surface of the seventh bank layer. The organic pattern, the electrode pattern, and the auxiliary electrode pattern may also be on the fourth tip.

[0027] In an embodiment, along the thickness direction of the substrate, the height of the first bank layer may be greater than the height of the second bank layer.

[0028] In an embodiment of the present disclosure, a method of providing a display device may include: providing a substrate including a display area including an emission area and a non-emission area, and a non-display area adjacent to the display area; and performing the following steps in the display area: in the emission area, providing an anode electrode of a light-emitting element and a sacrificial layer on the anode electrode; providing a pixel defining layer on the sacrificial layer and on the non-emission area of the substrate; providing a bank structure including a first bank layer, a second bank layer, a third bank layer, a fourth bank layer, a fifth bank layer, a sixth bank layer, a seventh bank layer, and an eighth bank layer sequentially stacked on the pixel defining layer; providing a photoresist pattern on the eighth bank layer to expose an area of the bank structure overlapping with the anode electrode; at an area of the bank structure, removing the bank structure and the pixel defining layer by a first etching process using the photoresist pattern, the first etching process including: forming holes in the bank structure and the pixel defining layer corresponding to the emission area, the holes exposing the sacrificial layer to the outside of the bank structure and the pixel defining layer; and forming side surfaces of the first bank layer, the second bank layer, the third bank layer, the fourth bank layer, the fifth bank layer, the sixth bank layer, the seventh bank layer, and the eighth bank layer exposed to the holes; in the holes, performing a second etching process to remove a portion of the sacrificial layer exposed by the holes, while providing a first tip of the second bank layer protruding from a side surface of the first bank layer, a second tip of the fourth bank layer protruding from a side surface of the third bank layer, a third tip of the sixth bank layer protruding from a side surface of the fifth bank layer, and a fourth tip of the eighth bank layer protruding from a side surface of the seventh bank layer; sequentially providing an organic layer, a cathode electrode layer, an auxiliary electrode layer, and a first encapsulation layer on the anode electrode and on the eighth bank layer to form: an organic layer including a light-emitting layer on the anode electrode and an organic pattern on the first tip and disconnected from the light-emitting layer; a cathode electrode layer including a cathode electrode on the light-emitting layer and an electrode pattern on the organic pattern and disconnected from the cathode electrode; and an auxiliary electrode layer including an auxiliary electrode on the cathode electrode and an auxiliary electrode pattern on the electrode pattern and disconnected from the auxiliary electrode, and wherein the auxiliary electrode contacts a side surface of the first bank layer and the first tip of the second bank layer; providing a mask pattern on the first encapsulation layer, the mask pattern overlapping with the holes and an area of the bank structure adjacent to the holes; and removing portions of each of the organic layer, the cathode electrode layer, the auxiliary electrode layer, and the first encapsulation layer except for areas overlapping with the mask pattern by a third etching process, the third etching process including: forming a light-emitting element including the anode electrode, the light-emitting layer, and the cathode electrode; maintaining the organic pattern, the electrode pattern, and the auxiliary electrode pattern on each of the first tip, the second tip, and the third tip; and forming a cavity between the first encapsulation layer and a top surface of the eighth bank layer, the cavity exposing the top surface of the eighth bank layer to the outside of the first encapsulation layer.

[0029] In an embodiment of the present disclosure, a display device includes: a substrate including a display area including an emission area and a non-emission area, and a non-display area adjacent to the display area. The non-emission area includes: a pixel defining layer located on the non-emission area of the substrate; a first bank structure located on the pixel defining layer, and the first bank structure includes a first bank layer and a second bank layer on the first bank layer and having a first tip, and the first tip protrudes toward the emission area beyond a side surface of the first bank layer facing the emission area; a second bank structure located on the first bank structure, and the second bank structure includes a third bank layer and a fourth bank layer on the third bank layer and having a second tip, and the second tip protrudes toward the emission area beyond a side surface of the third bank layer facing the emission area. The emission area includes: a light-emitting layer located on the emission area of the substrate, and the light-emitting layer is in contact with the side surface of the first bank layer; a cathode electrode located on the light-emitting layer, and the cathode electrode is in contact with the side surface of the first bank layer; an auxiliary electrode located on the cathode electrode, and the auxiliary electrode is in contact with the side surface of the first bank layer and the first tip of the second bank layer; and a first encapsulation layer on the second bank structure and the auxiliary electrode.

[0030] In an embodiment, the display device may further include: an organic pattern located on the first tip, the organic pattern includes the same material as the light-emitting layer, and the organic pattern is spaced apart from the light-emitting layer; an electrode pattern located on the organic pattern, the electrode pattern includes the same material as the cathode electrode, and the electrode pattern is spaced apart from the cathode electrode; and an auxiliary electrode pattern located on the electrode pattern, the auxiliary electrode pattern includes the same material as the auxiliary electrode, and the auxiliary electrode pattern is spaced apart from the auxiliary electrode.

[0031] In an embodiment, the electrode pattern may completely cover the organic pattern, and the auxiliary electrode pattern completely covers the electrode pattern.

[0032] In an embodiment, the second bank layer may have a side surface facing the emission area, and the side surface of the second bank layer includes a first portion in contact with the organic pattern, a second portion in contact with the electrode pattern, and a third portion in contact with the auxiliary electrode pattern.

[0033] In an embodiment, the second portion may be located between the first portion and the third portion.

[0034] In an embodiment, the organic pattern, the electrode pattern, and the auxiliary electrode pattern may overlap in a direction perpendicular to the second tip and the substrate (the thickness direction of the substrate).

[0035] In an embodiment, within the first bank structure, the second bank layer may have a first surface facing the first bank layer, and the first surface includes a first portion in contact with the first bank layer, a second portion in contact with the auxiliary electrode, and a third portion in contact with the first encapsulation layer, and the second portion is located between the first portion and the third portion.

[0036] In an embodiment, the first surface of the second dam layer may be completely covered by the first dam layer, the auxiliary electrode, and the first encapsulation layer.

[0037] In an embodiment, within the second dam structure, the fourth dam layer may have a side surface facing the emission region and a first surface (upper surface) positioned in a direction opposite to the direction in which the third dam layer is positioned, and the side surface of the fourth dam layer is in complete contact with the first encapsulation layer.

[0038] In an embodiment, the display device may further include a second encapsulation layer positioned on the first encapsulation layer, wherein the first surface of the fourth dam layer and the first encapsulation layer are spaced apart from each other in a direction perpendicular to the substrate and the second encapsulation layer is interposed between the first surface of the fourth dam layer and the first encapsulation layer.

[0039] In an embodiment, the first surface of the fourth dam layer may be in complete contact with the second encapsulation layer.

[0040] In an embodiment, a portion of the first surface of the fourth dam layer may be covered by the first encapsulation layer.

[0041] In an embodiment, the display device may further include a residual pattern in the emission region, and the residual pattern is positioned between the substrate and the pixel defining layer in a direction perpendicular to the substrate, wherein the residual pattern may overlap with the first tip and the second tip in a direction perpendicular to the substrate.

[0042] In an embodiment, the residual pattern may overlap with the organic pattern, the electrode pattern, and the auxiliary electrode pattern in a direction perpendicular to the substrate.

[0043] In an embodiment, the display device may further include a third dam structure positioned between the first dam structure and the second dam structure, wherein the third dam structure includes a fifth dam layer and a sixth dam layer having a third tip on the fifth dam layer, the third tip protruding toward the emission region beyond the side surface of the fifth dam layer facing the emission region, and the organic pattern, the electrode pattern, and the auxiliary electrode pattern are positioned on the third tip.

[0044] In an embodiment, the organic pattern, the electrode pattern, and the auxiliary electrode pattern positioned on the first tip and the organic pattern, the electrode pattern, and the auxiliary electrode pattern positioned on the third tip may overlap in a direction perpendicular to the substrate.

[0045] In an embodiment, the first encapsulation layer may completely cover the first tip, the second tip, and the third tip, and the side surfaces of the third dam layer and the fifth dam layer are in contact with the first encapsulation layer.

[0046] In an embodiment, the display device may further include a fourth bank structure located between the second bank structure and the third bank structure, where the fourth bank structure includes a seventh bank layer and an eighth bank layer on the seventh bank layer and having a fourth tip, the fourth tip protruding toward the emission region beyond a side surface of the seventh bank layer facing the emission region, and an organic pattern, an electrode pattern, and an auxiliary electrode pattern are located on the fourth tip.

[0047] In an embodiment, the height of the first bank layer may be greater than the height of the second bank layer.

[0048] In an embodiment of the present disclosure, a method of manufacturing (providing) a display device includes: forming a substrate including a display region including an emission region and a non-emission region, and a non-display region adjacent to the display region; and performing the following steps in the display region: forming an anode electrode in the emission region and a sacrificial layer on the anode electrode, and then forming a pixel defining layer completely covering the sacrificial layer and the substrate, and a bank structure including first, second, third, fourth, fifth, sixth, seventh, and eighth bank layers sequentially stacked, in the non-emission region; forming a photoresist (photoresist pattern) on the eighth bank layer to expose a portion of the bank structure overlapping with the anode electrode; partially removing the pixel defining layer and the bank structure by a first etching process to form a hole exposing the sacrificial layer overlapping with the anode electrode, and then performing a second etching process to remove a portion of the sacrificial layer overlapping with the hole, while forming a first tip of the second bank layer protruding toward the hole beyond a side surface of the first bank layer, a second tip of the fourth bank layer protruding toward the hole beyond a side surface of the third bank layer, a third tip of the sixth bank layer protruding toward the hole beyond a side surface of the fifth bank layer, and a fourth tip of the eighth bank layer protruding toward the hole beyond a side surface of the seventh bank layer; and forming a light-emitting layer, a cathode electrode, an auxiliary electrode, and a first encapsulation layer completely on the anode electrode and the eighth bank layer, forming a hard mask at a portion overlapping with the anode electrode and near the anode electrode, and then removing the light-emitting layer, the cathode electrode, the auxiliary electrode, and the first encapsulation layer located in a portion where the hard mask is not formed by a third etching process to form a light-emitting element, while forming an organic pattern, an electrode pattern, and an auxiliary electrode pattern on each of the first tip, the second tip, and the third tip, and forming a cavity between the first encapsulation layer and a top surface of the eighth bank layer to expose the top surface of the eighth bank layer, where, in the formation of the auxiliary electrode, the auxiliary electrode contacts a side surface of the first bank layer and the first tip of the second bank layer.

[0049] The display device of the embodiment can provide a high-resolution display device by forming a light-emitting element through a maskless photolithography process, and also provides a display device in which moisture penetration defects caused by moisture and oxygen are solved.

[0050] However, the effects of the embodiments are not limited to the effects described herein. By referring to the claims, the above and other effects of the embodiments will become more apparent to those of ordinary skill in the art to which the embodiments pertain. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The above and other aspects and features of the present disclosure will become more apparent by describing embodiments of the present disclosure in detail with reference to the accompanying drawings, in which:

[0052] Figure 1 is a schematic perspective view of an electronic device according to an embodiment;

[0053] Figure 2 is a perspective view showing a display device included in the electronic device according to an embodiment;

[0054] Figure 3 is Figure 2 a schematic cross-sectional view of the display device of ;

[0055] Figure 4 is a plan view showing the arrangement of emission regions in the display region of ; Figure 3 the display region of ;

[0056] Figure 5 is Figure 4 a schematic cross-sectional view of the display region taken along line X1-X1' of ;

[0057] Figure 6 is Figure 5 an enlarged schematic cross-sectional view of the first emission region in ;

[0058] Figure 7 is Figure 6 an enlarged cross-sectional view of region A of ;

[0059] Figure 8 is a schematic cross-sectional view of the display region taken along line X1-X1' of according to an embodiment; Figure 4 the display region of ;

[0060] Figure 9 is a schematic cross-sectional view of the display region taken along line X1-X1' of according to an embodiment; Figure 4 the display region of ;

[0061] Figure 10 is a schematic cross-sectional view of the display region taken along line X1-X1' of according to an embodiment; and Figure 4 the display region of ;

[0062] Figures 11 to 20 is a cross-sectional view showing an embodiment of a schematic method of manufacturing (or providing) a display element layer and a thin film encapsulation layer included in the display device of ; Figure 5 the display device of ; Detailed implementation manners

[0063] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Like reference numerals always refer to like elements. In the drawings and text of this disclosure, reference numerals indicating the singular form of an element may also be used to refer to a plurality of such singular elements.

[0064] It will be understood that when an element is referred to as being "associated with" another element, such as "on" another element, the element may be directly on the other element, or there may be intervening elements between the element and the other element. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements.

[0065] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element", "first component", "first region", "first layer" or "first section" discussed later may be named a "second element", "second component", "second region", "second layer" or "second section" without departing from the teachings herein.

[0066] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. Unless the context clearly dictates otherwise, the singular forms "a", "an", and "the" as used herein are intended to include the plural forms including "at least one". Thus, a reference to "an" element in a claim after a reference to "the" element includes one element and a plurality of elements. For example, unless the context clearly dictates otherwise, "an element" has the same meaning as "at least one element". "At least one" should not be construed as being limited to "one" or "a". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more of the associated listed items. It will also be understood that when used in this specification, the terms "comprises" and / or "comprising", "includes" and / or "including" specify the presence of the stated features, regions, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components, and / or groups thereof.

[0067] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another as shown in the figures. It will be understood that relative terms are also intended to cover different orientations of the device in addition to the orientations described in the figures. For example, if the device is flipped in one figure, an element described as on the "lower" side of other elements will be oriented on the "upper" side of said other elements. Thus, depending on the specific orientation of the figure, the term "lower" can cover both the "lower" and "upper" orientations. Similarly, if the device is flipped in one figure, an element described as "beneath" or "under" other elements will be oriented "above" the other elements. Thus, the terms "beneath" or "under" can include both the upper and lower orientations.

[0068] Taking into account the measurements discussed and the errors associated with the measurement of a particular quantity (e.g., the limitations of a measurement system), "about" or "approximate" as used herein includes the stated value and means within an acceptable deviation range of a particular value as determined by one of ordinary skill in the art. Terms such as "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0069] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will also be understood that terms, such as those defined in a general dictionary, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted in an idealized or overly formal sense, unless expressly so defined herein.

[0070] Embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments. As such, variations in the shape of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, the embodiments described herein should not be construed as limited to the specific shapes of regions shown herein, but include, for example, shape deviations resulting from manufacturing. For example, regions illustrated or described as flat may typically have rough and / or non-linear features. Additionally, sharp corners of the illustrations may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the exact shape of the regions and are not intended to limit the scope of the claims.

[0071] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0072] Figure 1 is a schematic perspective view of an electronic device 1 according to an embodiment.

[0073] Referring to Figure 1 , the electronic device 1 displays a dynamic image or a still image. The electronic device 1 may refer to any electronic device that provides (or has) a display screen. Examples of the electronic device 1 may include a television, a laptop computer, a monitor, a billboard, an Internet of Things device, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an e-book, a portable multimedia player (PMP), a navigation device, a gaming device, a digital camera, and a camcorder, etc., that provide a display screen.

[0074] Figure 1The first direction (X-axis direction), the second direction (Y-axis direction), and the third direction (Z-axis direction) are defined such that they cross or intersect differently from each other. The first direction (X-axis direction) and the second direction (Y-axis direction) may be perpendicular to each other, the first direction (X-axis direction) and the third direction (Z-axis direction) may be perpendicular to each other, and the second direction (Y-axis direction) and the third direction (Z-axis direction) may be perpendicular to each other, but are not limited thereto. It can be understood that the first direction (X-axis direction) refers to the horizontal direction in the drawing, the second direction (Y-axis direction) refers to the vertical direction in the drawing, and the third direction (Z-axis direction) refers to the up-and-down direction in the drawing (for example, the thickness direction). One direction and another direction among the above first to third directions may cross each other to define a plane.

[0075] In the following description, unless otherwise stated, "direction" may refer to two directions extending along the same direction (for example, one direction and the direction opposite to the one direction). In addition, when it is necessary to distinguish between two "directions" extending in two opposite directions, one side will be referred to as "one side in the direction", and the other side will be referred to as "the other side in the direction". Refer to Figure 1 , the direction pointed to by the arrow indicating the direction is referred to as one side, and the opposite direction is referred to as the other side.

[0076] Hereinafter, for simplicity of description, when referring to the surface of the electronic device 1 or each component constituting the electronic device 1, one main surface facing one side in the direction of displaying an image (i.e., the third direction (Z-axis direction)) is referred to as one surface, and the main surface that is the opposite surface of the one surface is referred to as the other surface. However, the present disclosure is not limited thereto, and one surface and the other surface of a component may be referred to as the front surface and the rear surface, respectively, or may also be referred to as the first surface or the second surface. In addition, when describing the relative positions of each of the components of the electronic device 1, one side in the third direction (Z-axis direction) may be referred to as the upper side, and the other side in the third direction (Z-axis direction) may be referred to as the lower side.

[0077] The shape of the electronic device 1 can be modified in various ways. For example, the electronic device 1 may have a planar shape such as a rectangular shape elongated to define a main direction in the horizontal direction, a rectangular shape elongated to define a main direction in the vertical direction, a square shape, a quadrilateral shape with rounded corners (vertices), other polygonal shapes, and a circular shape.

[0078] The electronic device 1 may include a display area DA and a non-display area NDA adjacent to the display area DA. The display area DA is an area (e.g., a planar area) where a screen or an image can be displayed, and the non-display area NDA is an area (e.g., a planar area) where no screen (or image) is displayed. The display area DA may also be referred to as an active area, and the non-display area NDA may also be referred to as a non-active area. The display area DA may substantially occupy the center of the electronic device 1. Here, the display area DA may be spaced apart from the outer edge of the electronic device 1.

[0079] Figure 2 is a perspective view showing a display device 10 included in the electronic device 1 according to an embodiment.

[0080] Referring to Figure 2 Figure 2 , the electronic device 1 according to an embodiment may include a display device 10. The display device 10 may provide a screen at which an image is displayed through the electronic device 1. Examples of the display device 10 may include an inorganic light-emitting diode display device, an organic light-emitting diode display device, a quantum dot light-emitting display device, a plasma display device, and a field emission display device. In the following description, a case where an organic light-emitting diode display device is applied as the display device will be exemplified, but the present disclosure is not limited thereto, and other display devices may be applied within the scope of the same technical spirit.

[0081] The display device 10 may have a planar shape similar to the planar shape of the electronic device 1. For example, in a plan view, the display device 10 may have a shape similar to a rectangular shape having a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction). The corners where the short side in the first direction (X-axis direction) and the long side in the second direction (Y-axis direction) intersect may be rounded to have a curvature, but it is not limited thereto, and they may be formed at right angles. The planar shape of the display device 10 is not limited to a quadrilateral shape, and it may be formed or provided in a shape similar to another polygon shape, a circular shape, or an oval shape.

[0082] The display device 10 may include a display panel 100, a display driver 200, a circuit board 300, and a touch driver 400.

[0083] The display panel 100 may include a main area MA and a sub-area SBA. The main area MA may include a display area DA including pixels for displaying an image, and a non-display area NDA adjacent to the display area DA (such as provided around the display area DA or along the display area DA).

[0084] The display area DA may be from a plurality of openings or a plurality of emission areas EA to be described later (see Figure 4)Emitted light. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining an emission region EA or an opening, and a self-emitting element. For example, the self-emitting element may include at least one of an organic light-emitting diode (LED) including an organic light-emitting layer, a quantum dot LED including a quantum dot light-emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but is not limited thereto. In the following drawings, a case where the self-emitting element is an organic light-emitting diode is illustrated by way of example.

[0085] The non-display area NDA may be an area outside the display area DA (such as closer to the outer edge of the electronic device 1 than the display area DA). The non-display area NDA may be defined as an edge area of the main area MA of the display panel 100.

[0086] The sub-area SBA may be an area extending from one side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded, or curled so as to be bent, folded, or curled. For example, when the display device 10 is bent at the sub-area SBA, the sub-area SBA may overlap the main area MA in the thickness direction (e.g., the third direction (Z-axis direction)). The sub-area SBA may include a display driver 200 and a pad portion connected to the circuit board 300. In an embodiment, the sub-area SBA may be omitted, and the display driver 200 and the pad portion may be located in the non-display area NDA. In an embodiment, the sub-area SBA may be considered a part of the non-display area NDA, but is not limited thereto.

[0087] The display driver 200 may output signals and voltages as electrical signals for driving the display panel 100. The display driver 200 may be formed (or provided) as an integrated circuit (IC) and mounted on the display panel 100 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method. For example, the display driver 200 may be disposed in the sub-area SBA, and the display driver 200 may overlap the main area MA in the thickness direction by bending of the sub-area SBA. Again, for example, the display driver 200 may be mounted on the circuit board 300.

[0088] The circuit board 300, which is a component outside the display panel 100, may be attached to the display panel 100 at the pad portion of the display panel 100 by using an anisotropic conductive film (ACF). The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film (such as a chip on film).

[0089] The touch driver 400 may be mounted on the circuit board 300. The touch driver 400 may be connected to the touch sensor layer 180 of the display panel 100 (see Figure 3 ). The touch driver 400 may be formed as an integrated circuit.

[0090] Figure 3 is Figure 2 a schematic cross-sectional view of the display device 10. Figure 3 shows the Figure 2 display device 10 bent at the sub-region SBA.

[0091] Referring to Figure 3 , the display panel 100 may include a display layer DPL, a touch sensor layer 180, and a color filter layer 190. The display layer DPL may include a substrate 110, a thin film transistor layer 130 of pixel circuits within the pixel circuit layer, a display element layer 150, and a thin film encapsulation layer 170 as a packaging layer.

[0092] The substrate 110 may be a base substrate or a base member. The substrate 110 may be a flexible substrate that can be bent, folded, or curled. For example, the substrate 110 may include a polymer resin such as polyimide (PI), but is not limited thereto. In an embodiment, the substrate 110 may include a glass material or a metal material.

[0093] The thin film transistor layer 130 may be disposed on the substrate 110. The thin film transistor layer 130 may be located in the display area DA, the non-display area NDA, and the sub-region SBA. The thin film transistor layer 130 may include a plurality of thin film transistors TFT (see Figure 4 ) that constitute the pixel PX (see Figure 5 ).

[0094] The display element layer 150 may be located on the thin film transistor layer 130. The display element layer 150 may be positioned to overlap with the display area DA. The display element layer 150 may include a plurality of light emitting elements ED (see Figure 5 ). For example, the light emitting element ED of the embodiment may include at least one of an organic light emitting diode (LED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but is not limited thereto.

[0095] The thin film encapsulation layer 170 may be positioned on the display element layer 150. The thin film encapsulation layer 170 may be positioned to overlap with the display area DA and the non-display area NDA. The thin film encapsulation layer 170 may cover the top surface and the side surface of the display element layer 150 and protect the display element layer 150 from external oxygen and moisture.

[0096] The touch sensor layer 180 may be located on the thin film encapsulation layer 170. The touch sensor layer 180 may be positioned to overlap with the display area DA and the non-display area NDA. The touch sensor layer 180 may sense an external input such as a touch from a user or from an input tool by using a mutual capacitance method or a self-capacitance method.

[0097] The color filter layer 190 may be positioned on the touch sensor layer 180. The color filter layer 190 may be positioned to overlap with the display area DA and the non-display area NDA. The color filter layer 190 may absorb a part of the light from the outside of the display device 10 to reduce the reflected light caused by the external light. Therefore, the color filter layer 190 may prevent color distortion caused by the reflection of the external light.

[0098] Since the color filter layer 190 is directly disposed on the touch sensor layer 180, the display device 10 may not require a separate substrate for the color filter layer 190. Therefore, the thickness of the display device 10 may be relatively small. In addition, depending on the embodiment, the color filter layer 190 may be omitted.

[0099] As Figure 3 shown, a portion of the display layer DPL overlapping with the sub-region SBA may be bendable to be bent. When a part of the display layer DPL is bent, the display driver 200, the circuit board 300, and the touch driver 400 may overlap with the main region MA in the third direction (Z-axis direction).

[0100] Figure 4 is a plan view showing Figure 3 the arrangement of the emission regions EA in the display area DA.

[0101] Referring to Figure 4 , the display area DA of the embodiment may include a plurality of first emission regions EA1, a plurality of second emission regions EA2, and a plurality of third emission regions EA3, and a non-emission region NLA adjacent to the emission regions EA. The non-emission region NLA may be positioned to surround the plurality of first emission regions EA1, the plurality of second emission regions EA2, and the plurality of third emission regions EA3.

[0102] The non-emission region NLA may block each light emitted from the plurality of first emission regions EA1, the plurality of second emission regions EA2, and the plurality of third emission regions EA3. Therefore, the non-emission region NLA may help prevent the various lights emitted from the plurality of first emission regions EA1, the plurality of second emission regions EA2, and the plurality of third emission regions EA3 from mixing with each other. The pixel defining layer 151 (see Figure 5 ) and the bank structure 160 (see Figure 5 ) to be described later may be located in the non-emission region NLA.

[0103] The emission area EA may include a first emission area EA1, a second emission area EA2, and a third emission area EA3 that emit light of different colors. The first emission area EA1, the second emission area EA2, and the third emission area EA3 may emit red light, green light, and blue light, respectively, and depending on the type of the light-emitting element ED, the color of the light emitted from each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be different, which will be described later. In an embodiment, the first emission area EA1 may emit red light of a first color, the second emission area EA2 may emit green light of a second color, and the third emission area EA3 may emit blue light of a third color, but the present disclosure is not limited thereto. In the drawings, the size (e.g., planar dimension) and shape (e.g., planar shape) of each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 are shown to be the same, but are not limited thereto. The size and shape of each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be freely adjusted according to the desired characteristics.

[0104] A plurality of first emission areas EA1, a plurality of second emission areas EA2, and a plurality of third emission areas EA3 may be defined by a first opening OP1 and a second opening OP2. For example, the first opening OP1 may be defined by a pixel defining layer 151, which will be described later, and the second opening OP2 may be defined by a bank structure 160, which will be described later. In a plan view, the second opening OP2 may completely surround the first opening OP1, and the second opening OP2 may be completely surrounded by a non-emission area NLA.

[0105] In some embodiments, at least one first emission area EA1, at least one second emission area EA2, and at least one third emission area EA3 that are adjacent to each other may constitute a pixel group PXG. The pixel group PXG may be the smallest unit that emits white light. However, the type and / or number of the corresponding first emission area EA1, second emission area EA2, and third emission area EA3 that constitute the pixel group PXG may vary depending on the embodiment.

[0106] Figure 5 is a schematic cross-sectional view of a display area DA (see Figure 4 ) taken along the line X1-X1' of Figure 4 . Figure 5 is a partial cross-sectional view of the display device 10 that overlaps with the display area DA, and shows a schematic cross-section of a display layer DPL. That is, Figure 5 shows cross-sections of a substrate 110, a thin film transistor layer 130, a display element layer 150, and a thin film encapsulation layer 170 of the display device 10. Since in the above Figure 3The base 110 is described in [reference], so the description of the base 110 will be omitted.

[0107] Referring to Figure 5 , the thin film transistor layer 130 may be located on the base 110. The thin film transistor layer 130 may include a first buffer layer 111, thin film transistors TFT, a gate insulating layer 113, a first interlayer insulating layer 121, capacitor electrodes CPE, a second interlayer insulating layer 123, a first connection electrode CNE1, a first via layer 125, a second connection electrode CNE2, and a second via layer 127.

[0108] The first buffer layer 111 may be positioned on the base 110. The first buffer layer 111 may include an inorganic layer capable of preventing the penetration of air or moisture. For example, the first buffer layer 111 may include a plurality of inorganic layers stacked alternately.

[0109] The thin film transistors TFT may be disposed on the first buffer layer 111 and may constitute the pixel circuits of each of a plurality of pixels PX (see Figure 4 ). For example, the thin film transistors TFT may be switching transistors or driving transistors of the pixel circuits. The thin film transistors TFT may include an active layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0110] The active layer ACT may be located on the first buffer layer 111. The active layer ACT may overlap with the gate electrode GE in the third direction (Z-axis direction) and may be insulated from the gate electrode GE by the gate insulating layer 113. In a part of the active layer ACT, the material of the active layer ACT may be made or provided as a conductor (e.g., an electrical conductor) to form the source electrode SE and the drain electrode DE.

[0111] The gate electrode GE may be located on the gate insulating layer 113. The gate electrode GE may overlap with the active layer ACT and the gate insulating layer 113 may be interposed between the gate electrode GE and the active layer ACT.

[0112] The gate insulating layer 113 may be located on the active layer ACT. The gate insulating layer 113 may cover the active layer ACT and the first buffer layer 111 and may insulate the active layer ACT from the gate electrode GE. The gate insulating layer 113 may include contact holes defined therein, and the first connection electrode CNE1 passes through the contact holes.

[0113] The first interlayer insulating layer 121 may cover the gate electrode GE and the gate insulating layer 113. The first interlayer insulating layer 121 may include contact holes defined therein, and the first connection electrode CNE1 passes through the contact holes. The contact holes of the first interlayer insulating layer 121 may be connected to the contact holes of the gate insulating layer 113 and the contact holes of the second interlayer insulating layer 123, or the contact holes of the first interlayer insulating layer 121 may overlap with the contact holes of the gate insulating layer 113 and the contact holes of the second interlayer insulating layer 123.

[0114] The capacitor electrode CPE may be located on the first interlayer insulating layer 121. The capacitor electrode CPE may overlap the gate electrode GE in the third direction (Z-axis direction). The capacitor electrode CPE and the gate electrode GE may form a capacitance together.

[0115] The second interlayer insulating layer 123 may cover the capacitor electrode CPE and the first interlayer insulating layer 121. The second interlayer insulating layer 123 may include contact holes through which the first connection electrode CNE1 passes. The contact holes of the second interlayer insulating layer 123 may be connected to the contact holes of the first interlayer insulating layer 121 and the contact holes of the gate insulating layer 113.

[0116] The first connection electrode CNE1 may be located on the second interlayer insulating layer 123. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 may extend through the contact holes provided in the first interlayer insulating layer 121, the second interlayer insulating layer 123, and the gate insulating layer 113 to contact (e.g., physically contact and / or electrically contact) the drain electrode DE of the thin film transistor TFT.

[0117] The first via layer 125 may cover the first connection electrode CNE1 and the second interlayer insulating layer 123. The first via layer 125 may planarize the underlying structure, such as planarizing the profile of the lower layer. The first via layer 125 may include contact holes defined therein, and the second connection electrode CNE2 passes through the contact holes.

[0118] The second connection electrode CNE2 may be located on the first via layer 125. The second connection electrode CNE2 may extend through the contact holes formed in the first via layer 125 to contact the first connection electrode CNE1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 to the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3.

[0119] The second via layer 127 may cover the second connection electrode CNE2 and the first via layer 125. The second via layer 127 may include contact holes defined therein, and the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 pass through the contact holes.

[0120] The display element layer 150 may be located on the second via layer 127. The display element layer 150 may include a light-emitting element ED, an auxiliary electrode AX, a pixel defining layer 151, a residual pattern 153, and a bank structure 160.

[0121] The light-emitting element ED of the embodiment may include an anode electrode AE, a light-emitting layer EL, and a cathode electrode CE. The light-emitting element ED may include a first light-emitting element ED1 disposed in the first emission region EA1, a second light-emitting element ED2 disposed in the second emission region EA2, and a third light-emitting element ED3 disposed in the third emission region EA3.

[0122] Depending on the material of the light-emitting layer EL, the light-emitting element ED overlapping with the first emission region EA1, the second emission region EA2, and the third emission region EA3 may emit light of different colors. For example, the first light-emitting element ED1 may emit red light of a first color, the second light-emitting element ED2 may emit green light of a second color, and the third light-emitting element ED3 may emit blue light of a third color.

[0123] The anode electrode AE may be located on the second via layer 127. The anode electrode AE may be electrically connected to the drain electrode DE of the thin-film transistor TFT through a first connection electrode CNE1 and a second connection electrode CNE2.

[0124] The anode electrode AE may include a first anode electrode AE1 disposed in the first emission region EA1, a second anode electrode AE2 disposed in the second emission region EA2, and a third anode electrode AE3 disposed in the third emission region EA3. The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may be positioned on the second via layer 127 and spaced apart from each other in the direction along the thin-film transistor layer 130.

[0125] In an embodiment, the anode electrode AE may have a stacked structure formed by stacking a layer containing a material having a high work function (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium oxide (In2O3)) and a layer containing a reflective material (such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), magnesium fluoride (MgF2), or a combination thereof). For example, the anode electrode AE may have a multilayer structure of ITO / Mg, ITO / MgF2, ITO / Ag, and ITO / Ag / ITO, but is not limited thereto.

[0126] The pixel defining layer 151 may be located on the second via layer 127 and the anode electrode AE. The solid portion of the pixel defining layer 151 may separate and insulate the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 from each other. The pixel defining layer 151 in the embodiment may include a solid portion defining a first opening OP1. The pixel defining layer 151 may include sidewalls defining the first opening OP1. The pixel defining layer 151 including the solid portion and having an opening defined therein may be disposed on the entire surface of the second via layer 127, and may expose a part of the top surface of the anode electrode AE to the outside of the pixel defining layer 151. In other words, the pixel defining layer 151 may expose the anode electrode AE at a portion overlapping with the first opening OP1, and the light emitting layer EL may be directly located on the anode electrode AE at a portion overlapping with the first opening OP1.

[0127] The pixel defining layer 151 may include an inorganic insulating material. For example, the pixel defining layer 151 may include silicon oxide, silicon nitride, and silicon oxynitride.

[0128] The bank structure 160 of the embodiment may be located on the pixel defining layer 151 at a portion overlapping with the non-emitting area NLA. The bank structure 160 of the embodiment may define a second opening OP2. That is, the solid portion of the bank as the bank structure 160 may define a corresponding opening therein. The second opening OP2 with or without the first opening OP1 may define a bank opening.

[0129] The bank structure 160 of the embodiment may include a first bank structure 160-1, a second bank structure 160-2, a third bank structure 160-3, and a fourth bank structure 160-4. The first bank structure 160-1, the second bank structure 160-2, the third bank structure 160-3, and the fourth bank structure 160-4 are sequentially stacked in the third direction (Z-axis direction).

[0130] The first bank structure 160-1 of the embodiment may be located on the pixel defining layer 151. The first bank structure 160-1 of the embodiment may include a first bank layer 161 and a second bank layer 162 including different metal materials from each other. The first bank structure 160-1 of the embodiment may include (or define) a first tip TIP1 protruding toward the emission area EA. The first bank layer 161 of the embodiment may electrically connect the first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3 positioned to overlap with the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively.

[0131] The second bank structure 160-2 of the embodiment may be located on the first bank structure 160-1. The second bank structure 160-2 may include a first bank layer 163 and a second bank layer 164 including different metal materials from each other. The second bank structure 160-2 of the embodiment may include a second tip TIP2 protruding toward the emission region EA.

[0132] The third bank structure 160-3 of the embodiment may be located on the second bank structure 160-2. The third bank structure 160-3 may include a first bank layer 165 and a second bank layer 166 including different metal materials from each other. The third bank structure 160-3 of the embodiment may include a third tip TIP3 protruding toward the emission region EA.

[0133] The fourth bank structure 160-4 of the embodiment may be located on the third bank structure 160-3. The fourth bank structure 160-4 may include a first bank layer 167 and a second bank layer 168 including different metal materials from each other. The fourth bank structure 160-4 of the embodiment may include a fourth tip TIP4 protruding toward the emission region EA.

[0134] The corresponding first bank layer may include sidewalls defining a second opening OP2. The corresponding second bank layer may protrude more than the sidewalls to define a corresponding tip among the tips TIP. The tips TIP included in the bank structure 160 of the embodiment may be positioned to overlap each other and / or overlap with the emission region EA, and the first tip TIP1, the second tip TIP2, the third tip TIP3, and the fourth tip TIP4 may overlap each other in the third direction (Z-axis direction). One or more of each of the first bank layer and the second bank layer may define a bank of the bank structure 160 provided in the non-emission region NLA.

[0135] In the display device 10 of the embodiment, the bank structure 160 includes the tip TIP such that in the manufacturing process of the display device 10, the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3, and the first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3 that are positioned to overlap with the first emission region EA1, the second emission region EA2, and the third emission region EA3, respectively, can be formed without a separate fine metal mask. Therefore, in the display device 10 of the embodiment, it is possible to form a plurality of light-emitting elements ED applicable to a high-resolution display device that requires a high pixel integration density.

[0136] The light-emitting layer EL of the embodiment can be located on the anode electrode AE respectively. The light-emitting layer EL can be an organic light-emitting layer made of an organic material and can be formed on the anode electrode AE by a deposition process. In the light-emitting layer EL, when the thin-film transistor TFT applies a predetermined voltage to the anode electrode AE and the cathode electrode CE receives a common voltage or a cathode voltage, holes and electrons can move to the light-emitting layer EL through the hole transport layer and the electron transport layer respectively, and can recombine with each other to emit light in the light-emitting layer EL.

[0137] The light-emitting layer EL can include a first light-emitting layer EL1, a second light-emitting layer EL2, and a third light-emitting layer EL3 disposed in a first emission region EA1, a second emission region EA2, and a third emission region EA3 respectively. For example, the first light-emitting layer EL1 can be a light-emitting layer that emits red light of a first color, the second light-emitting layer EL2 can be a light-emitting layer that emits green light of a second color, and the third light-emitting layer EL3 can be a light-emitting layer that emits blue light of a third color, but the present disclosure is not limited thereto.

[0138] In some embodiments, the ends of the anode electrode AE and the pixel defining layer 151 can be positioned to be spaced apart from each other in a third direction (Z-axis direction). The residual pattern 153 can be positioned at a portion or gap where the anode electrode AE and the pixel defining layer 151 are spaced apart from each other. The residual pattern 153 will be described later.

[0139] The cathode electrode CE of the embodiment can be located on the light-emitting layer EL respectively. The cathode electrode CE can include a transparent conductive material such that the light generated in the light-emitting layer EL can be emitted. The cathode electrode CE can receive a common voltage or a low-potential voltage. When the anode electrode AE receives a voltage corresponding to a data voltage and the cathode electrode CE receives a low-potential voltage, a potential difference is formed between the anode electrode AE and the cathode electrode CE, so that the light-emitting layer EL can emit light.

[0140] In the embodiment, the cathode electrode CE can include a layer containing a material having a low work function (such as Li, Ca, LiF, Cu, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF2, Ba or their compounds or compositions (for example, a composition of Ag, Pd, and Cu)) or a material having a multilayer structure such as LiF / Ca or LiF / Al. The cathode electrode CE can further include a transparent metal oxide layer disposed on the layer containing the material having a low work function.

[0141] The cathode electrode CE may include a first cathode electrode CE1, a second cathode electrode CE2, and a third cathode electrode CE3 respectively disposed in a first emission region EA1, a second emission region EA2, and a third emission region EA3. The first cathode electrode CE1 may be disposed on the first light-emitting layer EL1 in the first emission region EA1, the second cathode electrode CE2 may be disposed on the second light-emitting layer EL2 in the second emission region EA2, and the third cathode electrode CE3 may be disposed on the third light-emitting layer EL3 in the third emission region EA3. The first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3 of the embodiment may not be directly connected and may be electrically connected through a first bank layer 161.

[0142] The auxiliary electrode AX of the embodiment may be respectively located on the cathode electrode CE. The auxiliary electrode AX of the embodiment may help to promote the electrical connection between the cathode electrode CE and the first bank layer 161 and may help to prevent moisture and oxygen from penetrating into the cathode electrode CE.

[0143] The auxiliary electrode AX may be made of (or include) a transparent conductive oxide (TCO) (for example, indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ZITO)).

[0144] The auxiliary electrode AX may include a first auxiliary electrode AX1, a second auxiliary electrode AX2, and a third auxiliary electrode AX3 respectively disposed in the first emission region EA1, the second emission region EA2, and the third emission region EA3. The first auxiliary electrode AX1 may be disposed on the first cathode electrode CE1 in the first emission region EA1, the second auxiliary electrode AX2 may be disposed on the second cathode electrode CE2 in the second emission region EA2, and the third auxiliary electrode AX3 may be disposed on the third cathode electrode CE3 in the third emission region EA3. The first auxiliary electrode AX1, the second auxiliary electrode AX2, and the third auxiliary electrode AX3 of the embodiment may be electrically connected through the cathode electrode CE and the first bank layer 161.

[0145] On the first tip TIP1 of the first bank structure 160-1, a plurality of first organic patterns ELP1, a plurality of second organic patterns ELP2, a plurality of third organic patterns ELP3, a plurality of first electrode patterns CEP1, a plurality of second electrode patterns CEP2, a plurality of third electrode patterns CEP3, and a plurality of first auxiliary electrode patterns AXP1, a plurality of second auxiliary electrode patterns AXP2, and a plurality of third auxiliary electrode patterns AXP3 can be positioned. In a plan view, the plurality of first organic patterns ELP1, the plurality of second organic patterns ELP2, the plurality of third organic patterns ELP3, the plurality of first electrode patterns CEP1, the plurality of second electrode patterns CEP2, the plurality of third electrode patterns CEP3, and the plurality of first auxiliary electrode patterns AXP1, the plurality of second auxiliary electrode patterns AXP2, and the plurality of third auxiliary electrode patterns AXP3 can be positioned to surround the first opening OP1 of the pixel defining layer 151. The plurality of first organic patterns ELP1, the plurality of second organic patterns ELP2, the plurality of third organic patterns ELP3, the plurality of first electrode patterns CEP1, the plurality of second electrode patterns CEP2, the plurality of third electrode patterns CEP3, and the plurality of first auxiliary electrode patterns AXP1, the plurality of second auxiliary electrode patterns AXP2, and the plurality of third auxiliary electrode patterns AXP3 can also be located on the second tip TIP2 of the second bank structure 160-2 and the third tip TIP3 of the third bank structure 160-3.

[0146] The plurality of first organic patterns ELP1, the plurality of second organic patterns ELP2, and the plurality of third organic patterns ELP3 can include the same materials as the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3, respectively. Specifically, the first organic pattern ELP1 can include the same material as the first light-emitting layer EL1, the second organic pattern ELP2 can include the same material as the second light-emitting layer EL2, and the third organic pattern ELP3 can include the same material as the third light-emitting layer EL3. During the manufacturing process of the display device 10, due to the tip TIP of the bank structure 160, the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3 can be traces or patterns formed by the disconnection of the corresponding light-emitting material layers for forming the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3.

[0147] The first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 may be respectively located on the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3. For example, the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 may be directly located on the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3 respectively. The arrangement relationship between the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 and the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3 may be the same as the arrangement relationship between the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 and the first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3. The first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 may respectively include the same materials as the first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3. In the manufacturing process of the display device 10, due to the tip TIP of the bank structure 160, the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 may be traces or patterns formed by the disconnection of the corresponding cathode electrode material layers for forming the first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3.

[0148] The first auxiliary electrode pattern AXP1, the second auxiliary electrode pattern AXP2, and the third auxiliary electrode pattern AXP3 may be respectively located on the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3. For example, the first auxiliary electrode pattern AXP1, the second auxiliary electrode pattern AXP2, and the third auxiliary electrode pattern AXP3 may be directly located on the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3, respectively. The arrangement relationship between the first auxiliary electrode pattern AXP1, the second auxiliary electrode pattern AXP2, and the third auxiliary electrode pattern AXP3 and the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 may be the same as the arrangement relationship between the first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3 and the first auxiliary electrode AX1, the second auxiliary electrode AX2, and the third auxiliary electrode AX3. The first auxiliary electrode pattern AXP1, the second auxiliary electrode pattern AXP2, and the third auxiliary electrode pattern AXP3 may respectively include the same materials as the first auxiliary electrode AX1, the second auxiliary electrode AX2, and the third auxiliary electrode AX3. During the manufacturing process of the display device 10, due to the tip TIP of the bank structure 160, the first auxiliary electrode pattern AXP1, the second auxiliary electrode pattern AXP2, and the third auxiliary electrode pattern AXP3 may be traces or patterns formed by the disconnection of the corresponding auxiliary electrode material layers for forming the first auxiliary electrode AX1, the second auxiliary electrode AX2, and the third auxiliary electrode AX3.

[0149] That is to say, the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3, as well as the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 may be the corresponding patterns of the same first light-emitting material layer to the third light-emitting material layer. Similarly, the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3, as well as the first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3 may be the corresponding patterns of the same first cathode electrode material layer to the third cathode electrode material layer. The first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3, as well as the first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3 may be the corresponding patterns of the same first auxiliary electrode material layer to the third auxiliary electrode material layer. Since elements may be formed in the same process and / or include the same materials as each other in the same layer, the elements may be the corresponding parts of the same material layer, and the elements may be on the same layer by forming an interface with the same lower layer or upper layer, etc., but not limited thereto.

[0150] The thin film encapsulation layer 170 serving as an encapsulation layer may be disposed on the display element layer 150. The thin film encapsulation layer 170 may include at least one inorganic layer to prevent oxygen or moisture from penetrating into the display element layer 150. The thin film encapsulation layer 170 may include at least one organic layer to protect the display element layer 150 from foreign substances such as dust. The thin film encapsulation layer 170 of the embodiment may include a first encapsulation layer 171, a second encapsulation layer 173, and a third encapsulation layer 175 that are sequentially stacked.

[0151] The first encapsulation layer 171 of the embodiment may be located on the light-emitting element ED and the bank structure 160. The first encapsulation layer 171 may be formed by a chemical vapor deposition (CVD) process and may be formed with a uniform thickness along the contour of the lower structure. Here, the thickness may be defined in a direction orthogonal to the surface on which the first encapsulation layer 171 is provided.

[0152] An end or edge portion of the first encapsulation layer 171 of the embodiment may be spaced apart from the bank structure 160 in a third direction (Z-axis direction). A cavity (or gap) may be formed at a portion where the first encapsulation layer 171 and the bank structure 160 are spaced apart from each other. In other words, the first encapsulation layer 171 may be spaced apart from the bank structure 160 in the third direction (Z-axis direction) and a cavity may be interposed between the first encapsulation layer 171 and the bank structure 160.

[0153] The first encapsulation layer 171 may include an inorganic material. For example, the first encapsulation layer 171 may include alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide (ZnO x , which may be ZnO or ZnO2), silicon oxide, silicon nitride, and silicon oxynitride.

[0154] The first encapsulation layer 171 of the embodiment may include a first inorganic layer 171-1, a second inorganic layer 171-2, and a third inorganic layer 171-3 as patterns, which are positioned to overlap with the first emission region EA1, the second emission region EA2, and the third emission region EA3, respectively. The first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 may be spaced apart from each other in a first direction (X-axis direction) and a solid portion of the bank structure 160 may be interposed therebetween. In other words, the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 may be positioned to be spaced apart from each other at a portion overlapping with the non-emission region NLA on the bank structure 160.

[0155] In the drawings, the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 are shown as being formed on the same layer, but the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 may be formed in different processes respectively. Exemplarily, the first inorganic layer 171-1 may be formed after the first cathode electrode CE1 is formed, the second inorganic layer 171-2 may be formed after the second cathode electrode CE2 is formed, and the third inorganic layer 171-3 may be formed after the third cathode electrode CE3 is formed. The manufacturing process will be described later.

[0156] The second encapsulation layer 173 of the embodiment may be located on the first encapsulation layer 171. The second encapsulation layer 173 may flatten or planarize the stepped portion formed by the first encapsulation layer 171.

[0157] The second encapsulation layer 173 may include a polymer-based material. The polymer-based material may include acrylic resin, epoxy resin, silicone resin, silicone acrylic resin, polyimide, polyethylene, etc.

[0158] The third encapsulation layer 175 may be located on the second encapsulation layer 173. The third encapsulation layer 175 may include the same material as the first encapsulation layer 171. The third encapsulation layer 175 may prevent oxygen or moisture from penetrating into the first encapsulation layer 171 and the second encapsulation layer 173.

[0159] Figure 6 is Figure 5 An enlarged schematic cross-sectional view of the first emission region EA1 in Figure 7 is Figure 6 An enlarged cross-sectional view of region A of

[0160] Referring to Figure 6 FIG. [FIGURE NUMBER], the pixel defining layer 151 may be located on the second via layer 127 and the first anode electrode AE1. The end of the pixel defining layer 151 may be spaced apart from the end of the first anode electrode AE1 in the third direction (Z-axis direction) to overlap with the second opening OP2, and the residual pattern 153 may be located between the pixel defining layer 151 and the first anode electrode AE1. The residual pattern 153 may be arranged to contact both sides of the first light-emitting layer EL1 in the first direction (X-axis direction). In addition, the residual pattern 153 may overlap with the tip TIP of the bank structure 160 in the third direction (Z-axis direction).

[0161] The first bank layer 161 included in the first bank structure 160-1 may be positioned to contact the pixel defining layer 151. The first bank layer 161 may include a metal having high conductivity. For example, the first bank layer 161 may include at least one of aluminum (Al) and copper (Cu).

[0162] In some embodiments, the first bank layer 161 may include a side surface 1c facing the first opening OP1. The side surface 1c of the first bank layer 161 may be an inclined surface. In other words, the side surface 1c of the first bank layer 161 may be inclined between the first direction (X-axis direction) and the third direction (Z-axis direction). The side surface 1c of the first bank layer 161 may include a structure that is recessed more than the pixel defining layer 151 in the first direction (X-axis direction). That is to say, the side surface 1c may be outside the first opening OP1.

[0163] The first light emitting layer EL1 and the first cathode electrode CE1 of the embodiment may be formed by a thermal deposition process during the manufacturing process. The thermal deposition process for forming the first light emitting layer EL1 and the first cathode electrode CE1 may be performed while applying the corresponding materials obliquely in an inclined direction with respect to the surface of the first anode electrode AE1. Therefore, the first light emitting layer EL1 and the first cathode electrode CE1 may be in contact with the side surface 1c of the first bank layer 161 at the portion overlapping the second opening OP2. As described above, the first cathode electrode CE1 of the embodiment may be electrically connected to the first bank layer 161.

[0164] In addition, the first auxiliary electrode AX1 of the embodiment may be formed by a sputtering process during the manufacturing process. Generally, compared with the thermal deposition process, the sputtering process may have higher step coverage characteristics. Therefore, the first auxiliary electrode AX1 may completely cover the first cathode electrode CE1 at the portion overlapping the first opening OP1, and may completely cover the first light emitting layer EL1 and the first cathode electrode CE1 located on the side surface 1c of the first bank layer 161 at the portion overlapping the second opening OP2. The first auxiliary electrode AX1 of the embodiment completely covers the first cathode electrode CE1 and is in contact with the side surface 1c of the first bank layer 161, and thus may contribute to connecting the first cathode electrode CE1 and the first bank layer 161 to each other (e.g., physical connection and / or electrical connection) without separation defects. This manufacturing process will be described later.

[0165] In some embodiments, depending on the structure that will be in contact with the side surface 1c of the first bank layer 161, the side surface 1c of the first bank layer 161 may include a first portion 1ca, a second portion 1cb, and a third portion 1cc. The side surface 1c and its respective portions may extend along the Y-axis direction to define the plane of the side surface 1c and its respective portions.

[0166] The first part 1ca can be a part in contact with the first light-emitting layer EL1, the second part 1cb can be a part in contact with the first cathode electrode CE1, and the third part 1cc can be a part in contact with the first auxiliary electrode AX1. In other words, the side surface 1c of the first bank layer 161 can be completely covered by the end surfaces (or outer surfaces) of the first light-emitting layer EL1, the first cathode electrode CE1, and the first auxiliary electrode AX1 in the bank opening, and can be in complete contact with the first light-emitting layer EL1, the first cathode electrode CE1, and the first auxiliary electrode AX1. Due to the contact, an element can form a (physical) interface between them.

[0167] The second bank layer 162 of the embodiment can be located on the first bank layer 161. The second bank layer 162 can include a metal material having high electrical stability and high adhesion to the metal included in the first bank layer 161. In addition, the second bank layer 162 can include a metal material that is more stable than the metal material of the first bank layer 161 in the etching solution used in the etching process. For example, the second bank layer 162 can include any one of molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0168] In some embodiments, the second bank layer 162 can include a top surface 2a, a bottom surface 2b, and a side surface 2c. The top surface 2a of the second bank layer 162 can be a surface facing the second bank structure 160-2, the bottom surface 2b of the second bank layer 162 can be a surface opposite to the top surface 2a and facing the first bank layer 161, and the side surface 2c of the second bank layer 162 can be a surface facing the first opening OP1 and connecting the top surface 2a and the bottom surface 2b to each other.

[0169] The side surface 2c of the embodiment can protrude more than the side surface 1c of the first bank layer 161. Therefore, the end of the second bank layer 162 of the embodiment can have or define a first tip TIP1 that protrudes beyond the side surface 1c of the first bank layer 161 toward the first emission region EA1. An undercut can be formed by the first tip TIP1 and the side surface 1c of the first bank layer 161.

[0170] During the manufacturing process of the first bank structure 160-1, the first tip TIP1 of the embodiment can be formed by the difference in the etching rate of the material for forming the first bank layer 161 and the etching rate of the material for forming the second bank layer 162 for the same etching solution. This manufacturing process will be described later.

[0171] In some embodiments, the height H1 of the first bank layer 161 can be greater than the height H2 of the second bank layer 162. For example, the height H1 of the first bank layer 161 can be from about 5000 angstroms to about within a range, and the height H2 of the second bank layer 162 can be from about to about within a range.

[0172] Referring to Figure 7 , the first auxiliary electrode AX1 of the embodiment can be in contact with the second bank layer 162 at the bottom surface 2b of the second bank layer 162. As described above, the process for forming the first auxiliary electrode AX1 of the embodiment can be performed by a sputtering process, so that the process for forming the first auxiliary electrode AX1 can have high step coverage characteristics. Therefore, the first auxiliary electrode AX1 of the embodiment can be in contact with a part of the second bank layer 162 and the first bank layer 161.

[0173] In some embodiments, depending on the structure that will be in contact with the bottom surface 2b of the second bank layer 162, the bottom surface 2b of the second bank layer 162 can include a first portion 2ba, a second portion 2bb, and a third portion 2bc. The first portion 2ba of the bottom surface 2b can be the portion in contact with the first bank layer 161, the second portion 2bb of the bottom surface 2b can be the portion in contact with the first auxiliary electrode AX1, and the third portion 2bc of the bottom surface 2b can be the portion in contact with the first inorganic layer 171-1. The second portion 2bb can be located between the first portion 2ba and the third portion 2bc in the first direction (X-axis direction). The bottom surface 2b of the second bank layer 162 can be completely covered by the first bank layer 161, the first auxiliary electrode AX1, and the first encapsulation layer 171, and the bottom surface 2b of the second bank layer 162 can be in complete contact with the first bank layer 161, the first auxiliary electrode AX1, and the first encapsulation layer 171.

[0174] The first organic pattern ELP1, the first electrode pattern CEP1, and the first auxiliary electrode pattern AXP1 can be located on the top surface 2a of the second bank layer 162 at a portion overlapping with the first tip TIP1 of the embodiment. The first auxiliary electrode pattern AXP1 of the embodiment can be positioned to completely cover the first electrode pattern CEP1, and the first electrode pattern CEP1 can be positioned to completely cover the first organic pattern ELP1. The first organic pattern ELP1 can be in contact with the top surface 2a and extend from the top surface 2a to be disposed on the side surface 2c of the second bank layer 162.

[0175] In some embodiments, depending on the structure that will contact the side surface 2c of the second dam layer 162, the side surface 2c of the second dam layer 162 may include a first portion 2ca, a second portion 2cb, and a third portion 2cc. The first portion 2ca may be the portion in contact with the first organic pattern ELP1, the second portion 2cb may be the portion in contact with the first electrode pattern CEP1, and the third portion 2cc may be the portion in contact with the first auxiliary electrode pattern AXP1. The second portion 2cb may be located between the first portion 2ca and the third portion 2cc.

[0176] The side surface 2c of the second dam layer 162 may be in full contact with the first organic pattern ELP1, the first electrode pattern CEP1, and the first auxiliary electrode pattern AXP1, and may be completely covered by the first organic pattern ELP1, the first electrode pattern CEP1, and the first auxiliary electrode pattern AXP1.

[0177] Referring Figure 6 and Figure 7 As shown in FIGS. and, the first dam layer 163 included in the second dam structure 160-2 of the embodiment may be located on the first dam structure 160-1. The first dam layer 163 may include a metal having high electrical conductivity. For example, the first dam layer 163 may include at least one of aluminum (Al) and copper (Cu).

[0178] In some embodiments, the first dam layer 163 may include a side surface 3c facing the first opening OP1. The side surface 3c of the first dam layer 163 may be an inclined surface. In other words, the side surface 3c of the first dam layer 163 may be inclined between the first direction (X-axis direction) and the third direction (Z-axis direction). The side surface 3c of the first dam layer 163 may have a structure that is recessed toward one side in the first direction (X-axis direction) compared to the side surface 4c of the second dam layer 164.

[0179] The side surface 3c of the first dam layer 163 may be completely covered by the first encapsulation layer 171, and a part of the side surface 3c of the first dam layer 163 may be in contact with the first encapsulation layer 171. Although the first organic pattern ELP1, the first electrode pattern CEP1, and the first auxiliary electrode pattern AXP1 are shown in the drawings as being in contact with the side surface 3c of the first dam layer 163, the present disclosure is not limited thereto. Depending on the process conditions, the first organic pattern ELP1, the first electrode pattern CEP1, and the first auxiliary electrode pattern AXP1 may be formed to be spaced apart from the side surface 3c of the first dam layer 163.

[0180] The second embankment layer 164 included in the second embankment structure 160-2 of the embodiment may be located on the first embankment layer 163. The second embankment layer 164 may include a metal material having high electrical stability and high adhesion to the metal included in the first embankment layer 163. In addition, the second embankment layer 164 may include a metal material that is more stable than the metal material of the first embankment layer 163 in the etching solution used in the etching process. For example, the second embankment layer 164 may include any one of molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0181] In some embodiments, the second embankment layer 164 may include a top surface 4a and a side surface 4c. The top surface 4a of the second embankment layer 164 may be a surface facing the third embankment structure 160-3, and the side surface 4c of the second embankment layer 164 may be a surface facing the first opening OP1. The side surface 4c of the second embankment layer 164 may protrude toward the first emission region EA1 beyond the side surface 3c of the first embankment layer 163. Accordingly, the second embankment layer 164 may have a second tip TIP2 that protrudes toward the first emission region EA1 beyond the side surface 3c of the first embankment layer 163. An undercut may be formed between the second tip TIP2 and the side surface 3c of the first embankment layer 163.

[0182] During the manufacturing process of the second embankment structure 160-2, the second tip TIP2 of the embodiment may be formed by the difference in the etching rate of the material for forming the first embankment layer 163 and the etching rate of the material for forming the second embankment layer 164 for the same etching solution. This manufacturing process will be described later.

[0183] In some embodiments, the height H3 of the first embankment layer 163 may be in the range from about to about and the height H4 of the second embankment layer 164 may be in the range from about to about of the range.

[0184] The first organic pattern ELP1, the first electrode pattern CEP1, and the first auxiliary electrode pattern AXP1 may be located on the top surface 4a of the second embankment layer 164 at a portion overlapping with the second tip TIP2 of the embodiment. The first organic pattern ELP1 may be in contact with the top surface 4a and the side surface 4c of the second embankment layer 164. The first electrode pattern CEP1 located on the second tip TIP2 may completely cover the first organic pattern ELP1, and the first auxiliary electrode pattern AXP1 may completely cover the first electrode pattern CEP1. Redundant descriptions are omitted.

[0185] The first embankment layer 165 included in the third embankment structure 160-3 of the embodiment may be located on the second embankment structure 160-2. The first embankment layer 165 may include a metal having a high electrical conductivity. For example, the first embankment layer 165 may include at least one of aluminum (Al) and copper (Cu).

[0186] In some embodiments, the first embankment layer 165 may include a side surface 5c facing the first opening OP1. The side surface 5c of the first embankment layer 165 may be an inclined surface. In other words, the side surface 5c of the first embankment layer 165 may be inclined between the first direction (X-axis direction) and the third direction (Z-axis direction). The side surface 5c of the first embankment layer 165 may have a structure that is recessed toward one side in the first direction (X-axis direction) compared to the side surface 6c of the second embankment layer 166.

[0187] The side surface 5c of the first embankment layer 165 may be completely covered by the first encapsulation layer 171, and a part of the side surface 5c of the first embankment layer 165 may be in contact with the first encapsulation layer 171. Although the first organic pattern ELP1, the first electrode pattern CEP1, and the first auxiliary electrode pattern AXP1 are shown in the drawings as being in contact with the side surface 5c of the first embankment layer 165, the present disclosure is not limited thereto. Depending on the process conditions, the first organic pattern ELP1, the first electrode pattern CEP1, and the first auxiliary electrode pattern AXP1 may be spaced apart from the side surface 5c of the first embankment layer 165.

[0188] The second embankment layer 166 included in the third embankment structure 160-3 of the embodiment may be located on the first embankment layer 165. The second embankment layer 166 may include a metal material having high electrical stability and high adhesion to the metal included in the first embankment layer 165. In addition, the second embankment layer 166 may include a metal material that is more stable than the metal material of the first embankment layer 165 in an etching solution used in an etching process. For example, the second embankment layer 166 may include any one of molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0189] In some embodiments, the second embankment layer 166 may include a top surface 6a and a side surface 6c. The top surface 6a of the second embankment layer 166 may be a surface facing the fourth embankment structure 160-4, and the side surface 6c of the second embankment layer 166 may be a surface facing the first opening OP1. The side surface 6c of the second embankment layer 166 may protrude toward the first emission region EA1 beyond the side surface 5c of the first embankment layer 165. Therefore, the second embankment layer 166 may have a third tip TIP3 that protrudes toward the first emission region EA1 beyond the side surface 5c of the first embankment layer 165. An undercut may be formed between the third tip TIP3 and the side surface 5c of the first embankment layer 165.

[0190] During the manufacturing process of the third embankment structure 160-3, the third tip TIP3 of the embodiment can be formed by the difference in the etching rates of the material for forming the first embankment layer 165 and the material for forming the second embankment layer 166 for the same etching solution. This manufacturing process will be described later.

[0191] In some embodiments, the height H5 of the first embankment layer 165 can be in the range from about to about and the height H6 of the second embankment layer 166 can be in the range from about to about

[0192] The first organic pattern ELP1, the first electrode pattern CEP1, and the first auxiliary electrode pattern AXP1 can be located on the third tip TIP3 of the embodiment. The first organic pattern ELP1 can be in contact with the top surface 6a and the side surface 6c of the second embankment layer 166 at the overlapping portion with the third tip TIP3. The first electrode pattern CEP1 located on the third tip TIP3 can completely cover the first organic pattern ELP1, and the first auxiliary electrode pattern AXP1 can completely cover the first electrode pattern CEP1. Redundant descriptions are omitted.

[0193] The first embankment layer 167 included in the fourth embankment structure 160-4 of the embodiment can be located on the third embankment structure 160-3. The first embankment layer 167 can include a metal having high conductivity. For example, the first embankment layer 167 can include at least one of aluminum (Al) and copper (Cu).

[0194] In some embodiments, the first embankment layer 167 can include a side surface 7c facing the first opening OP1. The side surface 7c of the first embankment layer 167 can be an inclined surface. In other words, the side surface 7c of the first embankment layer 167 can be inclined between the first direction (X-axis direction) and the third direction (Z-axis direction). The side surface 7c of the first embankment layer 167 can have a structure that is recessed toward one side in the first direction (X-axis direction) compared to the side surface 8c of the second embankment layer 168.

[0195] The side surface 7c of the first embankment layer 167 can be completely covered by the first encapsulation layer 171, and a part of the side surface 7c of the first embankment layer 167 can be in contact with the first encapsulation layer 171. Although the first organic pattern ELP1, the first electrode pattern CEP1, and the first auxiliary electrode pattern AXP1 are shown in the drawings as being in contact with the side surface 7c of the first embankment layer 167, the present disclosure is not limited thereto. Depending on the process conditions, the first organic pattern ELP1, the first electrode pattern CEP1, and the first auxiliary electrode pattern AXP1 can be spaced apart from the side surface 7c of the first embankment layer 167.

[0196] ​In the fourth embankment structure 160-4 of the embodiment, the second embankment layer 168 included may be located on the first embankment layer 167. The second embankment layer 168 may include a metal material having high electrical stability and high adhesion to the metal included in the first embankment layer 167. The second embankment layer 168 may include a metal material that is more stable than the metal material of the first embankment layer 167 in the etching solution used in the etching process. For example, the second embankment layer 168 may include any one of molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0197] In some embodiments, the second embankment layer 168 may include a top surface 8a and a side surface 8c. The top surface 8a of the second embankment layer 168 may be a surface located in a direction opposite to the direction facing the first embankment layer 167, and the side surface 8c of the second embankment layer 168 may be a surface facing the first opening OP1. The side surface 8c of the second embankment layer 168 may protrude toward the first emission region EA1 beyond the side surface 7c of the first embankment layer 167. Accordingly, the second embankment layer 168 may have a fourth tip TIP4 that protrudes toward the first emission region EA1 beyond the side surface 7c of the first embankment layer 167. An undercut may be formed between the fourth tip TIP4 and the side surface 7c of the first embankment layer 167.

[0198] During the manufacturing process of the fourth embankment structure 160-4, the fourth tip TIP4 of the embodiment may be formed by the difference in the etching rate of the material for forming the first embankment layer 167 and the etching rate of the material for forming the second embankment layer 168 for the same etching solution. This manufacturing process will be described later.

[0199] In some embodiments, the height H7 of the first embankment layer 167 may be in the range from about to about and the height H8 of the second embankment layer 168 may be in the range from about to about of the range.

[0200] In some embodiments, the top surface 8a of the second embankment layer 168 may be spaced apart from the first inorganic layer 171-1 in the third direction (Z-axis direction) (such as, by a gap). A cavity may be formed between the first inorganic layer 171-1 and the top surface 8a of the second embankment layer 168.

[0201] During the manufacturing process of the display device 10, the materials for forming the first light-emitting layer EL1, the materials for forming the first cathode electrode CE1, and the materials for forming the first auxiliary electrode AX1 may be temporarily located between the fourth bank structure 160-4 and the first inorganic layer 171-1, and then removed by subsequent etching processes. That is, a cavity formed between the first inorganic layer 171-1 and the top surface 8a of the second bank layer 168 may be formed by removing, through subsequent etching processes during the manufacturing process of the display device 10, the materials that have been positioned and temporarily formed the first light-emitting layer EL1, the materials for forming the first cathode electrode CE1, and the materials for forming the first auxiliary electrode AX1. This manufacturing process will be described later.

[0202] The first inorganic layer 171-1 of the embodiment may be located on the first auxiliary electrode AX1 at a portion overlapping with the first opening OP1, and may completely cover the first light-emitting element ED1. In addition, the first inorganic layer 171-1 may cover the first auxiliary electrode AX1, the tip TIP of the bank structure 160, the first organic pattern ELP1, the first electrode pattern CEP1, and the first auxiliary electrode pattern AXP1 at a portion overlapping with the second opening OP2. In addition, the first inorganic layer 171-1 may cover a part of the bank structure 160 at a portion overlapping with the non-emission region NLA.

[0203] The first inorganic layer 171-1 of the embodiment may completely cover the side surface 8c of the second bank layer 168, and may be in complete contact with the side surface 8c of the second bank layer 168. However, the first inorganic layer 171-1 may not be in contact with the top surface 8a of the second bank layer 168.

[0204] The second encapsulation layer 173 of the embodiment may flatten (or planarize) the step portions formed by the first inorganic layer 171-1 at portions overlapping with the first emission region EA1 and the non-emission region NLA. In addition, the second encapsulation layer 173 may fill the cavity formed between the first inorganic layer 171-1 and the fourth bank structure 160-4. The second encapsulation layer 173 may completely cover the top surface 8a of the second bank layer 168 included in the fourth bank structure 160-4, and may be in complete contact with the top surface 8a of the second bank layer 168.

[0205] In the display device 10 of the embodiment, the bank structure 160 includes a first bank structure 160-1, a second bank structure 160-2, a third bank structure 160-3, and a fourth bank structure 160-4 that are sequentially stacked in the third direction (Z-axis direction) to form a multi-layer bank, so that the penetration paths of moisture and oxygen (penetration paths of H2O and O2) can be formed as long as possible along the thickness direction. Therefore, the display device 10 of the embodiment can solve the reliability defects caused by the penetration of moisture and oxygen.

[0206] In addition, the display device 10 of the embodiment includes a first auxiliary electrode AX1 for assisting the electrical connection between the first cathode electrode CE1 and the first bank layer 161, so that contact defects between the first bank layer 161 and the first cathode electrode CE1 of the display device 10 can be solved.

[0207] For simplicity of description, the first emission region EA1 and the display element layer 150 (see Figure 5 ) and the thin film encapsulation layer 170 (see Figure 5 ) that are positioned to overlap near the first emission region EA1 have been shown and described schematically in cross-section. However, except that the materials of the emission layers respectively correspond to the colors of the light emitted at the specific emission regions, the display element layer 150 and the thin film encapsulation layer 170 that are positioned to overlap the second emission region EA2 and the third emission region EA3 may also have the same structure and characteristics.

[0208] Figure 8 is a schematic cross-sectional view of the display region DA (see Figure 4 ) taken along the line X1-X1' of Figure 4 according to the embodiment.

[0209] Referring to Figure 8 , the display device 30 of the embodiment is different from the above display device 10 in that the bank structure 160 includes a first bank structure 160-1, a second bank structure 160-2, a third bank structure 160-3, a fourth bank structure 160-4, and a fifth bank structure 160-5 that are sequentially stacked in the third direction (Z-axis direction). That is, Figure 8 the display region DA in

[0210] includes five pairs of bank layers that make up the first bank structure 160-1, the second bank structure 160-2, the third bank structure 160-3, the fourth bank structure 160-4, and the fifth bank structure 160-5, and the fifth bank structure 160-5 provides the uppermost bank structure. Hereinafter, the common description of the display device 10 and the display device 30 will be omitted, and the differences will be described later.In some embodiments, the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3, the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3, and the first auxiliary electrode pattern AXP1, the second auxiliary electrode pattern AXP2, and the third auxiliary electrode pattern AXP3 may be located on a fourth tip TIP4 included in a fourth dam structure 160-4. Specifically, the first organic pattern ELP1, the first electrode pattern CEP1, and the first auxiliary electrode pattern AXP1 may be located on the fourth tip TIP4 at a portion overlapping with the first emission region EA1, the second organic pattern ELP2, the second electrode pattern CEP2, and the second auxiliary electrode pattern AXP2 may be located on the fourth tip TIP4 at a portion overlapping with the second emission region EA2, and the third organic pattern ELP3, the third electrode pattern CEP3, and the third auxiliary electrode pattern AXP3 may be located on the fourth tip TIP4 at a portion overlapping with the third emission region EA3.

[0211] The first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3, the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3, and the first auxiliary electrode pattern AXP1, the second auxiliary electrode pattern AXP2, and the third auxiliary electrode pattern AXP3 may cover a side surface 8c of the second dam layer 168, and the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3, the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3, and the first auxiliary electrode pattern AXP1, the second auxiliary electrode pattern AXP2, and the third auxiliary electrode pattern AXP3 may be in contact with the side surface 8c of the second dam layer 168.

[0212] The first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3, the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3, and the first auxiliary electrode pattern AXP1, the second auxiliary electrode pattern AXP2, and the third auxiliary electrode pattern AXP3 may cover a part of a top surface 8a of the second dam layer 168, and the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3 may be in contact with the top surface 8a of the second dam layer 168.

[0213] A fifth dam structure 160-5 of an embodiment may include a first dam layer 169A and a second dam layer 169B made of different materials and having different functions. The first dam layer 169A of the embodiment may be located on the fourth dam structure 160-4. The first dam layer 169A may include a metal having high electrical conductivity, for example, at least one of aluminum (Al) and copper (Cu).

[0214] In some embodiments, the first dam layer 169A may include a side surface 9ac facing the first opening OP1. The side surface 9ac of the first dam layer 169A may be an inclined surface. In other words, the side surface 9ac of the first dam layer 169A may be inclined between the first direction (X-axis direction) and the third direction (Z-axis direction). The side surface 9ac of the first dam layer 169A may have a structure that is recessed toward one side in the first direction (X-axis direction) compared to the side surface 9bc of the second dam layer 169B.

[0215] The first encapsulation layer 171 may completely cover the side surface 9ac of the first dam layer 169A and may contact a part of the side surface 9ac of the first dam layer 169A. Although the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3, the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3, and the first auxiliary electrode pattern AXP1, the second auxiliary electrode pattern AXP2, and the third auxiliary electrode pattern AXP3 are shown in the drawings as contacting the side surface 9ac of the first dam layer 169A, the present disclosure is not limited thereto. Depending on process conditions, the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3, the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3, and the first auxiliary electrode pattern AXP1, the second auxiliary electrode pattern AXP2, and the third auxiliary electrode pattern AXP3 may be spaced apart from the side surface 9ac of the first dam layer 169A.

[0216] The second dam layer 169B included in the fifth dam structure 160-5 of the embodiment may be located on the first dam layer 169A. The second dam layer 169B may include a metal material having high electrical stability and high adhesion to the metal included in the first dam layer 169A. The second dam layer 169B may include a metal material that is more stable than the metal material of the first dam layer 169A in an etching solution used in an etching process. For example, the second dam layer 169B may include any one of molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0217] In some embodiments, the second dam layer 169B may include a top surface 9ba and a side surface 9bc. The top surface 9ba of the second dam layer 169B may be a surface located in a direction opposite to the direction facing the first dam layer 169A, and the side surface 9bc of the second dam layer 169B may be a surface facing the first opening OP1.

[0218] The side surface 9bc of the second dam layer 169B may protrude toward the emission region EA beyond the side surface 9ac of the first dam layer 169A. Accordingly, the second dam layer 169B may have a fifth tip TIP5 that protrudes toward the emission region EA beyond the side surface 9ac of the first dam layer 169A. An undercut may be formed between the fifth tip TIP5 and the side surface 9ac of the first dam layer 169A.

[0219] During the manufacturing process of the fifth dam structure 160-5, the fifth tip TIP5 of the embodiment may be formed by a difference in the etching rate of the material for forming the first dam layer 169A and the etching rate of the material for forming the second dam layer 169B for the same etching solution. In other words, in the same etching solution, the etching rate of the first dam layer 169A may be higher than the etching rate of the second dam layer 169B.

[0220] In some embodiments, the height H9 of the first dam layer 169A may be in the range from about to about and the height H10 of the second dam layer 169B may be in the range from about to about

[0221] In some embodiments, the top surface 9ba of the second dam layer 169B may be spaced apart from the first encapsulation layer 171 in a third direction (Z-axis direction). A cavity may be formed between the first encapsulation layer 171 and the top surface 9ba of the second dam layer 169B. A redundant description of the cavity is omitted.

[0222] The first encapsulation layer 171 of the embodiment may completely cover the side surface 9bc of the second dam layer 169B and may be in complete contact with the side surface 9bc of the second dam layer 169B. However, the first encapsulation layer 171 may not be in contact with the top surface 9ba of the second dam layer 169B.

[0223] The second encapsulation layer 173 of the embodiment may fill the cavity formed between the first encapsulation layer 171 and the fifth dam structure 160-5. The second encapsulation layer 173 may completely cover the top surface 9ba of the second dam layer 169B included in the fifth dam structure 160-5 and may be in complete contact with the top surface 9ba of the second dam layer 169B.

[0224] Figure 9 is a schematic cross-sectional view of a display region DA (see Figure 4 ) taken along line X1-X1' of an embodiment. Figure 4 )

[0225] Refer to Figure 9 ​, the display device 50 of the embodiment is different from the above-mentioned display device 10 in that the bank structure 160 includes a first bank structure 160-1, a second bank structure 160-2, and a third bank structure 160-3. That is to say, Figure 9 the display area DA in

[0226] includes three pairs of bank layers that make up the first bank structure 160-1, the second bank structure 160-2, and the third bank structure 160-3, where the third bank structure 160-3 provides the uppermost bank structure. Hereinafter, the common description of the display device 10 and the display device 50 will be omitted, and the differences will be described later.

[0227] The first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3, the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3, and the first auxiliary electrode pattern AXP1, the second auxiliary electrode pattern AXP2, and the third auxiliary electrode pattern AXP3 may not be located on the third tip TIP3 of the embodiment.

[0228] The first encapsulation layer 171 of the embodiment may completely cover the side surface 6c of the second bank layer 166 and may be in complete contact with the side surface 6c of the second bank layer 166. However, the first encapsulation layer 171 may not be in contact with the top surface 6a of the second bank layer 166.

[0229] The second encapsulation layer 173 of the embodiment may fill the cavity formed between the first encapsulation layer 171 and the third bank structure 160-3. The second encapsulation layer 173 may completely cover the top surface 6a of the second bank layer 166 included in the third bank structure 160-3 and may be in complete contact with the top surface 6a of the second bank layer 166.

[0230] Figure 10 is a schematic cross-sectional view of the display area DA (see Figure 4 ) taken along the line X1-X1' according to the embodiment. Figure 4 )

[0231] Referring to Figure 10 , the display device 70 of the embodiment is different from the above-mentioned display device 10 in that the bank structure 160 includes a first bank structure 160-1 and a second bank structure 160-2. That is to say, Figure 10The display area DA therein includes two pairs of bank layers that make up the first bank structure 160-1 and the second bank structure 160-2, where the second bank structure 160-2 provides the topmost bank structure. Hereinafter, the common description of the display device 10 and the display device 70 will be omitted, and the differences will be described later.

[0232] In some embodiments, the top surface 4a of the second bank layer 164 included in the second bank structure 160-2 may be spaced apart from the first encapsulation layer 171 in a third direction (Z-axis direction). A cavity may be formed between the first encapsulation layer 171 and the top surface 4a of the second bank layer 164. Redundant descriptions of the cavity are omitted.

[0233] The first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3, the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3, and the first auxiliary electrode pattern AXP1, the second auxiliary electrode pattern AXP2, and the third auxiliary electrode pattern AXP3 may not be located on the second tip TIP2 of the embodiment.

[0234] The first encapsulation layer 171 of the embodiment may completely cover the side surface 4c of the second bank layer 164 and may be in complete contact with the side surface 4c of the second bank layer 164. However, the first encapsulation layer 171 may not be in contact with the top surface 4a of the second bank layer 164.

[0235] The second encapsulation layer 173 of the embodiment may fill the cavity formed between the first encapsulation layer 171 and the second bank structure 160-2. The second encapsulation layer 173 may completely cover the top surface 4a of the second bank layer 164 included in the second bank structure 160-2 and may be in complete contact with the top surface 4a of the second bank layer 164.

[0236] Figures 11 to 20 is a cross-sectional view of an embodiment showing a schematic method of manufacturing (or providing) the display element layer 150 (see Figure 5 ) and the thin film encapsulation layer 170 (see Figure 5 ) included in the display device 10. Hereinafter, the formation order of each layer in the manufacturing process of the display element layer 150 and the thin film encapsulation layer 170 shown in Figure 5 will be described. Figure 5 The manufacturing process of each layer of the display element layer 150 and the thin film encapsulation layer 170 shown in

[0237] Referring to Figure 11 , a plurality of anode electrodes AE of the anode electrode layer, a sacrificial layer SFL including a plurality of sacrificial patterns, a pixel defining material layer 151L, and a bank structure material layer 160L including a pair of bank layers may be provided on the thin film transistor layer 130. Although not shown in the figure, the thin film transistor layer 130 may be provided on a substrate 110 (see Figure 5) above, and the structure of the thin film transistor layer 130 is the same as that described above with reference to Figure 5 and its detailed description is omitted.

[0238] The solid portions of the anode electrode AE may include a first anode electrode AE1, a second anode electrode AE2, and a third anode electrode AE3 that are spaced apart from each other on the thin film transistor layer 130. The solid portion of the sacrificial layer SFL may be located on each of the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. The sacrificial layer SFL may help prevent the top surfaces of the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 from contacting the pixel defining material layer 151L.

[0239] The sacrificial layer SFL may include an oxide semiconductor. For example, the sacrificial layer SFL may include at least one of indium gallium zinc oxide (IGZO), tin zinc oxide (ZTO), and indium tin oxide (ITO).

[0240] The pixel defining material layer 151L may be arranged to completely cover the sacrificial layer SFL, the anode electrode AE, and the thin film transistor layer 130, and the bank structure material layer 160L may be positioned to completely cover the pixel defining material layer 151L. The bank structure material layer 160L may include a first bank structure material layer 160-1L, a second bank structure material layer 160-2L, a third bank structure material layer 160-3L, and a fourth bank structure material layer 160-4L sequentially stacked in the third direction (Z-axis direction). Each of the first bank structure material layer 160-1L, the second bank structure material layer 160-2L, the third bank structure material layer 160-3L, and the fourth bank structure material layer 160-4L includes a pair of bank material layers, such as an upper bank layer and a lower bank layer. The first bank structure material layer 160-1L, the second bank structure material layer 160-2L, the third bank structure material layer 160-3L, and the fourth bank structure material layer 160-4L may be respective preliminary bank structure layers. For example, the first bank structure material layer 160-1L may include a first bank material layer 161L and a second bank material layer 162L as a first pair of preliminary bank layers and the first bank material layer 161L and the second bank material layer 162L are stacked in this order, the second bank structure material layer 160-2L may include a first bank material layer 163L and a second bank material layer 164L as a second pair of preliminary bank layers and the first bank material layer 163L and the second bank material layer 164L are stacked in this order, the third bank structure material layer 160-3L may include a first bank material layer 165L and a second bank material layer 166L as a third pair of preliminary bank layers and the first bank material layer 165L and the second bank material layer 166L are stacked in this order, and the fourth bank structure material layer 160-4L may include a first bank material layer 167L and a second bank material layer 168L as a fourth pair of preliminary bank layers and the first bank material layer 167L and the second bank material layer 168L are stacked in this order.

[0241] Next, referring to Figure 12 and Figure 13, a photoresist PR as a first photoresist is formed on the uppermost preliminary embankment layer (e.g., the fourth embankment structural material layer 160-4L), while exposing the portion of the uppermost preliminary embankment layer that overlaps or corresponds to the anode electrode AE. Next, a first etching process (first etching) for partially etching the first embankment structural material layer 160-1L, the second embankment structural material layer 160-2L, the third embankment structural material layer 160-3L, the fourth embankment structural material layer 160-4L, and the underlying pixel definition material layer 151L is performed while using the photoresist PR as a mask. For example, the first etching process (first etching) can be performed as a dry etching. Since the first etching process (first etching) is performed as a dry etching process, the embankment structural material layer 160L and the pixel definition material layer 151L that overlap with the anode electrode AE can be partially isotropically etched. The first embankment structural material layer 160-1L, the second embankment structural material layer 160-2L, the third embankment structural material layer 160-3L, the fourth embankment structural material layer 160-4L, and the underlying pixel definition material layer 151L can together define a first stacked structure.

[0242] Due to this process, holes HOL (e.g., preliminary pixel openings, preliminary embankment openings, preliminary emission openings, etc.) can be formed at the portions overlapping with the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3, and the sacrificial layer SFL provided on the anode electrode AE can be exposed. Due to this process, the pixel definition material layer 151L can be formed in the form of the pixel definition layer 151 shown in Figure 5 . Here, the sacrificial layer SFL is exposed to the outside of the first stacked structure at each of the preliminary emission openings (e.g., holes HOL).

[0243] Next, referring to Figure 14 and Figure 15 , a photoresist PR as a second photoresist is formed on the fourth embankment structural material layer 160-4L, and a second etching process (second etching) for etching the material layers inside the holes HOL and overlapping with the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 is performed. For example, the second etching process (second etching) can be performed as a wet etching process. Depending on the characteristics of each material layer, the second etching process (second etching) can be performed anisotropically.

[0244] In this process, the sidewalls of the pixel definition layer 151 that define the pixel openings (e.g., at the emission openings) are etched to form inclined inner surfaces (see Figures 13 to 15 ). Also in this process (see Figures 13 to 15 ), the first embankment material layer 161L and the second embankment material layer 162L included in the first embankment structural material layer 160-1L can be in the form of those included inFigure 5 The first dam layer 161 and the second dam layer 162 in the first dam structure 160-1 shown in form, and the first dam material layer 163L and the second dam material layer 164L included in the second dam structure material layer 160-2L can be in the form of the first dam layer 163 and the second dam layer 164 included in Figure 5 the second dam structure 160-2 shown in. In addition, the first dam material layer 165L and the second dam material layer 166L included in the third dam structure material layer 160-3L can be in the form of the first dam layer 165 and the second dam layer 166 included in Figure 5 the third dam structure 160-3 shown in, and the first dam material layer 167L and the second dam material layer 168L included in the fourth dam structure material layer 160-4L can be in the form of the first dam layer 167 and the second dam layer 168 included in Figure 5 the fourth dam structure 160-4 shown in.

[0245] In this process, the material for forming the second dam layer 162 included in the first dam structure 160-1 can have an etching rate lower than that of the first dam layer 161. In other words, in the same etching process, the material for forming the first dam layer 161 of the embodiment can have an etching rate higher than that of the second dam layer 162. Therefore, the second dam layer 162 of the embodiment can have a first tip TIP1 that protrudes beyond the side surface of the first dam layer 161 toward the hole HOL. In addition, the material for forming the second dam layer 164 included in the second dam structure 160-2 can have an etching rate lower than that of the first dam layer 163, so that the second dam layer 164 of the embodiment can have a second tip TIP2 that protrudes beyond the side surface of the first dam layer 163 toward the hole HOL. In addition, the material for forming the second dam layer 166 included in the third dam structure 160-3 can have an etching rate lower than that of the first dam layer 165, so that the second dam layer 166 of the embodiment can have a third tip TIP3 that protrudes beyond the side surface of the first dam layer 165 toward the hole HOL. In addition, the material for forming the second dam layer 168 included in the fourth dam structure 160-4 can have an etching rate lower than that of the first dam layer 167, so that the second dam layer 168 of the embodiment can have a fourth tip TIP4 that protrudes beyond the side surface of the first dam layer 167 toward the hole HOL.

[0246] Meanwhile, in this process, the portions of the sacrificial layer SFL that are disposed on the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 and exposed at the preliminary emission openings can be removed. However, the sacrificial layer SFL may not be completely removed, and a part of the sacrificial layer SFL may remain as a residual pattern 153 in the space between the pixel defining layer 151 and the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. The residual pattern 153 may overlap with the tip TIP of the bank structure 160 in the third direction (Z-axis direction). Other redundant descriptions are omitted.

[0247] Next, referring to Figure 16 , the first light-emitting layer EL1 and the first cathode electrode CE1 are deposited on the first anode electrode AE1, thereby forming the first light-emitting element ED1. The aforementioned layers for forming the first light-emitting element ED1 can be provided at each of the holes HOL (see Figure 15 ).

[0248] The first light-emitting layer EL1 and the first cathode electrode CE1 of the embodiment can be formed by a thermal deposition process. In the display device 10 of the embodiment, the bank structure 160 includes a tip TIP, such that the deposition process for forming the first light-emitting layer EL1 and the deposition process for forming the first cathode electrode CE1 can be performed without a separate fine metal mask.

[0249] In this process, the deposition process for forming the first light-emitting layer EL1 can be performed while the first light-emitting material is provided at an angle of about 45° to about 50° with respect to the top surface of the first anode electrode AE1 (or with respect to the top surface of the first anode electrode AE1). Thus, the first light-emitting layer EL1 can be formed on the pixel defining layer 151 and deposited on the first anode electrode AE1, and can also be formed on the side surface 1c of the first bank layer 161 covered by the first tip TIP1. The above-mentioned first light-emitting layer EL1 can be provided at each of the holes HOL.

[0250] The deposition process for forming the first cathode electrode CE1 in the embodiment can be performed while the cathode electrode material is provided at an angle of about 30° or less with respect to the top surface of the first anode electrode AE1. In other words, the deposition process for forming the first cathode electrode CE1 can be performed by tilting at an angle relatively closer to the horizontal direction than the deposition process for forming the first light-emitting layer EL1. Thus, the first cathode electrode CE1 can be deposited on the first anode electrode AE1 and formed on the pixel defining layer 151, and can also be formed on the side surface 1c of the first bank layer 161 covered by the first tip TIP1. The first cathode electrode CE1 can completely cover the first light-emitting layer EL1.

[0251] In an embodiment, the material for forming the first light-emitting layer EL1 and the material for forming the first cathode electrode CE1 may be formed on the first anode electrode AE1, and may also be formed on the second anode electrode AE2, the third anode electrode AE3, the first tip TIP1, the second tip TIP2, the third tip TIP3, and the second bank layer 168 included in the fourth bank structure 160-4. Due to this process, the first organic pattern ELP1 and the first electrode pattern CEP1 may be formed on the first tip TIP1, the second tip TIP2, and the third tip TIP3 adjacent to the hole HOL. As described above, the first organic pattern ELP1 and the first electrode pattern CEP1 may be traces formed because the material for forming the first light-emitting layer EL1 and the material for forming the first cathode electrode CE1 are disconnected due to the tips TIP of the bank structure 160. That is, the first organic pattern ELP1 and the first light-emitting layer EL1 may correspond to emission regions of the same color (e.g., the first emission region EA1 (see Figure 5 ).

[0252] Next, a first auxiliary electrode AX1 is formed on the first light-emitting element ED1. The first auxiliary electrode AX1 of the embodiment may be formed by a sputtering device. Therefore, compared with the process for forming the first light-emitting layer EL1 and the first cathode electrode CE1, the process for forming the first auxiliary electrode AX1 in the embodiment may have a higher step coverage property. Therefore, the first auxiliary electrode AX1 of the embodiment may completely cover the first light-emitting layer EL1 and the first cathode electrode CE1, and may contact the side surface 1c of the first bank layer 161 and the bottom surface 2b of the second bank layer 162. Redundant descriptions are omitted.

[0253] In addition, the material for forming the first auxiliary electrode AX1 of the embodiment may be formed on the first light-emitting element ED1, and may also be formed on the second anode electrode AE2, the third anode electrode AE3, the first tip TIP1, the second tip TIP2, the third tip TIP3, and the second bank layer 168 included in the fourth bank structure 160-4. Due to this process, the first auxiliary electrode pattern AXP1 may be formed on the first tip TIP1, the second tip TIP2, and the third tip TIP3. As described above, the first auxiliary electrode pattern AXP1 may be a trace formed because the material for forming the first auxiliary electrode AX1 is disconnected due to the tip TIP of the bank structure 160 and is not connected to the first auxiliary electrode AX1. The first auxiliary electrode pattern AXP1 may completely cover the first organic pattern ELP1 and the first electrode pattern CEP1. Redundant descriptions are omitted.

[0254] Next, refer to Figure 17, the first encapsulation material layer 171L is completely formed on the first auxiliary electrode AX1 and the first auxiliary electrode pattern AXP1. The first encapsulation material layer 171L and the multiple layers thereunder can together define a second stacked structure. The first encapsulation material layer 171L can be formed by a chemical vapor deposition (CVD) process and can be formed to have a uniform thickness along the contour formed by the lower structure. That is, the first encapsulation material layer 171L can include a stepped portion at the portion overlapping with the anode electrode AE and the dam structure 160.

[0255] Next, a hard mask is formed at the portion overlapping with the first light-emitting element ED1 of the first emission region EA1 and extends from the first emission region EA1 to the adjacent region near the first light-emitting element ED1, and a third etching process (third etch) for etching the portion where the hard mask is not formed is performed. For example, the third etching process (third etch) can be performed by alternately performing a dry etching process and a wet etching process. In this process, the first light-emitting layer EL1, the first cathode electrode CE1, the first auxiliary electrode AX1, the first organic pattern ELP1, the first electrode pattern CEP1, the first auxiliary electrode pattern AXP1, and the first encapsulation material layer 171L disposed in the region where the hard mask is not formed can be completely removed. The hard mask used in this process can include indium gallium zinc oxide (IGZO). That is, the first light-emitting layer EL1, the first cathode electrode CE1, the first auxiliary electrode AX1, the first organic pattern ELP1, the first electrode pattern CEP1, the first auxiliary electrode pattern AXP1, and the first encapsulation material layer 171L are retained within the emission opening at the first emission region EA1 (see Figure 5 ).

[0256] As Figure 18 shown, due to this process, the first encapsulation material layer 171L (see Figure 17 ) can be formed in the form of the first inorganic layer 171-1 as shown in Figure 5 , and a cavity can be formed in the third direction (Z-axis direction) between the first inorganic layer 171-1 and the second dam layer 168 included in the fourth dam structure 160-4. The materials for forming the first light-emitting layer EL1, the materials for forming the first cathode electrode CE1, and the materials for forming the first auxiliary electrode AX1 disposed on the second dam layer 168 adjacent to the first emission region EA1 (see Figure 5 ) can be etched by the third etching process (third etch) to form the cavity. In this process, one surface of the second dam layer 168 facing the cavity can be exposed to the outside of the first inorganic layer 171-1.

[0257] Meanwhile, due to this process, the second anode electrode AE2 and the third anode electrode AE3 at the color emission regions different from the first emission region EA1 can be exposed again, the residual pattern 153 overlapping with the second anode electrode AE2 and the third anode electrode AE3 can be retained, and the holes HOL can be reopened at the portions overlapping with the second anode electrode AE2 and the third anode electrode AE3.

[0258] Next, the above process is repeated to form the second light-emitting element ED2 (see Figure 19 ) and the third light-emitting element ED3 (see Figure 19 ). That is, this process can be repeated for the different color emission regions defined by the respective light-emitting material layers.

[0259] Referring to Figure 19 , due to this process, the second organic pattern ELP2, the second electrode pattern CEP2, and the second auxiliary electrode pattern AXP2 can be formed on the first tip TIP1, the second tip TIP2, and the third tip TIP3 respectively positioned to overlap with the second light-emitting element ED2 at the second emission region EA2 (see Figure 5 ). In addition, the third organic pattern ELP3, the third electrode pattern CEP3, and the third auxiliary electrode pattern AXP3 can be formed on the first tip TIP1, the second tip TIP2, and the third tip TIP3 respectively positioned to overlap with the third light-emitting element ED3 at the third emission region EA3 (see Figure 5 ).

[0260] In addition, due to this process, the second inorganic layer 171-2 and the third inorganic layer 171-3 shown in Figure 5 can be formed, so as to form the first encapsulation layer 171 together with the previously formed first inorganic layer 171-1. A cavity can be formed between the second inorganic layer 171-2 and the second bank layer 168 in the third direction (Z-axis direction), and a cavity can also be formed between the third inorganic layer 171-3 and the second bank layer 168 in this direction (Z-axis direction). Redundant descriptions are omitted.

[0261] Next, referring to Figure 20 , the second encapsulation layer 173 is formed to flatten the step portion included in the first encapsulation layer 171, and then, the third encapsulation layer 175 is formed on the second encapsulation layer 173, thereby forming the thin-film encapsulation layer 170 shown in Figure 5 .

[0262] In this process, the second encapsulation layer 173 may fill the interior of the cavity located between the fourth bank structure 160-4 and the first encapsulation layer 171. In other words, the fourth bank structure 160-4 and the first encapsulation layer 171 may be spaced apart in the third direction (Z-axis direction), and the second encapsulation layer 173 is interposed between the fourth bank structure 160-4 and the first encapsulation layer 171. In addition, the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 may be spaced apart in the first direction (X-axis direction), and the second encapsulation layer 173 is interposed between them. As a result, the display element layer 150 and the thin film encapsulation layer 170 included in the display device 10 of the embodiment may be formed.

[0263] In an embodiment, the display device includes a display area including an emission area and a non-emission area. The non-emission area includes a pixel defining layer, and a first bank structure and a second bank structure each including a pair of bank layers. The pair of bank layers includes a first bank layer having a side surface facing the emission area, and a second bank layer including a tip protruding from the side surface of the first bank layer. The emission area includes a light emitting layer in contact with the side surface of the first bank layer, a cathode electrode on the light emitting layer and in contact with the side surface of the first bank layer, an auxiliary electrode on the cathode electrode and in contact with the side surface of the first bank layer and the tip of the second bank layer, and a first encapsulation layer on the second bank structure and on the auxiliary electrode.

[0264] The display device may further include: an organic layer including a light emitting layer and an organic pattern on the first tip and disconnected from the light emitting layer; a cathode electrode layer including a cathode electrode and an electrode pattern on the organic pattern and disconnected from the cathode electrode; an auxiliary electrode layer including an auxiliary electrode and an auxiliary electrode pattern on the electrode pattern and disconnected from the auxiliary electrode. The organic pattern, the electrode pattern, and the auxiliary electrode pattern may overlap each other along the thickness direction of the substrate.

[0265] The display device may further include a residual pattern in the emission area and overlapping the first tip and the second tip. In the emission area, the anode electrode and the pixel defining layer are spaced apart from each other, and a gap is formed between the anode electrode and the pixel defining layer, and the residual pattern is in the gap between the anode electrode and the pixel defining layer.

[0266] The first encapsulation layer may extend from the emission area to overlap a portion of the upper surface of the uppermost bank layer adjacent to the emission area.

[0267] The display device may further include a second encapsulation layer on the first encapsulation layer. The upper surface of the uppermost bank layer and the first encapsulation layer are spaced apart from each other, and a gap is formed between them, and the second encapsulation layer extends into the gap between the upper surface of the uppermost bank layer and the first encapsulation layer.

[0268] In an embodiment, a method of providing a display device includes: providing a substrate including a display region including an emission region and a non-emission region, and a non-display region adjacent to the display region. The method further includes: in the display region, providing an anode electrode of a light-emitting element and a sacrificial layer on the anode electrode; in the emission region, providing a pixel defining layer on the sacrificial layer and on the non-emission region of the substrate; providing a bank structure including a first bank layer, a second bank layer, a third bank layer, a fourth bank layer, a fifth bank layer, a sixth bank layer, a seventh bank layer, and an eighth bank layer sequentially stacked on the pixel defining layer (e.g., refer to Figure 11 ); providing a photoresist pattern on the eighth bank layer to expose a region of the bank structure overlapping with the anode electrode; at the region of the bank structure, removing the bank structure and the pixel defining layer by a first etching process using the photoresist pattern (e.g., refer to Figure 12 ), the first etching process including: forming holes in the bank structure corresponding to the emission region and in the pixel defining layer, the holes exposing the sacrificial layer to the outside of the bank structure and the pixel defining layer; and forming, for each of the first bank layer, the second bank layer, the third bank layer, the fourth bank layer, the fifth bank layer, the sixth bank layer, the seventh bank layer, and the eighth bank layer, side surfaces exposed to the holes (e.g., refer to Figure 13 ); in the holes, performing a second etching process to remove a part of the sacrificial layer exposed by the holes, while providing a first tip of the second bank layer protruding from a side surface of the first bank layer, a second tip of the fourth bank layer protruding from a side surface of the third bank layer, a third tip of the sixth bank layer protruding from a side surface of the fifth bank layer, and a fourth tip of the eighth bank layer protruding from a side surface of the seventh bank layer (e.g., refer to Figure 14 and Figure 15 ); sequentially providing an organic layer, a cathode electrode layer, an auxiliary electrode layer, and a first encapsulation layer on the anode electrode and the eighth bank layer to form: an organic layer including a light-emitting layer on the anode electrode and an organic pattern on the first tip and disconnected from the light-emitting layer; a cathode electrode layer including a cathode electrode on the light-emitting layer and an electrode pattern on the organic pattern and disconnected from the cathode electrode; an auxiliary electrode layer including an auxiliary electrode on the cathode electrode and an auxiliary electrode pattern on the electrode pattern and disconnected from the auxiliary electrode; and an auxiliary electrode in contact with a side surface of the first bank layer and the first tip of the second bank layer (e.g., refer to Figure 16 ); providing a mask pattern (e.g., a hard mask) on the first encapsulation layer, the mask pattern overlapping with the holes and a region of the bank structure adjacent to the holes; and removing, by a third etching process, portions of each of the organic layer, the cathode electrode layer, the auxiliary electrode layer, and the first encapsulation layer other than regions overlapping with the mask pattern (e.g., refer to Figure 17); The third etching process includes: forming a light-emitting element including an anode electrode, a light-emitting layer, and a cathode electrode; maintaining an organic pattern, an electrode pattern, and an auxiliary electrode pattern on each of the first tip, the second tip, and the third tip; and forming a cavity between the top surface of the first encapsulation layer and the top surface of the eighth dike layer, the cavity exposing the top surface of the eighth dike layer to the outside of the first encapsulation layer (for example, refer to Figure 18 ).

[0269] The present invention should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0270] Although the present invention has been specifically shown and described with reference to embodiments of the present invention, those of ordinary skill in the art will understand that various changes may be made in form and detail without departing from the spirit or scope of the present invention as defined by the appended claims.

Claims

1. A display device, wherein, The display device includes: a substrate including a display area including an emission area and a non-emission area, and a non-display area adjacent to the display area; The non-emission area includes: a pixel defining layer; a first bank structure on the pixel defining layer, the first bank structure including a first bank layer and a second bank layer, the first bank layer including a side surface facing the emission area, the second bank layer on the first bank layer and including a first tip protruding from the side surface of the first bank layer; and a second bank structure on the first bank structure, the second bank structure including a third bank layer and a fourth bank layer, the third bank layer including a side surface facing the emission area, the fourth bank layer on the third bank layer and including a second tip protruding from the side surface of the third bank layer; The emission area includes: a light-emitting layer of a light-emitting element in contact with the side surface of the first bank layer; a cathode electrode of the light-emitting element on the light-emitting layer and in contact with the side surface of the first bank layer; and an auxiliary electrode on the cathode electrode and in contact with the side surface of the first bank layer and the first tip of the second bank layer; and a first encapsulation layer on the second bank structure and on the auxiliary electrode.

2. The display device according to claim 1, wherein, The display device further includes: an organic layer including the light-emitting layer and an organic pattern on the first tip and disconnected from the light-emitting layer; a cathode electrode layer including the cathode electrode and an electrode pattern on the organic pattern and disconnected from the cathode electrode; and an auxiliary electrode layer including the auxiliary electrode and an auxiliary electrode pattern on the electrode pattern and disconnected from the auxiliary electrode.

3. The display device according to claim 2, wherein Along the first tip: the electrode pattern completely covers the organic pattern, and the auxiliary electrode pattern completely covers the electrode pattern.

4. The display device according to claim 2, wherein, Within the first bank structure: the second bank layer includes a side surface facing the emission area, and the side surface of the second bank layer includes a first portion in contact with the organic pattern, a second portion in contact with the electrode pattern, and a third portion in contact with the auxiliary electrode pattern.

5. The display device according to claim 4, wherein, Along the side surface of the second bank layer, the second portion is between the first portion and the third portion.

6. The display device according to claim 2, wherein, The organic pattern, the electrode pattern, and the auxiliary electrode pattern overlap with each other along the thickness direction of the substrate.

7. The display device according to claim 2, wherein, Within the first bank structure: the second bank layer includes a first surface facing the first bank layer, the first surface of the second bank layer includes a first portion in contact with the first bank layer, a second portion in contact with the auxiliary electrode, and a third portion in contact with the first encapsulation layer, and the second portion is between the first portion and the third portion.

8. The display device according to claim 7, wherein, The first surface of the second bank layer is completely covered by the first bank layer, the auxiliary electrode, and the first encapsulation layer.

9. The display device according to claim 2, wherein, Within the second bank structure: the fourth bank layer includes a side surface facing the emission area and an upper surface positioned in a direction opposite to the direction in which the third bank layer is positioned, and the side surface of the fourth bank layer is in complete contact with the first encapsulation layer.

10. The display device according to claim 9, wherein, The display device further includes a second encapsulation layer on the first encapsulation layer. Wherein, the upper surface of the fourth bank layer and the first encapsulation layer are spaced apart from each other and a gap is formed between the upper surface of the fourth bank layer and the first encapsulation layer, and the second encapsulation layer extends into the gap between the upper surface of the fourth bank layer and the first encapsulation layer.

11. The display device according to claim 10, wherein, The upper surface of the fourth bank layer is in complete contact with the second encapsulation layer.

12. The display device according to claim 11, wherein, The first encapsulation layer extends from the emission region to overlap a portion of the upper surface of the fourth bank layer adjacent to the emission region.

13. The display device according to claim 2, wherein, The display device further includes a residual pattern in the emission region and overlapping the first tip and the second tip. Wherein, within the emission region: the anode electrode of the light-emitting element and the pixel defining layer are spaced apart from each other and a gap is formed between the anode electrode of the light-emitting element and the pixel defining layer, and the residual pattern is in the gap between the anode electrode and the pixel defining layer.

14. The display device according to claim 13, wherein, The residual pattern overlaps the organic pattern, the electrode pattern, and the auxiliary electrode pattern.

15. The display device according to claim 2, wherein, The display device further includes a third bank structure between the first bank structure and the second bank structure along the thickness direction of the substrate. Wherein, the third bank structure includes a fifth bank layer and a sixth bank layer. The fifth bank layer includes a side surface facing the emission region. The sixth bank layer is on the fifth bank layer and includes a third tip protruding beyond the side surface of the fifth bank layer, and the organic pattern, the electrode pattern, and the auxiliary electrode pattern are further on the third tip.

16. The display device according to claim 15, wherein, The organic pattern, the electrode pattern, and the auxiliary electrode pattern on the first tip and the organic pattern, the electrode pattern, and the auxiliary electrode pattern on the third tip overlap each other along the thickness direction of the substrate.

17. The display device according to claim 16, wherein, the first encapsulation layer completely covers the first tip, the second tip, and the third tip, and the side surface of the third bank layer and the side surface of the fifth bank layer are in contact with the first encapsulation layer.

18. The display device according to claim 15, wherein, The display device further includes a fourth bank structure between the second bank structure and the third bank structure along the thickness direction of the substrate. Wherein, the fourth bank structure includes a seventh bank layer and an eighth bank layer. The seventh bank layer includes a side surface facing the emission region. The eighth bank layer is on the seventh bank layer and includes a fourth tip protruding beyond the side surface of the seventh bank layer, and the organic pattern, the electrode pattern, and the auxiliary electrode pattern are further on the fourth tip.

19. The display device according to claim 1, wherein, Along the thickness direction of the substrate, the height of the first bank layer is greater than the height of the second bank layer.

20. A method of providing a display device, wherein, The method includes: providing a substrate including a display region including an emission region and a non-emission region, and a non-display region adjacent to the display region; and performing the following steps in the display region: in the emission region, providing an anode electrode of a light-emitting element and a sacrificial layer on the anode electrode; Provide a pixel defining layer on the sacrificial layer and on the non-emitting region of the substrate; Provide a dam structure including a first dam layer, a second dam layer, a third dam layer, a fourth dam layer, a fifth dam layer, a sixth dam layer, a seventh dam layer, and an eighth dam layer sequentially stacked on the pixel defining layer; Provide a photoresist pattern on the eighth dam layer to expose the region of the dam structure overlapping with the anode electrode; At the region of the dam structure, remove the dam structure and the pixel defining layer by a first etching process using the photoresist pattern, the first etching process including: Form holes in the dam structure corresponding to the emission region and in the pixel defining layer, the holes exposing the sacrificial layer to the outside of the dam structure and the pixel defining layer; and For each of the first dam layer, the second dam layer, the third dam layer, the fourth dam layer, the fifth dam layer, the sixth dam layer, the seventh dam layer, and the eighth dam layer, form side surfaces exposed to the holes; Inside the holes, perform a second etching process to remove the portion of the sacrificial layer exposed by the holes, while together providing a first tip of the second dam layer protruding from the side surface of the first dam layer, a second tip of the fourth dam layer protruding from the side surface of the third dam layer, a third tip of the sixth dam layer protruding from the side surface of the fifth dam layer, and a fourth tip of the eighth dam layer protruding from the side surface of the seventh dam layer; Sequentially provide an organic layer, a cathode electrode layer, an auxiliary electrode layer, and a first encapsulation layer on the anode electrode and on the eighth dam layer to form: The organic layer including a light-emitting layer on the anode electrode and an organic pattern on the first tip and disconnected from the light-emitting layer; The cathode electrode layer including the cathode electrode on the light-emitting layer and an electrode pattern on the organic pattern and disconnected from the cathode electrode; and The auxiliary electrode layer including an auxiliary electrode on the cathode electrode and an auxiliary electrode pattern on the electrode pattern and disconnected from the auxiliary electrode, and wherein the auxiliary electrode contacts the side surface of the first dam layer and the first tip of the second dam layer; Provide a mask pattern on the first encapsulation layer, the mask pattern overlapping with the holes and the regions of the dam structure adjacent to the holes; and Remove portions of each of the organic layer, the cathode electrode layer, the auxiliary electrode layer, and the first encapsulation layer other than the regions overlapping with the mask pattern by a third etching process, the third etching process including: Form a light-emitting element including the anode electrode, the light-emitting layer, and the cathode electrode; Maintain the organic pattern, the electrode pattern, and the auxiliary electrode pattern on each of the first tip, the second tip, and the third tip; and Form a cavity between the top surface of the first encapsulation layer and the top surface of the eighth dam layer, the cavity exposing the top surface of the eighth dam layer to the outside of the first encapsulation layer.

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