Display device and method of manufacturing same

Abstract

A display device and a method of manufacturing the same are provided. The display device includes: a substrate; a pixel electrode disposed on the substrate; a pixel defining layer disposed on an edge of the pixel electrode; a light emitting layer disposed on the pixel electrode; a common electrode disposed on the light emitting layer; a first bank disposed on the pixel defining layer and including a first side surface adjacent to the common electrode and a second side surface opposite to the first side surface; and a second bank disposed on the first bank and including a first side surface partially overlapping the common electrode and a second side surface opposite the first side surface of the second bank. The first side surface of the second bank protrudes than the first side surface of the first bank, and the second side surface of the second bank is aligned with the second side surface of the first bank.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority and all benefits arising therefrom to Korean Patent Application No. 10-2024-0006688, filed with the Korean Intellectual Property Office on January 16, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device and a method of manufacturing the display device. Background Art

[0004] With the development of the information society, the demand for various types of display devices for displaying images is increasing. For example, display devices have been applied to various electronic devices, such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs. The display device may be a flat panel display device, such as a liquid crystal display device, a field emission display device, or an organic light emitting display device. Among flat panel display devices, a self-emitting display device may include light emitting elements, where each of the pixels of the display panel may emit light by itself, thereby displaying an image without a backlight unit providing light to the display panel.

[0005] Recently, display devices have been applied to glasses-type devices to provide virtual reality and augmented reality. In some cases, in order to apply the display device to a glasses-type device, the display device is implemented in a very small size of two inches or less, but has a high pixel integration that supports high resolution. For example, some display devices applied to glasses-type devices may have a high pixel integration of 400 pixels per inch (PPI) or more.

[0006] For the case where the display device is implemented in a very small size but has a high pixel integration as described above, since the area of the light emitting region of the light emitting element is reduced, it is difficult to implement separate light emitting elements for each light emitting region using a mask process. Summary of the Invention

[0007] Aspects of the present disclosure provide a display device capable of forming separate light emitting elements for each light emitting region without using a mask process.

[0008] Aspects of the present disclosure also provide a display device including a large light transmission region.

[0009] However, the aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the following detailed description of the present disclosure.

[0010] Details of other embodiments are included in the detailed description and the drawings.

[0011] According to an embodiment of the present disclosure, a display device includes: a substrate; a pixel electrode disposed on the substrate; a pixel defining layer disposed on an edge of the pixel electrode; a light-emitting layer disposed on the pixel electrode; a common electrode disposed on the light-emitting layer; a first bank disposed on the pixel defining layer, and the first bank includes a first side surface adjacent to the common electrode and a second side surface opposite to the first side surface; and a second bank disposed on the first bank, and the second bank includes a first side surface partially overlapping with the common electrode and a second side surface opposite to the first side surface of the second bank, wherein the first side surface of the second bank protrudes more than the first side surface of the first bank, and the second side surface of the second bank is aligned with the second side surface of the first bank.

[0012] The substrate may include a light-transmissive region and a display region surrounding the light-transmissive region and including a light-emitting region, the first side surface of the second bank may face the light-emitting region, and the second side surface of the second bank may face the light-transmissive region.

[0013] The pixel defining layer may include a first side surface and a second side surface opposite to the first side surface of the pixel defining layer, the first side surface of the pixel defining layer may protrude more than the first side surface of the first bank, and the second side surface of the pixel defining layer may be aligned with the second side surface of the first bank.

[0014] The display device may further include a thin-film transistor layer disposed between the pixel electrode and the substrate, wherein the thin-film transistor layer may be exposed in the light-transmissive region.

[0015] The display device may further include a thin-film encapsulation layer disposed on the thin-film transistor layer, the second bank, and the common electrode.

[0016] The thin-film encapsulation layer may be in contact with the thin-film transistor layer.

[0017] The display device may further include a first inorganic layer disposed on the common electrode and the first side surface of the first bank and a second inorganic layer disposed on the second side surface of the first bank and the thin-film transistor layer.

[0018] The first inorganic layer and the second inorganic layer may be spaced apart from an upper surface of the second bank.

[0019] The thin-film encapsulation layer may include a lower inorganic encapsulation layer disposed on the common electrode and an organic encapsulation layer disposed on the lower inorganic encapsulation layer, and the organic encapsulation layer may be in contact with the thin-film transistor layer in the light-transmissive region.

[0020] The thin-film transistor layer may include a buffer layer, a gate insulating layer, an interlayer insulating layer, and a passivation layer sequentially disposed on the substrate, and the thin-film encapsulation layer may be in contact with the passivation layer and the interlayer insulating layer.

[0021] The thin film encapsulation layer may include an inorganic encapsulation layer disposed on the common electrode, a reinforcing layer disposed on the inorganic encapsulation layer, the second bank, and the thin film transistor layer, and an organic encapsulation layer disposed on the reinforcing layer.

[0022] The common electrode may be in contact with the first side surface of the first bank.

[0023] The display device may further include an optical device overlapping the light transmission region.

[0024] According to an embodiment of the present disclosure, a display device includes: a substrate including a light transmission region and a display region surrounding the light transmission region and including a light emitting region; a thin film transistor layer disposed on the substrate; a light emitting element disposed on the thin film transistor layer in the light emitting region; a first bank surrounding the light emitting element, on the thin film transistor layer, and the first bank includes a first side surface facing the light emitting region and a second side surface facing the light transmission region; and a second bank disposed on the first bank, and the second bank includes a first side surface facing the light emitting region and a second side surface facing the light transmission region, wherein the first side surface of the second bank protrudes more than the first side surface of the first bank, and the second side surface of the second bank is aligned with the second side surface of the first bank.

[0025] The first bank and the second bank may overlap the display region and may not overlap the light transmission region.

[0026] The light emitting element may include a pixel electrode, a light emitting layer, and a common electrode sequentially disposed on the thin film transistor layer, and one end of the common electrode may be in contact with the first side surface of the first bank.

[0027] According to an embodiment of the present disclosure, a method of manufacturing a display device includes: forming a pixel electrode on a substrate; forming a sacrificial layer on the pixel electrode; forming a pixel defining material layer on the sacrificial layer and the substrate; forming a first bank material layer on the pixel defining material layer; forming a second bank material layer on the first bank material layer; forming a photoresist on the second bank material layer; and reducing the thickness of the photoresist in some regions of the photoresist.

[0028] Reducing the thickness of the photoresist in some regions of the photoresist may include performing a halftone exposure process, and etching an uncovered portion of the second bank material layer based on performing the halftone exposure process.

[0029] The method may further include etching an uncovered portion of the first bank material layer; and etching the side surface of the first bank material layer to expose the lower surface of the second bank material layer.

[0030] The method may further include removing some portions of the second bank material layer and some portions of the first bank material layer such that the side surfaces of the second bank material layer and the first bank material layer can be aligned.

[0031] Since the bank structure has an asymmetric cross-section at the boundary of the non-display region surrounded by the display region, the display device according to an embodiment may have a large light transmission region.

[0032] However, the effects of the embodiments are not limited to the effects described herein. By referring to the claims, the above and other effects of the embodiments will become more apparent to those of ordinary skill in the art. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other aspects and features of the present disclosure will become more apparent by describing embodiments of the present disclosure in detail with reference to the accompanying drawings, in which:

[0034] Figure 1 is a schematic perspective view of an electronic device according to an embodiment;

[0035] Figure 2 is a perspective view showing a display device included in the electronic device according to an embodiment;

[0036] Figure 3 is a cross-sectional view of the display device Figure 2 viewed from the side;

[0037] Figure 4 is a plan view showing an arrangement of light-emitting regions in a display region of the display device according to an embodiment;

[0038] Figure 5 is a cross-sectional view showing an example of the display device taken along the line Figure 4 I-I' of;

[0039] Figure 6 is Figure 5 an enlarged cross-sectional view of region A2 of;

[0040] Figure 7 is Figure 2 an enlarged plan view of region A1 of;

[0041] Figure 8 is a cross-sectional view showing an example of the display device taken along the line Figure 7 II-II' of;

[0042] Figure 9 is Figure 8 an enlarged cross-sectional view of region A3 of;

[0043] Figures 10 to 13 is a view showing another example of the display panel Figure 8An enlarged cross-sectional view of region A3; and

[0044] Figures 14 to 20 are cross-sectional views sequentially showing the process of manufacturing a display device according to an embodiment. Detailed Description

[0045] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the present invention are shown. However, aspects supported by the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, the example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example aspects of the present disclosure to those skilled in the art.

[0046] It will also be understood that when a layer or substrate is referred to as being "on" another layer or substrate, the layer or substrate may be directly on the other layer or substrate, or an intervening layer may also be present. Throughout the specification, like reference numerals indicate like components.

[0047] It will be understood that although terms such as "first" and "second" may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, without departing from the teachings of the present invention, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element. Unless otherwise clearly stated, singular forms of terms may include plural forms.

[0048] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly dictates otherwise, "a", "an", "the", and "at least one" do not denote a limitation of quantity and are intended to include both the singular and the plural. For example, "an element" has the same meaning as "at least one element" unless the context clearly dictates otherwise. "At least one" will not be construed as a limitation of "a" or "an". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be further understood that when the terms "comprises" and / or "comprising" or "includes" and / or "including" are used in this specification, it indicates the presence of the stated features, regions, wholes, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components, and / or groups thereof.

[0049] Taking into account the measurements under discussion and errors associated with the measurement of a particular quantity, "about" or "approximate" as used herein includes the stated value and includes the appropriate deviation range of a particular value as determined by a person of ordinary skill in the art. For example, the term "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0050] For ease of description, spatially relative terms such as "under", "below", "lower", "above", and "upper" may be used herein to describe the relationship of one element or feature to another element(s) or feature(s) as shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element or feature that is described as "under" or "below" another element or feature will then be oriented "above" the other element or feature. Thus, the term "under" can encompass both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative terms used herein are to be interpreted accordingly.

[0051] Embodiments are described herein with reference to sectional views of schematic illustrations of example embodiments. As such, variations in the shape of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, the embodiments described herein should not be construed as limited to the specific shapes of regions shown herein, but include deviations in shapes due to, for example, manufacturing. For example, a region shown or described as flat will typically have rough and / or non-linear features. Additionally, sharp corners shown may be rounded. Thus, regions shown in the figures are schematic in nature, and their shapes are not intended to show the exact shape of a region and are not intended to limit the scope of the claims.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in a general dictionary, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted in an idealized or overly formal sense.

[0053] It should be appreciated that the various embodiments of the present disclosure and the terms used therein are not intended to limit the technical features set forth herein to specific embodiments, and include various variations, equivalents, or alternatives for the corresponding embodiments. Regarding the description of the drawings, like reference numerals may be used to refer to like or related elements. It will be understood that, unless the relevant context clearly dictates otherwise, the singular form of a noun corresponding to an item may include one or more things. As used herein, each of the phrases such as "A or B", "at least one of A and B", "A, B, or C", and "at least one of A, B, and C" may include any one or all possible combinations of the items listed together in the corresponding one of these phrases.

[0054] Hereinafter, embodiments will be described with reference to the drawings.

[0055] Figure 1 is a schematic perspective view of an electronic device 1 according to an embodiment.

[0056] Referring to Figure 1 , the electronic device 1 may display a moving image or a still image. The electronic device 1 may refer to any electronic device that provides a display screen. For example, the electronic device 1 may include a television, a notebook computer, a monitor, a billboard, an Internet of Things device, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, smart glasses, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an e-book, a portable multimedia player (PMP), a navigator, a game console, a digital camera, and a video camera, etc., that provide a display screen.

[0057] The electronic device 1 may include a display device 10 that provides a display screen (see Figure 2 ). Examples of the display device 10 may include an inorganic light emitting diode display device, an organic light emitting diode display device, a quantum dot light emitting display device, a plasma display device, and a field emission display device. Hereinafter, an example of using an organic light emitting diode display device as the display device 10 is shown, but the embodiments of the present disclosure are not limited thereto, and the embodiments of the present disclosure may also be applied to other display devices as long as the same technical concept is applicable thereto.

[0058] The embodiments of the present disclosure support various shapes of the electronic device 1. For example, in a plan view, the electronic device 1 may have a shape such as a rectangle with a long width, a rectangle with a long length, a square, a quadrilateral with rounded corners (vertices), other polygons, or a circle as an example. In a plan view, the shape of the display area DA of the electronic device 1 may also be similar to the overall shape of the electronic device 1. In Figure 1In this, an electronic device 1 having a rectangular shape and having a long length in the second direction DR2 is shown.

[0059] The electronic device 1 may include a display area DA and a non-display area NDA. The display area DA is an area where a screen can be displayed, and the non-display area NDA is an area where a screen is not displayed. The display area DA may also be referred to as an active area, and the non-display area NDA may also be referred to as a non-active area. The display area DA generally may occupy the center of the electronic device 1.

[0060] The non-display area NDA may include a first non-display area NDA1 and a second non-display area NDA2. The first non-display area NDA1 may surround the display area DA, and the second non-display area NDA2 may be positioned inside the display area DA and surrounded by the display area DA. The second non-display area NDA2 may correspond to a component area, and the second non-display area NDA2 is an area provided for attaching various functions to components of the electronic device 1.

[0061] Figure 2 is a perspective view showing a display device 10 included in an electronic device 1 (see Figure 1 ) according to an embodiment.

[0062] Referring to Figure 2 , an electronic device 1 according to an embodiment may include a display device 10. The display device 10 may provide a screen to be displayed by the electronic device 1. The display device 10 may have a planar shape similar to the planar shape of the electronic device 1. For example, in a plan view, the display device 10 may have a shape similar to a rectangle having a short side in the first direction DR1 and a long side in the second direction DR2. The corners where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be rounded and have a curvature, but are not limited thereto, and the corners may be formed at right angles. The planar shape of the display device 10 is not limited to a quadrilateral, and may be formed to be similar to other polygons, a circle, or an ellipse.

[0063] The display device 10 may include a display panel 100, a display driver 200, a circuit board 300, a touch driver 400, and an optical device 500 (see Figure 3 ).

[0064] The display panel 100 may include a main area MA and a sub-area SBA.

[0065] The main area MA may include a display area DA including pixels that display an image and a non-display area NDA that does not display an image because it does not include pixels. The display area DA may emit light from a plurality of light-emitting areas or a plurality of opening areas. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer that defines a light-emitting area or an opening area, and a self-luminous element.

[0066] For example, the self-luminous element may include, but is not limited to, at least one of an organic light-emitting diode (LED) including an organic light-emitting layer, a quantum dot LED including a quantum dot light-emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED.

[0067] The non-display area NDA may include a first non-display area NDA1 disposed around the display area DA and a second non-display area NDA2 surrounded by the display area DA. The first non-display area NDA1 may be an area outside the display area DA and may be defined as an edge area of the main area MA of the display panel 100. The first non-display area NDA1 may include a gate driver (not shown) that supplies a gate signal to a gate line and a fan-out line (not shown) that connects the display driver 200 and the display area DA. The second non-display area NDA2 may be located inside the display area DA and may be a light-transmissive area through which light can pass.

[0068] The sub-area SBA may be an area extending from one side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded, or curled, etc. In an example where the sub-area SBA is bent, the sub-area SBA may overlap the main area MA in the thickness direction DR3 (third direction DR3). The sub-area SBA may include the display driver 200 and a pad portion connected to the circuit board 300. In another embodiment, the sub-area SBA may be omitted, and the display driver 200 and the pad portion may be provided in the non-display area NDA.

[0069] The display driver 200 may output signals and voltages for driving the display panel 100. The display driver 200 may supply a data voltage to a data line. The display driver 200 may supply a power voltage to a power line and may supply a gate control signal to the gate driver. The display driver 200 may be formed as an integrated circuit (IC) and may be mounted on the display panel 100 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method. For example, the display driver 200 may be provided in the sub-area SBA, and the display driver 200 may overlap the main area MA in the thickness direction by bending the sub-area SBA. As another example, the display driver 200 may be mounted on the circuit board 300.

[0070] An anisotropic conductive film (ACF) can be used to attach a circuit board 300 to a pad portion of a display panel 100. Leads of the circuit board 300 can be electrically connected to the pad portion of the display panel 100. The circuit board 300 can be a flexible film, such as a flexible printed circuit board, a printed circuit board, or a chip on film, for example.

[0071] A touch driver 400 can be mounted on the circuit board 300. The touch driver 400 can be connected to a touch sensing unit of the display panel 100. The touch driver 400 can supply a touch driving signal to a plurality of touch electrodes of the touch sensing unit and can sense an amount of change in capacitance between the plurality of touch electrodes. For example, the touch driving signal can be a pulse signal having a predetermined frequency. The touch driver 400 can calculate whether an input has been made and input coordinates based on the amount of change in capacitance between the plurality of touch electrodes. The touch driver 400 can be formed as an integrated circuit (IC).

[0072] The display device 10 can further include an optical device 500. The optical device 500 can be disposed in a second non-display area NDA2 on a rear surface of the display device 10. The optical device 500 can emit or receive light in the infrared, ultraviolet, and visible light bands. For example, the optical device 500 can be an optical sensor that detects light incident on the display device 10, such as a proximity sensor, an illuminance sensor, and a camera sensor or an image sensor, for example.

[0073] Figure 3 as viewed from the side Figure 2 is a cross-sectional view of the display device 10. Specifically, Figure 3 relates to the Figure 1 side surface of the display device 10 in a folded state.

[0074] Referring to Figure 3 , the display device 10 can include a display panel 100 and a cover window CW. The display panel 100 can include a display layer DU and a color filter layer CFL. The display layer DU can include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and a thin film encapsulation layer TFEL.

[0075] The substrate SUB can be a base substrate or a base member. The substrate SUB can be a flexible substrate that can be bent, folded, or curled, etc. For example, the substrate SUB can include a polymer resin such as polyimide (PI) as an example, but is not limited thereto. In another embodiment, the substrate SUB can include a glass material or a metal material.

[0076] The thin film transistor layer TFTL may be disposed on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors constituting a pixel circuit of a pixel. The thin film transistor layer TFTL may further include a scan line, a data line, a power line, a scan control line, a fan-out line connecting the display driver 200 and the data line, and a lead connecting the display driver 200 and the pad portion. Each of the thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. In an example where the scan driver is formed on one side of the non-display area NDA of the display panel 100, the scan driver may include a thin film transistor.

[0077] The thin film transistor layer TFTL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistors, the scan line, the data line, and the power line of each pixel of the thin film transistor layer TFTL may be disposed in the display area DA. The scan control line and the fan-out line of the thin film transistor layer TFTL may be disposed in the non-display area NDA. The lead of the thin film transistor layer TFTL may be disposed in the sub-area SBA.

[0078] The light-emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light-emitting element layer EML may include a plurality of light-emitting elements including a first electrode, a second electrode, and a light-emitting layer that emits light, and a pixel defining layer that defines a pixel. The plurality of light-emitting elements of the light-emitting element layer EML may be disposed in the display area DA.

[0079] In an embodiment, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. In an example where the first electrode receives a voltage through the thin film transistor of the thin film transistor layer TFTL and the second electrode receives a cathode voltage, holes and electrons may move to the organic light-emitting layer through the hole transport layer and the electron transport layer, respectively, and may recombine with each other in the organic light-emitting layer to emit light.

[0080] In another embodiment, the light-emitting element may include a quantum dot light-emitting diode including a quantum dot light-emitting layer, an inorganic light-emitting diode including an inorganic semiconductor, or a micro light-emitting diode.

[0081] The thin film encapsulation layer TFEL may cover the upper surface and the side surface of the light-emitting element layer EML, and may protect the light-emitting element layer EML. The thin film encapsulation layer TFEL may include at least one inorganic film and at least one organic film for encapsulating the light-emitting element layer EML.

[0082] The color filter layer CFL may be disposed on the thin film encapsulation layer TFEL. The color filter layer CFL may include a plurality of color filters corresponding to each of the plurality of light emitting regions. Each of the color filters may selectively transmit light of a specific wavelength and block or absorb light of different wavelengths. The color filter layer CFL may absorb a part of the light introduced from the outside of the display device 10 to reduce the reflected light caused by the external light. Accordingly, the color filter layer CFL may prevent color distortion caused by the reflection of the external light.

[0083] Since the color filter layer CFL is directly disposed on the thin film encapsulation layer TFEL, the display device 10 may be implemented without a separate substrate for the color filter layer CFL. Accordingly, the display device 10 may have a relatively small thickness.

[0084] The cover window CW may be disposed on the color filter layer CFL. The cover window CW may be attached to the color filter layer CFL through a transparent bonding member such as an optically clear adhesive (OCA) film, for example.

[0085] Figure 4 is a plan view showing a part of the display device 10 according to an embodiment. Figure 4 is a plan view showing the arrangement of the light emitting regions EA1, EA2, and EA3 in the display area DA of the display device 10 according to an embodiment.

[0086] Referring to Figure 4 , the display device 10 may include a plurality of light emitting regions EA1, EA2, and EA3 disposed in the display area DA. The light emitting regions EA1, EA2, and EA3 may include a first light emitting region EA1, a second light emitting region EA2, and a third light emitting region EA3 that emit light of different colors. The first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3 may emit red light, green light, and blue light, respectively, and depending on the types of the light emitting elements ED1, ED2, and ED3 (see Figure 5 ), the color of the light emitted from each of the light emitting regions EA1, EA2, and EA3 may be different. As an example, the first light emitting region EA1 may emit red light, the second light emitting region EA2 may emit green light, and the third light emitting region EA3 may emit blue light. However, embodiments of the present disclosure are not limited thereto.

[0087] The plurality of light emitting regions EA1, EA2, and EA3 may be arranged in a type, for example, a rhombus Type. For example, the first light-emitting region EA1 and the third light-emitting region EA3 may be spaced apart from each other in the first direction DR1, and may be alternately arranged in the first direction DR1 and the second direction DR2. The second light-emitting region EA2 may be spaced apart from another adjacent second light-emitting region EA2 in the first direction DR1 and the second direction DR2. The second light-emitting region EA2 and the first light-emitting region EA1 or the second light-emitting region EA2 and the third light-emitting region EA3 may be alternately arranged in any direction in the plane formed by the first direction DR1 and the second direction DR2.

[0088] The first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be defined by a pixel defining layer PDL (see Figure 5 ) to be described later.

[0089] Figure 5 is a cross-sectional view showing a part of the display device 10 (see Figure 4 ) according to an embodiment. Specifically, Figure 5 is a cross-sectional view showing an example of the display device 10 taken along the line I-I' of Figure 4 , and shows cross-sections of a substrate SUB, a thin-film transistor layer TFTL, a light-emitting element layer EML, a thin-film encapsulation layer TFEL, and a color filter layer CFL.

[0090] The thin-film transistor layer TFTL may include a first buffer layer BF1, a lower metal layer BML, a second buffer layer BF2, a thin-film transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0091] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic film capable of preventing penetration of air or moisture. For example, the first buffer layer BF1 may include a plurality of inorganic films stacked alternately.

[0092] The lower metal layer BML may be disposed on the first buffer layer BF1. For example, the lower metal layer BML may be formed of a single layer or multiple layers formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or their alloys.

[0093] The second buffer layer BF2 may cover the first buffer layer BF1 and the lower metal layer BML. The second buffer layer BF2 may include an inorganic film capable of preventing penetration of air or moisture. For example, the second buffer layer BF2 may include a plurality of inorganic films stacked alternately.

[0094] The thin film transistor TFT can be disposed on the second buffer layer BF2 and can constitute the pixel circuit of each of the plurality of pixels. For example, the thin film transistor TFT can be a driving transistor or a switching transistor of the pixel circuit. The thin film transistor TFT can include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0095] The semiconductor layer ACT can be disposed on the second buffer layer BF2. The semiconductor layer ACT can overlap with the lower metal layer BML and the gate electrode GE in the thickness direction DR3 and can be insulated from the gate electrode GE through the gate insulating layer GI. In a part of the semiconductor layer ACT, the material of the semiconductor layer ACT can become a conductor to form the source electrode SE and the drain electrode DE.

[0096] The gate electrode GE can be disposed on the gate insulating layer GI. The gate electrode GE can overlap with the semiconductor layer ACT in the thickness direction DR3 and the gate insulating layer GI is interposed between the gate electrode GE and the semiconductor layer ACT.

[0097] The gate insulating layer GI can be disposed on the semiconductor layer ACT. For example, the gate insulating layer GI can cover the semiconductor layer ACT and the second buffer layer BF2 and can insulate the semiconductor layer ACT and the gate electrode GE from each other. The gate insulating layer GI can include a contact hole through which the first connection electrode CNE1 penetrates.

[0098] The first interlayer insulating layer ILD1 can cover the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 can include a contact hole through which the first connection electrode CNE1 penetrates. The contact hole of the first interlayer insulating layer ILD1 can be connected to the contact hole of the gate insulating layer GI and the contact hole of the second interlayer insulating layer ILD2.

[0099] The capacitor electrode CPE can be disposed on the first interlayer insulating layer ILD1. The capacitor electrode CPE can overlap with the gate electrode GE in the thickness direction DR3. The capacitor electrode CPE and the gate electrode GE can form a capacitance.

[0100] The second interlayer insulating layer ILD2 can cover the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 can include a contact hole through which the first connection electrode CNE1 penetrates. The contact hole of the second interlayer insulating layer ILD2 can be connected to the contact hole of the first interlayer insulating layer ILD1 and the contact hole of the gate insulating layer GI.

[0101] The first connection electrode CNE1 can be disposed on the second interlayer insulating layer ILD2. The first connection electrode CNE1 can electrically connect the drain electrode DE of the thin film transistor TFT and the second connection electrode CNE2 to each other. The first connection electrode CNE1 can be embedded in a contact hole formed in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the drain electrode DE of the thin film transistor TFT.

[0102] The first passivation layer PAS1 can cover the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first passivation layer PAS1 can protect the thin film transistor TFT. The first passivation layer PAS1 can include a contact hole through which the second connection electrode CNE2 penetrates.

[0103] The second connection electrode CNE2 can be disposed on the first passivation layer PAS1. The second connection electrode CNE2 can electrically connect the first connection electrode CNE1 and the pixel electrodes AE1, AE2, and AE3 of the light emitting element ED to each other. The second connection electrode CNE2 can be embedded in a contact hole formed in the first passivation layer PAS1 and contact the first connection electrode CNE1.

[0104] The second passivation layer PAS2 can cover the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 can include contact holes through which the pixel electrodes AE1, AE2, and AE3 of the light emitting element ED penetrate.

[0105] The light emitting element layer EML can be disposed on the thin film transistor layer TFTL. The light emitting element layer EML can include a light emitting element ED, a pixel defining layer PDL, a capping layer (not shown), and a bank structure BNS. The light emitting element ED can include pixel electrodes AE1, AE2, and AE3, light emitting layers EL1, EL2, and EL3, and common electrodes CE1, CE2, and CE3.

[0106] Figure 6 is a cross-sectional view showing a first light emitting region EA1 (see Figure 4 ) of the display device 10 according to another embodiment (see Figure 5 ). Specifically, Figure 6 is Figure 5 an enlarged cross-sectional view of region A2 of

[0107] In addition to Figure 5 also refer to Figure 6, the display device 10 may include a plurality of light-emitting regions EA1, EA2, and EA3 disposed in the display area DA. The light-emitting regions EA1, EA2, and EA3 may be defined as regions where the pixel electrodes AE1, AE2, and AE3, the light-emitting layers EL1, EL2, and EL3, and the common electrodes CE1, CE2, and CE3 overlap in the thickness direction of the substrate SUB. The light-emitting regions EA1, EA2, and EA3 may include regions where light is emitted from the light-emitting elements ED1, ED2, and ED3 and passes through the color filter layer CFL in the third direction DR3. In the light-emitting elements ED1, ED2, and ED3, the pixel electrodes AE1, AE2, and AE3, the light-emitting layers EL1, EL2, and EL3, and the common electrodes CE1, CE2, and CE3 are stacked in this order. The light-emitting regions EA1, EA2, and EA3 may include a first light-emitting region EA1, a second light-emitting region EA2, and a third light-emitting region EA3 that are spaced apart from each other and emit light of the same or different colors.

[0108] In an embodiment, the areas or sizes of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be the same as or different from each other. For example, in the display device 10, the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may have different areas. However, embodiments of the present disclosure are not limited thereto. The area of the third light-emitting region EA3 may be larger than the areas of the first light-emitting region EA1 and the second light-emitting region EA2, and the area of the second light-emitting region EA2 may be larger than the area of the first light-emitting region EA1. The intensity of the light emitted from the light-emitting regions EA1, EA2, and EA3 may vary according to the areas of the light-emitting regions EA1, EA2, and EA3, and the color of the image displayed on the display device 10 may be controlled by adjusting the areas of the light-emitting regions EA1, EA2, and EA3.

[0109] In the display device 10, one first light-emitting region EA1, one second light-emitting region EA2, and one third light-emitting region EA3 that are adjacent to each other may form a pixel group. A pixel group may express white grayscale by including the light-emitting regions EA1, EA2, and EA3 that emit light of different colors. However, embodiments of the present disclosure are not limited thereto, and the combination of the light-emitting regions EA1, EA2, and EA3 constituting a pixel group may be variously modified according to the arrangement of the light-emitting regions EA1, EA2, and EA3 and the colors of the light emitted from the light-emitting regions EA1, EA2, and EA3.

[0110] The display device 10 may include a plurality of light-emitting elements ED1, ED2, and ED3 disposed in different light-emitting regions EA1, EA2, and EA3. The light-emitting elements ED1, ED2, and ED3 may include a first light-emitting element ED1 disposed in the first light-emitting region EA1, a second light-emitting element ED2 disposed in the second light-emitting region EA2, and a third light-emitting element ED3 disposed in the third light-emitting region EA3.

[0111] Each of the light-emitting elements ED1, ED2, and ED3 includes pixel electrodes AE1, AE2, and AE3, light-emitting layers EL1, EL2, and EL3, and common electrodes CE1, CE2, and CE3, and depending on the materials of the light-emitting layers EL1, EL2, and EL3, the light-emitting elements ED1, ED2, and ED3 disposed in different light-emitting regions EA1, EA2, and EA3 may emit light of different colors. For example, the first light-emitting element ED1 disposed in the first light-emitting region EA1 may emit red light having a peak wavelength in the range of 610 nm to 650 nm, the second light-emitting element ED2 disposed in the second light-emitting region EA2 may emit green light having a peak wavelength in the range of 510 nm to 550 nm, and the third light-emitting element ED3 disposed in the third light-emitting region EA3 may emit blue light having a peak wavelength in the range of 440 nm to 480 nm. The first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 constituting one pixel may express white grayscale by including the light-emitting elements ED1, ED2, and ED3 that emit light of different colors. Alternatively, the light-emitting layers EL1, EL2, and EL3 may include two or more materials that emit light of different colors, such that one light-emitting layer may emit mixed light. For example, the light-emitting layers EL1, EL2, and EL3 may emit yellow light by including a material that emits red light and a material that emits green light, or may emit white light by including a material that emits red light, a material that emits green light, and a material that emits blue light.

[0112] The pixel electrodes AE1, AE2, and AE3 may be disposed on the second passivation layer PAS2. The pixel electrodes AE1, AE2, and AE3 may be respectively disposed in the plurality of light-emitting regions EA1, EA2, and EA3. The pixel electrodes AE1, AE2, and AE3 may include a first pixel electrode AE1 disposed in the first light-emitting region EA1, a second pixel electrode AE2 disposed in the second light-emitting region EA2, and a third pixel electrode AE3 disposed in the third light-emitting region EA3. The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be disposed on the second passivation layer PAS2 to be spaced apart from each other.

[0113] The pixel electrodes AE1, AE2, and AE3 can be electrically connected to the drain electrode DE of the thin film transistor TFT through the first connection electrode CNE1 and the second connection electrode CNE2. The edges of the pixel electrodes AE1, AE2, and AE3 spaced apart from each other can be covered by the pixel defining layer PDL, so that the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 can be insulated from each other.

[0114] The pixel electrodes AE1, AE2, and AE3 can include a transparent electrode material and / or a conductive metal material, and can have a single-layer or multi-layer structure. The metal material can be one or more of silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), lanthanum (La), and titanium (Ti). The transparent electrode material can be one or more of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), and titanium nitride (TiN).

[0115] The light emitting layers EL1, EL2, and EL3 can be disposed on the pixel electrodes AE1, AE2, and AE3. The light emitting layers EL1, EL2, and EL3 can be organic light emitting layers formed of an organic material, and can be formed on the pixel electrodes AE1, AE2, and AE3 by a deposition process. The light emitting layers EL1, EL2, and EL3 can have a multi-layer structure, and a hole injection material, a hole transport material, a light emitting material, an electron transport material, or / and an electron injection material can each form a layer. In an example where the thin film transistor TFT applies a predetermined voltage to the pixel electrodes AE1, AE2, and AE3 of the light emitting elements ED1, ED2, and ED3 and the common electrodes CE1, CE2, and CE3 of the light emitting elements ED1, ED2, and ED3 receive a common voltage or a cathode voltage, holes and electrons are each injected and transported, and the holes and electrons can recombine with each other in the light emitting layers EL1, EL2, and EL3 to emit light.

[0116] The light emitting layers EL1, EL2, and EL3 can include a first light emitting layer EL1, a second light emitting layer EL2, and a third light emitting layer EL3 respectively disposed in different light emitting regions EA1, EA2, and EA3. The first light emitting layer EL1 can be disposed on the first pixel electrode AE1 in the first light emitting region EA1, the second light emitting layer EL2 can be disposed on the second pixel electrode AE2 in the second light emitting region EA2, and the third light emitting layer EL3 can be disposed on the third pixel electrode AE3 in the third light emitting region EA3. Each of the plurality of light emitting layers EL1, EL2, and EL3 can emit light of a different color, or one of the light emitting layers EL1, EL2, or EL3 can emit mixed light. In an embodiment, the first light emitting layer EL1 can emit red light, the second light emitting layer EL2 can emit green light, and the third light emitting layer EL3 can emit blue light.

[0117] The light-emitting layers EL1, EL2, and EL3 may be disposed on the upper surface of the pixel defining layer PDL. In an embodiment, compared with the side surface of the pixel defining layer PDL, the side surface of the residual pattern RP may be recessed, and a part of the light-emitting layers EL1, EL2, and EL3 may be disposed in the space between the pixel electrodes AE1, AE2, and AE3 and the pixel defining layer PDL. In an embodiment, the light-emitting layers EL1, EL2, and EL3 may be in contact with the pixel defining layer PDL, the residual pattern RP, and the pixel electrodes AE1, AE2, and AE3.

[0118] The common electrodes CE1, CE2, and CE3 may be disposed on the light-emitting layers EL1, EL2, and EL3. The common electrodes CE1, CE2, and CE3 include a transparent conductive material such that the light generated in the light-emitting layers EL1, EL2, and EL3 can be emitted. The common electrodes CE1, CE2, and CE3 may receive a common voltage or a low-potential voltage. In an example where the pixel electrodes AE1, AE2, and AE3 receive voltages corresponding to data voltages and the common electrodes CE1, CE2, and CE3 receive low-potential voltages, the light-emitting layers EL1, EL2, and EL3 may emit light when a potential difference is formed between the pixel electrodes AE1, AE2, and AE3 and the common electrodes CE1, CE2, and CE3.

[0119] The common electrodes CE1, CE2, and CE3 may include a first common electrode CE1, a second common electrode CE2, and a third common electrode CE3 disposed in different light-emitting regions EA1, EA2, and EA3. The first common electrode CE1 may be disposed on the first light-emitting layer EL1 in the first light-emitting region EA1, the second common electrode CE2 may be disposed on the second light-emitting layer EL2 in the second light-emitting region EA2, and the third common electrode CE3 may be disposed on the third light-emitting layer EL3 in the third light-emitting region EA3. The first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may be spaced apart from each other.

[0120] A capping layer (not shown) may be selectively disposed on the common electrodes CE1, CE2, and CE3. The capping layer may include an organic or inorganic insulating material and cover the patterns disposed on the light-emitting elements ED1, ED2, and ED3. The capping layer may prevent the light-emitting elements ED1, ED2, and ED3 from being damaged by external air. The capping layer may include a first capping layer, a second capping layer, and a third capping layer disposed in different light-emitting regions EA1, EA2, and EA3, respectively. The first capping layer to the third capping layer may be spaced apart from each other.

[0121] The pixel defining layer PDL may be disposed on the second passivation layer PAS2 and expose the upper surfaces of the pixel electrodes AE1, AE2, and AE3 to define the light emitting regions EA1, EA2, and EA3. The pixel defining layer PDL may include an inorganic insulating material. The pixel defining layer PDL may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, a tantalum oxide layer, a hafnium oxide layer, a zinc oxide (ZnO x , which may be ZnO or ZnO2) layer, and an amorphous silicon layer, but is not limited thereto.

[0122] According to an embodiment, the pixel defining layer PDL may be disposed on the edges of the pixel electrodes AE1, AE2, and AE3 and may be spaced apart from the upper surfaces of the pixel electrodes AE1, AE2, and AE3. The pixel defining layer PDL may partially overlap the upper surfaces of the pixel electrodes AE1, AE2, and AE3 in the thickness direction DR3 of the substrate SUB and may not be in direct contact with the upper surfaces of the pixel electrodes AE1, AE2, and AE3, and a residual pattern RP may be disposed between the pixel defining layer PDL and the pixel electrodes AE1, AE2, and AE3. The pixel defining layer PDL may be in direct contact with the side surfaces of the pixel electrodes AE1, AE2, and AE3.

[0123] The residual pattern RP may be disposed on the edge of each of the pixel electrodes AE1, AE2, and AE3. Due to the residual pattern RP, the pixel defining layer PDL may not be in direct contact with the upper surfaces of the pixel electrodes AE1, AE2, and AE3. The residual pattern RP may be formed by removing a part of the sacrificial layer disposed on the pixel electrodes AE1, AE2, and AE3 during the process of manufacturing the display device 10. The residual pattern RP may include a metal or an oxide semiconductor material.

[0124] The display device 10 may include a plurality of bank structures BNS disposed on the pixel defining layer PDL. The bank structure BNS may have a structure in which banks BN1 and BN2 including different materials are sequentially stacked, the bank structure BNS may include a plurality of openings including the light emitting regions EA1, EA2, and EA3, and the bank structure BNS may be disposed to overlap the light blocking regions of the color filters CF1, CF2, and CF3 to be described later.

[0125] The first bank BN1 may be disposed on the pixel defining layer PDL. In a direction opposite to the direction toward the light emitting regions EA1, EA2, and EA3, a side surface of the first bank BN1 may be recessed from a side surface of the pixel defining layer PDL. In a direction opposite to the direction toward the light emitting regions EA1, EA2, and EA3, the side surface of the first bank BN1 may be recessed from a side surface of the second bank BN2, which will be described later. That is, for example, the side surface of the first bank BN1 may be recessed away from a given light emitting region (e.g., the light emitting region EA1) compared to a corresponding side surface of the pixel defining layer PDL.

[0126] According to an embodiment, the first bank BN1 may include a metal material. In an embodiment, the first bank BN1 may include aluminum (Al), an oxide of aluminum (Al), or an alloy of aluminum (Al).

[0127] The common electrodes CE1, CE2, and CE3 may be in direct contact with the side surface of the first bank BN1. For example, with respect to each of the common electrodes CE1, CE2, and CE3, one end and the other end may be in contact with the side surface of the first bank BN1, respectively. The common electrodes CE1, CE2, and CE3 of different light emitting elements ED1, ED2, and ED3 may each be in direct contact with the first bank BN1, and the first bank BN1 includes a conductive material such that the common electrodes CE1, CE2, and CE3 may be electrically connected to each other through the first bank BN1. The first bank BN1 may have an upper surface positioned higher than the common electrodes CE1, CE2, and CE3. A height from the substrate SUB to the upper surface of the first bank BN1 may be greater than a height from the substrate SUB to the common electrodes CE1, CE2, and CE3.

[0128] According to an embodiment, the light-emitting layers EL1, EL2, and EL3 may be in direct contact with the side surface of the first bank BN1. The contact area between the common electrodes CE1, CE2, and CE3 and the side surface of the first bank BN1 may be larger than the contact area between the light-emitting layers EL1, EL2, EL3 and the side surface of the first bank BN1. The common electrodes CE1, CE2, and CE3 may be arranged to have an area larger than the area of the light-emitting layers EL1, EL2, and EL3 on the side surface of the first bank BN1, or the common electrodes CE1, CE2, and CE3 may be arranged at a higher position on the side surface of the first bank BN1. In another way of expression, the surface area of the common electrodes CE1, CE2, and CE3 in contact with the side surface of the first bank BN1 may be larger than the surface area of the light-emitting layers EL1, EL2, and EL3 in contact with the side surface of the first bank BN1 (or the common electrodes CE1, CE2, and CE3 in contact with the side surface of the first bank BN1 may be positioned higher than the light-emitting layers EL1, EL2, and EL3 in contact with the side surface of the first bank BN1). Since the common electrodes CE1, CE2, and CE3 of the different light-emitting elements ED1, ED2, and ED3 are electrically connected through the first bank BN1, a larger contact area between the common electrodes CE1, CE2, and CE3 and the first bank BN1 can provide an advantage compared to other methods.

[0129] The second bank BN2 may be provided on the first bank BN1. The second bank BN2 may include openings overlapping each of the light-emitting regions EA1, EA2, and EA3, and each opening may include a side surface. Compared with the first bank BN1, the second bank BN2 may include a tip TIP or an eaves as a protruding region. The side surface of the second bank BN2 may protrude toward the light-emitting regions EA1, EA2, and EA3 compared with the side surface of the first bank BN1.

[0130] Since the side surface of the second bank BN2 has a shape protruding toward the light-emitting regions EA1, EA2, and EA3 compared with the side surface of the first bank BN1, an undercut structure of the first bank BN1 may be formed under the tip TIP of the second bank BN2.

[0131] In the display device 10 according to the embodiment, since the bank structure BNS includes tips TIP protruding toward the light-emitting regions EA1, EA2, and EA3, the light-emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 spaced apart from each other can be formed by a deposition process and an etching process instead of a mask process. In some aspects, the embodiments of the present disclosure support separately forming different layers in different light-emitting regions EA1, EA2, and EA3 by a deposition process. For example, the embodiments of the present disclosure support forming the light-emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 of the light-emitting elements ED1, ED2, and ED3 by a deposition process without using a mask, such that the deposited materials are not connected between the light-emitting regions EA1, EA2, and EA3 and are disconnected from the bank structure BNS between the deposited materials by the tips TIP of the second bank BN2. By forming the materials for forming a specific layer on the entire surface of the display device 10 and then etching and removing the layers formed in the undesired regions, the embodiments of the present disclosure support separately forming different layers in different light-emitting regions EA1, EA2, and EA3. In the display device 10, the embodiments of the present disclosure support forming different light-emitting elements ED1, ED2, and ED3 for each of the light-emitting regions EA1, EA2, and EA3 by a deposition and etching process without using a mask process, omitting unnecessary configurations from the display device 10, and minimizing the area of the non-display region NDA.

[0132] The second bank BN2 may include a metal material different from that of the first bank BN1. The metal material of the second bank BN2 and the metal material of the first bank BN1 are removed together by dry etching. When wet etching is performed, the metal material of the second bank BN2 may be a material having an etching rate much slower than that of the first bank BN1 or not being etched. In an embodiment, the first bank BN1 may include aluminum (Al), an oxide of aluminum (Al), or an alloy of aluminum (Al), and the second bank BN2 may include titanium (Ti), an oxide of titanium (Ti), or an alloy of titanium (Ti).

[0133] The tips TIP of the second bank BN2 may overlap the common electrodes CE1, CE2, and CE3, the light-emitting layers EL1, EL2, and EL3, and the pixel defining layer PDL in a direction perpendicular to the substrate SUB (i.e., the thickness direction DR3 of the substrate SUB). One end and the other end of the common electrodes CE1, CE2, and CE3 may overlap the second bank BN2 in the thickness direction DR3 of the substrate SUB.

[0134] The thin film encapsulation layer TFEL can be disposed on the light emitting elements ED1, ED2, and ED3 and the bank structure BNS, and can cover the plurality of light emitting elements ED1, ED2, and ED3 and the bank structure BNS. The thin film encapsulation layer TFEL can include at least one inorganic thin film to prevent oxygen or moisture from penetrating into the light emitting element layer EML. The thin film encapsulation layer TFEL can include at least one organic film to protect the light emitting element layer EML from foreign substances (such as dust for example).

[0135] In an embodiment, the thin film encapsulation layer TFEL can include a lower inorganic encapsulation layer TFE1, an organic encapsulation layer TFE2, and an upper inorganic encapsulation layer TFE3 stacked in sequence.

[0136] Each of the lower inorganic encapsulation layer TFE1 and the upper inorganic encapsulation layer TFE3 can include one or more inorganic insulating materials. For example, the inorganic insulating material can be alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide (ZnO x , which can be ZnO or ZnO2), silicon oxide, silicon nitride, and / or silicon oxynitride.

[0137] The organic encapsulation layer TFE2 can include a polymer-based material. Examples of the polymer-based material can include acrylic resins, epoxy resins, polyimides, and polyethylene, etc. For example, the organic encapsulation layer TFE2 can include an acrylic resin, for example, polymethyl methacrylate or polyacrylic acid. The organic encapsulation layer TFE2 can be formed by curing monomers or coating polymers.

[0138] The lower inorganic encapsulation layer TFE1 can be disposed on the light emitting elements ED1, ED2, and ED3 and the bank structure BNS. The lower inorganic encapsulation layer TFE1 can include a first inorganic layer TL1, a second inorganic layer TL2, and a third inorganic layer TL3 disposed to correspond to different light emitting regions EA1, EA2, and EA3 respectively. The lower inorganic encapsulation layer TFE1 can optionally further include a fourth inorganic layer TL4 disposed in the second non-display region NDA2 (light transmission region TA) (see Figure 9 ). The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can each include an inorganic insulating material covering the light emitting elements ED1, ED2, and ED3. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can prevent the light emitting elements ED1, ED2, and ED3 from being damaged by external air.

[0139] Since the lower inorganic encapsulation layer TFE1 can be formed by chemical vapor deposition (CVD), the lower inorganic encapsulation layer TFE1 can be formed along the steps (step portions) of the deposition layer. For example, the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can also form a thin film on the lower portion of the undercut formed by the tip TIP of the dam structure BNS. The lower inorganic encapsulation layers TL1, TL2, and TL3 (i.e., the lower inorganic encapsulation layer TFE1) can be disposed along the upper surface, side surface, and lower surface of the second dam BN2, the side surface of the first dam BN1, and the upper surfaces of the common electrodes CE1, CE2, and CE3. The lower inorganic encapsulation layers TL1, TL2, and TL3 can be in contact with the lower surface of the second dam BN2, thereby preventing moisture from external air from permeating.

[0140] The first inorganic layer TL1 can be disposed on the first light-emitting element ED1 and the dam structure BNS surrounding the first light-emitting element ED1 without overlapping with the second light-emitting element ED2 and the third light-emitting element ED3. The second inorganic layer TL2 can be disposed on the second light-emitting element ED2 and the dam structure BNS surrounding the second light-emitting element ED2 without overlapping with the first light-emitting element ED1 and the third light-emitting element ED3. The third inorganic layer TL3 can be disposed on the third light-emitting element ED3 and the dam structure BNS surrounding the third light-emitting element ED3 without overlapping with the first light-emitting element ED1 and the second light-emitting element ED2. The fourth inorganic layer TL4 can overlap with the second non-display area NDA2 (light transmission area TA) without overlapping with the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3.

[0141] The first inorganic layer TL1 can be formed after the first common electrode CE1 is formed, the second inorganic layer TL2 can be formed after the second common electrode CE2 is formed, and the third inorganic layer TL3 can be formed after the third common electrode CE3 is formed. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can be disposed on the dam structure BNS to be spaced apart from each other.

[0142] The lower inorganic encapsulation layers TL1, TL2, and TL3 are disposed on the upper surface and the lower surface of the light-emitting elements ED1, ED2, and ED3 and the second dam BN2 surrounding them, but can be spaced apart from the upper surface of the second dam BN2. That is, the lower inorganic encapsulation layers TL1, TL2, and TL3 can have an undercut structure on the second dam BN2. The separation space between the lower inorganic encapsulation layers TL1, TL2, and TL3 and the upper surface of the second dam BN2 can be a space for removing the materials of the light-emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 deposited on the entire surface.

[0143] The organic encapsulation layer TFE2 is disposed on the second bank BN2 and the lower inorganic encapsulation layers TL1, TL2, and TL3. A part of the organic encapsulation layer TFE2 may be disposed in the separation space between the lower inorganic encapsulation layers TL1, TL2, and TL3 and the upper surface of the second bank BN2. In the region where the second bank BN2 and the lower inorganic encapsulation layers TL1, TL2, and TL3 overlap, the second bank BN2, the organic encapsulation layer TFE2, and the lower inorganic encapsulation layers TL1, TL2, and TL3 may be sequentially disposed. In the tip region, the organic encapsulation layer TFE2 and the lower inorganic encapsulation layers TL1, TL2, and TL3 may be sequentially disposed on the second bank BN2, and the organic encapsulation layer TFE2 may be disposed again on the lower inorganic encapsulation layers TL1, TL2, and TL3. In other words, a part of the organic encapsulation layer TFE2 may be disposed between the upper surface of the second bank BN2 and the lower inorganic encapsulation layers TL1, TL2, and TL3 on the tip TIP of the second bank BN2, and another part of the organic encapsulation layer TFE2 may be disposed on the lower inorganic encapsulation layers TL1, TL2, and TL3.

[0144] In an embodiment, in the display area DA, the entire upper surface of the second bank BN2 may be in contact with the organic encapsulation layer TFE2. The first lower surface of the lower inorganic encapsulation layers TL1, TL2, and TL3 (i.e., the respective first lower surfaces of the lower inorganic encapsulation layers TL1, TL2, and TL3) may be the surface opposite to the upper surface of the second bank BN2 and may be in contact with the organic encapsulation layer TFE2. The organic encapsulation layer TFE2 may be in contact with the side surface of the second bank BN2.

[0145] The upper inorganic encapsulation layer TFE3 may be disposed on the organic encapsulation layer TFE2. The upper inorganic encapsulation layer TFE3 may include alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide (ZnO x , which may be ZnO or ZnO2), silicon oxide, silicon nitride, and / or silicon oxynitride.

[0146] The display device 10 may include a plurality of color filters CF1, CF2, and CF3 disposed on the light-emitting regions EA1, EA2, and EA3. Each of the plurality of color filters CF1, CF2, and CF3 may include a filter pattern region and a light-blocking region. The filter pattern region may be formed such that the filter pattern region overlaps with the light-emitting regions EA1, EA2, and EA3 or the openings of the bank structure BNS, and the filter pattern region may form a light output region from which light emitted from the light-emitting regions EA1, EA2, and EA3 is emitted. The light-blocking region is a region through which light cannot transmit because the plurality of color filters CF1, CF2, and CF3 are stacked thereon.

[0147] The color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3 that are set to correspond to different light-emitting regions EA1, EA2, and EA3, respectively. The color filters CF1, CF2, and CF3 may include colorants, such as dyes or pigments that absorb light in wavelength bands other than a specific wavelength band, and may be set to correspond to the colors of light emitted from the light-emitting regions EA1, EA2, and EA3. For example, the first color filter CF1 may be a red color filter that is set such that the first color filter CF1 overlaps with the first light-emitting region EA1 and may transmit only the first red light. The second color filter CF2 may be a green color filter that is set such that the second color filter CF2 overlaps with the second light-emitting region EA2 and may transmit only the second green light. The third color filter CF3 may be a blue color filter that is set such that the third color filter CF3 overlaps with the third light-emitting region EA3 and may transmit only the third blue light.

[0148] In the display device 10, since the color filters CF1, CF2, and CF3 are set to overlap with each other, the intensity of the reflected light caused by external light can be reduced. In addition, the color of the light reflected by external light can also be controlled by adjusting the arrangement, shape, and area of the color filters CF1, CF2, and CF3 in the plan view.

[0149] An outer coating OC may be provided on the color filters CF1, CF2, and CF3 to flatten the upper ends of the color filters CF1, CF2, and CF3. The outer coating OC may be a colorless light-transmissive layer that has no color in the visible light band. For example, the outer coating OC may include a colorless light-transmissive organic material, such as an acrylic resin.

[0150] In an embodiment, the display panel 100 may include a second non-display area NDA2 (which is a light-transmissive area TA through which light is transmitted) inside the display area DA.

[0151] Figure 7 is an enlarged view of the second non-display area NDA2 of the display panel 100 (see Figure 2 ). Figure 7 is Figure 2 an enlarged plan view of the area A1 of Figure 8 and Figure 7 is a cross-sectional view showing an example of the display device 10 (see Figure 4 ) taken along II-II' of Figure 9 is Figure 8 an enlarged cross-sectional view of the area A3 of

[0152] Refer to Figures 7 to 9, the display panel 100 includes a display area DA in which a light-emitting element layer EML is disposed and a second non-display area NDA2 in which the light-emitting element layer EML is not disposed. The second non-display area NDA2 is a light-transmission area TA through which light is transmitted, and a configuration through which light cannot be transmitted can be removed from the second non-display area NDA2. In an embodiment, the cover window CW, the thin-film encapsulation layer TFEL, and the thin-film transistor layer TFTL may overlap with the second non-display area NDA2 (light-transmission area TA). The thin-film transistor layer TFTL may be exposed in the light-transmission area TA without being covered by the light-emitting element layer EML.

[0153] The optical device 500 may be disposed in the second non-display area NDA2 (light-transmission area TA). Light incident from the outside may pass through some layers in the light-transmission area TA and reach the optical device 500. As shown in the drawings, a part of the second non-display area NDA2 of the substrate SUB is removed and the optical device 500 is disposed at that position, but the embodiments of the present disclosure are not limited thereto. The optical device 500 may be disposed on the rear surface of the substrate SUB without removing a part of the substrate SUB.

[0154] At the boundary between the second non-display area NDA2 and the display area DA, a bank structure BNS may be disposed between the light-emitting areas EA1, EA2, and EA3 (see Figure 5 ) and the second non-display area NDA2, and may have an asymmetric cross-section. The second bank BN2 includes a tip TIP (see Figure 6 ) protruding toward the light-emitting areas EA1, EA2, and EA3, but does not have an area protruding toward the second non-display area NDA2.

[0155] The first bank BN1 may include a surface facing the light-emitting areas EA1, EA2, and EA3 (see Figure 5) the first side surface BN1_S1 facing the first non-display area NDA1 and the second side surface BN1_S2 facing the second non-display area NDA2. The second bank BN2 may include a first side surface BN2_S1 facing the light-emitting areas EA1, EA2, and EA3 and a second side surface BN2_S2 facing the second non-display area NDA2. The first side surface BN1_S1 and the second side surface BN1_S2 of the first bank BN1 may be surfaces opposite to each other on a cross-section of the substrate SUB cut in the thickness direction DR3. The first side surface BN2_S1 and the second side surface BN2_S2 of the second bank BN2 may be surfaces opposite to each other on a cross-section of the substrate SUB cut in the thickness direction DR3. The first side surface BN2_S1 of the second bank BN2 may protrude toward the light-emitting areas EA1, EA2, and EA3 compared to the first side surface BN1_S1 of the first bank BN1, and the second side surface BN2_S2 of the second bank BN2 may be aligned with the second side surface BN1_S2 of the first bank BN1. Since the bank structure BNS through which light does not pass does not have a tip toward the light-transmissive area TA, the display device 10 may have a wide light-transmissive area TA.

[0156] The pixel defining layer PDL may have an asymmetric cross-section at the boundary between the second non-display area NDA2 and the display area DA. The pixel defining layer PDL may include a first side surface PDL_S1 facing the light-emitting areas EA1, EA2, and EA3 and a second side surface PDL_S2 facing the second non-display area NDA2. The first side surface PDL_S1 and the second side surface PDL_S2 of the pixel defining layer PDL may be surfaces opposite to each other on a cross-section of the substrate SUB cut in the thickness direction DR3. The pixel defining layer PDL may have a first side surface PDL_S1 that protrudes toward the light-emitting areas EA1, EA2, and EA3 compared to the first bank BN1, and may have a second side surface PDL_S2 that is aligned with the second side surface BN1_S2 of the first bank BN1 toward the second non-display area NDA2 (light-transmissive area TA). The first side surface PDL_S1 of the pixel defining layer PDL, the first side surface BN1_S1 of the first bank BN1, and the first side surface BN2_S1 of the second bank BN2 are not aligned with each other, but the second side surface PDL_S2 of the pixel defining layer PDL, the second side surface BN1_S2 of the first bank BN1, and the second side surface BN2_S2 of the second bank BN2 may be aligned with each other.

[0157] At least in Figure 9As shown, the first side surface BN2_S1 of the second bank BN2 faces the light-emitting region (e.g., the light-emitting region EA1, the light-emitting region EA2, or the light-emitting region EA3). The second side surface BN2_S2 of the second bank BN2 faces the second non-display region NDA2 (light-transmitting region TA). In another expression, the first side surface BN2_S1 of the second bank BN2 protrudes into the light-emitting region (e.g., the light-emitting region EA1, the light-emitting region EA2, or the light-emitting region EA3) or is included in the light-emitting region (e.g., the light-emitting region EA1, the light-emitting region EA2, or the light-emitting region EA3), and the second side surface BN2_S2 of the second bank BN2 protrudes into the second non-display region NDA2 (light-transmitting region TA) or is included in the second non-display region NDA2 (light-transmitting region TA).

[0158] The fourth inorganic layer TL4 may be disposed between the organic encapsulation layer TFE2 and the thin-film transistor layer TFTL in the second non-display region NDA2 (light-transmitting region TA). The fourth inorganic layer TL4 may cover the outer surfaces of the bank structure BNS, the pixel definition layer PDL, and the thin-film transistor layer TFTL. The fourth inorganic layer TL4 may be disposed on the second side surface BN2_S2 of the second bank BN2, the second side surface BN1_S2 of the first bank BN1, and the second side surface PDL_S2 of the pixel definition layer PDL. A part of the fourth inorganic layer TL4 may be disposed on the second bank BN2 and spaced apart from the upper surface of the second bank BN2. The organic encapsulation layer TFE2 may be disposed in the separation space between the fourth inorganic layer TL4 and the upper surface of the second bank BN2. In an embodiment, the fourth inorganic layer TL4 may be directly formed on the thin-film transistor layer TFTL and may be in contact with the second passivation layer PAS2 of the thin-film transistor layer TFTL.

[0159] The fourth inorganic layer TL4 may be formed during the process of forming any one of the first inorganic layer TL1, the second inorganic layer TL2 (see Figure 5 ), and the third inorganic layer TL3 (see Figure 5 ) of the lower inorganic encapsulation layer TFE1 (see Figure 5 ), and may include the same material or film quality as the one inorganic layer. The fourth inorganic layer TL4 may be spaced apart from the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3, but is not limited thereto. The fourth inorganic layer TL4 may also be connected to any one of the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3.

[0160] Figure 10 and Figure 11 are enlarged cross-sectional views of region A3 showing another example of the display panel 100 (see Figure 3 ). That is, Figure 8 is related to Figure 10 is withFigure 9 A magnified cross-sectional view of a region A3_1 similar to region A3, and Figure 11 is a magnified cross-sectional view of a region A3_2 similar to region A3 of Figure 9 . To increase the light transmittance in the second non-display region NDA2 (light transmission region TA), a part of the thin film transistor layer TFTL can be removed. After removing a part of the thin film transistor layer TFTL by a laser process, a thin film encapsulation layer TFEL can be formed.

[0161] Figure 10 The embodiment of Figure 9 differs from the embodiment of

[0162] in that the second passivation layer PAS2 and the first passivation layer PAS1 of the thin film transistor layer TFTL are removed in the second non-display region NDA2 (light transmission region TA) and the second interlayer insulating layer ILD2 is exposed. Figure 10 Referring to

[0163] Figure 11 The embodiment of Figure 9 differs from the embodiment of

[0164] in that the second passivation layer PAS2, the first passivation layer PAS1, the second interlayer insulating layer ILD2 and the first interlayer insulating layer ILD1 of the thin film transistor layer TFTL are removed in the second non-display region NDA2 (light transmission region TA) and the gate insulating layer GI is exposed. Figure 11 Referring to

[0165] The present disclosure is not limited to Figure 10 and Figure 11In the example aspect shown, some layers of the thin film transistor layer TFTL may be removed from the second non-display area NDA2 (light transmission area TA) to increase the light transmittance.

[0166] Figure 12 is an enlarged cross-sectional view of region A3 of another example of the display panel 100 (see Figure 3 ). That is, Figure 8 is an enlarged cross-sectional view of region A3_3 similar to region A3 of Figure 12 is similar to Figure 9 . Figure 12 The embodiment of Figure 9 differs from the embodiment of Figure 9 in that the fourth inorganic layer TL4 (see

[0167] When the fourth inorganic layer TL4 includes a plurality of inorganic films having different refractive indexes, the transmittance of light passing through the second interlayer insulating film 142 may be reduced due to the difference in the refractive indexes of the plurality of inorganic films. Alternatively, when the fourth inorganic layer TL4 is a single-layer film different from the second passivation layer PAS2, the transmittance of light passing through the fourth inorganic layer TL4 may be reduced due to the difference in the refractive indexes of the fourth inorganic layer TL4 and the second passivation layer PAS2.

[0168] As Figure 12 shown, based on the formation of the organic encapsulation layer TFE2 directly on the thin film transistor layer TFTL in the second non-display area NDA2 (light transmission area TA), the embodiments of the present disclosure can prevent the transmittance of light passing through the light transmission area TA from being reduced due to the fourth inorganic layer TL4.

[0169] Figure 13 is an enlarged cross-sectional view of region A3 of another example of the display panel 100 (see Figure 3 ). That is, Figure 8 is an enlarged cross-sectional view of region A3_5 similar to region A3 of Figure 13 is similar to Figure 9 . Figure 13 The embodiment of Figure 12 differs from the embodiment of

[0170] in that an enhancement layer TFE4 is further included between the organic encapsulation layer TFE2 and the thin film transistor layer TFTL, between the organic encapsulation layer TFE2 and the lower inorganic encapsulation layer TL1, and between the organic encapsulation layer TFE2 and the second bank BN2. Figure 5 The enhancement layer TFE4 may be formed on the entire surface of the substrate SUB (see Figure 5)(e.g., the lower inorganic encapsulation layers TL1, TL2 (see Figure 5 ) and TL3 (see Figure 5 )) of the lower inorganic encapsulation layer TFE1 of the lower inorganic encapsulation layer, and between the organic encapsulation layer TFE2. The reinforcing layer TFE4 can prevent the lower inorganic encapsulation layer TFE1 from deforming or separating from the lower surface of the tip TIP of the second bank BN2 (see Figure 6 ). The reinforcing layer TFE4 can be a part of the thin film encapsulation layer TFEL, and can enhance the encapsulation effect of the lower inorganic encapsulation layers TL1, TL2, and TL3.

[0171] The reinforcing layer TFE4 can have excellent step coverage and cover the undercut structure of the lower inorganic encapsulation layer TFE1. In other words, the reinforcing layer TFE4 can also be formed in the separation space between the lower inorganic encapsulation layer TFE1 and the second bank BN2. The reinforcing layer TFE4 can be disposed on the second side surface BN2_S2 of the second bank BN2, the second side surface BN1_S2 of the first bank BN1, and the second side surface PDL_S2 of the pixel defining layer PDL. The reinforcing layer TFE4 can be in direct contact with the second passivation layer PAS2 of the thin film transistor layer TFTL.

[0172] The reinforcing layer TFE4 can include silicon oxide, aluminum oxide, zirconium oxide, hafnium oxide, cesium oxide, iron oxide, indium oxide, molybdenum oxide, or tin oxide, but is not limited thereto.

[0173] Hereinafter, the process (method) of manufacturing the display device 10 according to an embodiment will be described with reference to other drawings.

[0174] In the description of the process (method), operations can be performed in an order different from the order shown and / or described, or operations can be performed in a different order or at different times. Certain operations can also be excluded from the process, one or more operations can be repeated, or other operations can be added. Descriptions such as "can be disposed" and "can be formed" of elements include methods, processes, and techniques for disposing elements, forming elements, positioning elements, and modifying elements, etc. according to the example aspects described herein.

[0175] Figures 14 to 20 are cross-sectional views showing in sequence the process of manufacturing the display device 10 according to an embodiment (see Figure 2 ). Figures 14 to 20 shows the process of forming a light emitting element layer EML (see Figure 8 ) and a part of the lower inorganic encapsulation layer TFE1 (see Figure 8 ) at the boundary and periphery of the display area DA and the second non-display area NDA2 of the display device 10. Hereinafter, the formation process of each layer in the process of manufacturing the display device 10 will be omitted, and the formation order of each layer will be described.

[0176] Referring to Figure 14 , the process may include forming a first pixel electrode AE1, a sacrificial layer SFL, a pixel defining material layer PDLL, and a plurality of bank material layers BNL1 and BNL2 on a second passivation layer PAS2. The bank material layers BNL1 and BNL2 may be formed integrally. For example, the process may include forming the bank material layers BNL1 and BNL2 such that the bank material layers BNL1 and BNL2 completely cover the second passivation layer PAS2.

[0177] Although not shown in the drawings, a thin film transistor layer TFTL (see Figure 5 ) may be disposed on a substrate SUB (see Figure 5 ), and the structure of the thin film transistor layer TFTL is the same as the structure described herein with reference to Figure 5 . For the sake of brevity, its repeated description is omitted.

[0178] Next, referring to Figure 15 , the process may include forming a photoresist PR on the second bank material layer BNL2, and the process may include performing a first etching process to remove a portion of the second bank material layer BNL2. The photoresist PR is applied on the second bank material layer BNL2, and exposes a light emitting region EA1, EA2, and EA3 (see Figure 5 ) and a portion of a second non-display region NDA2. The process may include performing a halftone exposure process. The halftone exposure process may remove the portion of the second bank material layer BNL2 that is not covered by the photoresist PR, and at the same time, remove a portion of the photoresist PR on the edge of the second non-display region NDA2. Thus, for example, the process may include reducing the thickness of the photoresist PR in one or more regions of the photoresist PR. Based on the first etching process, a first bank material layer BNL1 is exposed relative to the light emitting regions EA1, EA2, and EA3 and the second non-display region NDA2. The thickness of the photoresist PR at the edge of the second non-display region NDA2 (e.g., the edge of the second non-display region NDA2 adjacent to the display region DA) may be smaller than the thickness of the photoresist PR at the edge of the display region DA (e.g., the edge of the display region DA adjacent to the second non-display region NDA2).

[0179] Next, referring to Figure 16 , the process may include performing a second etching process to remove the portion of the first bank material layer BNL1 that is not covered by the photoresist PR. In an embodiment, the second etching process may be an anisotropic dry etching process. Based on the second etching process, a pixel defining material layer PDLL is exposed relative to the light emitting regions EA1, EA2, and EA3 (see Figure 5 ) and the second non-display region NDA2.

[0180] Next, referring to Figure 17 , the process may include forming an undercut structure of the first bank material layer BNL1 by a third etching process. The first bank material layer BNL1 may have an etching rate faster than that of the second bank material layer BNL2, and based on the third etching process, a side surface of the second bank material layer BNL2 may be formed such that the side surface of the second bank material layer BNL2 protrudes compared to the side surface of the first bank material layer BNL1. The undercut structure of the first bank material layer BNL1 may be formed below the second bank material layer BNL2 by the third etching process. In an embodiment, the third etching process may be an isotropic wet etching. The third etching process may use an alkaline etchant.

[0181] Next, referring to Figure 18 , the process may include removing the photoresist PR and the bank structure BNS (i.e., the first bank BN1 and the second bank BN2) of the second non-display area NDA2 by a fourth etching process. The fourth etching process may remove the relatively thin photoresist PR and the second bank material layer BNL2 (see Figure 17 ) and the first bank material layer BNL1 (see Figure 17 ) below the photoresist PR. By the fourth etching process, a bank structure BNS having an asymmetric cross-section may be obtained. Based on the fourth etching process, the second side surface BN1_S2 of the first bank BN1 and the second side surface BN2_S2 of the second bank BN2 may be aligned, and the first side surface BN2_S1 of the second bank BN2 may protrude compared to the first side surface BN1_S1 of the first bank BN1 (as marked at Figure 9 ). In an embodiment, the fourth etching process may be an anisotropic dry etching process.

[0182] Next, referring to Figure 19 , the process may include performing a fifth etching process that may remove the photoresist PR, remove the light-emitting regions EA1, EA2, and EA3 (see Figure 5 ) and the pixel defining layer PDL of the second non-display area NDA2, and expose the sacrificial layer SFL (see Figure 18 ). Next, the process may include removing a part of the sacrificial layer SFL (for example, as shown previously at Figure 18 ), and exposing the first pixel electrode AE1.

[0183] The sacrificial layer SFL may protect the first pixel electrode AE1 from plasma during the dry etching process. In some embodiments, the sacrificial layer SFL is not completely removed in the fifth etching process, and a part of the sacrificial layer SFL may remain as some residual pattern RP between the pixel defining layer PDL and the first pixel electrode AE1.

[0184] Next, as shown in Figure 20As shown, the process may include forming a first light-emitting element ED1 by stacking a first light-emitting layer EL1 and a first common electrode CE1 on a first pixel electrode AE1. In this case, since the first light-emitting layer EL1 and the first common electrode CE1 are formed on the entire surface of the substrate SUB (see Figure 5 ), the process may further include forming a first light-emitting pattern layer (not shown) and a first electrode pattern layer (not shown) including the same materials as the first light-emitting layer EL1 and the first common electrode CE1 on the second bank BN2.

[0185] The material deposited on the entire surface of the substrate SUB is disconnected by the protruding side surface or tip TIP of the second bank BN2 (see Figure 6 ), so that the first light-emitting layer EL1 in the opening and the first light-emitting pattern layer on the second bank BN2 can be separated. The process may include forming the first electrode pattern on the first light-emitting pattern layer while forming the first common electrode CE1 on the first light-emitting layer EL1. In this case, for example, the process may also include sequentially forming the first light-emitting pattern layer and the first electrode pattern layer in the second non-display area NDA2.

[0186] Next, the process may include forming a first inorganic material layer covering the first common electrode CE1 and the first electrode pattern layer. In an embodiment, the process may include forming the first inorganic material layer by chemical vapor deposition (CVD). The process may include forming the first inorganic material layer along the step (step portion) between the first light-emitting element ED1 and the bank structure BNS.

[0187] Next, the process may include removing a part of the first inorganic material layer, and the process may include removing the first electrode pattern layer and the first light-emitting pattern layer on the second bank BN2. The process may include forming a photoresist (not shown) as a mask in the region overlapping with the first light-emitting region EA1 and the edge region surrounding the first light-emitting region EA1, and further removing the first inorganic material layer not covered by the mask. Through such a process, the first inorganic layer TL1 remains in the region overlapping with the first light-emitting region EA1 and the edge region surrounding the first light-emitting region EA1. The process may include removing the first light-emitting pattern layer and the first electrode pattern layer provided between the upper surface of the first inorganic layer TL1 and the second bank material layer BNL2, and further forming an undercut structure of the first inorganic layer TL1. In this case, the process may further include removing the first light-emitting pattern layer and the first electrode pattern layer in the second non-display area NDA2.

[0188] In some embodiments, if necessary, the process may include forming the first inorganic layer TL1 (see Figure 5 ), the second inorganic layer TL2 (see Figure 5 ) and the third inorganic layer TL3 (seeFigure 5 ) during the process of () to form a fourth inorganic layer TL4 in the second non-display area NDA2 (see Figure 9 ). Optionally, or additionally, in some embodiments, when necessary, the process may include forming a bank structure BNS having an asymmetric cross-section (see Figure 10 ) and then removing a part of the thin film transistor layer TFTL (see Figure 10 ) from the second non-display area NDA2 (see Figure 10 ) by performing a laser process.

[0189] Embodiments of the present disclosure have been described above with reference to the accompanying drawings. However, those of ordinary skill in the art to which the present disclosure pertains will understand that various modifications and changes can be made without departing from the technical spirit or basic characteristics of the present disclosure. Therefore, it should be understood that the embodiments described herein are illustrative in all aspects and not restrictive.

Claims

1. A display device, wherein, The display device includes: a substrate; a pixel electrode disposed on the substrate; a pixel defining layer disposed on an edge of the pixel electrode; a light-emitting layer disposed on the pixel electrode; a common electrode disposed on the light-emitting layer; a first bank disposed on the pixel defining layer, and the first bank includes a first side surface adjacent to the common electrode and a second side surface opposite to the first side surface; and a second bank disposed on the first bank, and the second bank includes a first side surface partially overlapping with the common electrode and a second side surface opposite to the first side surface of the second bank, wherein: the first side surface of the second bank protrudes more than the first side surface of the first bank, and the second side surface of the second bank is aligned with the second side surface of the first bank.

2. The display device according to claim 1, wherein: the pixel defining layer includes a first side surface and a second side surface opposite to the first side surface of the pixel defining layer, the first side surface of the pixel defining layer protrudes more than the first side surface of the first bank, and the second side surface of the pixel defining layer is aligned with the second side surface of the first bank.

3. The display device according to claim 1, wherein: the substrate includes a light-transmitting region and a display region surrounding the light-transmitting region, wherein the display region includes a light-emitting region, the first side surface of the second bank faces the light-emitting region, and the second side surface of the second bank faces the light-transmitting region.

4. The display device according to claim 3, wherein, The display device further includes a thin-film transistor layer disposed between the pixel electrode and the substrate, wherein the thin-film transistor layer is exposed in the light-transmitting region.

5. The display device according to claim 4, wherein, The display device further includes a thin-film encapsulation layer disposed on the thin-film transistor layer, the second bank, and the common electrode.

6. The display device according to claim 5, wherein, The thin-film encapsulation layer is in contact with the thin-film transistor layer.

7. The display device according to claim 5, wherein: the thin-film encapsulation layer includes: a lower inorganic encapsulation layer disposed on the common electrode; and an organic encapsulation layer disposed on the lower inorganic encapsulation layer, and the organic encapsulation layer is in contact with the thin-film transistor layer in the light-transmitting region.

8. The display device according to claim 5, wherein: the thin-film transistor layer includes a buffer layer, a gate insulating layer, an interlayer insulating layer, and a passivation layer sequentially disposed on the substrate, and the thin-film encapsulation layer is in contact with the passivation layer and the interlayer insulating layer.

9. The display device according to claim 5, wherein, The thin-film encapsulation layer includes: a lower inorganic encapsulation layer disposed on the common electrode; a reinforcing layer disposed on the lower inorganic encapsulation layer, the second bank, and the thin-film transistor layer; and an organic encapsulation layer disposed on the reinforcing layer.

10. The display device according to claim 4, wherein, The display device further includes: a first inorganic layer disposed on the common electrode and the first side surface of the first bank; and a second inorganic layer disposed on the second side surface of the first bank and the thin-film transistor layer.

11. The display device according to claim 10, wherein, The first inorganic layer and the second inorganic layer are spaced apart from an upper surface of the second bank.

12. The display device according to claim 3, wherein, The display device further includes an optical device overlapping with the light transmission region.

13. The display device according to claim 1, wherein, The common electrode contacts the first side surface of the first bank.

14. A display device, wherein, The display device includes: a substrate including a light transmission region and a display region surrounding the light transmission region, wherein the display region includes a light emitting region; a thin film transistor layer disposed on the substrate; a light emitting element disposed on the thin film transistor layer in the light emitting region; a first bank surrounding the light emitting element, disposed on the thin film transistor layer, and the first bank includes a first side surface facing the light emitting region and a second side surface facing the light transmission region; and a second bank disposed on the first bank, and the second bank includes a first side surface facing the light emitting region and a second side surface facing the light transmission region, wherein the first side surface of the second bank protrudes more than the first side surface of the first bank, and the second side surface of the second bank is aligned with the second side surface of the first bank.

15. The display device according to claim 14, wherein, The first bank and the second bank overlap with the display region and do not overlap with the light transmission region.

16. The display device according to claim 14, wherein: the light emitting element includes a pixel electrode, a light emitting layer, and a common electrode sequentially disposed on the thin film transistor layer, and one end of the common electrode contacts the first side surface of the first bank.

17. A method of manufacturing a display device, wherein, The method includes: forming a pixel electrode on a substrate; forming a sacrificial layer on the pixel electrode; forming a pixel defining material layer on the sacrificial layer and the substrate; forming a first bank material layer on the pixel defining material layer; forming a second bank material layer on the first bank material layer; forming a photoresist on the second bank material layer; and reducing the thickness of the photoresist in some regions of the photoresist.

18. The method according to claim 17, wherein, The reducing the thickness of the photoresist in some regions of the photoresist includes: performing a halftone exposure process, wherein based on the performing of the halftone exposure process, the portion of the second bank material layer not covered by the photoresist is etched.

19. The method according to claim 17, wherein, The method further includes: etching the portion of the first bank material layer not covered by the photoresist; and etching the side surface of the first bank material layer, wherein etching the side surface of the first bank material layer exposes the lower surface of the second bank material layer.

20. The method according to claim 19, wherein The method further includes removing some portions of the second bank material layer and some portions of the first bank material layer so that the side surface of the second bank material layer and the side surface of the first bank material layer are aligned.

Images