Display device

Abstract

The invention relates to a display device. According to one embodiment, a display device includes: a substrate; a first lower electrode disposed above the substrate; an inorganic insulating layer covering a peripheral edge portion of the first lower electrode; a partition wall having a lower portion disposed on the inorganic insulating layer and formed of a conductive material, and an upper portion disposed on the lower portion and protruding from each of a first side surface of the lower portion and a second side surface on the opposite side to the first side surface; a first laminated film including a first organic layer in contact with the first lower electrode, and a first upper electrode disposed on the first organic layer and in contact with the lower portion; a first barrier layer which is disposed on the first laminated film, is in contact with the first side surface, extends above the partition wall, forms a gap with the upper portion, and is formed of a first inorganic insulating material; a first sealing layer that overlaps the first barrier layer and is formed of a second inorganic insulating material different from the first inorganic insulating material; and a resin layer that covers the first sealing layer and fills the gap.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority based on Japanese Patent Application No. 2024 - 006221 filed on January 18, 2024, and incorporates by reference all of the descriptions recited in the Japanese application. Technical field

[0003] Embodiments of the present invention relate to a display device. Background art

[0004] In recent years, display devices using organic light - emitting diodes (OLEDs) as display elements have been put into practical use. The display element includes a pixel circuit including thin - film transistors, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. The organic layer includes functional layers such as a hole - transporting layer and an electron - transporting layer in addition to a light - emitting layer.

[0005] In the process of manufacturing such a display element, techniques for suppressing a reduction in reliability are required. Summary of the invention

[0006] An object of an embodiment is to provide a display device capable of suppressing a reduction in reliability.

[0007] According to one embodiment, a display device includes:

[0008] a substrate; a first lower electrode disposed above the substrate; an inorganic insulating layer covering a peripheral portion of the first lower electrode; a partition wall having a lower portion disposed on the inorganic insulating layer and formed of a conductive material, and an upper portion disposed above the lower portion and protruding from a first side surface of the lower portion and a second side surface opposite to the first side surface; a first stacked film including a first organic layer in contact with the first lower electrode and a first upper electrode disposed above the first organic layer and in contact with the lower portion; a first barrier layer disposed above the first stacked film, in contact with the first side surface, extending above the partition wall, forming a gap between the first barrier layer and the upper portion, and formed of a first inorganic insulating material; a first sealing layer overlapping the first barrier layer and formed of a second inorganic insulating material different from the first inorganic insulating material; and a resin layer covering the first sealing layer and filling the gap.

[0009] According to one embodiment, a display device includes:

[0010] A substrate; a first lower electrode disposed above the substrate; an inorganic insulating layer covering a peripheral portion of the first lower electrode; a partition wall having a lower portion disposed on the inorganic insulating layer and formed of a conductive material, and an upper portion disposed above the lower portion and protruding from a first side surface of the lower portion and a second side surface opposite to the first side surface; a first stacked film including a first organic layer in contact with the first lower electrode and a first upper electrode disposed above the first organic layer and in contact with the lower portion; a resin layer disposed above the upper portion; a first barrier layer overlapping with the resin layer and formed of a first inorganic insulating material; and a first sealing layer overlapping with the first barrier layer and formed of a second inorganic insulating material different from the first inorganic insulating material.

[0011] According to the embodiment, a display device capable of suppressing a reduction in reliability can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 FIG. is a diagram showing a configuration example of a display device DSP.

[0013] Figure 2 FIG. is an example diagram showing the layout of sub-pixels SP1, SP2, and SP3.

[0014] Figure 3 is along Figure 2 A schematic cross-sectional view of the display device DSP taken along line A-B in

[0015] Figure 4 FIG. is a diagram for explaining a manufacturing method of the display device DSP.

[0016] Figure 5 FIG. is a diagram for explaining a manufacturing method of the display device DSP.

[0017] Figure 6 FIG. is a diagram for explaining a manufacturing method of the display device DSP.

[0018] Figure 7 FIG. is a diagram for explaining a manufacturing method of the display device DSP.

[0019] Figure 8 FIG. is a diagram for explaining a manufacturing method of the display device DSP.

[0020] Figure 9 FIG. is a diagram for explaining a manufacturing method of the display device DSP.

[0021] Figure 10 FIG. is a diagram for explaining a manufacturing method of the display device DSP.

[0022] Figure 11 FIG. is a diagram for explaining a manufacturing method of the display device DSP.

[0023] Figure 12 It is a diagram for explaining a manufacturing method of a display device DSP.

[0024] Figure 13 It is a diagram for explaining a manufacturing method of a display device DSP.

[0025] Figure 14 It is a diagram for explaining a manufacturing method of a display device DSP.

[0026] Figure 15 It is a diagram for explaining a manufacturing method of a display device DSP.

[0027] Figure 16 It is a diagram for explaining a manufacturing method of a display device DSP.

[0028] Figure 17 It is a diagram for explaining a manufacturing method of a display device DSP.

[0029] Figure 18 It is a diagram for explaining a manufacturing method of a display device DSP.

[0030] Figure 19 It is a diagram for explaining a manufacturing method of a display device DSP.

[0031] Figure 20 It is a diagram for explaining a manufacturing method of a display device DSP.

[0032] Figure 21 It is a cross-sectional view showing another configuration example of a display device DSP.

[0033] Figure 22 It is a cross-sectional view showing another configuration example of a display device DSP.

[0034] Figure 23 It is a cross-sectional view showing another configuration example of a display device DSP.

[0035] Figure 24 It is a cross-sectional view showing another configuration example of a display device DSP. Detailed implementation mode

[0036] One implementation mode will be described with reference to the accompanying drawings.

[0037] The disclosure is merely an example, and appropriate modifications that can be easily conceived by those skilled in the art to maintain the gist of the invention are of course included within the scope of the present invention. In addition, regarding the drawings, for the sake of clearer explanation, the width, thickness, shape, etc. of each part may sometimes be schematically represented, but this is merely an example and does not limit the interpretation of the present invention. In addition, in this specification and each figure, for components that perform the same or similar functions as the components described in the drawings that have already appeared, there are cases where the same reference numerals are marked and repeated detailed descriptions are appropriately omitted.

[0038] It should be noted that, for ease of understanding, the X-axis, Y-axis, and Z-axis that are orthogonal to each other are depicted in the drawings as needed. The direction along the X-axis is referred to as the first direction X, the direction along the Y-axis is referred to as the second direction Y, and the direction along the Z-axis is referred to as the third direction Z. Viewing various elements parallel to the third direction Z is referred to as a top view.

[0039] The display device of the present embodiment is an organic electroluminescent display device having an organic light-emitting diode (OLED) as a display element, and can be mounted on a television, a personal computer, a vehicle-mounted device, a tablet terminal, a smartphone, a mobile phone terminal, etc.

[0040] Figure 1 It is a diagram showing a configuration example of the display device DSP.

[0041] The display device DSP has a display panel PNL on an insulating substrate 10. The display panel PNL has a display area DA for displaying an image and a peripheral area SA outside the display area DA. The substrate 10 can be glass or a flexible resin film.

[0042] In the present embodiment, the shape of the substrate 10 when viewed from above is rectangular. However, the shape of the substrate 10 when viewed from above is not limited to a rectangle, and can also be other shapes such as a square, a circle, or an ellipse.

[0043] The display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. The pixel PX includes a plurality of sub-pixels SP. In one example, the pixel PX includes a sub-pixel SP1 of a first color, a sub-pixel SP2 of a second color, and a sub-pixel SP3 of a third color. The first color, the second color, and the third color are different from each other. It should be noted that the pixel PX may also include sub-pixels SP of other colors such as white together with or instead of any one of the sub-pixels SP1, SP2, and SP3.

[0044] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switch elements formed of thin film transistors, for example.

[0045] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and the drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the driving transistor 3 and the capacitor 4. In the driving transistor 3, one of the source electrode and the drain electrode is connected to the power supply line PL and the capacitor 4, and the other is connected to the anode of the display element DE.

[0046] Note that the configuration of the pixel circuit 1 is not limited to the illustrated example. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0047] The display element DE is an organic light emitting diode (OLED) as a light emitting element, and is sometimes referred to as an organic EL element.

[0048] The peripheral area SA has a plurality of terminals TE arranged in one direction. In the illustrated example, the plurality of terminals TE are arranged along the first direction X. Each of the terminals TE extends in the second direction Y, but is not limited thereto. Such a plurality of terminals TE are electrically connected to a flexible printed circuit board and an IC chip, for example.

[0049] Figure 2 It is a diagram showing an example of the layout of the sub-pixels SP1, SP2, and SP3.

[0050] In the illustrated example, the sub-pixels SP2 and SP3 are arranged in the second direction Y. The sub-pixels SP1 and SP2 are arranged in the first direction X, and the sub-pixels SP1 and SP3 are arranged in the first direction X.

[0051] When the sub-pixels SP1, SP2, and SP3 have such a layout, columns in which the sub-pixels SP2 and SP3 are alternately arranged in the second direction Y and columns in which a plurality of sub-pixels SP1 are arranged in the second direction Y are formed in the display area DA. These columns are alternately arranged in the first direction X.

[0052] Note that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to Figure 2 the example. As another example, the sub-pixels SP1, SP2, and SP3 in each pixel PX may also be arranged in sequence in the first direction X.

[0053] An inorganic insulating layer 5 and partition walls 6 are disposed in a display area DA. The inorganic insulating layer 5 has openings AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3, respectively. The inorganic insulating layer 5 having these openings AP1, AP2, and AP3 is sometimes referred to as ribs.

[0054] The partition walls 6 overlap the inorganic insulating layer 5 in a plan view. The partition walls 6 are formed in a lattice shape surrounding the openings AP1, AP2, and AP3. The partition walls 6 may also have openings in the sub-pixels SP1, SP2, and SP3 similarly to the inorganic insulating layer 5. The partition walls 6 have conductivity and are electrically connected to a terminal TE having a common potential among a plurality of terminals TE shown in Figure 1 the figure.

[0055] The sub-pixels SP1, SP2, and SP3 each include display elements DE1, DE2, and DE3 as a display element DE.

[0056] The display element DE1 of the sub-pixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that respectively overlap the opening AP1. A peripheral portion of the lower electrode LE1 is covered by the inorganic insulating layer 5. The lower electrode LE1, the organic layer OR1, and the upper electrode UE1 are surrounded by the partition walls 6 in a plan view. Peripheral portions of the organic layer OR1 and the upper electrode UE1 each overlap the inorganic insulating layer 5 in a plan view. The organic layer OR1 includes, for example, a light-emitting layer that emits light in a blue wavelength region.

[0057] The display element DE2 of the sub-pixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that respectively overlap the opening AP2. A peripheral portion of the lower electrode LE2 is covered by the inorganic insulating layer 5. The lower electrode LE2, the organic layer OR2, and the upper electrode UE2 are surrounded by the partition walls 6 in a plan view. Peripheral portions of the organic layer OR2 and the upper electrode UE2 each overlap the inorganic insulating layer 5 in a plan view. The organic layer OR2 includes, for example, a light-emitting layer that emits light in a green wavelength region.

[0058] The display element DE3 of the sub-pixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that respectively overlap the opening AP3. A peripheral portion of the lower electrode LE3 is covered by the inorganic insulating layer 5. The lower electrode LE3, the organic layer OR3, and the upper electrode UE3 are surrounded by the partition walls 6 in a plan view. Peripheral portions of the organic layer OR3 and the upper electrode UE3 each overlap the inorganic insulating layer 5 in a plan view. The organic layer OR3 includes, for example, a light-emitting layer that emits light in a red wavelength region.

[0059] In the illustrated example, the outer shapes of the lower electrodes LE1, LE2, and LE3 are represented by dashed lines, and the outer shapes of the organic layers OR1, OR2, and OR3 and the upper electrodes UE1, UE2, and UE3 are represented by single-dot dashed lines. It should be noted that the outer shapes of the illustrated lower electrodes, organic layers, and upper electrodes do not necessarily reflect the exact shapes.

[0060] The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anodes of display elements. The upper electrodes UE1, UE2, and UE3 correspond to the cathodes or common electrodes of display elements and are in contact with the partition wall 6.

[0061] The lower electrode LE1 is electrically connected to the pixel circuit 1 of the sub-pixel SP1 (see Figure 1 ). The lower electrode LE2 is electrically connected to the pixel circuit 1 of the sub-pixel SP2. The lower electrode LE3 is electrically connected to the pixel circuit 1 of the sub-pixel SP3.

[0062] In the illustrated example, the areas of the openings AP1, AP2, and AP3 are different from each other. The area of the opening AP1 is larger than the area of the opening AP2, and the area of the opening AP2 is larger than the area of the opening AP3. In other words, the area of the lower electrode LE1 exposed from the opening AP1 is larger than the area of the lower electrode LE2 exposed from the opening AP2, and the area of the lower electrode LE2 exposed from the opening AP2 is larger than the area of the lower electrode LE3 exposed from the opening AP3.

[0063] Figure 3 is a schematic cross-sectional view of the display device DSP along the A-B line in Figure 2 .

[0064] The circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes Figure 1 various circuits such as the pixel circuit 1 shown and various wirings such as the scanning line GL, signal line SL, and power supply line PL. The circuit layer 11 is covered with an insulating layer 12. The insulating layer 12 is an organic insulating layer that planarizes the unevenness generated by the circuit layer 11.

[0065] The lower electrodes LE1, LE2, and LE3 are disposed on the insulating layer 12 and are separated from each other. The inorganic insulating layer 5 is disposed on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The opening AP1 of the inorganic insulating layer 5 overlaps with the lower electrode LE1, the opening AP2 overlaps with the lower electrode LE2, and the opening AP3 overlaps with the lower electrode LE3. The peripheral portions of the lower electrodes LE1, LE2, and LE3 are covered with the inorganic insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3 respectively through contact holes provided in the insulating layer 12. It should be noted that the contact holes of the insulating layer 12 are omitted in Figure 3 .

[0066] The partition wall 6 includes a lower portion 61 disposed on the inorganic insulating layer 5 and having conductivity, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a larger width than the lower portion 61. Both end portions of the upper portion 62 protrude beyond the respective side surfaces of the lower portion 61. The shape of such a partition wall 6 is referred to as a cantilever shape.

[0067] In the illustrated example, the lower portion 61 has a first conductive layer 63 disposed on the inorganic insulating layer 5 and a second conductive layer 64 disposed on the first conductive layer 63. The first conductive layer 63 is formed thinner than the second conductive layer 64. Both end portions of the first conductive layer 63 protrude beyond the respective side surfaces of the second conductive layer 64.

[0068] The upper portion 62 has a first thin film 65 disposed on the second conductive layer 64 and a second thin film 66 disposed on the first thin film 65. Both end portions of the first thin film 65 and the second thin film 66 protrude beyond the respective side surfaces of the second conductive layer 64.

[0069] The organic layer OR1 contacts the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed from the opening AP1, and its peripheral portion is located on the inorganic insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and contacts the lower portion 61.

[0070] The organic layer OR2 contacts the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed from the opening AP2, and its peripheral portion is located on the inorganic insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and contacts the lower portion 61.

[0071] The organic layer OR3 contacts the lower electrode LE3 through the opening AP3, covers the lower electrode LE3 exposed from the opening AP3, and its peripheral portion is located on the inorganic insulating layer 5. The upper electrode UE3 covers the organic layer OR3 and contacts the lower portion 61.

[0072] In the illustrated example, the sub-pixel SP1 has a cover layer CP1, a barrier layer BL1, and a sealing layer SE1, the sub-pixel SP2 has a cover layer CP2, a barrier layer BL2, and a sealing layer SE2, and the sub-pixel SP3 has a cover layer CP3, a barrier layer BL3, and a sealing layer SE3. The cover layers CP1, CP2, and CP3 each function as an optical adjustment layer for improving the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3. It should be noted that the cover layers CP1, CP2, and CP3 may be omitted.

[0073] The cover layer CP1 is disposed on the upper electrode UE1.

[0074] The cover layer CP2 is disposed on the upper electrode UE2.

[0075] The cover layer CP3 is disposed on the upper electrode UE3.

[0076] The barrier layer BL1 is disposed above the cover layer CP1, contacts the lower part 61, extends above the upper part 62, and forms a gap GP1 between it and the upper part 62.

[0077] The barrier layer BL2 is disposed above the cover layer CP2, contacts the lower part 61, extends above the upper part 62, and forms a gap GP2 between it and the upper part 62. Above the upper part 62, the barrier layer BL2 is separated from the barrier layer BL1.

[0078] The barrier layer BL3 is disposed above the cover layer CP3, contacts the lower part 61, extends above the upper part 62, and forms a gap GP3 between it and the upper part 62. Above the upper part 62, the barrier layer BL3 is separated from the barrier layers BL1 and BL2.

[0079] The sealing layer SE1 overlaps with the barrier layer BL1, does not contact the partition wall 6, and extends above the partition wall 6. In the illustrated example, a void CV1 surrounded by the sealing layer SE1 is formed at a position opposite to the lower part 61 below the upper part 62.

[0080] The sealing layer SE2 overlaps with the barrier layer BL2, does not contact the partition wall 6, extends above the partition wall 6, and is separated from the sealing layer SE1. In the illustrated example, a void CV2 surrounded by the sealing layer SE2 is formed at a position opposite to the lower part 61 below the upper part 62.

[0081] The sealing layer SE3 overlaps with the barrier layer BL3, does not contact the partition wall 6, extends above the partition wall 6, and is separated from the sealing layers SE1 and SE2. In the illustrated example, a void CV3 surrounded by the sealing layer SE3 is formed at a position opposite to the lower part 61 below the upper part 62.

[0082] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1, and the cover layer CP1 is referred to as the stacked film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2, and the cover layer CP2 is referred to as the stacked film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3, and the cover layer CP3 is referred to as the stacked film FL3.

[0083] The sealing layers SE1, SE2, and SE3 are covered by the resin layer 13. As shown in the figure, the resin layer 13 contacts the upper part of the partition wall 6 between the sealing layer SE1 and the sealing layer SE2 and between the sealing layer SE1 and the sealing layer SE3. In addition, the resin layer 13 fills the gaps GP1 surrounded by the upper part 62 and the barrier layer BL1, the gap GP2 surrounded by the upper part 62 and the barrier layer BL2, and the gap GP3 surrounded by the upper part 62 and the barrier layer BL3, respectively. It should be noted that there may be a case where the gaps GP1, GP2, and GP3 are not completely filled with the resin layer 13 and there are air bubbles.

[0084] The resin layer 13 is covered with a sealing layer 14. The sealing layer 14 is covered with an outer covering layer 15.

[0085] The inorganic insulating layer 5, the barrier layers BL1, BL2, BL3, the sealing layers SE1, SE2, SE3, and the sealing layer 14 are formed of inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), etc. The second inorganic insulating material for forming the sealing layers SE1, SE2, SE3 is a material different from the first inorganic insulating material for forming the barrier layers BL1, BL2, BL3. In addition, during the dry etching of the sealing layers SE1, SE2, SE3, the etching rate of the first inorganic insulating material is smaller than the etching rate of the second inorganic insulating material.

[0086] For example, the barrier layers BL1, BL2, BL3 are formed of silicon oxynitride as the first inorganic insulating material, and the sealing layers SE1, SE2, SE3 are formed of silicon nitride as the second inorganic insulating material. The inorganic insulating layer 5 is formed of silicon oxynitride as the same inorganic insulating material as the barrier layers BL1, BL2, BL3. The sealing layer 14 is formed of silicon nitride as the same inorganic insulating material as the sealing layers SE1, SE2, SE3.

[0087] The outer covering layer 15 is formed of the same resin material as the resin layer 13.

[0088] The lower part 61 of the partition wall 6 is formed of a conductive material and is electrically connected to the upper electrodes UE1, UE2, UE3. The first conductive layer 63 is formed of a titanium-based material such as titanium or a titanium compound, for example. The second conductive layer 64 is formed of a material different from the first conductive layer 63 and the upper part 62, and is formed of an aluminum-based material such as aluminum or an aluminum compound, for example.

[0089] The upper part 62 of the partition wall 6 is formed of a conductive material, for example, but may also be formed of an insulating material. The upper part 62 is formed of a material different from the lower part 61. The first thin film 65 is formed of a titanium-based material such as titanium or a titanium compound, for example. The second thin film 66 is formed of an oxide conductive material such as indium tin oxide (ITO), for example.

[0090] The lower electrodes LE1, LE2, LE3 are, for example, a multilayer body including a transparent layer formed of an oxide conductive material such as ITO and a reflective layer formed of a metal material such as silver. In one example, the lower electrodes LE1, LE2, LE3 are a multilayer body including a reflective layer between a pair of transparent layers.

[0091] The organic layer OR1 includes a light-emitting layer EM1. The organic layer OR2 includes a light-emitting layer EM2. The organic layer OR3 includes a light-emitting layer EM3. The light-emitting layers EM1, EM2, and EM3 are formed of materials different from each other. In one example, the light-emitting layer EM1 is formed of a material that emits light in the blue wavelength region, the light-emitting layer EM2 is formed of a material that emits light in the green wavelength region, and the light-emitting layer EM3 is formed of a material that emits light in the red wavelength region.

[0092] In addition, each of the organic layers OR1, OR2, and OR3 includes a plurality of functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0093] The upper electrodes UE1, UE2, and UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg), for example.

[0094] The cover layers CP1, CP2, and CP3 are multi-layers of a plurality of thin films. The plurality of thin films are all transparent and have different refractive indices from each other.

[0095] The illustrated circuit layer 11, insulating layer 12, and inorganic insulating layer 5 are disposed throughout the display area DA and the peripheral area SA.

[0096] Next, a method for manufacturing the display device DSP will be described. It should be noted that, in each of the drawings for explaining the manufacturing method, the illustration below the insulating layer 12 is omitted.

[0097] First, as Figure 4 shown, a processing substrate SUB having lower electrodes LE1, LE2, LE3, an inorganic insulating layer 5, and a partition wall 6 is prepared. The process of preparing the processing substrate SUB includes the following processes. That is, on the substrate 10, a circuit layer 11 and an insulating layer 12 are formed throughout the display area DA and the peripheral area SA. Then, lower electrodes LE1 of the sub-pixel SP1, lower electrodes LE2 of the sub-pixel SP2, and lower electrodes LE3 of the sub-pixel SP3 are formed on the insulating layer 12. Then, an inorganic insulating layer 5 covering the peripheral portions of the lower electrodes LE1, LE2, and LE3 is formed. Then, a partition wall 6 having a lower portion 61 located on the inorganic insulating layer 5 and an upper portion 62 located on the lower portion 61 is formed. The first conductive layer 63 of the lower portion 61 and the upper portion 62 protrude from the respective side surfaces of the second conductive layer 64 of the lower portion 61. It should be noted that the process of forming the openings AP1, AP2, and AP3 in the inorganic insulating layer 5 may be performed before forming the partition wall 6 or after forming the partition wall 6.

[0098] Next, a display element DE1 is formed.

[0099] First, as Figure 5As shown, a stacked film FL1 including an organic layer OR1, an upper electrode UE1, and a cover layer CP1 is formed. The process of forming the stacked film FL1 includes the following processes. That is, in the opening AP1, an organic layer OR1 in contact with the lower electrode LE1 is formed. The process of forming the organic layer OR1 includes processes of separately forming a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, an electron injection layer, etc. Then, an upper electrode UE1 covering the organic layer OR1 and in contact with the lower part 61 of the partition wall 6 is formed. Then, a cover layer CP1 located above the upper electrode UE1 is formed.

[0100] The organic layer OR1, the upper electrode UE1, and the cover layer CP1 are respectively formed by evaporation using the partition wall 6 as a mask. The stacked film FL1 is partitioned into multiple parts by the cantilever-shaped partition wall 6. These organic layer OR1, upper electrode UE1, and cover layer CP1 are continuously formed while maintaining a vacuum environment. Such a stacked film FL1 is formed not only above the lower electrode LE1 but also above the partition wall 6, the lower electrode LE2, and the lower electrode LE3.

[0101] Next, as Figure 6 shown, a barrier layer BL1 is formed by depositing silicon oxynitride as the first inorganic insulating material. The barrier layer BL1 continuously covers the partitioned parts of the stacked film FL1 and the partition wall 6. Such a barrier layer BL1 is formed by CVD (Chemical Vapor Deposition).

[0102] Next, as Figure 7 shown, a sealing layer SE1 is formed by depositing silicon nitride as the second inorganic insulating material. The sealing layer SE1 overlaps in a manner covering the barrier layer BL1. At this time, a void CV1 surrounded by the sealing layer SE1 is formed around the partition wall 6. Such a sealing layer SE1 is formed by CVD.

[0103] Next, as Figure 8 shown, a resist RS1 patterned into a specified shape is formed on the sealing layer SE1. The resist RS1 overlaps with the sub-pixel SP1 and a part of the surrounding partition wall 6.

[0104] Next, as Figure 9 shown, dry etching is performed using the resist RS1 as a mask to remove the sealing layer SE1 and the barrier layer BL1 exposed from the resist RS1. As a result, a part of the stacked film FL1 is exposed above the partition wall 6, and in addition, the stacked film FL1 above the lower electrode LE2 and the stacked film FL1 above the lower electrode LE3 are also exposed. In addition, the parts of the partition wall 6 facing the lower electrode LE2 and the lower electrode LE3 are also exposed.

[0105] Next, asFigure 10 As shown, the stacked film FL1 exposed from the resist RS1 is removed. At this time, in the stacked film FL1, the capping layer CP1, the upper electrode UE1, and the organic layer OR1 are sequentially removed. As a result, the stacked film FL1 covered by the resist RS1 remains in the sub-pixel SP1. In addition, a part of the upper portion 62 of the partition wall 6 is exposed, and the lower electrode LE2 and the lower electrode LE3 are also exposed.

[0106] Next, as Figure 11 shown, the resist RS1 is removed. As a result, the display element DE1 is formed in the sub-pixel SP1. When the resist RS1 is removed, the stacked film FL1 above the partition wall 6 is also removed. As a result, a gap GP1 is formed above the partition wall 6. The gap GP1 is open to the lower electrode LE2 and is also open to the lower electrode LE3.

[0107] Next, the display element DE2 is formed. The step of forming the display element DE2 is the same as the step of forming the display element DE1. Hereinafter, a simple description will be given.

[0108] First, as Figure 12 shown, a stacked film FL2 including an organic layer OR2, an upper electrode UE2, and a capping layer CP2 is formed on the lower electrode LE2. The stacked film FL2 is also formed on the sealing layer SE1, the partition wall 6, and the lower electrode LE3.

[0109] Next, as Figure 13 shown, a barrier layer BL2 is formed by depositing silicon oxynitride as the first inorganic insulating material. The barrier layer BL2 continuously covers the partitioned portions of the stacked film FL2, the sealing layer SE1, and the partition wall 6.

[0110] Next, as Figure 14 shown, a sealing layer SE2 is formed by depositing silicon nitride as the second inorganic insulating material. The sealing layer SE2 overlaps so as to cover the barrier layer BL2. At this time, a void CV2 surrounded by the sealing layer SE2 is formed around the partition wall 6.

[0111] Next, as Figure 15 shown, a resist RS2 patterned into a predetermined shape is formed on the sealing layer SE2. The resist RS2 overlaps with the sub-pixel SP2 and a part of the partition wall 6 around it.

[0112] Next, as Figure 16 shown, dry etching is performed using the resist RS2 as a mask to remove the sealing layer SE2 and the barrier layer BL2 exposed from the resist RS2. As a result, the stacked film FL2 on the sealing layer SE1, the stacked film FL2 on the partition wall 6, and the stacked film FL2 on the lower electrode LE3 are also exposed. In addition, the portion of the partition wall 6 facing the lower electrode LE3 is also exposed.

[0113] During dry etching of such a sealing layer SE2 and a barrier layer BL2, the previously formed sealing layer SE1 is also vulnerable to damage. Among them, the gap GP1 is surrounded by a barrier layer BL1 with an etching rate lower than that of the sealing layer SE1. Therefore, it is possible to prevent the gap GP1 and the void CV1 from being penetrated due to the recession of the sealing layer SE1. That is, the barrier layer BL1 and the sealing layer SE1 are interposed between the gap GP1 and the void CV1.

[0114] Therefore, it is possible to suppress the undesired expansion of the void CV1 caused by the intrusion of the etching gas into the void CV1, and in addition, it is possible to suppress the exposure of the stacked film FL1 from the sealing layer SE1

[0115] Next, as Figure 17 shown, the stacked film FL2 exposed from the resist RS2 is removed. At this time, in the stacked film FL2, the capping layer CP2, the upper electrode UE2, and the organic layer OR2 are removed in this order. As a result, the stacked film FL2 covered with the resist RS2 remains in the sub-pixel SP2. In addition, a part of the upper portion 62 of the partition wall 6 is exposed, and in addition, the lower electrode LE3 is exposed.

[0116] Next, as Figure 18 shown, the resist RS2 is removed. As a result, a display element DE2 is formed in the sub-pixel SP2. When the resist RS2 is removed, the stacked film FL2 above the partition wall 6 is also removed. As a result, a gap GP2 is formed above the partition wall 6.

[0117] Next, as Figure 19 shown, a display element DE3 is formed. The step of forming the display element DE3 is the same as the step of forming the display element DE1. That is, a stacked film FL3 including an organic layer OR3, an upper electrode UE3, and a capping layer CP3 is formed on the lower electrode LE3. Then, a barrier layer BL3 is formed on the stacked film FL3, and then, a sealing layer SE3 is formed. When the sealing layer SE3 is formed, a void CV3 surrounded by the sealing layer SE3 is formed around the partition wall 6. Then, a resist is formed on the sealing layer SE3, and the sealing layer SE3, the barrier layer BL3, the capping layer CP3, the upper electrode UE3, and the organic layer OR3 are patterned by etching using this resist as a mask. After this patterning, the resist is removed. At this time, a gap GP3 is formed above the partition wall 6. As a result, a display element DE3 is formed in the sub-pixel SP3.

[0118] Next, as Figure 20 shown, a resin layer 13 is formed. The resin layer 13 covers the sealing layers SE1, SE2, SE3, fills the gaps GP1, GP2, GP3, and is in contact with the barrier layers BL1, BL2, BL3. Then, as Figure 3As shown, a sealing layer 14 and an overlying layer 15 are formed in sequence. Thus, the display device DSP is completed.

[0119] It should be noted that in the above manufacturing process, it is assumed that the display element DE1 is formed first, then the display element DE2 is formed, and finally the display element DE3 is formed. However, the formation order of the display elements DE1, DE2, and DE3 is not limited to this example.

[0120] According to the display device DSP manufactured in this way, the penetration of the void CV1 and the gap GP1, the penetration of the void CV2 and the gap GP2, and the penetration of the void CV3 and the gap GP3 are suppressed. Therefore, the inflow of the resin layer 13 into the voids CV1, CV2, and CV3 is suppressed. In addition, the sealing failure of the laminated film FL1 caused by the sealing layer SE1, the sealing failure of the laminated film FL2 caused by the sealing layer SE2, and the sealing failure of the laminated film FL3 caused by the sealing layer SE3 are suppressed. Thus, the deterioration of the laminated films FL1, FL2, and FL3 due to moisture is suppressed, and the reduction in reliability can be suppressed.

[0121] Here, refer to Figure 20 The characteristics of the display device DSP manufactured through the above process will be described.

[0122] The barrier layer BL1 overlaps with the laminated film FL1 and is in contact with the side surface SS1 in the second conductive layer 64 of the lower part 61. The resin layer 13 is disposed on substantially the entire surface above the upper part 62. Above the partition wall 6, the barrier layer BL1 overlaps with the resin layer 13, and the sealing layer SE1 overlaps with the barrier layer BL1. The sealing layer SE1 is covered by the resin layer 13.

[0123] Regarding the thickness of the barrier layer BL1, the thickness T11 directly above the laminated film FL1 is smaller than the thickness T1 of the sealing layer SE1 (T11 < T1). In one example, the thickness T11 is 50 to 150 nm, and the thickness T1 is 1000 to 3000 nm.

[0124] The barrier layer BL1 directly above the partition wall 6 can be thinned when exposed to the etching gas during the dry etching of the sealing layers SE2 and SE3. Therefore, in the barrier layer BL1, the thickness T11 is greater than the thickness T12 directly above the partition wall 6 (T11 > T12). In addition, the thickness T12 is smaller than the height H of the gap GP1 (or the thickness of the resin layer 13 filled in the gap GP1) (H > T12).

[0125] The barrier layer BL2 overlaps with the stacked film FL2 and is in contact with the side surface SS2 on the opposite side of the side surface SS1 in the second conductive layer 64 of the lower part 61. Directly above the partition wall 6, the barrier layer BL2 overlaps with the resin layer 13, and the sealing layer SE2 overlaps with the barrier layer BL2. Among them, the barrier layers BL1 and BL2 are separated from each other, and the sealing layers SE1 and SE2 are separated from each other. The sealing layer SE2 is covered by the resin layer 13.

[0126] Regarding the thickness of the barrier layer BL2, the thickness T21 directly above the stacked film FL2 is smaller than the thickness T2 of the sealing layer SE2 (T21 < T2). In one example, the thickness T21 is the same as the thickness T11, and the thickness T2 is the same as the thickness T1.

[0127] The barrier layer BL2 directly above the partition wall 6 can be thinned when exposed to the etching gas during the dry etching of the sealing layer SE3. Therefore, in the barrier layer BL2, the thickness T21 is greater than the thickness T22 directly above the partition wall 6 (T21 > T22). In addition, the thickness T22 is different from the thickness T12 and is greater than the thickness T12 (T22 > T12).

[0128] The barrier layer BL3 overlaps with the stacked film FL3 and is in contact with the side surface SS3 in the second conductive layer 64 of the lower part 61. Directly above the partition wall 6, the barrier layer BL3 overlaps with the resin layer 13, and the sealing layer SE3 overlaps with the barrier layer BL3. Among them, the barrier layers BL1 and BL3 are separated from each other, and the sealing layers SE1 and SE3 are separated from each other. The sealing layer SE3 is covered by the resin layer 13.

[0129] Regarding the thickness of the barrier layer BL3, the thickness T31 directly above the stacked film FL3 is smaller than the thickness T3 of the sealing layer SE3 (T31 < T3). In one example, the thickness T31 is the same as the thickness T11, and the thickness T3 is the same as the thickness T1.

[0130] The barrier layer BL3 directly above the partition wall 6 is not exposed to the etching gas used for etching other sealing layers. Therefore, in the barrier layer BL3, the thickness T31 is the same as the thickness T32 directly above the partition wall 6 (T31 ≈ T32). In addition, the thickness T32 is greater than the thickness T12 (T32 > T12).

[0131] Next, another structural example will be described.

[0132] Figure 21 It is a cross-sectional view showing another structural example of the display device DSP.

[0133] Figure 21 The structural example shown is the same as Figure 20The difference from the illustrated configuration example is that the thicknesses T11, T21, and T31 are different from each other. In the illustrated example, it is assumed that they are formed in the order of the display element DE1, the display element DE2, and the display element DE3, and the thickness T21 is less than the thickness T11, and the thickness T31 is less than the thickness T21 (T11 > T21 > T31). Directly above the partition wall 6, the thicknesses T12, T22, and T32 are equal (T12 ≈ T22 ≈ T32). It should be noted that the thickness T11 is greater than the thickness T12 (T11 > T12), the thickness T21 is greater than the thickness T22 (T21 > T22), and the thicknesses T31 and T32 are equal (T31 ≈ T32).

[0134] In such a configuration example, similar to Figure 20 the illustrated configuration example, the resin layer 13 is filled in the gaps GP1, GP2, and GP3 respectively. In addition, the barrier layer BL1 and the sealing layer SE1 are interposed between the gap GP1 and the void CV1, the barrier layer BL2 and the sealing layer SE2 are interposed between the gap GP2 and the void CV2, and the barrier layer BL3 and the sealing layer SE3 are interposed between the gap GP3 and the void CV3. Therefore, the same effects as the above configuration example can be obtained.

[0135] Figure 22 It is a cross-sectional view showing another configuration example of the display device DSP.

[0136] Figure 22 The difference between the illustrated configuration example and Figure 20 the illustrated configuration example is that the barrier layer BL1 is separated into a first part BL11 that contacts the side surface SS1 and a second part (or a part that overlaps with the resin layer 13) BL12 that extends above the partition wall 6. That is, the resin layer 13 filled in the gap GP1 contacts the sealing layer SE1 between the first part BL11 and the second part BL12. Such a feature is formed by removing a part (a part with a locally thinner thickness) of the barrier layer BL1 surrounding the gap GP1 during the dry etching of the sealing layers SE2 and SE3.

[0137] In the illustrated example, the barrier layer BL2 is separated into a first part BL21 that contacts the side surface SS2 and a second part (or a part that overlaps with the resin layer 13) BL22 that extends above the partition wall 6. The resin layer 13 contacts the sealing layer SE2 between the first part BL21 and the second part BL22. Such a feature is formed by removing a part (a part with a locally thinner thickness) of the barrier layer BL2 surrounding the gap GP2 during the dry etching of the sealing layer SE3.

[0138] Note that in the barrier layer BL3, the portion in contact with the side surface SS3 and the portion extending above the partition wall 6 are formed continuously without separation.

[0139] In such a configuration example, similar to Figure 20 the configuration example shown, the resin layers 13 are filled in the gaps GP1, GP2, and GP3 respectively. In addition, the sealing layer SE1 is interposed between the gap GP1 and the void CV1, the sealing layer SE2 is interposed between the gap GP2 and the void CV2, and the sealing layer SE3 is interposed between the gap GP3 and the void CV3. Therefore, the same effects as those of the above configuration example can be obtained.

[0140] Figure 23 It is a cross-sectional view showing another configuration example of the display device DSP.

[0141] Figure 23 The configuration example shown is different from Figure 20 the configuration example shown in that the barrier layer BL3 is omitted. As described above, when the display element DE1, the display element DE2, and the display element DE3 are formed in sequence, the sealing layer SE3 is not exposed to the etching gas for etching the other sealing layers. Therefore, even if the barrier layer BL3 is omitted, it is possible to prevent the undesired recession of the sealing layer SE3, prevent the penetration between the gap GP3 and the void CV3, and prevent the exposure of the laminated film FL3 from the sealing layer SE3. Therefore, in such a configuration example, the same effects as those of the above configuration example can be obtained.

[0142] Figure 24 It is a cross-sectional view showing another configuration example of the display device DSP.

[0143] Figure 24 The configuration example shown is different from Figure 23 the configuration example shown in that not only the barrier layer BL3 is omitted, but also the barrier layer BL2 is omitted. In such a configuration example, the same effects as those of the above configuration example can be obtained.

[0144] In the above embodiment, for example, the lower electrode LE1 corresponds to the first lower electrode, and the lower electrode LE2 corresponds to the second lower electrode. The organic layer OR1 corresponds to the first organic layer, and the organic layer OR2 corresponds to the second organic layer. The upper electrode UE1 corresponds to the first upper electrode, and the upper electrode UE2 corresponds to the second upper electrode. In the partition wall 6, the side surface SS1 corresponds to the first side surface, and the side surface SS2 corresponds to the second side surface. The laminated film FL1 corresponds to the first laminated film, and the laminated film FL2 corresponds to the second laminated film. The barrier layer BL1 corresponds to the first barrier layer, and the barrier layer BL2 corresponds to the second barrier layer. The sealing layer SE1 corresponds to the first sealing layer, and the sealing layer SE2 corresponds to the second sealing layer.

[0145] As described above, according to the present embodiment, a display device capable of suppressing a reduction in reliability can be provided.

[0146] As described above, based on the display device described as an embodiment of the present invention, all display devices that can be implemented by a person skilled in the art through appropriate design changes also belong to the scope of the present invention as long as they include the gist of the present invention.

[0147] Within the scope of the idea of the present invention, various modifications can be conceived by a person skilled in the art, and these modifications should also be understood to belong to the scope of the present invention. For example, a solution obtained by a person skilled in the art by appropriately adding, deleting, or changing the design of the components in the above-described embodiment, or a solution obtained by adding, omitting, or changing the conditions of the process also belongs to the scope of the present invention as long as it has the gist of the present invention.

[0148] In addition, regarding other effects brought about by the solutions described in the above-described embodiment, effects that can be clearly understood from the description of this specification or effects that can be appropriately conceived by a person skilled in the art should of course be understood as effects brought about by the present invention.

Claims

1. A display device, comprising: a substrate; a first lower electrode disposed above the substrate; an inorganic insulating layer covering a peripheral portion of the first lower electrode; a partition wall having a lower portion disposed on the inorganic insulating layer and formed of a conductive material, and an upper portion disposed above the lower portion and protruding from a first side surface of the lower portion and a second side surface opposite to the first side surface; a first stacked film including a first organic layer in contact with the first lower electrode and a first upper electrode disposed above the first organic layer and in contact with the lower portion; a first barrier layer disposed above the first stacked film, in contact with the first side surface, extending above the partition wall, forming a gap between the first barrier layer and the upper portion, and formed of a first inorganic insulating material; a first sealing layer overlapping the first barrier layer and formed of a second inorganic insulating material different from the first inorganic insulating material; and a resin layer covering the first sealing layer and filling the gap.

2. The display device according to claim 1, wherein, The etching rate of the first inorganic insulating material is less than the etching rate of the second inorganic insulating material.

3. The display device according to claim 1, wherein, The first inorganic insulating material is silicon oxynitride, The second inorganic insulating material is silicon nitride.

4. The display device according to claim 1, wherein, In the first barrier layer, the thickness directly above the first stacked film is greater than the thickness directly above the partition wall.

5. The display device according to claim 1, wherein, In the first barrier layer, the thickness directly above the partition wall is less than the height of the gap.

6. The display device according to claim 1, further comprising: a second lower electrode disposed above the substrate and having a peripheral portion covered by the inorganic insulating layer; a second stacked film including a second organic layer in contact with the second lower electrode and a second upper electrode disposed above the second organic layer and in contact with the lower portion; a second barrier layer disposed above the second stacked film, in contact with the second side surface, extending above the partition wall, forming a gap between the second barrier layer and the upper portion, separated from the first barrier layer, and formed of the first inorganic insulating material; and a second sealing layer overlapping the second barrier layer, separated from the first sealing layer, and formed of the second inorganic insulating material, The thickness of the second barrier layer directly above the partition wall is greater than the thickness of the first barrier layer directly above the partition wall.

7. The display device according to claim 6, wherein, The thickness of the second barrier layer directly above the second stacked film is equal to the thickness of the first barrier layer directly above the first stacked film.

8. The display device according to claim 1, further comprising: a second lower electrode disposed above the substrate and having a peripheral portion covered by the inorganic insulating layer; a second stacked film including a second organic layer in contact with the second lower electrode and a second upper electrode disposed above the second organic layer and in contact with the lower portion; a second barrier layer disposed above the second stacked film, in contact with the second side surface, extending above the partition wall, forming a gap between the second barrier layer and the upper portion, separated from the first barrier layer, and formed of the first inorganic insulating material; and A second sealing layer, which overlaps with the second barrier layer, is separated from the first sealing layer, and is formed of the second inorganic insulating material. The thickness of the second barrier layer directly above the second stacked film is less than the thickness of the first barrier layer directly above the first stacked film.

9. The display device according to claim 8, wherein, The thickness of the second barrier layer directly above the partition wall is equal to the thickness of the first barrier layer directly above the partition wall.

10. The display device according to claim 1, further comprising a gap surrounded by the first sealing layer and opposite to the first side surface. The first barrier layer and the first sealing layer are interposed between the gap and the void.

11. The display device according to claim 1, wherein, The first barrier layer is separated into a first portion in contact with the first side surface and a second portion extending above the partition wall. The resin layer filled in the gap is in contact with the first sealing layer between the first portion and the second portion.

12. The display device according to claim 11, further comprising a gap surrounded by the first sealing layer and opposite to the first side surface. The first sealing layer is interposed between the gap and the void.

13. A display device, comprising: a substrate; a first lower electrode disposed above the substrate; an inorganic insulating layer covering the peripheral portion of the first lower electrode; a partition wall having a lower portion disposed above the inorganic insulating layer and formed of a conductive material, and an upper portion disposed above the lower portion and protruding from a first side surface of the lower portion and a second side surface opposite to the first side surface; a first stacked film including a first organic layer in contact with the first lower electrode and a first upper electrode disposed above the first organic layer and in contact with the lower portion; a resin layer disposed above the upper portion; a first barrier layer overlapping with the resin layer and formed of a first inorganic insulating material; and a first sealing layer overlapping with the first barrier layer and formed of a second inorganic insulating material different from the first inorganic insulating material.

14. The display device according to claim 13, further comprising: a second barrier layer overlapping with the resin layer, separated from the first barrier layer, and formed of the first inorganic insulating material; and a second sealing layer overlapping with the second barrier layer, separated from the first sealing layer, and formed of the second inorganic insulating material.

15. The display device according to claim 14, wherein, The thickness of the first barrier layer is different from the thickness of the second barrier layer.

16. The display device according to claim 14, wherein, The first sealing layer and the second sealing layer are covered by the resin layer.

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