Display device and method of manufacturing same

Abstract

A display device and a method of manufacturing the same are disclosed. The display device includes: a substrate; a lower electrode on the substrate; a pixel defining layer on the lower electrode and including a pixel opening through which a portion of the lower electrode is exposed; an intermediate layer on the lower electrode and including an emission layer; an upper electrode on the intermediate layer; the first inorganic encapsulation layer is located on the upper electrode; a second inorganic encapsulation layer on the first inorganic encapsulation layer and in the pixel opening of the pixel defining layer; and a third inorganic encapsulation layer on the second inorganic encapsulation layer, where the third inorganic encapsulation layer is directly on the first inorganic encapsulation layer in a region overlapping with the pixel defining layer and is spaced apart from the first inorganic encapsulation layer in a region overlapping with the pixel opening.

Description

[0001] This application claims the priority and all benefits derived therefrom of Korean Patent Application No. 10-2024-0007630, filed on January 17, 2024, the entire content of which is incorporated herein by reference. Technical Field

[0002] The present invention relates to a display device, and more particularly, to a display device and a method of manufacturing the display device. Background Art

[0003] A display device visually displays data. Recently, display devices have been used for various purposes. Moreover, as the thickness and weight of display devices have decreased, the range of applications of display devices has increased.

[0004] To implement a thin and light display device, the display device may encapsulate an emission region by using a thin film encapsulation layer instead of an encapsulation substrate formed of glass. The thin film encapsulation layer may prevent impurities such as oxygen or moisture from penetrating into the light emitting element, and may cover the display region of the display device to flatten the top surface of the display region. Summary of the Invention

[0005] One or more embodiments include a display device and a method of manufacturing the display device. However, the embodiments disclosed herein are examples and do not limit the scope of the present invention.

[0006] According to an embodiment, a display device includes: a substrate; a lower electrode disposed on the substrate; a pixel defining layer disposed on the lower electrode and including a pixel opening through which a portion of the lower electrode is exposed; an intermediate layer disposed on the lower electrode and including an emission layer; an upper electrode disposed on the intermediate layer; a first inorganic encapsulation layer disposed on the upper electrode; a second inorganic encapsulation layer disposed on the first inorganic encapsulation layer and in the pixel opening; and a third inorganic encapsulation layer disposed on the second inorganic encapsulation layer, wherein the third inorganic encapsulation layer is spaced apart from the first inorganic encapsulation layer in a region overlapping the pixel opening, and is directly disposed on the first inorganic encapsulation layer in a region overlapping the pixel defining layer.

[0007] In an embodiment, the film density of the second inorganic encapsulation layer may be lower than the film density of the first inorganic encapsulation layer.

[0008] In an embodiment, the film density of the second inorganic encapsulation layer may be lower than the film density of the third inorganic encapsulation layer.

[0009] In an embodiment, the second inorganic encapsulation layer may not overlap with the pixel defining layer.

[0010] In one embodiment, the second inorganic encapsulation layer may fill the pixel opening of the pixel definition layer.

[0011] In one embodiment, each of the first inorganic encapsulation layer and the third inorganic encapsulation layer may overlap with the pixel opening and the pixel definition layer.

[0012] In one embodiment, the film density of the first inorganic encapsulation layer may be in the range of about 2.6 g / cm 3 to about 3.5 g / cm 3 range.

[0013] In one embodiment, the film density of the second inorganic encapsulation layer may be in the range of about 1.6 g / cm 3 to about 2.3 g / cm 3 range.

[0014] In one embodiment, the film density of the third inorganic encapsulation layer may be in the range of about 2.6 g / cm 3 to about 3.5 g / cm 3 range.

[0015] In one embodiment, each of the first inorganic encapsulation layer and the second inorganic encapsulation layer may include a silicon element and a nitrogen element, wherein the ratio of the nitrogen element to the silicon element in the first inorganic encapsulation layer is less than the ratio of the nitrogen element to the silicon element in the second inorganic encapsulation layer.

[0016] In one embodiment, the refractive index of the first inorganic encapsulation layer may be greater than the refractive index of the second inorganic encapsulation layer.

[0017] According to one embodiment, a display device includes: a substrate; a first light-emitting element, a second light-emitting element, and a third light-emitting element, wherein each of the first light-emitting element to the third light-emitting element is located on the substrate and is configured to emit light of different colors; and an encapsulation layer located on the first light-emitting element to the third light-emitting element to encapsulate the first light-emitting element to the third light-emitting element. The encapsulation layer includes: a first inorganic encapsulation layer located on the first light-emitting element to the third light-emitting element; a second inorganic encapsulation layer located on the first inorganic encapsulation layer and having a lower film density than the first inorganic encapsulation layer, and including a first inorganic encapsulation pattern overlapping with the first light-emitting element, a second inorganic encapsulation pattern overlapping with the second light-emitting element, and a third inorganic encapsulation pattern overlapping with the third light-emitting element; and further includes a third inorganic encapsulation layer located on the second inorganic encapsulation layer, wherein the first inorganic encapsulation pattern, the second inorganic encapsulation pattern, and the third inorganic encapsulation pattern are spaced apart from each other.

[0018] In one embodiment, each of the first to third light-emitting elements may include a lower electrode, an emission layer on the lower electrode, and an upper electrode on the emission layer, wherein the display device further includes a pixel defining layer located on the lower electrode and including: a first pixel opening through which a part of the lower electrode of the first light-emitting element is exposed; a second pixel opening through which a part of the lower electrode of the second light-emitting element is exposed; and a third pixel opening through which a part of the lower electrode of the third light-emitting element is exposed, wherein the first inorganic encapsulation pattern is located in the first pixel opening, the second inorganic encapsulation pattern is located in the second pixel opening, and the third inorganic encapsulation pattern is located in the third pixel opening.

[0019] In one embodiment, each of the first to third inorganic encapsulation patterns may not overlap with the pixel defining layer.

[0020] In one embodiment, the third inorganic encapsulation layer may be spaced apart from the first inorganic encapsulation layer in a region overlapping with the first to third pixel openings, and may be directly located on the first inorganic encapsulation layer in a region overlapping with the pixel defining layer.

[0021] In one embodiment, each of the first inorganic encapsulation layer and the third inorganic encapsulation layer may overlap with the first to third pixel openings and the pixel defining layer.

[0022] In one embodiment, the film density of the third inorganic encapsulation layer may be greater than the film density of the second inorganic encapsulation layer.

[0023] According to one embodiment, a method of manufacturing a display device includes: forming a pixel defining layer having pixel openings on a lower electrode, with a part of the lower electrode exposed through the pixel openings; forming an emission layer on the lower electrode; forming an upper electrode on the emission layer; forming a first inorganic encapsulation layer on the upper electrode; forming a second inorganic encapsulation layer on the first inorganic encapsulation layer by using a mask having an opening portion in a region overlapping with the pixel openings to fill the pixel openings; and forming a third inorganic encapsulation layer on the second inorganic encapsulation layer, wherein the film density of the second inorganic encapsulation layer is lower than the film density of the first inorganic encapsulation layer.

[0024] In one embodiment, the third inorganic encapsulation layer may be spaced apart from the first inorganic encapsulation layer in the region overlapping with the pixel openings, and may be directly located on the first inorganic encapsulation layer in a region overlapping with the pixel defining layer.

[0025] In one embodiment, the deposition rate of the second inorganic encapsulation layer may be greater than that of the first inorganic encapsulation layer.

[0026] In one embodiment, the deposition rate of the third inorganic encapsulation layer may be less than that of the second inorganic encapsulation layer.

[0027] In one embodiment, the film density of the second inorganic encapsulation layer may be lower than that of the first inorganic encapsulation layer.

[0028] In one embodiment, the film density of the second inorganic encapsulation layer may be lower than that of the third inorganic encapsulation layer. Description of the Drawings

[0029] The above and other aspects, features, and advantages of the present invention will become more apparent from the following description in conjunction with the drawings, in which:

[0030] Figure 1 is a perspective view illustrating a display device according to an embodiment;

[0031] Figure 2A is an equivalent circuit diagram illustrating a pixel included in a display device according to an embodiment;

[0032] Figure 2B is an equivalent circuit diagram illustrating a pixel included in a display device according to an embodiment;

[0033] Figure 3 is a cross-sectional view schematically illustrating a display device according to an embodiment;

[0034] Figure 4A is a cross-sectional view schematically illustrating a method of manufacturing a display device according to an embodiment;

[0035] Figure 4B is a cross-sectional view schematically illustrating a method of manufacturing a display device according to an embodiment;

[0036] Figure 4C is a cross-sectional view schematically illustrating a method of manufacturing a display device according to an embodiment;

[0037] Figure 4D is a cross-sectional view schematically illustrating a method of manufacturing a display device according to an embodiment; and

[0038] Figure 4E is a cross-sectional view schematically illustrating a method of manufacturing a display device according to an embodiment. Detailed Description of the Invention

[0039] Reference will now be made in detail to the present invention, examples and embodiments of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present invention may have different forms and should not be construed as limited to the descriptions set forth herein. Accordingly, the embodiments are described below only by reference to the figures to illustrate aspects of the present invention. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variants thereof.

[0040] Since the scope of the present invention allows for various variations and many embodiments, certain embodiments will be illustrated in the accompanying drawings and described in the detailed description. The effects and features of the present invention and the methods for achieving them will be elucidated with reference to the embodiments described in detail below with reference to the drawings. However, the present invention is not limited to the following embodiments and can be implemented in various forms.

[0041] Although terms such as "first", "second", etc. may be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0042] As used herein, the singular forms "a" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise.

[0043] It will be further understood that the terms "comprises" or "comprising" when used herein specify the presence of the stated feature or component, but do not preclude the presence or addition of one or more other features or components.

[0044] It will be further understood that when a layer, region, or component is referred to as being "on" another layer, region, or component, it can be directly on the other layer, region, or component, or can be indirectly on the other layer, region, or component with intervening layers, regions, or components therebetween.

[0045] In addition, for ease of illustration, the dimensions of the components in the drawings may be enlarged or reduced. For example, since the dimensions (e.g., thickness) of the components in the drawings are arbitrarily illustrated for ease of illustration, the present invention is not limited thereto.

[0046] When a particular embodiment can be implemented differently, the specific process sequence may be different from that described. For example, two consecutively described processes may be performed substantially simultaneously, or may be performed in an order opposite to that described.

[0047] It will be understood that when a layer, region or component is referred to as "connected", these layers, regions or components may be directly connected, or may be indirectly connected using an intermediate layer, region or component therebetween. For example, when a layer, region or component is referred to as "electrically connected", these layers, regions or components may be directly electrically connected, or may be indirectly electrically connected using an intermediate layer, region or component therebetween.

[0048] The x-axis, y-axis and z-axis are not limited to the three axes of a rectangular coordinate system and may be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis may be oriented perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0049] In this specification, "A and / or B" means A or B or A and B. In this specification, "at least one of A and B" means A or B or A and B.

[0050] Figure 1 FIG. is a perspective view illustrating a display device 1 according to an embodiment.

[0051] In one embodiment and with reference to Figure 1 , the display device 1 may include a display area DA in which a plurality of pixels P are located and a non-display area NDA located outside the display area DA. Specifically, the non-display area NDA may completely surround the display area DA. Accordingly, the substrate 100 included in the display device 1 (see Figure 3 ) may include the display area DA and the non-display area NDA.

[0052] In one embodiment, each pixel P of the display device 1 is disposed in an area that can emit light of a specific color, and the display device 1 may provide an image by using the light emitted from the pixel P. For example, each pixel P may emit red light, green light or blue light.

[0053] In one embodiment, the display area DA may have any polygonal shape, including the quadrilateral shape as shown in Figure 1 . For example, the display area DA may have a rectangular shape with a horizontal length greater than a vertical length, a rectangular shape with a horizontal length less than a vertical length, or a square shape. In another embodiment, the display area DA may have any shape among various shapes, such as an oval shape or a circular shape. Thus, the display area DA may have any shape suitable for the desired final purpose.

[0054] In one embodiment, the non-display area NDA may be an area in which the pixel P is not located. A driver or the like for applying an electrical signal or power to the pixel P may be located in the non-display area NDA. Pads (not shown) to which various electronic devices or printed circuit boards may be electrically connected may be located in the non-display area NDA. The pads may be located in the non-display area NDA and may be spaced apart from each other, and may each be electrically connected to a printed circuit board or an integrated circuit board.

[0055] Figure 2A and Figure 2B is an equivalent circuit diagram showing one pixel P included in the display device 1 according to an embodiment.

[0056] In one embodiment and with reference to Figure 2A , each pixel P may include a pixel circuit PC connected to a scan line SL and a data line DL, and a light emitting element LED connected to the pixel circuit PC.

[0057] In one embodiment, the pixel circuit PC may include a driving thin film transistor T1, a switching thin film transistor T2, and a storage capacitor Cst.

[0058] The switching thin film transistor T2 transmits a data signal Dm input through the data line DL to the driving thin film transistor T1 according to a scan signal Sn input through the scan line SL.

[0059] In one embodiment, the storage capacitor Cst is connected to the switching thin film transistor T2 and a driving voltage line PL, and stores a voltage corresponding to the difference between the voltage received from the switching thin film transistor T2 and the first power supply voltage ELVDD (or driving voltage) supplied to the driving voltage line PL.

[0060] In one embodiment, the driving thin film transistor T1 may be connected to the driving voltage line PL and the storage capacitor Cst, and may control a driving current flowing from the driving voltage line PL to the light emitting element LED in response to the value of the voltage stored in the storage capacitor Cst. The light emitting element LED may emit light with a certain brightness due to the driving current.

[0061] Although in Figure 2A the pixel circuit PC is shown as including two thin film transistors and one storage capacitor, the present invention is not limited thereto.

[0062] In one embodiment and with reference to Figure 2B , the pixel circuit PC may include a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, a first initialization thin film transistor T4, a first emission control thin film transistor T5, a second emission control thin film transistor T6, and a second initialization thin film transistor T7.

[0063] Although in Figure 2B each pixel P is shown as including signal lines (e.g., SLn, SLn-1, EL, and DL), an initialization voltage line VL, and a driving voltage line PL, the present invention is not limited thereto. In another embodiment, at least one of the signal lines (e.g., SLn, SLn-1, EL, and DL) and / or the initialization voltage line VL may be shared by adjacent pixels.

[0064] In one embodiment, the drain electrode of the driving thin film transistor T1 may be electrically connected to the light emitting diode LED via the second emission control thin film transistor T6. The driving thin film transistor T1 receives the data signal Dm and supplies a driving current to the light emitting element LED according to the switching operation of the switching thin film transistor T2.

[0065] In one embodiment, the gate electrode of the switching thin film transistor T2 is connected to the first scan line SLn, and the source electrode of the switching thin film transistor T2 is connected to the data line DL. The drain electrode of the switching thin film transistor T2 may be connected to the source electrode of the driving thin film transistor T1 and may be connected to the driving voltage line PL via the first emission control thin film transistor T5.

[0066] The switching thin film transistor T2 is turned on according to the first scan signal Sn received through the first scan line SLn and performs a switching operation of transmitting the data signal Dm received through the data line DL to the source electrode of the driving thin film transistor T1.

[0067] In one embodiment, the gate electrode of the compensation thin film transistor T3 may be connected to the first scan line SLn. The source electrode of the compensation thin film transistor T3 may be connected to the drain electrode of the driving thin film transistor T1 and may be connected to the pixel electrode of the light emitting diode LED via the second emission control thin film transistor T6. The drain electrode of the compensation thin film transistor T3 may be connected to one electrode of the storage capacitor Cst, the source electrode of the first initialization thin film transistor T4, and the gate electrode of the driving thin film transistor T1. The compensation thin film transistor T3 is turned on according to the first scan signal Sn received through the first scan line SLn and diode - connects the driving thin film transistor T1 by connecting the gate electrode and the drain electrode of the driving thin film transistor T1.

[0068] In one embodiment, the gate electrode of the first initialization thin film transistor T4 may be connected to the second scan line (previous scan line) SLn - 1. The drain electrode of the first initialization thin film transistor T4 may be connected to the initialization voltage line VL. The source electrode of the first initialization thin film transistor T4 may be connected to one electrode of the storage capacitor Cst, the drain electrode of the compensation thin film transistor T3, and the gate electrode of the driving thin film transistor T1. The first initialization thin film transistor T4 may be turned on according to the second scan signal Sn - 1 received through the second scan line SLn - 1 and may perform an initialization operation of initializing the voltage of the gate electrode of the driving thin film transistor T1 by supplying the initialization voltage VINT to the gate electrode of the driving thin film transistor T1.

[0069] In one embodiment, the gate electrode of the first emission control thin film transistor T5 may be connected to the emission control line EL. The source electrode of the first emission control thin film transistor T5 may be connected to the driving voltage line PL. The drain electrode of the first emission control thin film transistor T5 is connected to the source electrode of the driving thin film transistor T1 and the drain electrode of the switching thin film transistor T2.

[0070] In one embodiment, the gate electrode of the second emission control thin film transistor T6 may be connected to the emission control line EL. The source electrode of the second emission control thin film transistor T6 may be connected to the drain electrode of the driving thin film transistor T1 and the source electrode of the compensation thin film transistor T3. The drain electrode of the second emission control thin film transistor T6 may be electrically connected to the pixel electrode of the light emitting diode LED. According to the emission control signal En received through the emission control line EL, the first emission control thin film transistor T5 and the second emission control thin film transistor T6 are turned on simultaneously. Accordingly, the first power supply voltage ELVDD is supplied to the light emitting diode LED to cause a driving current to flow through the light emitting diode LED.

[0071] In one embodiment, the gate electrode of the second initialization thin film transistor T7 may be connected to the second scan line SLn-1. The source electrode of the second initialization thin film transistor T7 may be connected to the pixel electrode of the light emitting element LED. The drain electrode of the second initialization thin film transistor T7 may be connected to the initialization voltage line VL. The second initialization thin film transistor T7 may be turned on according to the second scan signal Sn-1 received through the second scan line SLn-1 and may initialize the pixel electrode of the light emitting diode LED.

[0072] Although in Figure 2B one embodiment the first initialization thin film transistor T4 and the second initialization thin film transistor T7 are shown connected to the second scan line SLn-1, the present invention is not limited thereto. In another embodiment, the first initialization thin film transistor T4 may be connected to the second scan line SLn-1 which is the previous scan line to be driven according to the second scan signal Sn-1, and the second initialization thin film transistor T7 may be connected to a separate signal line (e.g., the next scan line) to be driven according to the signal transmitted to the separate scan line.

[0073] In one embodiment, the other electrode of the storage capacitor Cst may be connected to the driving voltage line PL. One electrode of the storage capacitor Cst may be connected to the gate electrode of the driving thin film transistor T1, the drain electrode of the compensation thin film transistor T3, and the source electrode of the first initialization thin film transistor T4.

[0074] The counter electrode (e.g., cathode) of the light emitting diode LED receives the second power supply voltage ELVSS (or common power supply voltage). Accordingly, the light emitting element LED receives a driving current from the driving thin film transistor T1 to emit light.

[0075] The pixel circuit PC is not limited to the number and circuit design of the thin film transistors and storage capacitors referred to Figure 2A and Figure 2B described, and in other embodiments, the number and circuit design can be modified in various ways.

[0076] Figure 3 FIG. is a cross-sectional view schematically illustrating a display device 1 according to an embodiment.

[0077] In one embodiment and with reference to Figure 3 , the display device 1 may include a substrate 100, a pixel circuit layer PCL disposed on the substrate 100, first to third light emitting elements LED1, LED2, and LED3 respectively disposed on the pixel circuit layer PCL, and a packaging layer 300 disposed on the light emitting elements LED1, LED2, and LED3.

[0078] In one embodiment, the substrate 100 may include glass, metal, or a polymer resin. The polymer resin may include, for example, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose acetate propionate, or a mixture thereof. However, in other embodiments, various modifications can be made. For example, in another embodiment, the substrate 100 may have a multilayer structure that includes two layers each containing a polymer resin and an isolation layer that contains an inorganic material (e.g., silicon oxide (SiO x ), silicon nitride (SiN x ), or silicon oxynitride (SiO x N y )) and is located between the two layers.

[0079] In one embodiment, the pixel circuit layer PCL may include a first pixel circuit PC1, a second pixel circuit PC2, and a third pixel circuit PC3. Each of the pixel circuits PC1, PC2, and PC3 may include transistors and storage capacitors as described in reference to Figure 2A or Figure 2B . In one embodiment, Figure 3 FIG. illustrates thin film transistors TFT and storage capacitors Cst provided in each of the pixel circuits PC1, PC2, and PC3.

[0080] In one embodiment, the pixel circuit layer PCL may include a buffer layer 101, a first insulating layer 103, a second insulating layer 105, a third insulating layer 107, a thin film transistor TFT, and a fourth insulating layer 110.

[0081] In one embodiment, the buffer layer 101 may be located on the substrate 100 to planarize the top surface of the substrate 100 and prevent impurities from penetrating from the substrate 100. The buffer layer 101 may include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ), or silicon oxynitride (SiO x N y ). The buffer layer 101 may have a single-layer or multi-layer structure including the above inorganic insulating materials.

[0082] In one embodiment, each of the first pixel circuit to the third pixel circuit PC1, PC2, and PC3 may include a thin film transistor TFT and a storage capacitor Cst. The thin film transistor TFT may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0083] In one embodiment, the semiconductor layer Act may be located on the buffer layer 101, where the semiconductor layer Act may include an oxide semiconductor and / or a silicon semiconductor. In one embodiment, when the semiconductor layer Act is formed of an oxide semiconductor, the semiconductor layer Act may include an oxide of at least one material selected from the group consisting of, for example, indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). For example, the semiconductor layer Act may be an InSnZnO (ITZO) semiconductor layer or an InGaZnO (IGZO) semiconductor layer. In another embodiment, when the semiconductor layer Act is formed of a silicon semiconductor, the semiconductor layer Act may include, for example, amorphous silicon or low-temperature polycrystalline silicon (LTPS).

[0084] In one embodiment, the gate electrode GE may be located on the semiconductor layer Act, and a first insulating layer 103 is provided therebetween. The gate electrode GE may overlap with the channel region of the semiconductor layer Act. The gate electrode GE may include a low-resistance metal material. For example, in one embodiment, the gate electrode GE may have a single-layer or multi-layer structure including at least one metal selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). The gate electrode GE may be connected to a gate line for applying an electrical signal to the gate electrode GE.

[0085] In one embodiment, the first insulating layer 103 may be located on the buffer layer 101 and may be located between the semiconductor layer Act and the gate electrode GE. The first insulating layer 103 may include an inorganic insulating material such as silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiOx N y ) alumina (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO x , which may be ZnO and / or ZnO2).

[0086] In one embodiment, the second insulating layer 105 may be located on the first insulating layer 103 and may cover the gate electrode GE. Similar to the first insulating layer 103, the second insulating layer 105 may comprise an inorganic insulating material such as silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), alumina (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO x , which may be ZnO and / or ZnO2).

[0087] In one embodiment, the second capacitor electrode CE2 of the storage capacitor Cst may be located on the second insulating layer 105. In one embodiment, the second capacitor electrode CE2 may overlap with the gate electrode GE. In this case, the gate electrode GE and the second capacitor electrode CE2 (overlapping with each other and with the second insulating layer 105 disposed therebetween) may constitute the storage capacitor Cst. That is, the gate electrode GE may be used as the first capacitor electrode CE1 of the storage capacitor Cst. Thus, the storage capacitor Cst and the thin film transistor TFT may overlap with each other. In another embodiment, the storage capacitor Cst and the thin film transistor TFT may not overlap with each other.

[0088] In one embodiment, the third insulating layer 107 may be located on the second insulating layer 105 and may cover the second capacitor electrode CE2. The third insulating layer 107 may comprise silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), alumina (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO x , which may be ZnO and / or ZnO2). The third insulating layer 107 may have a single-layer or multi-layer structure comprising the above inorganic insulating materials.

[0089] In one embodiment, each of the source electrode SE and the drain electrode DE may be located on the third insulating layer 107, wherein the source electrode SE and the drain electrode DE may be electrically connected to the semiconductor layer Act through contact holes formed in the first insulating layer 103, the second insulating layer 105, and the third insulating layer 107. The source electrode SE and the drain electrode DE may include a material having good electrical conductivity. At least one of the source electrode SE and the drain electrode DE may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a single-layer or multi-layer structure including the above materials. In one embodiment, at least one of the source electrode SE and the drain electrode DE may have a multi-layer structure including Ti / Al / Ti.

[0090] In one embodiment, the fourth insulating layer 110 may be located on the third insulating layer 107. The fourth insulating layer 110 may further be located on the source electrode SE and the drain electrode DE. Although the fourth insulating layer 110 is shown as having a single-layer structure, the present invention is not limited thereto, and in another embodiment, the fourth insulating layer 110 may have a multi-layer structure. The fourth insulating layer 110 may be an organic insulating layer including an organic material. The fourth insulating layer 110 may include an organic insulating material such as a general polymer (such as polymethyl methacrylate (PMMA) or polystyrene (PS)), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorinated polymer, a parylene polymer, a vinyl alcohol polymer, or a blend thereof. The fourth insulating layer 110 may planarize the top surfaces of the pixel circuits PC1, PC2, and PC3 to planarize the surfaces on which the light-emitting elements LED1, LED2, and LED3 will be located.

[0091] In one embodiment, the light-emitting elements LED1, LED2, and LED3 may emit light of different colors. For example, the first light-emitting element LED1 may emit red light, the second light-emitting element LED2 may emit green light, and the third light-emitting element LED3 may emit blue light.

[0092] In one embodiment, the light-emitting elements LED1, LED2, and LED3 may be organic light-emitting diodes each including an organic emission layer. In another embodiment, the light-emitting elements LED1, LED2, and LED3 may be inorganic light-emitting elements each including an inorganic emission layer. The light-emitting elements LED1, LED2, and LED3 may be micrometer-sized or nanometer-sized light-emitting elements. For example, the light-emitting elements LED1, LED2, and LED3 may be micro light-emitting elements. In another embodiment, the light-emitting elements LED1, LED2, and LED3 may be nanorod light-emitting elements. The nanorod light-emitting elements may include gallium nitride (GaN). In one embodiment, a color conversion layer may be disposed on each of the nanorod light-emitting elements. The color conversion layer may include quantum dots. In another embodiment, the light-emitting elements LED1, LED2, and LED3 may be quantum dot light-emitting diodes each including a quantum dot emission layer.

[0093] In one embodiment, the first light-emitting element LED1, the second light-emitting element LED2, and the third light-emitting element LED3 may be electrically connected to a first pixel circuit PC1, a second pixel circuit PC2, and a third pixel circuit PC3 located between the substrate 100 and the light-emitting elements LED1, LED2, and LED3, respectively, in a direction (e.g., the z direction) perpendicular to the top surface of the substrate 100.

[0094] In one embodiment, each of the light-emitting elements LED1, LED2, and LED3 may have a stacked structure including a lower electrode, an intermediate layer, and an upper electrode. The first lower electrodes 210a, 210b, and 210c of the first light-emitting diode LED1, the second light-emitting diode LED2, and the third light-emitting diode LED3 may be anodes, respectively, and the upper electrode 230 may be a cathode, but the present invention is not limited thereto. For example, in one embodiment, the light-emitting elements LED1, LED2, and LED3 may be inverted light-emitting elements. For example, in one embodiment, the first to third lower electrodes 210a, 210b, and 210c may be cathodes, respectively, and the upper electrode 230 may be an anode. For ease of explanation, it will be assumed that the first to third lower electrodes 210a, 210b, and 210c are anodes, respectively, and the upper electrode 230 is a cathode to describe the following content.

[0095] In one embodiment, the first light-emitting element LED1 may include a first lower electrode 210a, a first intermediate layer 220a, and an upper electrode 230. The first lower electrode 210a may be electrically connected to the first pixel circuit PC1. The second light-emitting element LED2 may include a second lower electrode 210b, a second intermediate layer 220b, and an upper electrode 230. The second lower electrode 210b may be electrically connected to the second pixel circuit PC2. The third light-emitting element LED3 may include a third lower electrode 210c, a third intermediate layer 220c, and an upper electrode 230. The third lower electrode 210c may be electrically connected to the third pixel circuit PC3.

[0096] In one embodiment, the lower electrodes 210a, 210b, and 210c may be respectively located on the fourth insulating layer 110. The lower electrodes 210a, 210b, and 210c may be electrically connected to thin film transistors TFTs provided in pixel circuits PC1, PC2, and PC3, respectively. For example, the first lower electrode 210a may be electrically connected to the thin film transistor TFT of the first pixel circuit PC1 through a contact hole in the fourth insulating layer 110.

[0097] In one embodiment, each of the lower electrodes 210a, 210b, and 210c may include a conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In another embodiment, each of the lower electrodes 210a, 210b, and 210c may include a reflective film including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In yet another embodiment, each of the lower electrodes 210a, 210b, and 210c may further include a film formed of ITO, IZO, ZnO, or In2O3 above and / or below the reflective film.

[0098] In one embodiment, the pixel defining layer 130 may be located on the fourth insulating layer 110. The pixel defining layer 130 may be located on the lower electrodes 210a, 210b, and 210c, and may include: a first pixel opening OP1 through which a part of the first lower electrode 210a is exposed; a second pixel opening OP2 through which a part of the second lower electrode 210b is exposed; and a third pixel opening OP3 through which a part of the third lower electrode 210c is exposed. That is, at least a part of the surfaces of the first lower electrode 210a, the second lower electrode 210b, and the third lower electrode 210c may be respectively exposed through the first pixel opening OP1, the second pixel opening OP2, and the third pixel opening OP3 defined in the pixel defining layer 130. In one embodiment, the parts exposed through the first to third pixel openings OP1, OP2, and OP3 of the pixel defining layer 130 may be respectively defined as a first emission region EA1, a second emission region EA2, and a third emission region EA3. The pixel defining layer 130 may include an organic insulating material and / or an inorganic insulating material.

[0099] In one embodiment, the first intermediate layer 220a, the second intermediate layer 220b, and the third intermediate layer 220c may be respectively located in the first pixel opening OP1, the second pixel opening OP2, and the third pixel opening OP3 of the pixel defining layer 130. The first intermediate layer 220a, the second intermediate layer 220b, and the third intermediate layer 220c may be respectively located on the first lower electrode 210a, the second lower electrode 210b, and the third lower electrode 210c. Each of the intermediate layers 220a, 220b, and 220c may include, for example, an emission layer. The emission layer may be, for example, an organic emission layer. The organic emission layer may contain an organic material, which includes a fluorescent or phosphorescent material that emits red, green, blue, or white light.

[0100] In one embodiment, the first intermediate layer 220a located between the first lower electrode 210a and the upper electrode 230 may emit light of a first color. The second intermediate layer 220b located between the second lower electrode 210b and the upper electrode 230 may emit light of a second color. The third intermediate layer 220c located between the third lower electrode 210c and the upper electrode 230 may emit light of a third color. For example, the intermediate layers 220a, 220b, and 220c may emit light of different colors.

[0101] In one embodiment, each of the intermediate layers 220a, 220b, and 220c may include a common layer located below and / or above the emission layer. The common layer may include a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and / or an electron injection layer (EIL), and may cover a plurality of lower electrodes, such as the lower electrodes 210a, 210b, and 210c, like the upper electrode 230. In other words, the upper electrode 230 and the common layer may be shared by the light emitting diodes LED1, LED2, and LED3.

[0102] In one embodiment, the upper electrode 230 may be located on the intermediate layers 220a, 220b, and 220c, and may completely cover the substrate 100 in the display area DA (see Figure 1 ). The upper electrode 230 may be a transmissive electrode or a reflective electrode, and may be formed of a conductive material having a low work function. For example, in one embodiment, the upper electrode 230 may include a transparent layer or a translucent layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. In another embodiment, the upper electrode 230 may further include a layer formed of ITO, IZO, ZnO, or In2O3 on the transparent layer or the translucent layer containing the above materials.

[0103] In one embodiment, the encapsulation layer 300 may encapsulate the light-emitting elements LED1, LED2, and LED3, and the encapsulation layer 300 may be located on the light-emitting elements LED1, LED2, and LED3. The encapsulation layer 300 may include a plurality of inorganic encapsulation layers including an inorganic material. For example, the encapsulation layer 300 may include a first inorganic encapsulation layer 310 disposed on the upper electrode 230, a second inorganic encapsulation layer 320 disposed on the first inorganic encapsulation layer 310, and a third inorganic encapsulation layer 330 disposed on the second inorganic encapsulation layer 320. In one embodiment, the encapsulation layer 300 may not include an organic encapsulation layer including an organic material.

[0104] In one embodiment, each of the first inorganic encapsulation layer 310 and the third inorganic encapsulation layer 330 may completely cover the substrate 100. For example, each of the first inorganic encapsulation layer 310 and the third inorganic encapsulation layer 330 may cover the light-emitting elements LED1, LED2, and LED3. For example, each of the first inorganic encapsulation layer 310 and the third inorganic encapsulation layer 330 may overlap with the pixel openings OP1, OP2, and OP3, and may overlap with the pixel defining layer 130. That is, each of the first inorganic encapsulation layer 310 and the third inorganic encapsulation layer 330 may overlap with a first emission region EA1, a second emission region EA2, and a third emission region EA3 defined by the first pixel opening OP1, the second pixel opening OP2, and the third pixel opening OP3, respectively, and may overlap with the pixel defining layer 130 located outside the emission regions EA1, EA2, and EA3.

[0105] In one embodiment, in a region overlapping with the pixel openings OP1, OP2, and OP3, since the second inorganic encapsulation layer 320 is located between the first inorganic encapsulation layer 310 and the third inorganic encapsulation layer 330, the third inorganic encapsulation layer 330 may be spaced apart from the first inorganic encapsulation layer 310. In other words, in the emission regions EA1, EA2, and EA3, the third inorganic encapsulation layer 330 may be spaced apart from the first inorganic encapsulation layer 310 in a direction perpendicular to the top surface of the substrate 100 (e.g., the z direction). In a region overlapping with the pixel openings OP1, OP2, and OP3, the encapsulation layer 300 may have a three-layer structure in which the first inorganic encapsulation layer 310, the second inorganic encapsulation layer 320, and the third inorganic encapsulation layer 330 are sequentially stacked.

[0106] In one embodiment, in a region overlapping with the pixel defining layer 130, the third inorganic encapsulation layer 330 may be directly located on the first inorganic encapsulation layer 310. In other words, in a region overlapping with the pixel defining layer 130, the third inorganic encapsulation layer 330 may be in contact with the first inorganic encapsulation layer 310. As Figure 3As shown, the encapsulation layer 300 may have a two-layer structure including a first inorganic encapsulation layer 310 and a third inorganic encapsulation layer 330 in a region overlapping with the pixel definition layer 130. However, the present invention is not limited thereto. In another embodiment, when the first inorganic encapsulation layer 310 and the third inorganic encapsulation layer 330 are deposited using the same precursor under the same deposition conditions (e.g., deposition method or deposition rate), the encapsulation layer 300 may have a single-layer structure in which the first inorganic encapsulation layer 310 and the third inorganic encapsulation layer 330 are combined with each other in a region overlapping with the pixel definition layer 130.

[0107] In one embodiment, the second inorganic encapsulation layer 320 may be located in each of the pixel openings OP1, OP2, and OP3. The second inorganic encapsulation layer 320 may overlap each of the pixel openings OP1, OP2, and OP3 and may not overlap with the pixel definition layer 130. The second inorganic encapsulation layer 320 may be located between the first inorganic encapsulation layer 310 and the third inorganic encapsulation layer 330 in each of the emission regions EA1, EA2, and EA3.

[0108] In one embodiment, the second inorganic encapsulation layer 320 may include a first inorganic encapsulation pattern 320a located in the first pixel opening OP1, a second inorganic encapsulation pattern 320b located in the second pixel opening OP2, and a third inorganic encapsulation pattern 320c located in the third pixel opening OP3. That is, the first inorganic encapsulation pattern 320a may be located in the first emission region EA1, the second inorganic encapsulation pattern 320b may be located in the second emission region EA2, and the third inorganic encapsulation pattern 320c may be located in the third emission region EA3. The first inorganic encapsulation pattern 320a may overlap with the first light-emitting element LED1, the second inorganic encapsulation pattern 320b may overlap with the second light-emitting element LED2, and the third inorganic encapsulation pattern 320c may overlap with the third light-emitting element LED3. The inorganic encapsulation patterns 320a, 320b, and 320c may be spaced apart from each other in a first direction (e.g., the x direction).

[0109] In one embodiment, the second inorganic encapsulation layer 320 may have a structure that fills each of the pixel openings OP1, OP2, and OP3. The first inorganic encapsulation pattern 320a, the second inorganic encapsulation pattern 320b, and the third inorganic encapsulation pattern 320c may respectively overlap with the first pixel opening OP1, the second pixel opening OP2, and the third pixel opening OP3 and may not overlap with the pixel definition layer 130.

[0110] Since the second inorganic encapsulation layer 320 is formed as a low-density layer as described below, the second inorganic encapsulation layer 320 can fill each of the pixel openings OP1, OP2, and OP3 of the pixel defining layer 130. Since the second inorganic encapsulation layer 320 does not overlap with the pixel defining layer 130 and fills each of the pixel openings OP1, OP2, and OP3, the top surface of the second inorganic encapsulation layer 320 can be located at substantially the same level as the top surface of the portion of the first inorganic encapsulation layer 310 that overlaps with the pixel defining layer 130. Accordingly, the top surface of the encapsulation layer 300 can be flattened.

[0111] Unlike the comparative example in which the top surface of the encapsulation layer 300 is flattened by completely forming an organic encapsulation layer on the substrate 100 in the display area DA, the embodiment may not include an organic encapsulation layer. Moreover, since the top surface of the encapsulation layer 300 is flattened by forming the second inorganic encapsulation layer 320 having a low density to overlap only with the pixel openings OP1, OP2, and OP3, the thickness of the encapsulation layer 300 can be reduced compared to the case where the organic encapsulation layer is completely formed on the top surface of the first inorganic encapsulation layer 310. That is, since the thickness Ta of the encapsulation layer 300 in the region overlapping with the pixel openings OP1, OP2, and OP3 and the thickness Tb of the encapsulation layer 300 in the region overlapping with the pixel defining layer 130 are reduced, the display device 1 having a small thickness can be provided.

[0112] For example, in one embodiment, in the region overlapping with the pixel openings OP1, OP2, and OP3, the thickness Ta of the encapsulation layer 300 can be about 3 μm or less. For example, in one embodiment, in the region overlapping with the pixel openings OP1, OP2, and OP3, the thickness Ta of the encapsulation layer 300 can be about 2 μm or less. For example, in one embodiment, in the region overlapping with the pixel defining layer 130, the thickness Tb of the encapsulation layer 300 can be about 1 μm or less. For example, in one embodiment, in the region overlapping with the pixel defining layer 130, the thickness Tb of the encapsulation layer 300 can be in the range of about 0.002 μm to about 0.02 μm. That is, the thickness of the encapsulation layer 300 located above the pixel defining layer 130 can be as small as about 1 μm or less.

[0113] In one embodiment, the thickness of the second inorganic encapsulation layer 320 in a direction perpendicular to the top surface of the substrate 100 (e.g., the thickness direction or the z direction) can be greater than the thickness of the first inorganic encapsulation layer 310. For example, the thickness of the first inorganic encapsulation layer 310 can be in the range of about to about , and the thickness of the second inorganic encapsulation layer 320 can be greater than about For example, the thickness of the third inorganic encapsulation layer 330 can be in the range of about to about , but is not limited thereto.

[0114] In one embodiment, each of the first inorganic encapsulation layer 310, the second inorganic encapsulation layer 320, and the third inorganic encapsulation layer 330 may include an inorganic material. For example, each of the inorganic encapsulation layers 310, 320, and 330 may include an inorganic material such as silicon nitride (SiN x ), silicon oxide (SiO x ), or silicon oxynitride (SiO x N y ).

[0115] In one embodiment, each of the inorganic encapsulation layers 310, 320, and 330 may include an inorganic material including silicon (Si) element and nitrogen (N) element. For example, each of the inorganic encapsulation layers 310, 320, and 330 may include silicon nitride (SiN x ), or silicon oxynitride (SiO x N y ).

[0116] In one embodiment, when each of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 320 includes an inorganic material including silicon (Si) element and nitrogen (N) element, the ratio of nitrogen element to silicon element (N / Si ratio) of the first inorganic encapsulation layer 310 may be less than the ratio of nitrogen element to silicon element (N / Si ratio) of the second inorganic encapsulation layer 320. For example, the ratio of nitrogen element to silicon element of the first inorganic encapsulation layer 310 may be less than about 0.75, and the ratio of nitrogen element to silicon element of the second inorganic encapsulation layer 320 may be greater than about 0.77. When each of the third inorganic encapsulation layer 330 and the second inorganic encapsulation layer 320 includes an inorganic material including silicon (Si) element and nitrogen (N) element, the ratio of nitrogen element to silicon element (N / Si ratio) of the third inorganic encapsulation layer 330 may be less than the ratio of nitrogen element to silicon element (N / Si ratio) of the second inorganic encapsulation layer 320. For example, the ratio of nitrogen element to silicon element of the third inorganic encapsulation layer 330 may be less than about 0.75, and the ratio of nitrogen element to silicon element of the second inorganic encapsulation layer 320 may be greater than about 0.77.

[0117] In one embodiment, the film density of the first inorganic encapsulation layer 310 and the film density of the second inorganic encapsulation layer 320 may be different from each other. Additionally, the film density of the third inorganic encapsulation layer 330 and the film density of the second inorganic encapsulation layer 320 may be different from each other. The film density of the second inorganic encapsulation layer 320 may be less than the film density of the first inorganic encapsulation layer 310. That is, the first inorganic encapsulation layer 310 may be a relatively high-density layer, and the second inorganic encapsulation layer 320 may be a relatively low-density layer. The film density of the second inorganic encapsulation layer 320 may be less than the film density of the third inorganic encapsulation layer 330. That is, the third inorganic encapsulation layer 330 may be a relatively high-density layer, and the second inorganic encapsulation layer 320 may be a relatively low-density layer. For example, in one embodiment, the film density of the first inorganic encapsulation layer 310 may be in the range of about 2.6 g / cm 3 to about 3.5 g / cm 3 For example, in one embodiment, the film density of the second inorganic encapsulation layer 320 may be in the range of about 1.6 g / cm 3 to about 2.3 g / cm 3 For example, in one embodiment, the film density of the third inorganic encapsulation layer 330 may be in the range of about 2.6 g / cm 3 to about 3.5 g / cm 3 In the region overlapping with the pixel openings OP1, OP2, and OP3, since the first inorganic encapsulation layer 310 and the third inorganic encapsulation layer 330, which are high-density layers, are respectively located below and above the second inorganic encapsulation layer 320, which is a low-density layer, the encapsulation layer 300 can prevent impurities such as oxygen or moisture from penetrating into the emission regions EA1, EA2, and EA3. In the region overlapping with the pixel defining layer 130, since the third inorganic encapsulation layer 330, which is a high-density layer, is further located on the first inorganic encapsulation layer 310, which is also a high-density layer, the isolation characteristics of the encapsulation layer 300 for preventing impurities such as oxygen or moisture from penetrating into the pixel defining layer 130 can be improved.

[0118]

[0119] ​In one embodiment, when the second inorganic encapsulation layer 320, which is a low-density layer, is directly formed on the light-emitting elements LED1, LED2, and LED3, the isolation characteristics of the second inorganic encapsulation layer 320 may be reduced due to the low film density. According to one embodiment, since the first inorganic encapsulation layer 310 having a high density is first formed and then the second inorganic encapsulation layer 320 having a low density is formed on the first inorganic encapsulation layer 310, the first inorganic encapsulation layer 310 can be used as a seed layer. Accordingly, compared with the case where the second inorganic encapsulation layer 320 is directly formed on the light-emitting elements LED1, LED2, and LED3 without forming the first inorganic encapsulation layer 310, the second inorganic encapsulation layer 320 may have a relatively high film density at the interface with the first inorganic encapsulation layer 310 disposed adjacent to the second inorganic encapsulation layer 320. Accordingly, the second inorganic encapsulation layer 320 can be formed at a relatively low density to fill and planarize the pixel openings OP1, OP2, and OP3, and the isolation characteristics of the second inorganic encapsulation layer 320 can also be improved.

[0120] In one embodiment, the refractive index of the first inorganic encapsulation layer 310 may be greater than the refractive index of the second inorganic encapsulation layer 320, and the refractive index of the third inorganic encapsulation layer 330 may be greater than the refractive index of the second inorganic encapsulation layer 320. For example, in one embodiment, the refractive index of the first inorganic encapsulation layer 310 may be about 1.85 or greater. For example, in one embodiment, the refractive index of the second inorganic encapsulation layer 320 may be about 1.75 to about 1.90. For example, in one embodiment, the refractive index of the third inorganic encapsulation layer 330 may be about 1.85 or greater.

[0121] Figures 4A to 4E A cross-sectional view schematically illustrating a method of manufacturing a display device according to one embodiment. Figures 4A to 4E In correspondence with Figure 3 the cross section corresponding to the cross-sectional view of the display device 1, a manufacturing method according to one embodiment is illustrated in sequence.

[0122] In one embodiment and with reference to Figure 4A a pixel circuit layer PCL disposed on the substrate 100, lower electrodes 210a, 210b, and 210c disposed on the pixel circuit layer PCL, and a pixel defining layer 130 disposed on the lower electrodes 210a, 210b, and 210c disposed on the pixel circuit layer PCL may be formed.

[0123] First, according to one embodiment, a pixel circuit layer PCL including pixel circuits PC1, PC2, and PC3 may be formed on the substrate 100. For example, a buffer layer 101, a semiconductor layer Act, a first insulating layer 103, a gate electrode GE, a second insulating layer 105, a second capacitor electrode CE2, a third insulating layer 107, source and drain electrodes SE and DE, and a fourth insulating layer 110 may be sequentially formed on the substrate 100.

[0124] Next, according to an embodiment, a first lower electrode 210a, a second lower electrode 210b, and a third lower electrode 210c that are respectively electrically connected to a first pixel circuit PC1, a second pixel circuit PC2, and a third pixel circuit PC3 may be formed on a pixel circuit layer PCL.

[0125] In one embodiment, the lower electrodes 210a, 210b, and 210c may be formed of a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In another embodiment, each of the lower electrodes 210a, 210b, and 210c may include a reflective film that includes silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In another embodiment, each of the lower electrodes 210a, 210b, and 210c may further include a film formed of ITO, IZO, ZnO, or In2O3 on and / or under the reflective film.

[0126] Next, according to an embodiment, a pixel defining layer 130 may be respectively formed on the first lower electrode 210a, the second lower electrode 210b, and the third lower electrode 210c. The pixel defining layer 130 includes: a first pixel opening OP1 through which a part of the first lower electrode 210a is exposed; a second pixel opening OP2 through which a part of the second lower electrode 210b is exposed; and a third pixel opening OP3 through which a part of the third lower electrode 210c is exposed. The pixel defining layer 130 may be formed of an organic material such as polyimide, polyacrylic acid, or hexamethyldisiloxane (HMDSO).

[0127] In one embodiment and with reference to Figure 4B , a first intermediate layer 220a, a second intermediate layer 220b, and a third intermediate layer 220c may be respectively formed on the first lower electrode 210a, the second lower electrode 210b, and the third lower electrode 210c, and an upper electrode 230 may be formed on the first intermediate layer 220a, the second intermediate layer 220b, and the third intermediate layer 220c to respectively form a first light-emitting element LED1, a second light-emitting element LED2, and a third light-emitting element LED3.

[0128] In one embodiment, each of the intermediate layers 220a, 220b, and 220c may be formed to include an emission layer and a common layer located below and / or above the emission layer. In one embodiment, the emission layers of the first intermediate layer 220a, the second intermediate layer 220b, and the third intermediate layer 220c may be formed in the first pixel opening OP1, the second pixel opening OP2, and the third pixel opening OP3 of the pixel defining layer 130, respectively. For example, the emission layers of the intermediate layers 220a, 220b, and 220c may be organic emission layers formed of an organic material including a fluorescent or phosphorescent material that emits different lights. In one embodiment, the common layers of the first intermediate layer 220a, the second intermediate layer 220b, and the third intermediate layer 220c may be completely formed on the display area DA of the substrate 100 (see Figure 1 ) to cover the first lower electrode 210a, the second lower electrode 210b, and the third lower electrode 210c, respectively.

[0129] In one embodiment, the upper electrode 230 may be formed to completely cover the display area DA of the substrate 100 (see Figure 1 ). The upper electrode 230 may be a transmissive electrode or a reflective electrode. The upper electrode 230 may be formed of a conductive material having a low work function. For example, in one embodiment, the upper electrode 230 may include a transparent layer or a translucent layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. In another embodiment, the upper electrode 230 may further include a layer formed of ITO, IZO, ZnO, or In2O3 on the transparent layer or the translucent layer containing the above materials.

[0130] In one embodiment and with reference to Figure 4C , the first inorganic encapsulation layer 310 may be formed on the light-emitting elements LED1, LED2, and LED3. The first inorganic encapsulation layer 310 may be formed on the upper electrode 230. The first inorganic encapsulation layer 310 may be formed to completely cover the display area DA of the substrate 100 (see Figure 1 ). For example, the first inorganic encapsulation layer 310 may overlap with the pixel openings OP1, OP2, and OP3, and may overlap with the pixel defining layer 130.

[0131] In one embodiment, the first inorganic encapsulation layer 310 may be formed as a high-density layer having a higher film density than that of the second inorganic encapsulation layer 320. For example, in one embodiment, the film density of the first inorganic encapsulation layer 310 may be in the range of about 2.6 g / cm 3 to about 3.5 g / cm 3 .

[0132] In one embodiment, the first inorganic encapsulation layer 310 may be formed by using a deposition process. For example, in one embodiment, the first inorganic encapsulation layer 310 may be deposited at a deposition rate of less than about . For example, the first inorganic encapsulation layer 310 may be formed by using atomic layer deposition (ALD) or chemical vapor deposition (CVD). For example, in one embodiment, the first inorganic encapsulation layer 310 may be formed by using plasma-enhanced ALD (PEALD) or plasma-enhanced CVD (PECVD). For example, in one embodiment, the thickness of the first inorganic encapsulation layer 310 may be in the range of about to about .

[0133] In one embodiment, the first inorganic encapsulation layer 310 may comprise an inorganic material. For example, the first inorganic encapsulation layer 310 may comprise an inorganic material such as silicon nitride (SiN x ), silicon oxide (SiO x ), or silicon oxynitride (SiO x N y ).

[0134] In one embodiment, the first inorganic encapsulation layer 310 may be formed by using a compound containing silicon and nitrogen elements as a precursor. For example, the first inorganic encapsulation layer 310 may be formed by using a silazane compound as a precursor. In this case, the first inorganic encapsulation layer 310 may be formed to comprise an inorganic material that at least includes silicon (Si) and nitrogen (N) elements. For example, in one embodiment, the first inorganic encapsulation layer 310 may comprise silicon nitride (SiN x ) or silicon oxynitride (SiO x N y ). For example, in one embodiment, the ratio of nitrogen element to silicon element in the first inorganic encapsulation layer 310 may be less than about 0.75. For example, the refractive index of the first inorganic encapsulation layer 310 may be about 1.85 or greater.

[0135] In one embodiment and with reference to Figure 4D , the second inorganic encapsulation layer 320 may be formed on the first inorganic encapsulation layer 310, where the second inorganic encapsulation layer 320 may be a low-density layer. For example, the second inorganic encapsulation layer 320 may be formed as a low-density layer having a film density lower than that of the first inorganic encapsulation layer 310. For example, in one embodiment, the film density of the second inorganic encapsulation layer 320 may be in the range of about 1.6 g / cm 3 to about 2.3 g / cm 3 .

[0136] In one embodiment, the second inorganic encapsulation layer 320 may be formed by using a mask 1000 including an opening portion TP and a blocking portion BP. The mask 1000 may be a mask for deposition. Specifically, the opening portion TP of the mask 1000 may be positioned to overlap each of the light-emitting elements LED1, LED2, and LED3 or the pixel openings OP1, OP2, and OP3, and the blocking portion BP of the mask 1000 may be positioned to overlap the pixel defining layer 130. Accordingly, the second inorganic encapsulation layer 320 may be deposited through the opening portion TP of the mask 1000 in each of the pixel openings OP1, OP2, and OP3.

[0137] In one embodiment, the second inorganic encapsulation layer 320 may include a plurality of inorganic encapsulation patterns spaced apart from each other. For example, a first inorganic encapsulation pattern 320a may be formed in the first pixel opening OP1, a second inorganic encapsulation pattern 320b may be formed in the second pixel opening OP2, and a third inorganic encapsulation pattern 320c may be formed in the third pixel opening OP3. The inorganic encapsulation patterns 320a, 320b, and 320c may be spaced apart from each other.

[0138] Since the second inorganic encapsulation layer 320 is formed as a low-density layer ranging from about 1.6 g / cm 3 to about 2.3 g / cm 3 the second inorganic encapsulation layer 320 may be formed to fill each of the pixel openings OP1, OP2, and OP3. That is, the first inorganic encapsulation pattern 320a, the second inorganic encapsulation pattern 320b, and the third inorganic encapsulation pattern 320c may be formed to fill the first pixel opening OP1, the second pixel opening OP2, and the third pixel opening OP3, respectively. In addition, the water vapor transmission rate (WVTR) of the second inorganic encapsulation layer 320 may be equal to or greater than about 2*10 -4 g / m 2 per day and less than about 4*10 -4 g / m 2 per day.

[0139] In one embodiment, the top surface of the second inorganic encapsulation layer 320 may be located at substantially the same level as the top surface of the portion of the first inorganic encapsulation layer 310 that overlaps the pixel defining layer 130. Accordingly, the top surfaces of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 320 may substantially form a flat top surface.

[0140] In one embodiment, the second inorganic encapsulation layer 320 may be formed by using a deposition process. The second inorganic encapsulation layer 320 may be deposited at a deposition rate higher than that of the first inorganic encapsulation layer 310. For example, in one embodiment, the second inorganic encapsulation layer 320 may be about Deposited at a deposition rate of or greater. For example, in one embodiment, the second inorganic encapsulation layer 320 may be formed by using ALD or CVD. For example, the second inorganic encapsulation layer 320 may be formed by using PEALD or PECVD. The thickness of the second inorganic encapsulation layer 320 may be greater than the thickness of the first inorganic encapsulation layer 310. For example, in one embodiment, the thickness of the second inorganic encapsulation layer 320 may be greater than about

[0141]

[0142] In one embodiment, the second inorganic encapsulation layer 320 may comprise an inorganic material. For example, the second inorganic encapsulation layer 320 may comprise an inorganic material such as silicon nitride (SiN x ), silicon oxide (SiO x ), or silicon oxynitride (SiO x N y ).

[0143] In one embodiment, the second inorganic encapsulation layer 320 may be formed by using a compound including a silicon element and a nitrogen element as a precursor. For example, the second inorganic encapsulation layer 320 may be formed by using a silazane compound as a precursor. In this case, the second inorganic encapsulation layer 320 may be formed to comprise an inorganic material that includes at least a silicon (Si) element and a nitrogen (N) element. For example, in one embodiment, the second inorganic encapsulation layer 320 may comprise silicon nitride (SiN x ), or silicon oxynitride (SiO x N y ). The ratio of nitrogen element to silicon element (N / Si ratio) of the second inorganic encapsulation layer 320 may be greater than the ratio of nitrogen element to silicon element (N / Si ratio) of the first inorganic encapsulation layer 310. For example, in one embodiment, the ratio of nitrogen element to silicon element of the second inorganic encapsulation layer 320 may be greater than about 0.77. The refractive index of the second inorganic encapsulation layer 320 may be less than the refractive index of the first inorganic encapsulation layer 310. For example, in one embodiment, the refractive index of the second inorganic encapsulation layer 320 may be in the range of about 1.75 to about 1.90.

[0144] In one embodiment and referring to Figure 4E , the third inorganic encapsulation layer 330 may be formed on the second inorganic encapsulation layer 320. The third inorganic encapsulation layer 330 may be formed to completely cover the display area DA of the substrate 100 (see Figure 1 ). For example, the third inorganic encapsulation layer 330 may overlap with the pixel openings OP1, OP2, and OP3 and may overlap with the pixel defining layer 130.

[0145] In one embodiment, the third inorganic encapsulation layer 330 may be spaced apart from the first inorganic encapsulation layer 310 in the regions overlapping with the pixel openings OP1, OP2, and OP3, and may be directly on the first inorganic encapsulation layer 310 in the regions overlapping with the pixel defining layer 130. In other words, in the regions overlapping with the pixel defining layer 130, the third inorganic encapsulation layer 330 may be in contact with the first inorganic encapsulation layer 310.

[0146] In one embodiment, the third inorganic encapsulation layer 330 may be formed as a high-density layer having a higher film density than the film density of the second inorganic encapsulation layer 320. For example, in one embodiment, the film density of the third inorganic encapsulation layer 330 may be in the range of about 2.6 g / cm 3 to about 3.5 g / cm 3 .

[0147] In one embodiment, the third inorganic encapsulation layer 330 may be formed by using a deposition process, in which the third inorganic encapsulation layer 330 may be deposited at a deposition rate lower than that of the second inorganic encapsulation layer 320. For example, in one embodiment, the third inorganic encapsulation layer 330 may be deposited at a deposition rate of less than about . For example, in one embodiment, the third inorganic encapsulation layer 330 may be formed by using ALD or CVD. For example, the third inorganic encapsulation layer 330 may be formed by using PEALD or PECVD. For example, in one embodiment, the thickness of the third inorganic encapsulation layer 330 may be in the range of about to about , but is not limited thereto. According to one embodiment, the third inorganic encapsulation layer 330 may have a thickness of more than about .

[0148] According to one embodiment, in the regions overlapping with the first pixel opening OP1, the second pixel opening OP2, and the third pixel opening OP3, the encapsulation layer 300 may include the first inorganic encapsulation layer 310, the second inorganic encapsulation layer 320, and the third inorganic encapsulation layer 330, and in the regions overlapping with the pixel defining layer 130, the encapsulation layer 300 may include the first inorganic encapsulation layer 310 and the third inorganic encapsulation layer 330, but may not include the second inorganic encapsulation layer 320. Since the second inorganic encapsulation layer 320 is positioned to overlap only with the pixel openings OP1, OP2, and OP3, the thickness Tb of the encapsulation layer 300 located on the pixel defining layer 130 (see Figure 3 ) may be as small as about 1 μm or less. In one embodiment, in the regions overlapping with the pixel defining layer 130, the thickness Tb of the encapsulation layer 300 may be in the range of about 0.002 μm to about 0.02 μm.

[0149] Since the display device according to the embodiment includes a first inorganic encapsulation layer, a second inorganic encapsulation layer located on the first inorganic encapsulation layer and in a pixel opening of the pixel defining layer, and a third inorganic encapsulation layer located on the second inorganic encapsulation layer, a thin display device can be provided.

[0150] It should be understood that the embodiments described herein should be considered only in a descriptive sense and not for purposes of limitation. The description of features or aspects in each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the figures, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the invention. In addition, embodiments or portions of embodiments may be combined in whole or in part without departing from the scope of the invention.

Claims

1. A display device, comprising: a substrate; a lower electrode located on the substrate; a pixel defining layer located on the lower electrode and including a pixel opening, a part of the lower electrode being exposed through the pixel opening; an intermediate layer located on the lower electrode and including an emission layer; an upper electrode located on the intermediate layer; a first inorganic encapsulation layer located on the upper electrode; a second inorganic encapsulation layer located on the first inorganic encapsulation layer and within the pixel opening; and a third inorganic encapsulation layer located on the second inorganic encapsulation layer, wherein the third inorganic encapsulation layer is spaced apart from the first inorganic encapsulation layer in a region overlapping the pixel opening, and is directly located on the first inorganic encapsulation layer in a region overlapping the pixel defining layer.

2. The display device according to claim 1, wherein the film density of the second inorganic encapsulation layer is lower than that of the first inorganic encapsulation layer.

3. The display device according to claim 1, wherein the film density of the second inorganic encapsulation layer is lower than that of the third inorganic encapsulation layer.

4. The display device according to claim 1, wherein the second inorganic encapsulation layer does not overlap with the pixel defining layer.

5. The display device according to claim 1, wherein the second inorganic encapsulation layer fills the pixel opening.

6. The display device according to claim 1, wherein each of the first inorganic encapsulation layer and the third inorganic encapsulation layer overlaps with the pixel opening and the pixel defining layer.

7. The display device according to claim 1, wherein the film density of the first inorganic encapsulation layer is in the range of 2.6 g / cm 3 to 3.5 g / cm 3 .

8. The display device according to claim 1, wherein the film density of the second inorganic encapsulation layer is in the range of 1.6 g / cm 3 to 2.3 g / cm 3 .

9. The display device according to claim 1, wherein the film density of the third inorganic encapsulation layer is in the range of 2.6 g / cm 3 to 3.5 g / cm 3 .

10. The display device according to claim 1, wherein each of the first inorganic encapsulation layer and the second inorganic encapsulation layer contains silicon element and nitrogen element, and wherein the ratio of the nitrogen element to the silicon element in the first inorganic encapsulation layer is less than the ratio of the nitrogen element to the silicon element in the second inorganic encapsulation layer.

11. The display device according to claim 1, wherein the refractive index of the first inorganic encapsulation layer is greater than that of the second inorganic encapsulation layer.

12. A display device, comprising: a substrate; a first light-emitting element, a second light-emitting element, and a third light-emitting element, wherein each of the first light-emitting element, the second light-emitting element, and the third light-emitting element is located on the substrate and is configured to emit light of different colors; and an encapsulation layer located on the first light-emitting element, the second light-emitting element, and the third light-emitting element to encapsulate the first light-emitting element, the second light-emitting element, and the third light-emitting element, wherein the encapsulation layer includes: a first inorganic encapsulation layer located on the first light-emitting element, the second light-emitting element, and the third light-emitting element; a second inorganic encapsulation layer located on the first inorganic encapsulation layer, having a lower film density than that of the first inorganic encapsulation layer, and including a first inorganic encapsulation pattern overlapping the first light-emitting element, a second inorganic encapsulation pattern overlapping the second light-emitting element, and a third inorganic encapsulation pattern overlapping the third light-emitting element; and a third inorganic encapsulation layer located on the second inorganic encapsulation layer, Wherein the first inorganic encapsulation pattern, the second inorganic encapsulation pattern, and the third inorganic encapsulation pattern are spaced apart from each other.

13. The display device according to claim 12, wherein each of the first light-emitting element, the second light-emitting element, and the third light-emitting element includes a lower electrode, an emission layer disposed on the lower electrode, and an upper electrode disposed on the emission layer. Wherein the display device further includes a pixel defining layer, the pixel defining layer being located on the lower electrode and including: A first pixel opening, a part of the lower electrode of the first light-emitting element being exposed through the first pixel opening; A second pixel opening, a part of the lower electrode of the second light-emitting element being exposed through the second pixel opening; And a third pixel opening, a part of the lower electrode of the third light-emitting element being exposed through the third pixel opening. Wherein the first inorganic encapsulation pattern is located in the first pixel opening. The second inorganic encapsulation pattern is located in the second pixel opening, and The third inorganic encapsulation pattern is located in the third pixel opening.

14. The display device according to claim 13, wherein each of the first inorganic encapsulation pattern, the second inorganic encapsulation pattern, and the third inorganic encapsulation pattern does not overlap with the pixel defining layer.

15. The display device according to claim 13, wherein the third inorganic encapsulation layer is spaced apart from the first inorganic encapsulation layer in a region overlapping with the first pixel opening, the second pixel opening, and the third pixel opening, and is directly located on the first inorganic encapsulation layer in a region overlapping with the pixel defining layer.

16. The display device according to claim 13, wherein each of the first inorganic encapsulation layer and the third inorganic encapsulation layer overlaps with the first pixel opening, the second pixel opening, the third pixel opening, and the pixel defining layer.

17. The display device according to claim 12, wherein the film density of the third inorganic encapsulation layer is greater than the film density of the second inorganic encapsulation layer.

18. A method of manufacturing a display device, the method comprising: Forming a pixel defining layer having a pixel opening on a lower electrode, a part of the lower electrode being exposed through the pixel opening; Forming an emission layer on the lower electrode; Forming an upper electrode on the emission layer; Forming a first inorganic encapsulation layer on the upper electrode; Forming a second inorganic encapsulation layer on the first inorganic encapsulation layer by using a mask having an opening portion in a region overlapping with the pixel opening to fill the pixel opening; And Forming a third inorganic encapsulation layer on the second inorganic encapsulation layer. Wherein the film density of the second inorganic encapsulation layer is lower than the film density of the first inorganic encapsulation layer.

19. The method according to claim 18, wherein the third inorganic encapsulation layer is spaced apart from the first inorganic encapsulation layer in the region overlapping with the pixel opening, and is directly located on the first inorganic encapsulation layer in a region overlapping with the pixel defining layer.

20. The method according to claim 18, wherein the deposition rate of the second inorganic encapsulation layer is greater than the deposition rate of the first inorganic encapsulation layer.

21. The method according to claim 18, wherein the deposition rate of the third inorganic encapsulation layer is less than the deposition rate of the second inorganic encapsulation layer.

22. The method according to claim 18, wherein the film density of the second inorganic encapsulation layer is lower than the film density of the third inorganic encapsulation layer.

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