Descriptor-based access method for flash memory unit, flash memory controller and system

Abstract

The present invention discloses a method for accessing flash memory cells based on descriptors, a flash memory controller, and a system, and relates to the field of flash memory technology. The method comprises the following steps: obtaining a descriptor chain through a descriptor queue; sequentially reading descriptors through a task scheduler to determine whether there are uncompleted access tasks for other descriptors in a suspended waiting area; if not, determining through the task scheduler whether the channel scheduling switch of the current descriptor is in the first state; if so, pausing the suspended waiting area to periodically query the execution unit for the task completion status of other descriptors in the suspended waiting area; scheduling the current descriptor to a task parser through the task scheduler, causing the task parser to parse the current descriptor and form a control instruction; and executing the access operation on the flash memory particles through the execution unit according to the control instruction. The method according to the present invention can simultaneously meet the requirements of sequential read and write and random read and write scenarios, thereby improving the working efficiency of the flash memory controller.

Description

Technical Field

[0001] The present invention relates to the field of flash memory technology, and in particular to a descriptor-based access method for a flash memory unit, a flash memory controller and system, and a storage medium. Background Art

[0002] Large-capacity storage devices such as eMMC, UFS, and SSDs typically utilize multiple stacked flash memory units. Therefore, read and write operations inevitably access NAND flash memory from different CEs / LUNs. In random read and write scenarios, multiple commands from the same CE / LUN are typically random and interleaved, allowing for out-of-order completion. However, in sequential read and write scenarios, if tasks from different CEs / LUNs exist in the descriptor queue, scheduling occurs. Under this mechanism, consecutive commands from the same CE / LUN are disrupted.

[0003] To meet the requirements of sequential read / write scenarios, ensuring that multiple consecutive instructions from the same CE / LUN are executed sequentially without being interrupted by other CE / LUNs, the existing technology requires that the descriptor queue of each flash memory access channel only allow one or more descriptors from a single CE / LUN at a time, and does not allow descriptors from different CE / LUNs to coexist. Specifically, each CE / LUN access request (one or more descriptors) is independently organized into a descriptor chain. Before the first address of a CE / LUN's descriptor chain is written to the descriptor reader register, the flash memory controller of the corresponding channel must return to an idle state. In other words, if other CE / LUN tasks are currently executing on the current channel, they must wait until all of them are parsed and executed, which reduces the overall efficiency of the controller. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes a descriptor-based access method for flash memory cells, a flash memory controller and system, and a storage medium. In sequential read / write scenarios, descriptors for different CEs / LUNs can be stored in the descriptor queue, meeting the requirements of both sequential and random read / write scenarios, thereby improving the operating efficiency of the flash memory controller.

[0005] A descriptor-based access method for a flash memory unit according to an embodiment of the present invention is applied to a flash memory controller, the flash memory controller including a descriptor queue, a task scheduler, a task parser, an execution unit, and a suspend wait area. The method includes the following steps:

[0006] Acquire, through the descriptor queue, a plurality of descriptor chains sent by a descriptor reader; the descriptor chain includes a plurality of descriptors, each of the descriptors includes access unit information and a channel scheduling switch; when the descriptor chain is sequentially read and written, the channel scheduling switch is in a first state, and the access unit information of all the descriptors in the descriptor chain is the same; when the descriptor chain is randomly read and written, the channel scheduling switch is in a second state;

[0007] Reading the descriptors in the descriptor queue in sequence by the task scheduler, and determining whether there are unfinished access tasks of other descriptors having the same access unit information as the current descriptor in the suspended waiting area;

[0008] If not, determining, by the task scheduler, whether the channel scheduling switch of the current descriptor is in the first state;

[0009] If yes, sending a signal to the suspend waiting area through the task scheduler to make the suspend waiting area suspend periodically querying the execution unit for the task completion status of other descriptors in the suspend waiting area;

[0010] Dispatching the current descriptor to the task parser through the task scheduler, so that the task parser parses the current descriptor to form a control instruction;

[0011] The execution unit performs an access operation on the flash memory particles according to the control instruction.

[0012] According to some embodiments of the present invention, each of the descriptors further includes a channel scheduling flag, and before obtaining the descriptor chain sent by the descriptor reader through the descriptor queue, the method further includes:

[0013] Creating descriptors by the CPU, connecting multiple descriptors in series to form a descriptor chain, and configuring the channel scheduling flag of the last descriptor in the descriptor chain to be the first flag, and configuring the channel scheduling flags of the remaining descriptors to be the second flag;

[0014] Determining whether the descriptor of the descriptor chain is sequentially read and written or randomly read and written;

[0015] When the descriptors of the descriptor chain are read and written sequentially, configuring the channel scheduling switches of all the descriptors of the descriptor chain to a first state by the CPU;

[0016] When the descriptors of the descriptor chain are randomly read and written, the channel scheduling switches of all the descriptors in the descriptor chain are configured to a second state through the CPU.

[0017] According to some embodiments of the present invention, the descriptor reader includes an entry register, an acquisition module, and a status register group; and acquiring the descriptor chain sent by the descriptor reader through the descriptor queue includes:

[0018] Writing the first address of the descriptor chain into the entry register through the CPU, configuring an identification number for the descriptor chain through the entry register, and identifying each descriptor in the descriptor chain with the identification number;

[0019] Reading the plurality of descriptors in the descriptor chain from the system cache according to the first address by the acquisition module, and sending the descriptors to the descriptor queue;

[0020] The completion status of each descriptor chain and each descriptor in each descriptor chain is recorded through the status register group.

[0021] According to some embodiments of the present invention, the descriptor includes an OPCODE pointer, access unit information, flash memory particle address information, system cache address, hardware control information and address information of the next descriptor, and the hardware control information includes a channel scheduling switch and a channel scheduling tag.

[0022] According to some embodiments of the present invention, after sequentially reading the descriptors in the descriptor queue by the task scheduler and determining whether there are other descriptors in the suspended waiting area that have uncompleted access tasks and have the same access unit information as the current descriptor, the method further includes:

[0023] If there are unfinished access tasks for other descriptors with the same access unit information as the current descriptor in the suspended waiting area, the task scheduler reads the next descriptor in the descriptor queue as the current descriptor, and repeats this step until there are no unfinished access tasks for other descriptors with the same access unit information as the current descriptor in the suspended waiting area.

[0024] According to some embodiments of the present invention, after determining, by the task scheduler, whether the channel scheduling switch of the current descriptor is in the first state, the method further includes:

[0025] When the channel scheduling switch of the current descriptor is in the second state, sending a second signal to the suspend waiting area through the task scheduler, so as to enable the suspend waiting area to periodically query the execution unit for the task completion status of other descriptors in the suspend waiting area;

[0026] Dispatching the current descriptor to the task parser through the task scheduler, so that the task parser parses the current descriptor to form a control instruction;

[0027] Executing an access operation on the flash memory particles according to the control instruction by the execution unit;

[0028] When the execution time exceeds a preset time, the current descriptor is stored in the suspended waiting area, the task parser suspends parsing of subsequent tasks of the current descriptor, and returns to the step of sequentially reading the descriptors in the descriptor queue through the task scheduler to determine whether there are unfinished access tasks of other descriptors having the same access unit information as the current descriptor in the suspended waiting area;

[0029] When the descriptor in the suspension waiting area meets the suspension exit condition, the suspension waiting area notifies the task scheduler. When the task scheduler is idle, the descriptor in the suspension waiting area is rescheduled for subsequent parsing and execution until the task of the descriptor is completed.

[0030] According to some embodiments of the present invention, the task scheduler dispatches the current descriptor to the task parser, so that the task parser parses the current descriptor to form a control instruction, including:

[0031] The task scheduler searches the OPCODE table for the corresponding task sequence according to the OPCODE pointer of the current descriptor, and sends the task sequence and the current descriptor to the task parser;

[0032] The task parser parses the current descriptor to determine whether the task sequence is a DMA start type, a suspend wait type, an FCU instruction type, or an end type;

[0033] If the type of the task sequence is a DMA start type, the task parser parses the current descriptor and generates an RDMA or WDMA start instruction;

[0034] Alternatively, if the type of the task sequence is a suspended waiting type, the task parser stores the current descriptor in the suspended waiting area and suspends subsequent parsing actions of the current descriptor;

[0035] Alternatively, if the type of the task sequence is an FCU instruction type, the task parser reads parameters and a command set in a command table according to the task, and generates an instruction for accessing the flash memory particles according to the parameters and the command set;

[0036] Alternatively, if the task type is an end type, the task parser generates an instruction for updating the descriptor state to a specified location in the system cache and ends the parsing task of the entire descriptor.

[0037] On the other hand, a flash memory controller according to an embodiment of the present invention includes: a descriptor queue, a task scheduler, a task parser, an execution unit and a suspension waiting area, and the flash memory controller is used to execute the above-mentioned descriptor-based access method to the flash memory unit.

[0038] On the other hand, a flash memory control system according to an embodiment of the present invention includes: a flash memory controller, a descriptor reader, a CPU, a bus and a system cache, wherein the bus is connected to the flash memory controller, the descriptor reader, the CPU and the system cache respectively, the descriptor reader is connected to the flash memory controller, and the flash memory control system is used to execute the descriptor-based access method for flash memory units as described above.

[0039] On the other hand, a computer storage medium according to an embodiment of the present invention stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the above-mentioned method for accessing a flash memory unit based on a descriptor.

[0040] According to embodiments of the present invention, the descriptor-based access method for flash memory cells, the flash memory controller, the system, and the storage medium have at least the following beneficial effects: by configuring a channel scheduling switch for the descriptor, the flash memory controller can determine whether the descriptor chain belongs to sequential read / write or random read / write through the channel scheduling switch, and adopt different access methods according to the requirements of the sequential read / write and random read / write scenarios, so that the method can achieve a method for seamless switching between parallel and serial operations. By adding channel scheduling control technology, when multiple descriptor chains exist in the descriptor queue at the same time, and the multiple descriptor chains have both sequential read / write and random read / write, the flash memory controller supports parallel operation and out-of-order completion of all CE / LUN descriptors; supports serial operation and sequential completion of all CE / LUN descriptors; and supports parallel operation and out-of-order completion of some CE / LUN descriptors and serial operation and sequential completion of other CE / LUN descriptors. In this way, regardless of the operation type and operation combination, the flash memory controller can handle it, and the various modules of the flash memory controller can work in a pipeline, improving the operating efficiency of the flash memory controller.

[0041] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments with reference to the accompanying drawings, in which:

[0043] Figure 1 A schematic structural diagram of a flash memory control system according to an embodiment of the present invention;

[0044] Figure 2 Schematic diagram of the structure of a descriptor according to an embodiment of the present invention;

[0045] Figure 3 Schematic diagram of the structure of a descriptor chain according to an embodiment of the present invention;

[0046] Figure 4 Schematic diagram of the structure of a descriptor reader and a flash memory controller according to an embodiment of the present invention;

[0047] Figure 5 Flowchart of the steps of a method for accessing a flash memory unit based on a descriptor according to an embodiment of the present invention;

[0048] Figure 6 3 is a schematic diagram of a specific process of a method for accessing a flash memory unit based on a descriptor according to an embodiment of the present invention. DETAILED DESCRIPTION

[0049] This section will describe in detail the specific embodiments of the present invention. The preferred embodiments of the present invention are shown in the accompanying drawings. The purpose of the accompanying drawings is to supplement the description of the text part of the specification with graphics, so that people can intuitively and vividly understand each technical feature and the overall technical solution of the present invention, but it should not be understood as a limitation on the scope of protection of the present invention.

[0050] In the description of the present invention, "several" means one or more, "many" means more than two, "greater than," "less than," and "exceed" are understood to exclude the number itself, while "above," "below," and "within" are understood to include the number itself. The use of "first" and "second" in the description is solely for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance, implicitly specifying the number of the indicated technical features, or implicitly specifying the order of the indicated technical features.

[0051] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, and connecting should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0052] eMMC (Embedded Multi Media Card) is a standard specification for embedded memory established by the MMC Association, primarily for products like mobile phones and tablets. eMMC is an embedded, non-volatile storage system primarily composed of flash memory, descriptor-based access methods for flash memory cells, and the eMMC protocol interface. It defines the physical architecture, access interface, and protocol for eMMC-based storage systems. With its compact size, low power consumption, and large capacity, eMMC is ideally suited as a storage medium for electronic devices such as smartphones, tablets, and mobile internet devices.

[0053] UFS (Universal Flash Storage) is a flash memory storage specification designed for use in consumer electronics such as digital cameras and smartphones. Its design goal is to develop a unified flash memory card format that provides high data transfer speeds and stability while reducing consumer confusion among the various memory card formats on the market and the need for different memory card adapters.

[0054] SSD: Solid State Disk, also known as solid-state drive, is a hard disk made of an array of solid-state electronic storage chips.

[0055] Nand Flash: Flash refers to a type of non-volatile memory that can be quickly erased and programmed electrically. Based on chip technology, Flash can be divided into two categories: Nor Flash and Nand Flash. Nand Flash memory, a type of Flash memory, uses a nonlinear macrocell model internally, providing a cost-effective solution for implementing large-capacity solid-state memory. Nand Flash memory offers advantages such as large capacity and fast rewrite speed, making it suitable for storing large amounts of data. Consequently, it is gaining increasing application in the industry, such as in embedded products like digital cameras, MP3 players, memory cards, and compact USB flash drives.

[0056] OPCODE: Operation Code, an operation code is used to describe the part of the machine code that specifies the operation to be performed in the machine language instruction. The instruction format and specifications that constitute the OPCODE are specified by the processor.

[0057] CE / LUN information: CE / LUN information refers to the CE and LUN information of the flash memory particles to be accessed, which must be specified in the descriptor. Each Nand Flash can have multiple CEs (independent chip select units), and each CE can have multiple LUNs (Logical Unit Number). LUN is the smallest independent unit in the flash memory that can execute commands and report its own status.

[0058] SRAM: Static Random-Access Memory, is a type of random access memory that retains data permanently as long as the power is on.

[0059] DDR: Double Data Rate, double data rate synchronous dynamic random access memory.

[0060] An embodiment of the present application proposes a method for accessing a flash memory unit based on a descriptor, which obtains several descriptor chains sent by a descriptor reader through a descriptor queue; reads the descriptors in sequence according to the descriptor order of the descriptor queue through a task scheduler to determine whether there are unfinished access tasks for other descriptors with the same access unit information as the current descriptor in the suspended waiting area; if not, determines through the task scheduler whether the channel scheduling switch of the current descriptor is in the first state; if so, sends a signal to the suspended waiting area through the task scheduler to pause the suspended waiting area and periodically query the execution unit for the task completion status of other descriptors in the suspended waiting area; schedules the current descriptor to the task parser through the task scheduler, so that the task parser parses the current descriptor to form a control instruction; executes the access operation on the flash memory particle according to the control instruction; obtains the next descriptor with the same identification number as the current descriptor in the descriptor queue as the current descriptor, and returns the step of scheduling the current descriptor to the task parser through the task scheduler, so that the task parser parses the current descriptor to form a control instruction, until the access tasks of all descriptors in the descriptor chain are completed. This method configures a channel scheduling switch for descriptors, allowing the flash memory controller to determine whether a descriptor chain is sequential or random. Based on the requirements of the sequential and random read / write scenarios, the flash memory controller uses different access methods, enabling seamless switching between parallel and serial operations. By adding channel scheduling control technology, when multiple descriptor chains exist simultaneously in the descriptor queue, and these chains perform both sequential and random read / write operations, the flash memory controller supports parallel operation and out-of-order completion of all CE / LUN descriptors; serial operation and sequential completion of all CE / LUN descriptors; and parallel operation and out-of-order completion of some CE / LUN descriptors while serial operation and sequential completion of other CE / LUN descriptors. This allows the flash memory controller to handle all operation types and combinations, enabling pipelined operation of its modules and improving its efficiency.

[0061] Refer to the following Figures 1 to 6 , describes in detail the descriptor-based access method for flash memory units, flash memory controller and system, and storage medium of an embodiment of the present invention.

[0062] like Figure 1 As shown, an embodiment of the present application proposes a flash memory control system, which includes: a flash memory controller 100, a descriptor reader 200, a CPU 300, a bus 400 and a system cache 500, wherein the bus 400 is connected to the flash memory controller 100, the descriptor reader 200, the CPU 300 and the system cache 500 respectively, and the descriptor reader 200 is connected to the flash memory controller 100.

[0063] It should be noted that the flash memory control system may include multiple flash memory controllers 100, each of which is used to access and control a corresponding flash memory unit (NAND). The CPU 300 is responsible for creating descriptors and concatenating multiple descriptors into a descriptor chain. It should be noted that a descriptor is a data structure constructed by the software layer through the CPU 300 to describe access tasks to the flash memory unit (NAND), such as erasing a block (the smallest erase unit in flash memory, which is composed of multiple blocks) and reading and writing a Nand page (a page is the smallest unit that can be read and written in flash memory, and a block contains multiple pages). Any common access operation can be implemented using a single descriptor or multiple descriptors. The software flexibly creates different descriptors to adapt to various scenarios. After creating the descriptor, the CPU 300 writes the descriptor to the system cache 500 via bus 400 (eMMC and UFS controller chips can use SRAM as the system cache, and SSDs can also use DDR as the system cache). The first address of the descriptor chain consisting of multiple descriptors is written to the descriptor reader 200.

[0064] like Figure 2 As shown, in some embodiments of the present application, a descriptor consists of multiple fields, including an OPCODE pointer, access unit information (hereinafter referred to as CE / LUN information), flash memory address information (i.e., Nand Flash address), system cache address, hardware control information, and the address information of the next descriptor. The hardware control information includes a channel scheduling switch and a channel scheduling flag. The OPCODE pointer is an index number of the OPCODE table described below. The task scheduler of the flash memory controller 100 uses this pointer to search the OPCODE table for the corresponding task sequence, schedule it, and send it to subsequent modules for parsing and execution. CE / LUN information refers to the CE and LUN information of the flash memory element being accessed, which must be specified in the descriptor. Nand Flash address refers to the address (block, page, etc.) of the flash memory element being accessed, which must also be specified in the descriptor. System cache address refers to the system cache address that must be specified in the descriptor. For example, for a Nand Flash read operation, the hardware must read data from a specific page of the flash memory element and move it to the destination address in the system cache. The hardware control information of the descriptor is used to guide the hardware to flexibly execute in accordance with the software requirements to meet the needs of different application scenarios; in this application, the hardware control information includes a channel scheduling switch and a channel scheduling flag, and the functions of the channel scheduling switch and the channel scheduling flag are described below. Figure 3As shown, the descriptor usually appears in the form of a descriptor chain. The descriptor chain includes multiple descriptors, so the descriptor also specifies the location of the next descriptor in the system cache.

[0065] like Figure 4 As shown, in some embodiments of the present application, the descriptor reader 200 includes an entry register (Entry), a fetch module (Fetch), and a status register group (Status). After the CPU 300 creates a descriptor chain, it writes the first address of the descriptor chain into the entry register; the fetch module reads each descriptor in the descriptor chain into the flash memory controller 100 based on the first address. The entry register configures an identification number for the descriptor chain, which serves as the descriptor chain ID. The identification number of subsequent descriptor chains can be increased by 1 based on the identification number of the current descriptor chain, or other rules can be used to configure a corresponding identification number for each descriptor chain. The status register group is used to indicate the completion status of each descriptor in the descriptor chain, as well as the completion status of the entire descriptor chain. By reading the status register group, the CPU 300 can obtain the execution status of each descriptor chain and each descriptor.

[0066] like Figure 4 As shown, in some embodiments of the present application, the flash memory controller 100 is composed of a front-stage module and a back-stage module, wherein the front-stage module is used to schedule and parse descriptors, generate control instructions, and then send the control instructions to the back-stage module for execution. It can be understood that the front-stage module is the control center and the back-stage module is the execution unit. The front-stage module sends control instructions to control and direct the operation of the back-stage module. Specifically, the front-stage module includes a descriptor queue, a task scheduler, a task parser, and a suspension waiting area, etc., and the back-stage module includes an execution unit. Among them, after the descriptor reader 200 reads the descriptor chain from the system cache 500, it is first sent to the descriptor queue for waiting. This queue can store multiple descriptor chains, providing space for the task scheduler to implement multi-CE / LUN parallel access or single CE / LUN serial access. When idle, the task scheduler selects descriptors that meet the scheduling conditions from the descriptor queue, schedules them out, and sends them to the task parser for parsing. The control instructions generated after parsing are sent to the hardware unit (FCU, WDMA, RDMA) corresponding to the execution unit for execution. Among them, FCU refers to Flash Control Unit, flash memory control unit; WDMA refers to Write DMA, write DMA; RDMA refers to Read DMA, read DMA.

[0067] The task scheduler relies on the OPCODE table to complete its work. The OPCODE table stores a large number of different task sequence combinations for use by the software when creating descriptors. The OPCODE pointer in each descriptor points to a specific task sequence in the OPCODE table, which is used to implement different access operations to the flash memory.

[0068] When the task parser parses and generates control instructions to be sent to the execution unit, it usually needs the assistance of the command table to complete the work. The instructions generated by the parsing include access operations on Nand particles through FCU and Nand IO (such as sending commands, addresses, and performing data read and write operations, erasing and status queries, etc.), RDMA and WDMA startup instructions, and instructions for updating descriptor status to the system cache.

[0069] After parsing a descriptor, multiple control commands are generated. Not all control commands can be executed immediately. Some control commands take a long time to execute. For example, a control command requires RDMA to read sufficient data from the system cache to the internal cache of the downstream module. During the execution of this control command, the Nand I / O will be in a busy state. If you wait until this descriptor is parsed and executed before parsing and executing other descriptors, the execution efficiency will be low. In order to improve the utilization and access efficiency of Nand IO, in this application example, a suspension waiting area is also designed in the front-end module, which makes full use of the feature that different CE / LUNs of Nand Flash particles can be accessed in parallel. After the control instructions that need to wait for a long time for execution results are sent to the back-end module, the subsequent task parsing actions of this descriptor are suspended. The task parser notifies the suspension waiting area to record the execution status of the current CE / LUN, the suspension exit waiting conditions, the current position of the task sequence in the OPCODE table, etc., and then releases resources to perform the scheduling and parsing of descriptors under other CE / LUNs, thereby achieving parallel access to different CE / LUNs of Nand Flash particles and improving the utilization efficiency of NandIO. When the back-end module feeds back a signal that meets the suspension exit conditions to the suspension waiting area, the descriptor task suspended under the corresponding CE / LUN can then be scheduled again and sent to the task parser for continued parsing and execution. It should be noted that the method of parallel access to different CEs / LUNs is suitable for random read and write scenarios. In sequential read and write scenarios, multiple consecutive instructions on the same CE / LUN need to be executed sequentially and must not be interrupted by other CEs / LUNs. The above method of parallel access to multiple CEs / LUNs is not suitable for sequential read and write scenarios.

[0070] To this end, the embodiment of the present application provides a descriptor-based access method for flash memory cells that is suitable for both sequential reading and writing and random reading and writing, such as Figure 5As shown, the method includes the following steps:

[0071] Step S100: obtaining a plurality of descriptor chains sent by the descriptor reader 200 through the descriptor queue;

[0072] Step S200: reading descriptors in sequence in the descriptor queue through the task scheduler, and determining whether there are unfinished access tasks for other descriptors having the same access unit information as the current descriptor in the suspended waiting area;

[0073] Step S300: If not, determine through the task scheduler whether the channel scheduling switch of the current descriptor is in the first state;

[0074] Step S400: If yes, a signal is sent to the suspend waiting area through the task scheduler, so that the suspend waiting area pauses and periodically queries the execution unit for the task completion status of other descriptors in the suspend waiting area;

[0075] Step S500: dispatching the current descriptor to the task parser through the task scheduler, so that the task parser parses the current descriptor to form a control instruction;

[0076] Step S600: The execution unit executes an access operation on the flash memory particles according to the control instruction.

[0077] It should be noted that, since the descriptor chain is constructed by the CPU 300 , before step S100 obtains the descriptor chains sent by the descriptor reader 200 through the descriptor queue, it further includes steps S10 to S40 :

[0078] Step S10: creating a descriptor by the CPU, connecting multiple descriptors in series to form a descriptor chain, and configuring the channel scheduling flag of the last descriptor in the descriptor chain to be the first flag, and configuring the channel scheduling flags of the remaining descriptors to be the second flag;

[0079] Step S20: determining whether the descriptors in the descriptor chain are sequential read / write or random read / write;

[0080] Step S30: When the descriptors of the descriptor chain are read and written sequentially, the channel scheduling switches of all the descriptors of the descriptor chain are configured to the first state by the CPU;

[0081] Step S40: When the descriptors of the descriptor chain are randomly read and written, the channel scheduling switches of all the descriptors in the descriptor chain are configured to the second state through the CPU.

[0082] Specifically, after the CPU 300 creates a descriptor, it writes the descriptor into the system cache 500 via the bus 400, and writes the first address of the descriptor chain composed of multiple descriptors into the descriptor reader 200. At the same time, in order to facilitate the subsequent task scheduler of the flash memory controller 100 to determine whether all descriptors in the current descriptor chain have completed the access task, in this application, a channel scheduling tag field is added to the hardware control information of the descriptor, and the channel scheduling tag of the last descriptor in the descriptor chain is configured as the first tag, and the channel scheduling tags of the remaining descriptors are configured as the second tag. For example, the channel scheduling tag of the last descriptor can be set to 0, and the channel scheduling tags of the remaining descriptors can be set to 1. Of course, the first tag and the second tag can also be set to other symbols. When the task scheduler finishes scheduling a descriptor, it reads the value of the channel scheduling tag of the descriptor. If the channel scheduling tag is 1, it means that there are still descriptors in the current descriptor chain that have not completed the access task; if the channel scheduling tag is 0, it means that all descriptors in the current descriptor chain have completed the access task. In addition, in order to subsequently distinguish whether the descriptor belongs to a sequential read and write scenario or a random read and write scenario, in this application, a channel scheduling switch field is added to the hardware control information of the descriptor. The switch state of the channel scheduling switch is used to distinguish between the sequential read and write scenario and the random read and write scenario. If all descriptors in the descriptor chain have the same access unit information (CE / LUN information) and belong to the sequential read and write scenario, the CPU300 will configure the channel scheduling switches of all descriptors in the descriptor chain to the first state (for example, set to the open state); if all descriptors in the descriptor chain have different CE / LUN information and belong to the random read and write scenario, the CPU300 will configure the channel scheduling switches of all descriptors in the descriptor chain to the second state (for example, set to the closed state).

[0083] In some embodiments of the present application, the above step S100 of acquiring, through the descriptor queue, a plurality of descriptor chains sent by the descriptor reader 200 further includes the following three steps:

[0084] Step S110: The CPU 300 writes the first address of the descriptor chain into the entry register, and configures an identification number for the descriptor chain through the entry register;

[0085] Step S120: reading multiple descriptors in the descriptor chain from the system cache 500 according to the first address through the acquisition module, and sending them to the descriptor queue;

[0086] Step S130: Record the completion status of each descriptor chain and each descriptor in each descriptor chain through the status register group.

[0087] After creating a descriptor chain, the CPU 300 writes the chain's starting address into the entry register. The acquisition module then reads each descriptor in the descriptor chain into the descriptor queue of the flash memory controller 100 based on the starting address. The entry register assigns an identification number to the descriptor chain. The status register group indicates the completion status of each descriptor in the descriptor chain, as well as the completion status of the entire descriptor chain. By reading the status register group, the CPU 300 can determine the execution status of each descriptor chain and each descriptor.

[0088] In step S200, after the descriptor queue obtains the descriptors of the descriptor chain, the task scheduler reads each descriptor in sequence according to the descriptor order of the descriptors in the descriptor queue. Each time a descriptor is read, the task scheduler determines whether there are any unfinished access tasks for other descriptors with the same CE / LUN information as the current descriptor in the suspended waiting area of ​​the flash memory controller 100. If so, the task scheduler is temporarily unable to schedule the current descriptor and needs to continue reading the next descriptor in the descriptor queue as the current descriptor. The above determination process is repeated until a descriptor for which no other descriptor with the same CE / LUN information is obtained in the suspended waiting area. If there are no unfinished access tasks for other descriptors with the same access unit information as the current descriptor in the suspended waiting area, step S300 is executed. At this point, the task scheduler determines whether the channel scheduling switch for the current descriptor is in the first state. If so, it indicates that all descriptors in the descriptor chain to which the descriptor belongs are in a sequential read / write scenario. The task scheduler then sends a signal to the pending area, causing it to pause its regular query of the execution unit for the task completion status of other descriptors in the pending area. The task scheduler then begins dispatching the current descriptor to the task parser, which parses the current descriptor and generates control instructions. The execution unit then executes the access operation on the flash memory device based on the control instructions. After the access operation on the current descriptor is completed, since the descriptor chain is in a sequential read / write scenario, the task scheduler schedules the next descriptor with the same identification number as the current descriptor (indicating that it belongs to the same descriptor chain), until the access operation on all descriptors in the descriptor chain is completed in sequence. It should be noted that in a sequential read / write scenario, even if the access time for a particular descriptor is too long, the task for that descriptor is not placed in the pending area. Instead, the task for the next descriptor is dispatched only after the access operation on that descriptor is completed. Therefore, it is necessary to suspend the suspend-wait area and periodically query the execution unit for the task completion status of other descriptors in the suspend-wait area.

[0089] like Figure 6 As shown, in some embodiments of the present application, after the above step S300, the following five steps are further included:

[0090] When the channel scheduling switch of the current descriptor is in the second state, a second signal is sent to the suspend waiting area through the task scheduler, so that the suspend waiting area can query the execution unit regularly about the task completion status of other descriptors in the suspend waiting area;

[0091] The task scheduler dispatches the current descriptor to the task parser, so that the task parser parses the current descriptor to form a control instruction;

[0092] The execution unit executes access operations on the flash memory particles according to the control instructions;

[0093] When the execution time exceeds the preset time, the current descriptor is stored in the suspended waiting area, the task parser suspends the subsequent tasks of parsing the current descriptor, and returns to step S200;

[0094] When the descriptor in the suspended waiting area meets the suspension exit condition, the suspended waiting area notifies the task scheduler. When the task scheduler is idle, the descriptor in the suspended waiting area is rescheduled for subsequent parsing and execution until the descriptor task is completed.

[0095] Specifically, when the channel scheduling switch of the current descriptor is in the second state, it indicates that all descriptors in the descriptor chain where the descriptor is located belong to the random read and write scenario. At this time, the task scheduler will send a signal to the suspended waiting area, enabling the suspended waiting area to periodically query the execution unit about the task completion status of other descriptors in the suspended waiting area, and then start scheduling the current descriptor to the task parser, so that the task parser parses the current descriptor to form a control instruction, and executes the access operation to the flash memory particles according to the control instruction through the execution unit. It should be noted that in random read and write scenarios, the descriptors in the descriptor chain may have different CE / LUN information, and descriptors with different CE / LUN information can be accessed in parallel. Therefore, if the execution time of a certain descriptor is too long, exceeding the preset time, the current descriptor will be stored in the suspended waiting area, causing the task parser to suspend the subsequent task of parsing the current descriptor and return to step S200, so that the task scheduler continues to read the next descriptor according to the descriptor order of the descriptor queue, and determines whether there are unfinished access tasks for other descriptors with the same access unit information as the next descriptor in the suspended waiting area. If not, the scheduling and parsing operations of the next descriptor can be performed. If so, the reading of the next descriptor continues. When the descriptor in the suspended waiting area meets the suspension exit condition, the suspended waiting area notifies the task scheduler. When the task scheduler is idle, the descriptor in the suspended waiting area is rescheduled for subsequent parsing and execution until the descriptor task is completed. In random read and write scenarios, when the execution time of a descriptor is too long, the subsequent tasks of the descriptor will be placed in a suspended waiting area, waiting for the execution unit to complete the current task of the descriptor, and then the subsequent tasks of the descriptor will be scheduled out of the suspended waiting area; therefore, it is necessary to periodically query the execution unit through the suspended waiting area about the task completion status of other descriptors in the suspended waiting area so that the descriptors that meet the suspended exit conditions can be rescheduled.

[0096] According to the method for accessing a flash memory unit based on a descriptor according to an embodiment of the present application, the specific operation process is as follows: Figure 6As shown, by configuring a channel scheduling switch and a channel scheduling flag for the descriptor, it can be determined whether the descriptor chain belongs to sequential read / write or random read / write, and different access methods are adopted according to the requirements of the sequential read / write and random read / write scenarios, so that the method can achieve a method of seamless switching between parallel operation and serial operation. By adding channel scheduling control technology, when there are multiple descriptor chains in the descriptor queue at the same time, and multiple descriptor chains have both sequential read / write and random read / write, the flash memory controller 100 supports all CE / LUN parallel operations and out-of-order completion; all CE / LUN serial operations and sequential completion; and some CE / LUN parallel operations and out-of-order completion, while other CE / LUN serial operations and sequential completion. In this way, regardless of the operation type and operation combination, the flash memory controller 100 can handle it, and the various modules of the flash memory controller 100 can work in a pipeline, improving the working efficiency of the flash memory controller 100.

[0097] The following describes in detail the process of scheduling, parsing and executing the descriptor by the flash memory controller 100 using a specific example. It should be noted that the following is only an exemplary description and does not specifically limit the present invention.

[0098] In the front-end module of the flash controller 100, the descriptors sent from the descriptor reader 200 are received through the descriptor queue. This queue can store multiple descriptors, providing space for the task scheduler to implement parallel access to multiple CEs / LUNs.

[0099]

[0100] Table 1 Descriptor queue example

[0101] See Table 1, which shows an example of a descriptor queue. A descriptor queue used to store descriptors can adopt a circular queue design to implement descriptor push (enqueue) and pop (pop) operations, as well as queue management. For example, queue fullness is determined by the relationship between the physical locations of the cache cells pointed to by the head / tail pointers. When a new descriptor is pushed in, the tail pointer automatically increments by 1, and when a descriptor is popped out, the head pointer automatically increments by 1. It's important to note that if a descriptor at a certain location has completed all scheduling and parsing (i.e., is in the done state), but is not in the cell pointed to by the head pointer, it does not meet the conditions for being popped and must wait until all previous descriptors have been popped out before it can be popped out. For example, in the example in Table 1, the descriptor at physical location 5 is already in the done state, but because the head pointer points to the cell at physical location 3, it does not meet the conditions for being popped.

[0102] Descriptors are generally scheduled by the task scheduler in head-to-tail (first-come-last-served) order, but out-of-order scheduling is possible in some cases (random read / write scenarios). Each LUN under each CE is the smallest storage unit for performing NandFlash access operations. Storage units under the same CE / LUN cannot be accessed out of order and must be executed sequentially. However, descriptors accessing storage units under different CEs / LUNs can be scheduled out of order to achieve parallel access, thereby improving NandFlash I / O utilization. For example, the descriptor pointed to by the head pointer in Table 1 (physical location 3) is in the running state (being scheduled) at this time. During parsing and execution, it is necessary to wait for a long time for the feedback result of the subsequent module. Therefore, the descriptor will be registered in the suspended waiting area of ​​the previous module and the subsequent parsing action will be suspended. At this time, the task scheduler has free time to search the next unit in the descriptor queue (physical location 4) to see if there is a candidate that meets the scheduling conditions (pending state). However, in this case, the access objects of the descriptor at physical location 4 and the descriptor pointed to by the head pointer belong to the same CE / LUN, which does not meet the scheduling conditions. The task scheduler continues to search downward and finds the descriptor at physical location 5 in the done state. Continuing to search downward, the descriptor at physical location 6 is in the pending state, and the CE / LUN of the access object is different from the previous descriptor, so it can be scheduled for parsing.

[0103] As mentioned earlier, each descriptor has an OPCODE pointer. After a candidate descriptor is scheduled out of the descriptor queue of the previous module, the task scheduler will use this pointer to read a string of task sequences from the corresponding position in the OPCODE table to parse and execute.

[0104]

[0105] Table 2. OPCODE table virtual case

[0106] Table 2 is a hypothetical example of an OPCODE table. Each cell or multiple cells can construct a complete task sequence. For example, the positions pointed to by pointers 3 and 4 each contain a task sequence of different lengths. The task sequence at OPCODE pointer 5 occupies two cells.

[0107] Let's take the OPCODE pointer 3 as an example to illustrate how a descriptor is scheduled for execution. The stored task sequence is assumed to be AA->BB->20->CC->FF. In this hypothetical example, AA indicates that RDMA needs to read data from system cache 500 into the internal cache of the downstream module, which requires a relatively long wait. BB indicates that the task sequence of the current descriptor needs to be registered in the pending wait area until the downstream module reports that RDMA has read enough data into the internal cache. During this wait, the task scheduler can schedule other descriptors for execution, thereby increasing parallelism. When the data reading is completed, the task scheduler continues to read out the task represented by 20 and sends it to the task parser for parsing. Assuming that this task represents the need to control the FCU of the subsequent module to access the Nand Flash particle through Nand IO, the task parser generates a control instruction by looking up the content of the position pointed to by 20 in the command table and combining it with the current descriptor content to parse and send it to the FCU. This instruction means that the internal cached data needs to be sent to a certain page of Nand Flash through the command method specified in the command table. CC means registering to the suspended waiting area again until the Nand Flash particle returns the completion signal. Because this waiting time will be very long, the scheduling and parsing of other descriptors will be allowed to be executed again in the middle. FF means that all tasks of the descriptor are completed, and a control instruction is sent to the WDMA of the subsequent module. WDMA needs to write the status of the descriptor to the specified location of the system cache.

[0108]

[0109] Table 3 Example of data structure of suspended waiting area

[0110] Table 3 shows an example of the data structure of the suspend wait area. Each storage unit under a CE / LUN combination records whether it is in a suspended state, the exit condition (wait event) after suspension, whether the exit condition is met, and the position in the OPCODE table where the task was suspended. When the task parser encounters a task sent by the task scheduler indicating a suspended action, it finds the corresponding unit in the suspend wait area based on the CE / LUN value, sets the "state" to "suspended", and records the "exit condition after suspension", such as waiting for the RB signal to be ready, waiting for RDMA to read enough data into the internal cache, or other conditions. The "exit condition met" field is set to "no", and the position of the task sequence in the OPCODE table when it was suspended is recorded, including the OPCODE pointer and the offset within the current unit.

[0111] After a period of waiting, the subsequent module returns a standard signal indicating that the exit condition is met after waiting for suspension. The "Exit Condition Satisfied" of the corresponding unit in the suspension waiting area is set to "YES". The task scheduler will reschedule the suspended descriptor task when it is idle, and continue to execute it according to the position recorded in the suspension waiting area.

[0112]

[0113] Table 4 Command table

[0114] Table 4 is a schematic diagram of the command table, which is used to generate FCU instructions sent to the execution unit. If the task sent by the task scheduler is to parse and generate FCU instructions, the task is a CMD pointer. The data content corresponding to the pointer will be read from the CMD table. The latter is various parameters and CMD SET. The task parser parses according to the following types:

[0115] 1) DMA startup type: reads the system cache address and other contents in the descriptor and parses them to generate RDMA or WDMA startup instructions;

[0116] 2) Suspend wait type: No instruction is generated. The corresponding unit in the suspend wait area is found according to the CE / LUN, the suspend state is registered, and the exit wait condition and the task sequence pause position are recorded.

[0117] 3) FCU instruction type: The task itself is a command table pointer. According to the pointer, the corresponding parameters and command set in the command table are read. At the same time, the descriptor content is read and the FCU instruction is generated according to the register configuration.

[0118] 4) End type: Generates an instruction to update the descriptor status to the specified address of the system cache and ends the task of the entire descriptor.

[0119] On the other hand, based on the above embodiment of the method for accessing a flash memory unit based on a descriptor, the present invention also proposes a flash memory controller, such as Figure 4 As shown, the flash memory controller includes: a descriptor queue, a task scheduler, a task parser, an execution unit and a suspension waiting area. The flash memory controller is used to execute the descriptor-based access method to the flash memory unit as described in the above-mentioned embodiment.

[0120] On the other hand, based on the descriptor-based access method for a flash memory unit in the above-mentioned embodiment, the present invention also proposes a computer storage medium, which stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the descriptor-based access method for a flash memory unit described in the above-mentioned embodiment.

[0121] Although specific embodiments are described herein, those skilled in the art will recognize that many other modifications or alternative embodiments are also within the scope of this disclosure. For example, any of the functions and / or processing capabilities described in conjunction with a particular device or component may be performed by any other device or component. In addition, although various exemplary implementations and architectures have been described in accordance with embodiments of the present disclosure, those skilled in the art will recognize that many other modifications to the exemplary implementations and architectures described herein are also within the scope of this disclosure.

[0122] Some aspects of the present disclosure have been described above with reference to the block diagrams and flow charts of the systems, methods, systems and / or computer program products according to the exemplary embodiments. It should be understood that the combination of one or more blocks in the block diagram and the flow chart and the blocks in the block diagram and the flow chart can be realized by executing computer executable program instructions respectively. Equally, according to some embodiments, some blocks in the block diagram and the flow chart may not need to be executed in the order shown, or may not need to be executed in full. In addition, additional components and / or operations beyond those components and / or operations shown in the blocks in the block diagram and the flow chart may be present in certain embodiments.

[0123] Therefore, the blocks in the block diagrams and flow charts support combinations of means for performing the specified functions, combinations of elements or steps for performing the specified functions, and program instruction means for performing the specified functions. It should also be understood that each block in the block diagrams and flow charts, and combinations of blocks in the block diagrams and flow charts, can be implemented by a dedicated hardware computer system that performs the specific functions, elements, or steps, or a combination of dedicated hardware and computer instructions.

[0124] The program modules, applications, etc. described herein may include one or more software components, including, for example, software objects, methods, data structures, etc. Each such software component may include computer-executable instructions that, in response to execution, cause at least a portion of the functionality described herein (e.g., one or more operations of the illustrative methods described herein) to be performed.

[0125] Software component can be encoded with any one in various programming languages.A kind of exemplary programming language can be low-level programming language, such as the assembly language associated with specific hardware architecture and / or operating system platform.Comprise that the software component of assembly language instruction may need to be converted to executable machine code by assembler before being executed by hardware architecture and / or platform.Another exemplary programming language can be a more advanced programming language, and it can be transplanted across multiple architectures.Comprise that the software component of more advanced programming language may need to be converted to intermediate representation by interpreter or compiler before execution.Other examples of programming language include but are not limited to macro language, shell or command language, job control language, script language, database query or search language or report writing language.In one or more exemplary embodiments, the software component that comprises the instruction of one in the above-mentioned programming language example can be directly executed by operating system or other software component, without first being converted into another form.

[0126] Software components can be stored as files or other data storage structures. Software components of similar types or related functions can be stored together, such as in a specific directory, folder, or library. Software components can be static (e.g., preset or fixed) or dynamic (e.g., created or modified at execution time).

[0127] The embodiments of the present invention are described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Various changes can be made within the knowledge of ordinary technicians in the relevant technical field without departing from the scope of the present invention.

Claims

1. A method for accessing a flash memory unit based on a descriptor, characterized in that: Applied to a flash memory controller, the flash memory controller includes a descriptor queue, a task scheduler, a task parser, an execution unit, and a suspend waiting area, the method includes: Acquire, through the descriptor queue, a plurality of descriptor chains sent by a descriptor reader; the descriptor chain includes a plurality of descriptors, each of the descriptors includes access unit information and a channel scheduling switch; when the descriptor chain is sequentially read and written, the channel scheduling switch is in a first state, and the access unit information of all the descriptors in the descriptor chain is the same; when the descriptor chain is randomly read and written, the channel scheduling switch is in a second state; Reading the descriptors in the descriptor queue in sequence by the task scheduler, and determining whether there are unfinished access tasks of other descriptors having the same access unit information as the current descriptor in the suspended waiting area; If not, determining, by the task scheduler, whether the channel scheduling switch of the current descriptor is in the first state; If yes, sending a signal to the suspend waiting area through the task scheduler to make the suspend waiting area suspend periodically querying the execution unit for the task completion status of other descriptors in the suspend waiting area; Dispatching the current descriptor to the task parser through the task scheduler, so that the task parser parses the current descriptor to form a control instruction; The execution unit performs an access operation on the flash memory particles according to the control instruction.

2. The method for accessing a flash memory unit based on a descriptor according to claim 1, wherein: Each of the descriptors further includes a channel scheduling tag. Before obtaining the descriptor chain sent by the descriptor reader through the descriptor queue, the method further includes: Creating descriptors by the CPU, connecting multiple descriptors in series to form a descriptor chain, and configuring the channel scheduling flag of the last descriptor in the descriptor chain to be the first flag, and configuring the channel scheduling flags of the remaining descriptors to be the second flag; Determining whether the descriptor of the descriptor chain is sequentially read and written or randomly read and written; When the descriptors of the descriptor chain are read and written sequentially, configuring the channel scheduling switches of all the descriptors of the descriptor chain to a first state by the CPU; When the descriptors of the descriptor chain are randomly read and written, the channel scheduling switches of all the descriptors in the descriptor chain are configured to a second state through the CPU.

3. The method for accessing a flash memory unit based on a descriptor according to claim 2, wherein: The descriptor reader includes an entry register, an acquisition module, and a status register group; and acquiring the descriptor chain sent by the descriptor reader through the descriptor queue includes: Writing the first address of the descriptor chain into the entry register through the CPU, configuring an identification number for the descriptor chain through the entry register, and identifying each descriptor in the descriptor chain with the identification number; Reading the plurality of descriptors in the descriptor chain from a system cache according to the first address by the acquisition module, and sending the descriptors to the descriptor queue; The completion status of each descriptor chain and each descriptor in each descriptor chain is recorded through the status register group.

4. The method for accessing a flash memory unit based on a descriptor according to claim 1, wherein: The descriptor includes an OPCODE pointer, access unit information, flash memory particle address information, system cache address, hardware control information and address information of the next descriptor. The hardware control information includes a channel scheduling switch and a channel scheduling tag.

5. The method for accessing a flash memory unit based on a descriptor according to claim 1, wherein: After sequentially reading the descriptors in the descriptor queue by the task scheduler and determining whether there are other descriptors in the suspended waiting area that have uncompleted access tasks and have the same access unit information as the current descriptor, the method further includes: If there are unfinished access tasks for other descriptors with the same access unit information as the current descriptor in the suspended waiting area, the task scheduler reads the next descriptor in the descriptor queue as the current descriptor, and repeats this step until there are no unfinished access tasks for other descriptors with the same access unit information as the current descriptor in the suspended waiting area.

6. The method for accessing a flash memory unit based on a descriptor according to claim 1, wherein: After determining by the task scheduler whether the channel scheduling switch of the current descriptor is in the first state, the method further includes: When the channel scheduling switch of the current descriptor is in the second state, sending a second signal to the suspend waiting area through the task scheduler, so as to enable the suspend waiting area to periodically query the execution unit for the task completion status of other descriptors in the suspend waiting area; Dispatching the current descriptor to the task parser through the task scheduler, so that the task parser parses the current descriptor to form a control instruction; Executing an access operation on the flash memory particles according to the control instruction by the execution unit; When the execution time exceeds a preset time, the current descriptor is stored in the suspended waiting area, the task parser suspends parsing of subsequent tasks of the current descriptor, and returns to the step of sequentially reading the descriptors in the descriptor queue through the task scheduler to determine whether there are unfinished access tasks of other descriptors having the same access unit information as the current descriptor in the suspended waiting area; When the descriptor in the suspension waiting area meets the suspension exit condition, the suspension waiting area notifies the task scheduler. When the task scheduler is idle, the descriptor in the suspension waiting area is rescheduled for subsequent parsing and execution until the task of the descriptor is completed.

7. The method for accessing a flash memory unit based on a descriptor according to claim 1, wherein: The task scheduler dispatches the current descriptor to the task parser, so that the task parser parses the current descriptor to form a control instruction, including: The task scheduler searches the OPCODE table for the corresponding task sequence according to the OPCODE pointer of the current descriptor, and sends the task sequence and the current descriptor to the task parser; The task parser parses the current descriptor to determine whether the task sequence is a DMA start type, a suspend wait type, an FCU instruction type, or an end type; wherein the FCU represents a flash memory control unit; If the type of the task sequence is a DMA start type, the task parser parses the current descriptor and generates an RDMA or WDMA start instruction; Alternatively, if the type of the task sequence is a suspended waiting type, the task parser stores the current descriptor in the suspended waiting area and suspends subsequent parsing actions of the current descriptor; Alternatively, if the type of the task sequence is an FCU instruction type, the task parser reads parameters and a command set in a command table according to the task, and generates an instruction for accessing the flash memory particles according to the parameters and the command set; Alternatively, if the task type is an end type, the task parser generates an instruction for updating the descriptor state to a specified location in the system cache and ends the parsing task of the entire descriptor.

8. A flash memory controller, characterized in that: include: A descriptor queue, a task scheduler, a task parser, an execution unit and a suspension waiting area, wherein the flash memory controller is used to execute the descriptor-based access method to the flash memory unit according to any one of claims 1 to 7.

9. A flash memory control system, characterized in that: include: The flash memory controller, descriptor reader, CPU, bus and system cache as described in claim 8, the bus is connected to the flash memory controller, the descriptor reader, the CPU and the system cache respectively, the descriptor reader is connected to the flash memory controller, and the flash memory control system is used to execute the descriptor-based access method for the flash memory unit as described in any one of claims 1-7.

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