Display panel and display device

Abstract

The embodiment of the invention discloses a display panel and a display device.The display panel comprises a first driving circuit with a first capacitor and a second driving circuit with a second capacitor, and the first capacitor and the second capacitor are adjacently and oppositely arranged between the first driving circuit and the second driving circuit; the first capacitor and the second capacitor are matched in a concave-convex mode, charge movement between the first driving circuit and the second driving circuit is blocked, then the distance between the first driving circuit and the second driving circuit can be narrowed, and a frame is narrowed; and secondly, through the concave-convex matching of the first capacitor and the second capacitor, not only is the limited space fully utilized to narrow the frame, but also the capacitance of the first capacitor and the second capacitor is improved, and the stability of the first driving circuit and the second driving circuit is further improved.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] The gate driving circuit of an OLED panel has multiple groups of driving circuits, and each group of driving circuits is provided with a bootstrap capacitor. The conventional design is to set the capacitor as a whole in a large-space area, generally in the lower area of each group of driving circuits. However, due to the requirement of a relatively large capacitance, the layout area of the capacitor is large. Therefore, the large-area design of the capacitor as a whole occupies a large amount of space and cannot achieve a narrow border. Secondly, in order to reduce the mutual influence between adjacent two groups of driving circuits due to charge movement, it is usually necessary to design a relatively wide spacing distance between adjacent two groups of driving circuits, and such a setting further widens the border. Summary of the Invention

[0003] Embodiments of this application provide a display panel and a display device, which can achieve a narrow border while reducing the risk of charge mutual influence between adjacent two groups of driving circuits.

[0004] Embodiments of this application provide a display panel, including a non-display area. The display panel includes:

[0005] A first driving circuit, arranged in the non-display area, the first driving circuit includes a first capacitor, and the first capacitor is arranged in a side edge area of the first driving circuit; and

[0006] A second driving circuit, arranged in the non-display area and on one side of the first driving circuit, the second driving circuit includes a second capacitor, and the second capacitor is arranged in an edge area of the second driving circuit close to the first driving circuit;

[0007] Wherein, in the display panel viewed from a top-down perspective, the first capacitor and the second capacitor are adjacent and oppositely arranged. A first groove and a first convex structure are formed on a side of the first capacitor facing the second capacitor, and a second groove and a second convex structure are formed on a side of the second capacitor facing the first capacitor. A part of the first convex structure extends and is arranged in the second groove, and a part of the second convex structure extends and is arranged in the first groove.

[0008] Optionally, in some embodiments of this application, the first driving circuit and the second driving circuit are arranged along a first direction;

[0009] The first capacitor includes a first part and a second part extending along a second direction, the second direction intersecting with the first direction. In the second direction, the first part is connected to the second part. In the first direction, the second part protrudes from the first part to form at least a part of the first convex structure, and the first part is recessed within the second part and forms at least a part of the first groove with the side surface of the second part;

[0010] The second capacitor includes a fifth part and a sixth part extending along the second direction. In the second direction, the sixth part is connected to the fifth part. In the first direction, the fifth part protrudes from the sixth part to form at least a part of the second convex structure, and the sixth part is recessed within the fifth part and forms at least a part of the second groove with the side surface of the fifth part;

[0011] A part of the second part extends and is disposed within the second groove, and a part of the fifth part extends and is disposed within the first groove.

[0012] Optionally, in some embodiments of the present application, the first driving circuit further includes a first transistor. In the second direction, the first transistor is disposed on a side of the second part away from the first part;

[0013] The first capacitor further includes a third part and a fourth part. The third part is connected to a side of the second part away from the first part, and the fourth part is connected to a side of the third part away from the second part. The third part extends along the second direction, and the fourth part extends along the first direction. In the first direction, the first transistor is disposed on a side of the third part away from the sixth part, and in the second direction, the first transistor is disposed between the fourth part and the second part.

[0014] Optionally, in some embodiments of the present application, the second capacitor includes a seventh part. The seventh part extends towards the first driving circuit in the first direction. The seventh part is connected to a side of the sixth part away from the fifth part. The fifth part, the sixth part, and the seventh part are connected to form the second groove. The second part, the third part, and the fourth part are connected to form the first convex structure. A part of the second part, a part of the fourth part, and the third part are disposed within the second groove;

[0015] In the first direction, the sixth part is further disposed on a side of the third part away from the first transistor; in the second direction, the seventh part is disposed on a side of the fourth part away from the first transistor.

[0016] Optionally, in some embodiments of the present application, the first driving circuit includes a second transistor. On the side of the second transistor close to the second driving circuit in the first direction, the fourth part and the seventh part are provided.

[0017] Optionally, in some embodiments of the present application, the first driving circuit includes a third transistor and a fourth transistor. In the second direction, the third transistor is disposed on the side of the fourth transistor away from the second part. In the first direction, the third transistor and the fourth transistor are disposed on the side of the first part away from the fifth part.

[0018] Optionally, in some embodiments of the present application, in the first direction, the second part extends away from the second capacitor and extends beyond the first part, and the part of the second part that extends beyond the first part is disposed between the first transistor and the fourth transistor in the second direction.

[0019] Optionally, in some embodiments of the present application, the first electrode of the third transistor and the first electrode of the fourth transistor are connected through the first electrode plate of the first capacitor, and the gate of the third transistor and the gate of the fourth transistor are connected through the second electrode plate of the first capacitor.

[0020] Optionally, in some embodiments of the present application, the second driving circuit includes a first thin-film transistor, and the first thin-film transistor is disposed on the side of the fifth part and the sixth part away from the first capacitor.

[0021] Optionally, in some embodiments of the present application, the second electrode of the first thin-film transistor includes a plurality of sub-electrodes connected in parallel, and the plurality of sub-electrodes are connected in parallel through the third electrode plate of the second capacitor;

[0022] The gate of the first thin-film transistor includes a plurality of sub-gates connected in parallel, and the plurality of sub-gates are connected in parallel through the fourth electrode plate of the second capacitor.

[0023] Correspondingly, an embodiment of the present application further provides a display device, which includes the display panel described in any one of the above embodiments.

[0024] The display panel according to an embodiment of the present application includes a first driving circuit having a first capacitor and a second driving circuit having a second capacitor. By arranging the first capacitor and the second capacitor adjacent to and opposite each other and between the first driving circuit and the second driving circuit, with the first capacitor and the second capacitor fitting in a concave-convex manner to block the charge movement between the first driving circuit and the second driving circuit, the distance between the first driving circuit and the second driving circuit can be narrowed, and thus the frame can be narrowed. Secondly, the concave-convex fitting of the first capacitor and the second capacitor not only makes full use of the limited space to narrow the frame, but also increases the capacitance of the first capacitor and the second capacitor, thereby improving the stability of the first driving circuit and the second driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a partial structural schematic diagram of the display panel provided by an embodiment of the present application;

[0026] Figure 2 is Figure 1 a top view schematic diagram of the first capacitor in

[0027] Figure 3 is Figure 1 a top view schematic diagram of the second capacitor in

[0028] Figure 4 is corresponding to Figure 1 a structural schematic diagram of the film layer where the first electrode plate of the first capacitor is located;

[0029] Figure 5 is corresponding to Figure 1 a structural schematic diagram of the film layer where the second electrode plate of the first capacitor is located;

[0030] Figure 6 is an equivalent circuit diagram of the first driving circuit of the display panel provided by an embodiment of the present application;

[0031] Figure 7 is an equivalent circuit diagram of the second driving circuit of the display panel provided by an embodiment of the present application;

[0032] Figure 8 is a structural schematic diagram of the display device provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0033] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application. In addition, it should be understood that the specific implementation manners described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, the embodiments can be combined with each other without further elaboration. And in the case of no contrary description, the orientation terms such as "upper" and "lower" usually refer to the upper and lower in the actual use or working state of the device, specifically the plane direction in the drawings; while "inner" and "outer" refer to the outline of the device; the terms "first", "second", "third", etc. are only used as labels, and no digital requirements are imposed or an order is established.

[0034] An embodiment of the present application provides a display panel and a display device, which will be described in detail below. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments.

[0035] Figure 1 is a partial schematic view of the display panel 100 of the embodiment of the present application from a top view. In Figure 1 it, the first direction F1 can be a direction parallel to one side of the display panel 100 in a plane view, and for example, can be the horizontal direction of the display panel 100. The second direction F2 can be a direction parallel to the other side of the display panel 100 in a plane view, and can be the longitudinal direction of the display panel 100.

[0036] Optionally, the first direction F1 and the second direction F2 intersect. In the embodiments of the present application, the case where the first direction F1 is perpendicular to the second direction F2 is taken as an example for description, but it is not limited thereto. For example, the two can intersect non-perpendicularly.

[0037] Please refer to Figure 1 , an embodiment of the present application provides a display panel 100, which includes a first driving circuit 10 and a second driving circuit 20. The first driving circuit 10 and the second driving circuit 20 are disposed in the non-display area of the display panel 100.

[0038] It should be noted that Figure 1 only a part of the first driving circuit 10 and a part of the second driving circuit 20 are shown. Secondly, the embodiments of the present application take the first driving circuit 10 and the second driving circuit 20 being located in the gate driving circuit area as an example for description, but it is not limited thereto.

[0039] The first driving circuit 10 includes a first capacitor C1-R, and the first capacitor C1-R is disposed in a side edge region of the first driving circuit 10. The second driving circuit 20 is disposed on one side of the first driving circuit 10. The second driving circuit 20 includes a second capacitor C1-I, and the second capacitor C1-I is disposed in an edge region of the second driving circuit 20 close to the first driving circuit 10.

[0040] Among them, in the display panel 100 viewed from a top-down perspective, the first capacitor C1-R and the second capacitor C1-I are adjacent and oppositely disposed. A first groove A1 and a first convex structure D1 are formed on a side of the first capacitor C1-R facing the second capacitor C1-I. A second groove A2 and a second convex structure D2 are formed on a side of the second capacitor C1-I facing the first capacitor C1-R. A part of the first convex structure D1 extends and is disposed in the second groove A2, and a part of the second convex structure D2 extends and is disposed in the first groove A1.

[0041] In the display panel 100 according to the embodiment of the present application, the first capacitor C1-R and the second capacitor C1-I are adjacent and oppositely disposed and are disposed between the first driving circuit 10 and the second driving circuit 20. The first capacitor C1-R and the second capacitor C1-I are in concave-convex fit to block the charge movement between the first driving circuit 10 and the second driving circuit 20. Furthermore, the distance between the first driving circuit 10 and the second driving circuit 20 can be narrowed, and thus the border can be narrowed. Secondly, the concave-convex fit of the first capacitor C1-R and the second capacitor C1-I not only makes full use of the limited space to narrow the border, but also increases the capacitance of the first capacitor C1-R and the second capacitor C1-I, and further improves the stability of the first driving circuit 10 and the second driving circuit 20.

[0042] In addition, compared with the design in which the opposite sides of the first capacitor C1-R and the second capacitor C1-I are straight and parallel, in the concave-convex fit of the first capacitor C1-R and the second capacitor C1-I, the concave-convex edges can disperse the direction of the electric field lines between the electrodes through an interleaved geometric structure, thereby reducing the coupling intensity of the edge electric field between the two, and further reducing the risk of mutual interference between the first capacitor C1-R and the second capacitor C1-I.

[0043] Optionally, in some embodiments of the present application, the first driving circuit 10 and the second driving circuit 20 are arranged along a first direction F1.

[0044] Please refer to Figures 1 to 3, the first capacitor C1-R includes a first portion 101 and a second portion 102 extending along a second direction F2. The second direction F2 intersects with a first direction F1. In the second direction F2, the first portion 101 is connected to the second portion 102. In the first direction F1, the second portion 102 protrudes from the first portion 101 to form at least a part of a first convex structure D1, and the first portion 101 is recessed within the second portion 102 and forms at least a part of a first groove A1 with the side surface of the second portion 102.

[0045] The second capacitor C1-I includes a fifth portion 105 and a sixth portion 106 extending along the second direction F2. In the second direction F2, the sixth portion 106 is connected to the fifth portion 105. In the first direction F1, the fifth portion 105 protrudes from the sixth portion 106 to form at least a part of a second convex structure D2, and the sixth portion 106 is recessed within the fifth portion 105 in a direction away from the first capacitor C1-R and forms at least a part of a second groove A2 with the side surface of the fifth portion 105.

[0046] A part of the second portion 102 extends and is disposed within the second groove A2, and a part of the fifth portion 105 extends and is disposed within the first groove A1.

[0047] It can be understood that multiple transistors of the first driving circuit 10 are all disposed on a side of the first capacitor C1-R away from the second driving circuit 20, and multiple thin-film transistors of the second driving circuit 20 are all disposed on a side of the second capacitor C1-I away from the first driving circuit 10. Thus, the transistors of the first driving circuit 10 and the thin-film transistors of the second driving circuit 20 are isolated by the first capacitor C1-R and the second capacitor C1-I, reducing the risk of mutual interference between the first driving circuit 10 and the second driving circuit 20.

[0048] It should be noted that the transistors are also thin-film transistors.

[0049] Optionally, in some embodiments of the present application, the first capacitor C1-R further includes a third portion 103 and a fourth portion 104. In the second direction F2, the third portion 103 is connected to a side of the second portion 102 away from the first portion 101, and the fourth portion 104 is connected to a side of the third portion 103 away from the second portion 102. The third portion 103 extends along the second direction F2, and the fourth portion 104 extends along the first direction F1.

[0050] The second capacitor C1-i includes a seventh portion 107 that extends toward the first driving circuit 10 in the first direction F1. The seventh portion 107 is connected to a side of the sixth portion 106 away from the fifth portion 105. The fifth portion 105, the sixth portion 106, and the seventh portion 107 are connected to form a second groove a2. The second portion 102, the third portion 103, and the fourth portion 104 are connected to form a first convex structure d1. Portions of the second portion 102, portions of the fourth portion 104, and the third portion 103 are disposed within the second groove a2.

[0051] It can be understood that the display panel 100 according to the embodiments of the present application adjusts the layout patterns of the first capacitor C1-r and the second capacitor C1-i according to the layout of each transistor and thin-film transistor. By setting the irregular-shaped first capacitor C1-r, the space between the transistors is fully utilized, which can not only meet the capacitance of the first capacitor C1-r, but also reduce the border. At the same time, by setting the irregular-shaped second capacitor C1-i, the space between the thin-film transistors is fully utilized and the pattern of the second capacitor C1-i is set according to the pattern of the first capacitor C1-r, which can not only meet the capacitance of the second capacitor C1-i, but also reduce the border.

[0052] Optionally, in some embodiments of the present application, in the first direction F1, the length of the seventh portion 107 is greater than the length of the fourth portion 104, so that the seventh portion 107 fully utilizes the corner space, improves the capacitance of the second capacitor C1-i, and narrows the border at the same time.

[0053] Optionally, in some embodiments of the present application, the first driving circuit 10 further includes a first transistor T56-r. In the second direction F2, the first transistor T56-r is disposed on a side of the second portion 102 away from the first portion 101.

[0054] In the first direction F1, the first transistor T56-r is disposed on a side of the third portion 103 away from the sixth portion 106. In the second direction F2, the first transistor T56-r is disposed between the fourth portion 104 and the second portion 102.

[0055] It can be understood that the third portion 103 and the fourth portion 104 are arranged to extend along the outer periphery of the first transistor T56-r to reduce the risk of interference signals entering the first transistor T56-r, and the first capacitor C1-r can be disposed in the vacant space below the first transistor T56-r, thereby increasing the capacitance of the first capacitor C1-r.

[0056] Optionally, in some embodiments of the present application, in the first direction F1, the sixth portion 106 is further disposed on a side of the third portion 103 away from the first transistor T56-r. In the second direction F2, the seventh portion 107 is disposed on a side of the fourth portion 104 away from the first transistor T56-r.

[0057] It should be noted that the sixth part 106 is connected to the seventh part 107 and wound around the outer peripheral side of the third part 103 and the fourth part 104, so as to form a double charge barrier between the first transistor T56-r and the thin film transistor of the second driving circuit 20, further reducing the risk of mutual interference between the two.

[0058] Secondly, the seventh part 107 extends and is arranged on the side of the fourth part 104 away from the first transistor T56-r, and the second capacitor c1-i can be arranged by making full use of the vacant space under the first transistor T56-r, thereby increasing the capacitance of the second capacitor c1-i.

[0059] Optionally, in some embodiments of the present application, the first driving circuit 10 includes a second transistor T11-r. In the first direction F1, the fourth part 104 and the seventh part 107 are arranged on the side of the second transistor T11-r close to the second driving circuit 20.

[0060] It can be understood that since the gate of the second transistor T11-r is connected to the gate of the first transistor T56-r, arranging the first transistor T56-r adjacent to the second transistor T11-r can shorten the gate connection line and save layout space; secondly, using the remaining corner space after arranging the first transistor T56-r and the second transistor T11-r to arrange the fourth part 104 and the seventh part 107 not only increases the capacitances of the first capacitor c1-r and the second capacitor c1-i, but also isolates the second transistor T11-r and the thin film transistor of the second driving circuit 20 by the fourth part 104 and the seventh part 107, further reducing the risk of mutual interference of charge migration between the two.

[0061] Optionally, in some embodiments of the present application, the first driving circuit 10 includes a third transistor T53-r and a fourth transistor T54-r. In the second direction F2, the third transistor T53-r is arranged on the side of the fourth transistor T54-r away from the second part 102. In the first direction F1, the third transistor T53-r and the fourth transistor T54-r are arranged on the side of the first part 101 away from the fifth part 105.

[0062] It can be understood that arranging the third transistor T53-r and the fourth transistor T54-r on the side of the first part 101 away from the second capacitor c1-i can reduce the risk of charge migration interference between the third transistor T53-r and the fourth transistor T54-r and the thin film transistors of the second driving circuit 20 respectively.

[0063] Optionally, in some embodiments, the first capacitor C1-R further includes an eighth portion 108, which extends along the first direction F1. The eighth portion 108 is connected to the side of the first portion 101 away from the second portion 102. In the second direction F2, the eighth portion 108 is disposed on the side of the third transistor T53-R away from the fourth transistor T54-R.

[0064] It can be understood that using the eighth portion 108 to isolate the third transistor T53-R from the transistors of other driving circuits in the second direction F2 can reduce the risk of charge migration interference between them and increase the capacitance of the first capacitor C1-R.

[0065] Optionally, in some embodiments of the present application, in the first direction F1, the second portion 102 extends away from the second capacitor C1-I and extends beyond the first portion 101. The portion of the second portion 102 extending beyond the first portion 101 is disposed between the first transistor T56-R and the fourth transistor T54-R in the second direction F2.

[0066] It can be understood that the second portion 102 is disposed in the space between the first transistor T56-R and the fourth transistor T54-R without occupying additional space, improving the space utilization rate of the first capacitor C1-R and narrowing the frame width.

[0067] Optionally, in some embodiments of the present application, please refer to Figure 4 and Figure 5 , the first electrode of the third transistor T53-R and the first electrode of the fourth transistor T54-R are connected through the first electrode plate 111 of the first capacitor C1-R, and the gate of the third transistor T53-R and the gate of the fourth transistor T54-R are connected through the second electrode plate 112 of the first capacitor C1-R.

[0068] It can be understood that using the first electrode plate 111 of the first capacitor C1-R as the connection line for the first electrode 131 of the third transistor T53-R and the first electrode 132 of the fourth transistor T54-R, and using the second electrode plate 112 of the first capacitor C1-R as the connection line for the gate G1 of the third transistor T53-R and the gate G2 of the fourth transistor T54-R, no additional connection lines need to be provided, saving wiring space and thus narrowing the frame.

[0069] Optionally, the first electrode 131 of the third transistor T53-R, the first electrode 132 of the fourth transistor T54-R, and the first electrode plate 111 of the first capacitor C1-R are disposed on the same layer. The gate G1 of the third transistor T53-R, the gate G2 of the fourth transistor T54-R, and the second electrode plate 112 of the first capacitor C1-R are disposed on the same layer.

[0070] Optionally, in some embodiments of the present application, the second driving circuit 20 includes a first thin-film transistor T21-i, and the first thin-film transistor T21-i is disposed on a side of the fifth portion 105 and the sixth portion 106 away from the first capacitor c1-r.

[0071] It can be understood that disposing the first thin-film transistor T21-i on a side of the fifth portion 105 and the sixth portion 106 away from the first capacitor c1-r can reduce the risk of charge migration interference between the first thin-film transistor T21-i and the third transistor T53-r and the fourth transistor T54-r respectively.

[0072] Optionally, in some embodiments of the present application, please refer to Figure 4 and Figure 5 , the second electrode of the first thin-film transistor T21-i includes a plurality of parallel sub-electrodes 121, and the plurality of sub-electrodes 121 are connected in parallel through the third electrode plate 113 of the second capacitor c1-i. The gate of the first thin-film transistor T21-i includes a plurality of parallel sub-gates 122, and the plurality of sub-gates 122 are connected in parallel through the fourth electrode plate 114 of the second capacitor c1-i.

[0073] It can be understood that using the third electrode plate 113 of the second capacitor c1-i as the connection line of the sub-electrodes 121 of the first thin-film transistor T21-i and the fourth electrode plate 114 of the second capacitor c1-i as the connection line of the sub-gates 122 of the first thin-film transistor T21-i can eliminate the need for additional connection lines, saving wiring space and thus narrowing the border.

[0074] Optionally, in some embodiments, both the first driving circuit 10 and the second driving circuit 20 are gate driving circuits, but are not limited thereto, and the two can also be other driving circuits.

[0075] Please refer to Figure 6 , the first driving circuit 10 is configured to output at least a first control signal to the second signal terminal REF[n]. The first control signal may be a compensation signal, and the second signal terminal REF[n] is connected to a pixel circuit in the display area.

[0076] The first driving circuit 10 includes a first transistor T56-r, a second transistor T11-r, a third transistor T53-r, a fourth transistor T54-r, a fifth transistor T21-r, a sixth transistor T31-r, a seventh transistor T41A-r, an eighth transistor T41B-r, a ninth transistor T42A-r, a tenth transistor T42B-r, an eleventh transistor T51A-r, a twelfth transistor T51B-r, a thirteenth transistor T52A-r, a fourteenth transistor T52B-r, a fifteenth transistor T55-r, a sixteenth transistor T61A-r, a seventeenth transistor T61B-r, a first capacitor c1-r, and a third capacitor c2-r.

[0077] Among them, the gate of the second transistor T11-r is connected to the first signal terminal INI[n + 1], the first electrode of the second transistor T11-r is connected to the first high potential terminal VGH1, and the second electrode of the second transistor T11-r is connected to the first node Q1.

[0078] The first electrode of the fifth transistor T21-r is connected to the first high potential terminal VGH1, the second electrode of the fifth transistor T21-r is connected to the second signal terminal REF[n], the gate of the fifth transistor T21-r and one plate of the third capacitor c2-r are connected to the first node Q1, and the other plate of the third capacitor c2-r is connected to the second signal terminal REF[n].

[0079] The first electrode of the sixth transistor T31-r is connected to the second signal terminal REF[n], the second electrode of the sixth transistor T31-r is connected to the second low potential terminal VGL2, and the gate of the sixth transistor T31-r is connected to the second node Q2.

[0080] The first electrode of the seventh transistor T41A-r is connected to the first node Q1, the second electrode of the seventh transistor T41A-r is connected to the third signal terminal Nn, the gate of the seventh transistor T41A-r is connected to the fourth signal terminal Gn[n - 1], the first electrode of the eighth transistor T41B-r is connected to the third signal terminal Nn, the second electrode of the eighth transistor T41B-r is connected to the first low potential terminal VGL1, and the gate of the eighth transistor T41B-r is connected to the fourth signal terminal Gn[n - 1].

[0081] The first electrode of the ninth transistor T42A-r is connected to the first node Q1, the second electrode of the ninth transistor T42A-r is connected to the third signal terminal Nn, the gate of the ninth transistor T42A-r is connected to the second node Q2. The first electrode of the tenth transistor T42B-r is connected to the third signal terminal Nn, the second electrode of the tenth transistor T42B-r is connected to the first low potential terminal VGL1, and the gate of the tenth transistor T42B-r is connected to the second node Q2.

[0082] The first electrode and the gate of the eleventh transistor T51A-r are both connected to the fourth signal terminal Gn[n-1], and the second electrode of the eleventh transistor T51A-r is connected to the third node Q3. The first electrode of the twelfth transistor T51B-r is connected to the third node Q3, the second electrode of the twelfth transistor T51B-r is connected to the fourth node Q4, and the gate of the twelfth transistor T51B-r is connected to the fourth signal terminal Gn[n-1].

[0083] The first electrode of the thirteenth transistor T52A-r is connected to the fourth node Q4, the second electrode of the thirteenth transistor T52A-r is connected to the third node Q3, and the gate of the thirteenth transistor T52A-r is connected to the fifth signal terminal INI[n]. The first electrode of the fourteenth transistor T52B-r is connected to the third node Q3, the second electrode of the fourteenth transistor T52B-r is connected to the first low potential terminal VGL1, and the gate of the fourteenth transistor T52B-r is connected to the fifth signal terminal INI[n].

[0084] The first electrode of the third transistor T53-r is connected to the first high potential terminal VGH1, the second electrode of the third transistor T53-r is connected to the third node Q3, and the gate of the third transistor T53-r is connected to the fourth node Q4. One electrode plate of the first capacitor c1-r is connected to the fourth node Q4, and the other electrode plate of the first capacitor c1-r is connected to the first high potential terminal VGH1. The first electrode of the fourth transistor T54-r is connected to the first high potential terminal VGH1, the second electrode of the fourth transistor T54-r is connected to the second node Q2, and the gate of the fourth transistor T54-r is connected to the fourth node Q4.

[0085] The first electrode of the fifteenth transistor T55-r is connected to the second node Q2, the second electrode of the fifteenth transistor T55-r is connected to the first low potential terminal VGL1, and the gate of the fifteenth transistor T55-r is connected to the first node Q1. The first electrode of the first transistor T56-r is connected to the second node Q2, the second electrode of the first transistor T56-r is connected to the first low potential terminal VGL1, and the gate of the first transistor T56-r is connected to the first signal terminal INI[n+1].

[0086] The first electrode of the sixteenth transistor T61A-r is connected to the first high potential terminal VGH1, the second electrode of the sixteenth transistor T61A-r is connected to the first electrode of the seventeenth transistor T61B-r, and the gate of the sixteenth transistor T61A-r is connected to the first node Q1. The second electrode of the seventeenth transistor T61B-r is connected to the third signal terminal Nn, and the gate of the seventeenth transistor T61B-r is connected to the first node Q1.

[0087] Please refer to Figure 1, in the second direction F2, the sixteenth transistor T61A-r, the seventeenth transistor T61B-r, the seventh transistor T41A-r, the eighth transistor T41B-r, the fifteenth transistor T55-r, and the second transistor T11-r are arranged in sequence.

[0088] Optionally, in some embodiments, please refer to Figure 7 , the second driving circuit 20 is configured to output at least a second control signal to the fifth signal terminal INI[n]. The second control signal may be a reset signal, and the fifth signal terminal INI[n] is connected to the pixel circuit.

[0089] The second driving circuit 20 includes a first thin-film transistor T21-i, a second thin-film transistor T11-i, a third thin-film transistor T31-i, a fourth thin-film transistor T41A-i, a fifth thin-film transistor T41B-i, a sixth thin-film transistor T42A-i, a seventh thin-film transistor T42B-i, an eighth thin-film transistor T43A-i, a ninth thin-film transistor T43B-i, a tenth thin-film transistor T51A-i, an eleventh thin-film transistor T51B-i, a twelfth thin-film transistor T52-i, a thirteenth thin-film transistor T53-i, a fourteenth thin-film transistor T54-i, a fifteenth thin-film transistor T55-i, a sixteenth thin-film transistor T61A-i, a seventeenth thin-film transistor T61B-i, and a second capacitor c1-i.

[0090] The gate of the second thin-film transistor T11-i is connected to the sixth signal terminal INI[n-2], the first electrode of the second thin-film transistor T11-i is connected to the second high potential terminal VGH2, and the second electrode of the second thin-film transistor T11-i is connected to the fifth node P1.

[0091] The gate of the first thin-film transistor T21-i is connected to the fifth node P1, the first electrode of the first thin-film transistor T21-i is connected to the clock signal terminal CKC, and the second electrode of the first thin-film transistor T21-i is connected to the fifth signal terminal INI[n]. One electrode plate of the second capacitor c1-i is connected to the fifth node P1, and the other electrode plate of the second capacitor c1-i is connected to the fifth signal terminal INI[n].

[0092] The gate of the third thin-film transistor T31-i is connected to the sixth node P2, the first electrode of the third thin-film transistor T31-i is connected to the fifth signal terminal INI[n], and the second electrode of the third thin-film transistor T31-i is connected to the third low potential terminal VHL3.

[0093] The gate of the fourth thin film transistor T41A-i is connected to the seventh signal terminal INI[n+2], the first electrode of the fourth thin film transistor T41A-i is connected to the fifth node P1, and the second electrode of the fourth thin film transistor T41A-i is connected to the eighth signal terminal N[n]. The gate of the fifth thin film transistor T41B-i is connected to the seventh signal terminal INI[n+2], the first electrode of the fifth thin film transistor T41B-i is connected to the eighth signal terminal N[n], and the second electrode of the fifth thin film transistor T41B-i is connected to the third low potential terminal VHL3.

[0094] The gate of the sixth thin film transistor T42A-i is connected to the sixth node P2, the first electrode of the sixth thin film transistor T42A-i is connected to the fifth node P1, and the second electrode of the sixth thin film transistor T42A-i is connected to the eighth signal terminal N[n]. The gate of the seventh thin film transistor T42B-i is connected to the sixth node P2, the first electrode of the seventh thin film transistor T42B-i is connected to the eighth signal terminal N[n], and the second electrode of the seventh thin film transistor T42B-i is connected to the third low potential terminal VHL3.

[0095] The gate of the eighth thin film transistor T43A-i is connected to the control signal terminal VST, the first electrode of the eighth thin film transistor T43A-i is connected to the fifth node P1, and the second electrode of the eighth thin film transistor T43A-i is connected to the eighth signal terminal N[n]. The gate of the ninth thin film transistor T43B-i is connected to the control signal terminal VST, the first electrode of the ninth thin film transistor T43B-i is connected to the eighth signal terminal N[n], and the second electrode of the ninth thin film transistor T43B-i is connected to the third low potential terminal VHL3.

[0096] The gate and the first electrode of the tenth thin film transistor T51A-i are connected to the low-frequency clock signal terminal LC, and the second electrode of the tenth thin film transistor T51A-i is connected to the first electrode of the eleventh thin film transistor T51B-i. The second electrode of the eleventh thin film transistor T51B-i is connected to the seventh node P3, and the gate of the eleventh thin film transistor T51B-i is connected to the low-frequency clock signal terminal LC.

[0097] The gate of the twelfth thin film transistor T52-i is connected to the fifth node P1, the first electrode of the twelfth thin film transistor T52-i is connected to the seventh node P3, and the second electrode of the twelfth thin film transistor T52-i is connected to the third low potential terminal VHL3.

[0098] The gate of the thirteenth thin film transistor T53-i is connected to the seventh node P3, the first electrode of the thirteenth thin film transistor T53-i is connected to the low-frequency clock signal terminal LC, and the second electrode of the thirteenth thin film transistor T53-i is connected to the sixth node P2.

[0099] The gate of the fourteenth thin film transistor T54-i is connected to the fifth node P1, the first electrode of the fourteenth thin film transistor T54-i is connected to the sixth node P2, and the second electrode of the fourteenth thin film transistor T54-i is connected to the third low potential terminal VHL3.

[0100] The gate of the fifteenth thin film transistor T55-i is connected to the sixth signal terminal INI[n - 2], the first electrode of the fifteenth thin film transistor T55-i is connected to the sixth node P2, and the second electrode of the fifteenth thin film transistor T55-i is connected to the third low potential terminal VHL3.

[0101] The gate of the sixteenth thin film transistor T61A-i is connected to the fifth node P1, the first electrode of the sixteenth thin film transistor T61A-i is connected to the second electrode of the seventeenth thin film transistor T61B-i, and the second electrode of the sixteenth thin film transistor T61A-i is connected to the eighth signal terminal N[n]. The gate of the seventeenth thin film transistor T61B-i is connected to the fifth node P1, and the first electrode of the seventeenth thin film transistor T61B-i is connected to the second high potential terminal VGH2.

[0102] Correspondingly, please refer to Figure 8 , the embodiment of the present application further provides a display device 1000, which includes the display panel 100 described in any one of the above embodiments.

[0103] It should be noted that the structure of the display panel 100 of the display device 1000 in the embodiment of the present application is similar to or the same as the structure of the display panel 100 in any one of the above embodiments. For specific details, please refer to Figures 1 to 7 the description, so it will not be elaborated here.

[0104] Optionally, the display device 1000 can be applied to various products and can be used within the various products, and the various products include, for example, televisions, notebook computers, monitors, billboards, Internet of Things devices, and portable electronic devices including mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic notebooks, e-books, portable multimedia players, navigation devices, and ultra-mobile personal computers.

[0105] In addition, according to some embodiments, the display device 1000 can be applied to wearable devices and can be used within the wearable devices, and the wearable devices include smart watches, watch phones, glasses-type displays, and head-mounted displays. In addition, according to some embodiments, the display device 1000 can be applied to the instrument panel for automobiles, the central instrument panel for automobiles, or the display screen in the central information display arranged on the dashboard, the in-vehicle mirror display replacing the side mirror of the automobile, and the display of the entertainment system arranged on the back of the front seat for the rear seat passengers in the automobile.

[0106] In the display device 100 according to the embodiment of the present application, the first capacitor c1-r and the second capacitor c1-i are arranged adjacent to and opposite each other and are disposed between the first driving circuit 10 and the second driving circuit 20. The first capacitor c1-r and the second capacitor c1-i are in concave-convex fit to block the charge movement between the first driving circuit 10 and the second driving circuit 20, thereby narrowing the distance between the first driving circuit 10 and the second driving circuit 20, and further narrowing the border. Secondly, the concave-convex fit of the first capacitor c1-r and the second capacitor c1-i not only makes full use of the limited space to narrow the border, but also increases the capacitance of the first capacitor c1-r and the second capacitor c1-i, thereby improving the stability of the first driving circuit 10 and the second driving circuit 20.

[0107] In addition, compared with the design in which the opposite sides of the first capacitor c1-r and the second capacitor c1-i are straight and parallel, the concave-convex fit of the first capacitor c1-r and the second capacitor c1-i can disperse the direction of the electric field lines between the electrodes through the staggered geometric structure at the concave-convex edges, thereby reducing the coupling intensity of the edge electric field between the two, and further reducing the risk of mutual interference between the first capacitor c1-r and the second capacitor c1-i.

[0108] The above has introduced in detail a display panel and a display device provided by the embodiment of the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A display panel, comprising a non-display area, characterized in that, The display panel includes: A first driving circuit disposed in the non-display area. The first driving circuit includes a first capacitor, and the first capacitor is disposed in an edge area on one side of the first driving circuit; and A second driving circuit disposed in the non-display area and on one side of the first driving circuit. The second driving circuit includes a second capacitor, and the second capacitor is disposed in an edge area on the side of the second driving circuit close to the first driving circuit; Wherein, in the display panel viewed from a top-down perspective, the first capacitor and the second capacitor are adjacent and oppositely disposed. A first groove and a first convex structure are formed on a side of the first capacitor facing the second capacitor, and a second groove and a second convex structure are formed on a side of the second capacitor facing the first capacitor. A part of the first convex structure extends and is disposed in the second groove, and a part of the second convex structure extends and is disposed in the first groove.

2. The display panel according to claim 1, wherein The first driving circuit and the second driving circuit are arranged along a first direction; The first capacitor includes a first part and a second part extending along a second direction, and the second direction intersects with the first direction. In the second direction, the first part is connected to the second part. In the first direction, the second part protrudes from the first part to form at least part of the first convex structure, and the first part is retracted inside the second part and forms at least part of the first groove with a side surface of the second part; The second capacitor includes a fifth part and a sixth part extending along the second direction. In the second direction, the sixth part is connected to the fifth part. In the first direction, the fifth part protrudes from the sixth part to form at least part of the second convex structure, and the sixth part is retracted inside the fifth part and forms at least part of the second groove with a side surface of the fifth part; A part of the second part extends and is disposed in the second groove, and a part of the fifth part extends and is disposed in the first groove.

3. The display panel according to claim 2, wherein The first driving circuit further includes a first transistor. In the second direction, the first transistor is disposed on a side of the second part away from the first part; The first capacitor further includes a third part and a fourth part. The third part is connected to a side of the second part away from the first part, and the fourth part is connected to a side of the third part away from the second part. The third part extends along the second direction, and the fourth part extends along the first direction. In the first direction, the first transistor is disposed on a side of the third part away from the sixth part. In the second direction, the first transistor is disposed between the fourth part and the second part.

4. The display panel according to claim 3, wherein The second capacitor includes a seventh part. The seventh part extends towards the first driving circuit in the first direction. The seventh part is connected to a side of the sixth part away from the fifth part. The fifth part, the sixth part and the seventh part are connected to form the second groove. The second part, the third part and the fourth part are connected to form the first convex structure. A part of the second part, a part of the fourth part and the third part are disposed in the second groove; In the first direction, the sixth part is also disposed on a side of the third part away from the first transistor; in the second direction, the seventh part is disposed on a side of the fourth part away from the first transistor.

5. The display panel according to claim 4, wherein The first driving circuit includes a second transistor. In the first direction, the fourth part and the seventh part are disposed on a side of the second transistor close to the second driving circuit.

6. The display panel according to claim 3, wherein The first driving circuit includes a third transistor and a fourth transistor. In the second direction, the third transistor is disposed on a side of the fourth transistor away from the second part. In the first direction, the third transistor and the fourth transistor are disposed on a side of the first part away from the fifth part.

7. The display panel according to claim 6, characterized in that, In the first direction, the second part extends away from the second capacitor and extends beyond the first part, and a portion of the second part that extends beyond the first part is disposed between the first transistor and the fourth transistor in the second direction.

8. The display panel according to claim 6, wherein The first electrodes of the third transistor and the fourth transistor are connected through the first electrode plate of the first capacitor, and the gates of the third transistor and the fourth transistor are connected through the second electrode plate of the first capacitor.

9. The display panel according to any one of claims 2-8, characterized in that, The second driving circuit includes a first thin-film transistor, and the first thin-film transistor is disposed on a side of the fifth part and the sixth part away from the first capacitor.

10. The display panel according to claim 9, wherein, The second electrode of the first thin-film transistor includes a plurality of parallel sub-electrodes, and the plurality of sub-electrodes are connected in parallel through the third electrode plate of the second capacitor; The gate of the first thin-film transistor includes a plurality of parallel sub-gates, and the plurality of sub-gates are connected in parallel through the fourth electrode plate of the second capacitor.

11. A display device, characterized in that, A display panel as claimed in any one of claims 1-10 is included.

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