Display device

Abstract

Disclosed is a display device which may include: a display panel including a display area and a non-display area surrounding the display area, and including a plurality of pixels and a plurality of selection signal generators disposed on the display area; and a timing controller configured to control the display panel. Each of the plurality of pixels may include: a first light emitting element; a first optical member configured to refract light from the first light emitting element; a second light emitting element configured to emit light of the same color as the first light emitting element; and a second optical member configured to refract light from the second light emitting element, and having a different shape from the first optical member. Each of the plurality of selection signal generators may control one of the first light emitting element and the second light emitting element included in at least one corresponding pixel of the plurality of pixels to emit light.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2024 - 0009708, filed with the Korean Intellectual Property Office on January 22, 2024, the disclosure of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a display device, and more particularly, to a display device capable of controlling a viewing angle. Background art

[0004] According to the development of technology in modern society, display devices are being used to provide information to users in various ways. Display devices are included not only in electronic signs that transmit visual information in only one direction, but also in various electronic devices that require higher technology to confirm user input and provide information in response to the confirmed input.

[0005] For example, a display device may be included in a vehicle to provide various types of information to the driver and passengers of the vehicle. However, the display device of the vehicle needs to appropriately display content so as not to interfere with the operation of the vehicle. For example, the display device needs to limit the display of content that may reduce driving attention during vehicle operation. Summary of the invention

[0006] An object to be achieved by the present disclosure is to provide a display device capable of independently controlling the driving mode of each area by dividing a display panel by area.

[0007] Another object to be achieved by the present disclosure is to provide a display device capable of minimizing the number of lines and pixel layout provided on a display panel.

[0008] Still another object to be achieved by the present disclosure is to provide a display device capable of achieving high resolution.

[0009] The objects of the present disclosure are not limited to the above - mentioned objects, and those skilled in the art can clearly understand other objects not mentioned above from the following description.

[0010] According to an aspect of the present disclosure, a display device may include: a display panel including a display area (active area) and a non-display area (non-active area) surrounding the display area, and including a plurality of pixels and a plurality of selection signal generators disposed on the display area; and a timing controller configured to control the display panel. Each of the plurality of pixels may include: a first light-emitting element; a first optical member configured to refract light from the first light-emitting element; a second light-emitting element configured to emit light of the same color as the first light-emitting element; and a second optical member configured to refract light from the second light-emitting element and having a shape different from that of the first optical member. Each of the plurality of selection signal generators may control one of the first light-emitting element and the second light-emitting element included in at least one corresponding pixel of the plurality of pixels to emit light.

[0011] Other details of the exemplary embodiments are included in the detailed description and the drawings.

[0012] According to an exemplary embodiment of the present disclosure, by dividing the display panel by region to independently control the driving mode of each region, each region can be driven in a first mode for providing content with a wide viewing angle or in a second mode for providing content with a narrow viewing angle.

[0013] According to an exemplary embodiment of the present disclosure, by dividing the display panel by region to independently control the driving mode of each region without increasing the number of lines and the pixel layout provided on the display panel, a display panel with high resolution can be achieved.

[0014] The effects of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned above will be clearly understood by those of ordinary skill in the art from the following description.

[0015] The objects to be achieved by the above-described present disclosure, the means for achieving the objects, and the effects of the present disclosure do not specify the essential features of the claims, and thus the scope of the claims is not limited to the disclosure of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other aspects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0017] Figure 1 is an exemplary diagram of a display device according to an exemplary embodiment of the present disclosure;

[0018] Figure 2is a functional block diagram of a display device according to an exemplary embodiment of the present disclosure;

[0019] Figures 3A to 3E is a diagram showing an example of a display panel included in the Figure 2 display device;

[0020] Figure 4 is a circuit diagram showing an example of a pixel circuit included in the Figure 2 display device;

[0021] Figure 5A and Figure 5B are waveform diagrams for describing the Figure 4 pixel circuit;

[0022] Figure 6 and Figure 7 are cross-sectional views of a part of a display device according to an exemplary embodiment of the present disclosure;

[0023] Figure 8 is a circuit diagram showing an example of a selection signal generation circuit included in the Figure 2 display device;

[0024] Figure 9 is a diagram for describing an example of the operation of the Figure 8 selection signal generation circuit;

[0025] Figures 10A to 10D is an equivalent circuit diagram for describing an example of the operation of the Figure 8 selection signal generation circuit;

[0026] Figure 11 is a circuit diagram showing another example of a pixel circuit included in the Figure 2 display device;

[0027] Figure 12 is a circuit diagram showing another example of a selection signal generation circuit included in the Figure 2 display device;

[0028] Figure 13 is a diagram for describing an example of the operation of the Figure 12 selection signal generation circuit;

[0029] Figures 14A to 14D is an equivalent circuit diagram for describing an example of the operation of the Figure 12 selection signal generation circuit;

[0030] Figure 15 is a circuit diagram showing another example of a selection signal generation circuit included in the Figure 2 display device;

[0031] Figure 16 Is used to describe Figure 15 A diagram of an example of the operation of a select signal generating circuit; and

[0032] Figures 17A to 17D Is used to describe Figure 15 FIG. 1 is an equivalent circuit diagram of an example of the operation of the selection signal generating circuit. DETAILED DESCRIPTION

[0033] By referring to the following and attached Figure 1 With the detailed description of the exemplary embodiments, the advantages and features of the present disclosure and the methods for achieving these advantages and features will be clear. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure of the present disclosure and the scope of the present disclosure.

[0034] The shapes, sizes, ratios, angles, numbers, etc. of the exemplary embodiments for describing the present disclosure shown in the accompanying drawings are merely examples, and the present disclosure is not limited thereto. Throughout the specification, similar reference numerals generally represent similar elements. In addition, in the following description of the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including", "having" and "consisting of..." used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only". Unless otherwise expressly stated, any reference to the singular may include the plural.

[0035] Even if not explicitly stated, the components are interpreted as including ordinary error ranges.

[0036] When terms such as “on,” “over,” “below,” and “beside” are used to describe the positional relationship between two parts, one or more parts may be located between the two parts unless these terms are used together with the terms “immediately” or “directly.”

[0037] When an element or layer is referred to as being “on” another element or layer, the other layer or element can be directly on or directly interposed between the other element.

[0038] Although the terms "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, in the technical concept of the present disclosure, the first component to be mentioned below may be the second component.

[0039] Like reference numerals generally refer to like elements throughout the specification.

[0040] For ease of description, the dimensions and thicknesses of each component shown in the drawings are illustrated, but the present disclosure is not limited to the dimensions and thicknesses of the components shown.

[0041] The features of the various embodiments of the present disclosure may be partially or fully adhered to or combined with each other, and may be interlocked and operated in technically different ways, and the embodiments may be implemented independently of each other or in association with each other.

[0042] Hereinafter, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the drawings.

[0043] Figure 1 is an exemplary view of a display device according to an exemplary embodiment of the present disclosure.

[0044] Referring to Figure 1 , the display device 100 may be disposed on at least a part of the instrument panel of a vehicle. The instrument panel of the vehicle may include components disposed in front of the front seats (e.g., driver seat, passenger seat) of the vehicle. For example, the instrument panel of the vehicle may have an input configuration for operating various functions inside the vehicle (e.g., air conditioner, audio system, navigation system).

[0045] The display device 100 may be operated as an input unit disposed on the instrument panel of the vehicle and may manipulate at least some of the various functions of the vehicle. In the display device 100, various information related to the vehicle may be provided, such as vehicle operation information (e.g., current vehicle speed, remaining fuel amount, driving distance), information about vehicle components (e.g., damage to vehicle tires), etc.

[0046] The display device 100 may be disposed to straddle the driver seat and the passenger seat disposed on the front seats of the vehicle. The users of the display device 100 may include the driver of the vehicle and the passenger sitting on the passenger seat. Both the driver and the passenger of the vehicle may use the display device 100.

[0047] Figure 1 The display device 100 shown may be only partially shown. Figure 1 The display device 100 shown may represent a display panel among the various components included in the display device 100. Specifically, for example, Figure 1 the display device 100 shown may represent at least a part of the display area and the non-display area of the display panel. Among the components of the display device 100, components other than Figure 1 the components shown may be installed inside the vehicle (or at least in part).

[0048] Figure 2It is a functional block diagram of a display device according to an exemplary embodiment of the present disclosure.

[0049] As a display device according to an exemplary embodiment of the present disclosure, an electroluminescent display device can be applied. As the electroluminescent display device, an organic light emitting diode display device, a quantum dot light emitting diode display device, or an inorganic light emitting diode display device can be used.

[0050] Referring to Figure 2 , the display device 100 may include a display panel PN, a data driving circuit DD, a gate driving circuit GD, and a timing controller TD.

[0051] The display panel PN may generate an image to be provided to a user. For example, the display panel PN may generate and display an image to be provided to the user through a plurality of pixels PX, and each pixel is provided with a pixel circuit.

[0052] The data driving circuit DD, the gate driving circuit GD, and the timing controller TD may provide signals for the operation of each pixel PX through signal lines. For example, the signal lines configured to provide signals for the operation of each pixel PX may include a plurality of data lines DL and a plurality of gate lines GL.

[0053] The plurality of data lines DL may include a plurality of lines arranged in a column direction and connected to the pixels PX arranged in one column direction, and the plurality of gate lines GL may include a plurality of lines arranged in a row direction and connected to the pixels PX arranged in one row direction.

[0054] In some cases, the display device 100 may further include a power supply unit. In this case, a signal for operating the pixel PX may be provided through a power line connecting the power supply unit and the display panel PN. According to an exemplary embodiment, the power supply unit may supply power to the data driving circuit DD and the gate driving circuit GD. The data driving circuit DD and the gate driving circuit GD may be driven based on the power supplied from the power supply unit.

[0055] For example, the data driving circuit DD may apply a data signal to each pixel PX through the plurality of data lines DL, the gate driving circuit GD may apply a gate signal to each pixel PX through the plurality of gate lines GL, and the power supply unit may supply a power voltage to each pixel PX through a power voltage supply line.

[0056] The timing controller TD may control the data driving circuit DD and the gate driving circuit GD. For example, the timing controller TD may rearrange the digital video data input from the outside to match the resolution of the display panel PN, and provide the rearranged digital video data to the data driving circuit DD.

[0057] The data driving circuit DD can convert digital video data input from the timing controller TD into an analog data voltage based on a data control signal, and provide the analog data voltage to a plurality of data lines DL.

[0058] The gate driving circuit GD can generate a scan signal and an emission signal based on a gate control signal. For example, the gate driving circuit GD can include a scan driver and a light emission signal driver. The scan driver can generate a scan signal in a row-by-row manner to drive at least one scan line connected to each pixel row, and provide the generated scan signal to the scan line. The light emission signal driver can generate an emission signal in a row-by-row manner to drive at least one emission signal line connected to each pixel row, and provide the generated emission signal to the emission signal line.

[0059] According to an exemplary embodiment, the gate driving circuit GD can be disposed on the display panel PN using an in-panel gate driver (GIP) method. For example, the gate driving circuit GD can be divided into a plurality of parts and respectively disposed on at least two side surfaces of the display panel PN.

[0060] The display panel PN can include a display area and a non-display area surrounding the display area.

[0061] The display area of the display panel PN can include a plurality of pixels PX arranged in a row direction and a column direction. For example, the plurality of pixels PX can be arranged in an area where a plurality of data lines DL and a plurality of gate lines GL intersect.

[0062] One pixel PX can include a plurality of sub-pixels that emit different colors. For example, one pixel PX can be implemented using three sub-pixels for blue, red, and green. However, the pixel PX is not limited thereto, and in some cases, the pixel PX can also include sub-pixels to further implement a specific color such as white.

[0063] In the pixel PX, the area that implements blue can be referred to as a blue sub-pixel, the area that implements red can be referred to as a red sub-pixel, and the area that implements green can be referred to as a green sub-pixel.

[0064] Each of the plurality of pixels PX can include a first light-emitting element and a second light-emitting element that emit the same color.

[0065] Each of the plurality of pixels PX can include a first optical member that refracts light from the first light-emitting element in a specific direction, and a second optical member that refracts light from the second light-emitting element in a specific direction. For example, the first optical member and the second optical member can each be implemented as a lens, but the exemplary embodiments of the present disclosure are not limited thereto.

[0066] For example, the first optical member is disposed in an optical region that provides light within a first range to form a first viewing angle, and the second optical member is disposed in an optical region that provides light within a second range to form a second viewing angle. The first range may correspond to a wider range than the second range. Accordingly, the first optical member and the second optical member may limit the viewing angle of each of the plurality of pixels PX.

[0067] A detailed description of the first optical member and the second optical member will be described below with reference to Figure 6 and Figure 7 .

[0068] The non-display region may be provided along the periphery of the display region. Various components for driving the sub-pixels provided in the pixels PX may be provided in the non-display region. For example, at least a part of the gate driving circuit GD may be provided in the non-display region. The non-display region may be referred to as a border region.

[0069] When the display panel PN is used for the vehicle described with reference to Figure 1 , the viewing field of at least some regions of the display panel PN needs to be limited according to the user's needs. For example, in a case where an image is displayed in a region that provides an entertainment function, seat information, etc. for a passenger sitting in the passenger seat, in the display region of the display panel PN, the image may interfere with the driving of the vehicle by the driver, and thus it may be necessary to limit the viewing field of the image displayed in this region according to the user's needs.

[0070] Accordingly, each pixel PX included in the display panel PN may be driven in a first mode or a second mode according to a driving mode. For example, when the pixel PX is driven in the first mode, a first light-emitting element included in the pixel PX emits light based on a selection signal to provide the light from the first light-emitting element to the first range through the first optical member, thereby forming a first viewing angle, for example, a wide viewing angle. In addition, when the pixel PX is driven in the second mode, a second light-emitting element included in the pixel PX emits light based on a selection signal to provide the light from the second light-emitting element to the second range through the second optical member, thereby forming a second viewing angle, for example, a narrow viewing angle. Here, the first mode may correspond to a mode of controlling the corresponding pixel PX in a shared mode, and the second mode may correspond to a mode of driving the corresponding pixel PX in a private mode.

[0071] Meanwhile, when controlling the driving mode, it is necessary to independently control the driving mode of each region by dividing the display panel PN by region. In this case, when a selection signal for controlling the driving mode of the pixels PX set in each region is generated from a driving circuit such as a D-IC and provided to the pixels PX in the corresponding region, the selection signal lines can be set in the entire display panel PN to provide the selection signal from the driving circuit to the pixels PX in the corresponding region. Therefore, the number of divided regions may be limited. For example, as the number of divided regions increases, the number of selection signal lines set in the entire display panel PN increases, which may cause problems such as an increase in the number of lines set in the entire display panel PN and the area occupied by the lines. In addition, when the pixel circuit is changed to receive the selection signal in a matrix form within each pixel PX to reduce the number of selection signal lines, transistors may be added within the pixel PX, so the pixel layout may be complicated, making it difficult to achieve high resolution.

[0072] Therefore, the display device 100 according to an exemplary embodiment of the present disclosure may further include at least one selection signal generator for controlling the driving mode of the pixels PX in the corresponding region for each divided region. The selection signal generator may be set on the display panel PN, and one selection signal generator may be set to commonly control the driving mode of the pixels PX set in the corresponding region by region.

[0073] The selection signal generator may control the driving mode of the pixels PX. For example, the selection signal generator may generate a selection signal and provide the generated selection signal to the pixels PX. As described above, the pixels PX may be driven in the first mode or the second mode based on the selection signal.

[0074] In this way, the selection signal generator for controlling the driving mode of the pixels PX may be set on the display panel PN. For example, the selection signal generator may be set in a region of the display area of the display panel PN where no pixels PX are set, and / or may be set on a layer different from the components included in the pixels PX. Therefore, as described above, the driving mode of each region can be independently controlled by dividing the display panel PN by region without increasing the number of selection signal lines connected from the driving circuit to the pixels PX or changing the pixel circuit. Therefore, by independently controlling the driving mode of each region by dividing the display panel PN by region, the number of lines set on the display panel PN and the pixel layout can be minimized, and high resolution can be achieved.

[0075] The following will refer to Figures 3A to 3E 、 Figures 8 to 10D and Figures 12 to 17D to describe the detailed description of the selection signal generator.

[0076] Figures 3A to 3Eis a diagram showing an example of a display panel included in a Figure 2 display device.

[0077] Meanwhile, Figures 3A to 3E the first display panel PN1, the second display panel PN2, the third display panel PN3, the fourth display panel PN4, and the fifth display panel PN5 shown each represent various exemplary embodiments of the display panel PN described with reference to Figure 2 description.

[0078] Referring to Figure 3A , the first display panel PN1 may include a plurality of selection signal generators SLG and a plurality of pixels PX.

[0079] Each of the plurality of selection signal generators SLG may be provided for each pixel PX to control the driving mode of the corresponding pixel PX. For example, as Figure 3A shown, each of the plurality of selection signal generators SLG may be provided on one side of each pixel PX. For example, the selection signal generator SLG and the pixel PX may be provided on the first display panel PN1 at a ratio of 1:1.

[0080] Each of the plurality of selection signal generators SLG may provide a selection signal to a corresponding one pixel PX to control the driving mode of the corresponding pixel PX. Therefore, the driving mode can be independently controlled for each pixel PX included in the first display panel PN1. For example, the first display panel PN1 includes a plurality of regions defined in units of one pixel PX, and the driving modes of the plurality of corresponding regions can be independently controlled. That is, in the case where the first display panel PN1 includes a plurality of pixels PX, the driving mode can be independently controlled for each individual pixel PX. Meanwhile, in this case, one selection signal generator SLG and a corresponding one pixel PX can be defined as a pixel block or a pixel unit.

[0081] Referring to Figure 3B , the second display panel PN2 may include a plurality of selection signal generators SLG and a plurality of pixels PX.

[0082] Each of the plurality of selection signal generators SLG may be provided for every two pixels PX to control the driving modes of the corresponding two pixels PX. For example, as Figure 3BAs shown, each of the multiple selection signal generators SLG can be disposed on one side in the row direction of any one of the two pixels PX disposed in the row direction. For example, the selection signal generator SLG and the pixel PX can be disposed on the second display panel PN2 at a ratio of 1:2. However, the present disclosure is not limited thereto, and each of the multiple selection signal generators SLG can be disposed on one side in the column direction of any one of the two pixels PX disposed in the column direction.

[0083] Each of the multiple selection signal generators SLG can provide a selection signal to the corresponding two pixels PX to jointly control the driving modes of the corresponding two pixels PX. Therefore, the driving modes can be independently controlled for every two pixels PX included in the second display panel PN2. For example, the second display panel PN2 includes a plurality of regions defined in units of two pixels PX, and the driving modes of the plurality of corresponding regions can be independently controlled. That is, in the case where the second display panel PN2 includes a plurality of pixels PX, the driving modes can be independently controlled for every two pixels PX. At the same time, in this case, one selection signal generator SLG and the two pixels PX corresponding thereto can be defined as a pixel block or a pixel unit.

[0084] Referring to Figure 3C , the third display panel PN3 can include a plurality of selection signal generators SLG and a plurality of pixels PX.

[0085] Each of the multiple selection signal generators SLG can be disposed for every three pixels PX to control the driving modes of the corresponding three pixels PX. For example, as Figure 3C shown, each of the multiple selection signal generators SLG can be disposed on one side in the row direction of any one of the three pixels PX disposed in the row direction. For example, the selection signal generator SLG and the pixel PX can be disposed on the third display panel PN3 at a ratio of 1:3. However, the present disclosure is not limited thereto, and each of the multiple selection signal generators SLG can be disposed on one side in the column direction of any one of the three pixels PX disposed in the column direction.

[0086] Each of the plurality of selection signal generators SLG can provide a selection signal to three corresponding pixels PX to jointly control the driving modes of the three corresponding pixels PX. Therefore, the driving modes can be independently controlled for every three pixels PX included in the third display panel PN3. For example, the third display panel PN3 includes a plurality of regions defined in units of three pixels PX, and the driving modes of the plurality of corresponding regions can be independently controlled. That is, in the case where the third display panel PN3 includes a plurality of pixels PX, the driving modes can be independently controlled for every three pixels PX. At the same time, in this case, one selection signal generator SLG and the three corresponding pixels PX can be defined as a pixel block or a pixel unit.

[0087] Referring to Figure 3D , the fourth display panel PN4 can include a plurality of selection signal generators SLG and a plurality of pixels PX.

[0088] Each of the plurality of selection signal generators SLG can be set for every six pixels PX to control the driving modes of the corresponding six pixels PX. For example, as Figure 3D shown, each of the plurality of selection signal generators SLG can be set on one side in the row direction of any one of the six pixels PX arranged in the row direction. For example, the selection signal generators SLG and the pixels PX can be set on the fourth display panel PN4 at a ratio of 1:6. However, the present disclosure is not limited thereto, and each of the plurality of selection signal generators SLG can be set on one side in the column direction of any one of the six pixels PX arranged in the column direction.

[0089] Each of the plurality of selection signal generators SLG can provide a selection signal to the corresponding six pixels PX to jointly control the driving modes of the corresponding six pixels PX. Therefore, the driving modes can be independently controlled for every six pixels PX included in the fourth display panel PN4. For example, the fourth display panel PN4 includes a plurality of regions defined in units of six pixels PX, and the driving modes of the plurality of corresponding regions can be independently controlled. That is, in the case where the fourth display panel PN4 includes a plurality of pixels PX, the driving modes can be independently controlled for every six pixels PX. At the same time, in this case, one selection signal generator SLG and the six corresponding pixels PX can be defined as a pixel block or a pixel unit.

[0090] Referring to Figure 3E , the fifth display panel PN5 can include a plurality of selection signal generators SLG and a plurality of pixels PX.

[0091] Each of the plurality of selection signal generators SLG may be provided for every six pixels PX to control the driving modes of the corresponding six pixels PX. For example, as Figure 3E shown, each of the plurality of selection signal generators SLG may be provided on one side in the row direction of two pixels PX arranged in the same column among the six pixels PX, where the six pixels PX are arranged such that there are three in each of two rows. For example, the selection signal generator SLG and the pixels PX may be provided on the fifth display panel PN5 at a ratio of 1:6. However, the present disclosure is not limited thereto, and each of the plurality of selection signal generators SLG may be provided on one side in the column direction of two pixels PX arranged in the same row among the six pixels PX, where the six pixels PX are arranged such that there are three in each of two columns.

[0092] Each of the plurality of selection signal generators SLG may supply selection signals to the corresponding six pixels PX to jointly control the driving modes of the corresponding six pixels PX. Accordingly, the driving modes may be independently controlled for every six pixels PX included in the fifth display panel PN5. For example, the fifth display panel PN5 includes a plurality of regions defined in units of six pixels PX, and the driving modes of the plurality of corresponding regions may be independently controlled. That is, in the case where the fifth display panel PN5 includes a plurality of pixels PX, the driving modes may be independently controlled for every six pixels PX.

[0093] Accordingly, the setting relationship between the selection signal generator SLG and the pixels PX included in the display panel PN of the display device 100 according to an exemplary embodiment of the present disclosure may be designed in various ways. Here, as described above, the region of the display panel PN is divided for each pixel PX jointly controlled by one selection signal generator SLG, and thus the driving mode may be independently controlled for each region. Accordingly, according to the design of the display device 100, the display panel PN may be divided into various regions, and thus the corresponding regions may be independently controlled. At the same time, in this case, one selection signal generator SLG and the six pixels PX corresponding thereto may be defined as a pixel block or a pixel unit.

[0094] Figure 4 is a circuit diagram showing an example of a pixel circuit included in a Figure 2 display device.

[0095] At the same time, Figure 4 the first pixel circuit PC1 shown represents an exemplary embodiment of a pixel circuit corresponding to each of the plurality of pixels PX included in the display device 100 described with reference to Figure 2 the description.

[0096] Referring to Figure 4, at least some of the plurality of transistors included in the first pixel circuit PC1 may be n-type transistors or p-type transistors. In the case of p-type transistors, the low-level voltage of each driving signal is the voltage for turning on the TFT, and the high-level voltage of each driving signal may be the voltage for turning off the TFT.

[0097] Here, the low-level voltage may correspond to a preset voltage lower than the high-level voltage. For example, the low-level voltage may include a voltage falling within the range of -8V to -12V. The high-level voltage may correspond to a preset voltage higher than the low-level voltage. For example, the high-level voltage may include a voltage falling within the range of 12V to 16V. According to an exemplary embodiment, the low-level voltage may be referred to as the first voltage, and the high-level voltage may be referred to as the second voltage. In this case, the first voltage may be lower than the second voltage.

[0098] The first pixel circuit PC1 may include a driving transistor DT, a plurality of switching transistors ST1 to ST6, a plurality of selection transistors TP1 and TP2, a storage capacitor Cst, and a plurality of light-emitting elements ED1 and ED2.

[0099] The driving transistor DT may control the driving current applied to the plurality of light-emitting elements ED1 and ED2 according to the source-gate voltage. The driving transistor DT may include a source electrode connected to a high-potential power line to which a high-potential power voltage VDD is supplied, a gate electrode connected to a second node N2, and a drain electrode connected to a third node N3.

[0100] The first switching transistor ST1 may apply the data voltage Vdata from the data line DL to the first node N1. The first switching transistor ST1 may include a source electrode connected to the data line DL, a drain electrode connected to the first node N1, and a gate electrode connected to a first scan signal line to which a first scan signal SCAN1 is applied. The first switching transistor ST1 may be turned on or off by the first scan signal SCAN1. Therefore, the first switching transistor ST1 may apply the data voltage Vdata from the data line DL to the first node N1 in response to the first scan signal SCAN1 having a low level as the conductive level.

[0101] The second switching transistor ST2 can diode-connect the gate electrode and the drain electrode of the driving transistor DT. The second switching transistor ST2 can include a drain electrode connected to the second node N2, a source electrode connected to the third node N3, and a gate electrode connected to the second scan signal line to which the second scan signal SCAN2 is applied. The second switching transistor ST2 can be turned on or off by the second scan signal SCAN2. Therefore, the second switching transistor ST2 can diode-connect the gate electrode and the drain electrode of the driving transistor DT in response to the second scan signal SCAN2 having a low level as the conductive level.

[0102] The third switching transistor ST3 can apply a reference voltage Vref to the first node N1. The third switching transistor ST3 can include a source electrode connected to the reference voltage line configured to provide the reference voltage Vref, a drain electrode connected to the first node N1, and a gate electrode connected to the emission signal line to which the emission signal EM is applied. The third switching transistor ST3 can be turned on or off by the emission signal EM. Therefore, the third switching transistor ST3 can send the reference voltage Vref to the first node N1 in response to the emission signal EM having a low level as the conductive level.

[0103] The fourth switching transistor ST4 can apply a reference voltage Vref to the anode electrode of the first light-emitting element ED1. The fourth switching transistor ST4 can include a source electrode connected to the reference voltage line configured to provide the reference voltage Vref, a drain electrode connected to the anode electrode of the first light-emitting element ED1, and a gate electrode connected to the second scan signal line to which the second scan signal SCAN2 is applied. The fourth switching transistor ST4 can be turned on or off by the second scan signal SCAN2. Therefore, the fourth switching transistor ST4 can apply the reference voltage Vref to the anode electrode of the first light-emitting element ED1 in response to the second scan signal SCAN2 having a low level as the conductive level.

[0104] The fifth switching transistor ST5 can apply a reference voltage Vref to the anode electrode of the second light-emitting element ED2. The fifth switching transistor ST5 can include a source electrode connected to the reference voltage line configured to provide the reference voltage Vref, a drain electrode connected to the anode electrode of the second light-emitting element ED2, and a gate electrode connected to the second scan signal line to which the second scan signal SCAN2 is applied. The fifth switching transistor ST5 can be turned on or off by the second scan signal SCAN2. Therefore, the fifth switching transistor ST5 can apply the reference voltage Vref to the anode electrode of the second light-emitting element ED2 in response to the second scan signal SCAN2 having a low level as the conductive level.

[0105] The sixth switching transistor ST6 can form a current path between the driving transistor DT and any one of the plurality of light-emitting elements ED1 and ED2. The sixth switching transistor ST6 can include a source electrode connected to the third node N3, a drain electrode connected to the fourth node N4, and a gate electrode connected to an emission signal line to which an emission signal EM is applied. The sixth switching transistor ST6 can be turned on or off by the emission signal EM. Accordingly, the sixth switching transistor ST6 can electrically connect the third node N3 and the fourth node N4 in response to the emission signal EM having a low level as a conduction level, so as to form a current path between the driving transistor DT and any one of the plurality of light-emitting elements ED1 and ED2.

[0106] The storage capacitor Cst can include a first electrode connected to the first node N1 and a second electrode connected to the second node N2. One electrode of the storage capacitor Cst can be connected to the gate electrode of the driving transistor DT, and the other electrode of the storage capacitor Cst can be connected to the first switching transistor ST1. When any one of the plurality of light-emitting elements ED1 and ED2 emits light, the storage capacitor Cst can store a specific voltage and keep the voltage of the gate electrode of the driving transistor DT constant.

[0107] The plurality of selection transistors TP1 and TP2 can include: a first selection transistor TP1 configured to form a current path for a first driving current flowing through the first light-emitting element ED1; and a second selection transistor TP2 configured to form a current path for a second driving current flowing through the second light-emitting element ED2.

[0108] The first selection transistor TP1 can be connected between the fourth node N4 and the first light-emitting element ED1, and the gate electrode of the first selection transistor TP1 can be connected to a first selection signal line that provides a first selection signal Ss. When the pixel PX of the first pixel circuit PC1 is driven in a first mode which is a shared mode, the first selection signal Ss is provided to the gate electrode of the first selection transistor TP1, so that the first selection transistor TP1 can be turned on. Accordingly, a current path for the first driving current flowing through the first light-emitting element ED1 can be formed, so that the first light-emitting element ED1 can emit light. At the same time, the first selection transistor TP1 can also be referred to as a first emission control transistor that controls the emission of the first light-emitting element ED1.

[0109] The second selection transistor TP2 can be connected between the fourth node N4 and the second light-emitting element ED2, and the gate electrode of the second selection transistor TP2 can be connected to a second selection signal line that provides a second selection signal Ps. When the pixel PX of the first pixel circuit PC1 is driven in the second mode, which is a private mode, the second selection signal Ps is provided to the gate electrode of the second selection transistor TP2, so that the second selection transistor TP2 can be turned on. Therefore, a current path for the second drive current flowing through the second light-emitting element ED2 can be formed, and thus the second light-emitting element ED2 can emit light. At the same time, the second selection transistor TP2 can also be referred to as a second emission control transistor that controls the emission of the second light-emitting element ED2.

[0110] The first light-emitting element ED1 can be connected between a first selection transistor TP1 that is turned on or off by a first selection signal Ss and a low-potential power line that provides a low-potential power voltage VSS. The second light-emitting element ED2 can be connected between a second selection transistor TP2 that is turned on or off by a second selection signal Ps and a low-potential power line that provides a low-potential power voltage VSS.

[0111] In this case, through the first selection transistor TP1 or the second selection transistor TP2 that is turned on according to the drive mode, the first light-emitting element ED1 or the second light-emitting element ED2 can be connected to other components (e.g., a drive transistor DT) of the first pixel circuit PC1. For example, the first light-emitting element ED1 can be connected to the drive transistor DT via the first selection transistor TP1 that is turned on in the first mode, and can provide light at a wide viewing angle as a first viewing angle in the first mode (i.e., a shared mode) through a first drive current. In addition, the second light-emitting element ED2 can be connected to the drive transistor DT via the second selection transistor TP2 that is turned on in the second mode, and can provide light at a narrow viewing angle as a second viewing angle in the second mode (i.e., a private mode) through a second drive current. Here, the drive mode can be specified by a user input or determined when a pre-specified condition is satisfied.

[0112] Figure 5A and Figure 5B are waveform diagrams for describing Figure 4 the pixel circuit.

[0113] At the same time, Figure 5A shows a waveform diagram for describing an example when driving the pixel PX applied to the first pixel circuit PC1 in the first mode, while Figure 5B shows a waveform diagram for describing an example when driving the pixel PX applied to the first pixel circuit PC1 in the second mode.

[0114] Refer to Figures 4 to 5B, in the first mode, only the first light-emitting element ED1 can emit light, while in the second mode, only the second light-emitting element ED2 can emit light. Here, as Figure 5A shown, the second selection signal Ps for controlling the emission of the second light-emitting element ED2 so that only the first light-emitting element ED1 emits light in the first mode can be output only at a high level that serves as an off level. Additionally, as Figure 5B shown, the first selection signal Ss for controlling the emission of the first light-emitting element ED1 so that only the second light-emitting element ED2 emits light in the second mode can be output only at a high level (or the first level) that serves as an off level.

[0115] Specifically, looking at the first mode which is a shared mode, referring to Figure 4 and Figure 5A , during the initialization period P1, a low-level second scan signal SCAN2, a low-level first selection signal Ss, and a low-level emission signal EM can be output. The second switching transistor ST2, the fourth switching transistor ST4, and the fifth switching transistor ST5 can be turned on by the low-level second scan signal SCAN2, the first selection transistor TP1 can be turned on by the low-level first selection signal Ss, and the third switching transistor ST3 and the sixth switching transistor ST6 can be turned on by the low-level emission signal EM.

[0116] The first node N1 can be initialized to the reference voltage Vref through the turned-on third switching transistor ST3. The voltage of the anode electrode of the first light-emitting element ED1 passing through the turned-on fourth switching transistor ST4 can be initialized to the reference voltage Vref, and the voltage of the anode electrode of the second light-emitting element ED2 passing through the turned-on fifth switching transistor ST5 can be initialized to the reference voltage Vref. The driving transistor DT is diode-connected through the turned-on second switching transistor ST2, and the gate electrode and the drain electrode of the driving transistor DT are short-circuited, so the driving transistor DT can operate like a diode. The reference voltage Vref sent to the anode electrode of the first light-emitting element ED1 through the turned-on fourth switching transistor ST4 is sent to the third node N3 and the second node N2 through the turned-on first selection transistor TP1 and the turned-on sixth switching transistor ST6, so the third node N3 and the second node N2 can also be initialized to the reference voltage Vref.

[0117] Next, during the sampling period P2, a first scan signal SCAN1 at a low level and a second scan signal SCAN2 at a low level can be output, and a first selection signal Ss at a high level can be output. A transmission signal EM at a high level is output, and thus the third switching transistor ST3 is turned off. At the same time, the first switching transistor ST1 is turned on by the first scan signal SCAN1 at a low level (or a second level, where the second level has a value lower than the first level), so that the data voltage Vdata can be sent to the first node N1. The driving transistor DT can be diode-connected through the turned-on second switching transistor ST2, and the difference voltage between the high-potential power supply voltage VDD and the threshold voltage can be sampled and provided to the second node N2.

[0118] At the same time, during the sampling period P2, the sixth switching transistor ST6 can be turned off by the transmission signal EM at a high level, and the first selection transistor TP1 can be turned off by the first selection signal Ss at a high level.

[0119] During the holding period P3, the first scan signal SCAN1 and the second scan signal SCAN2 can be output at a high level, and the first switching transistor ST1, the second switching transistor ST2, the fourth switching transistor ST4, and the fifth switching transistor ST5 can all be turned off. However, even if the first switching transistor ST1 is turned off, the data voltage Vdata input in the previous sampling period (e.g., the sampling period P2) can be maintained by the storage capacitor Cst.

[0120] Finally, during the transmission period P4, a first selection signal Ss at a low level and a transmission signal EM at a low level can be output, and a second selection signal Ps at a high level can be output. The reference voltage Vref is applied to the first node N1 through the third switching transistor ST3 turned on by the transmission signal EM at a low level, and the voltage of the first node N1 can be the difference voltage between the reference voltage Vref and the data voltage Vdata. This voltage change can also be reflected in the second node N2. The gate-source voltage of the driving transistor DT can be set to a value Vdata–Vref+Vth obtained by subtracting the reference voltage Vref from the data voltage Vdata and adding the threshold voltage Vth of the driving transistor DT to control the first driving current.

[0121] The first driving current is supplied from the driving transistor DT to the first light-emitting element ED1 through the sixth switching transistor ST6 turned on by the emission signal EM at a low level and the first selection transistor TP1 turned on by the first selection signal Ss at a low level. Thus, the first light-emitting element ED1 can emit light. However, the second selection signal Ps is output at a high level, so the second selection transistor TP2 is turned off, and thus the second driving current is not sent from the driving transistor DT to the second light-emitting element ED2. Therefore, when driving the first pixel circuit PC1 in the first mode, the first driving current is only applied to the first light-emitting element ED1, and thus only the first light-emitting element ED1 can emit light.

[0122] Next, looking at the second mode which is a private mode, refer to Figure 4 and Figure 5B , except that the first selection signal Ss and the second selection signal Ps are output contrary to the first mode which is a shared mode, the first pixel circuit PC1 can be driven in the second mode in substantially the same manner as the first mode. That is, during the emission period P4 when the second light-emitting element ED2 emits light, the first selection signal Ss can be output only at a high level which is the turn-off level, and the second selection signal Ps can be output at a low level which is the turn-on level.

[0123] Specifically, during the initialization period P1, the first scan signal SCAN1 can be output at a high level, and the second scan signal SCAN2 can be output at a low level. In addition, the first selection signal Ss can be output at a high level, and the second selection signal Ps and the emission signal EM can be output at a low level. Thus, the second switching transistor ST2, the fourth switching transistor ST4, and the fifth switching transistor ST5 can be turned on by the second scan signal SCAN2, the second selection transistor TP2 can be turned on by the second selection signal Ps, and the third switching transistor ST3 and the sixth switching transistor ST6 can be turned on by the emission signal EM.

[0124] The first node N1 can be initialized to the reference voltage Vref by a third switching transistor ST3 turned on by the emission signal EM, and the anode electrodes of the first light-emitting element ED1 and the second light-emitting element ED2 can be initialized to the reference voltage Vref by each of a fourth switching transistor ST4 and a fifth switching transistor ST5 turned on by the second scan signal SCAN2. The driving transistor DT can be diode-connected through the turned-on second switching transistor ST2 and operates like a diode. Finally, the reference voltage Vref sent to the anode electrode of the second light-emitting element ED2 through the turned-on fifth switching transistor ST5 can be sent to the third node N3 and the second node N2 through the turned-on second selection transistor TP2 and the turned-on sixth switching transistor ST6, so that the third node N3 and the second node N2 can be initialized to the reference voltage Vref.

[0125] Next, during the sampling period P2, the first scan signal SCAN1 at a low level and the second scan signal SCAN2 at a low level can be output, and the second selection signal Ps and the emission signal EM can be output from a low level to a high level. The emission signal EM at a high level is output, so that the third switching transistor ST3 can be turned off, and the first switching transistor ST1 is turned on by the first scan signal SCAN1 at a low level, so that the data voltage Vdata can be sent to the first node N1. The driving transistor DT can be diode-connected through the turned-on second switching transistor ST2, and the differential voltage between the high-potential power supply voltage VDD and the threshold voltage can be sampled and provided to the second node N2.

[0126] Meanwhile, during the sampling period P2, the sixth switching transistor ST6 can be turned off by the emission signal EM at a high level, and the second selection transistor TP2 can be turned off by the second selection signal Ps at a high level.

[0127] Finally, during the emission period P4, the second selection signal Ps at a low level and the emission signal EM at a low level can be output, and the first selection signal Ss at a high level can be output. The reference voltage Vref is applied to the first node N1 through the third switching transistor ST3 turned on by the emission signal EM at a low level, and the voltage of the first node N1 can be the differential voltage between the reference voltage Vref and the data voltage Vdata. This voltage change can also be reflected in the second node N2. The gate-source voltage of the driving transistor DT can be set to a value Vdata–Vref+Vth obtained by subtracting the reference voltage Vref from the data voltage Vdata and adding the threshold voltage Vth of the driving transistor DT to control the second driving current.

[0128] The second driving current is supplied from the driving transistor DT to the second light-emitting element ED2 through the sixth switching transistor ST6 turned on by the emission signal EM at a low level and the second selection transistor TP2 turned on by the second selection signal Ps at a low level. Therefore, the second light-emitting element ED2 can emit light. However, the first selection signal Ss is output at a high level, so the first selection transistor TP1 is turned off, and thus the first driving current is not sent from the driving transistor DT to the first light-emitting element ED1. Therefore, when driving the first pixel circuit PC1 in the second mode, the second driving current is only applied to the second light-emitting element ED2, and thus only the second light-emitting element ED2 can emit light.

[0129] Figure 6 and Figure 7 is a cross-sectional view of a part of a display device according to an exemplary embodiment of the present disclosure.

[0130] Figure 6 shows a pixel provided with the first optical member 161, Figure 7 shows a pixel provided with the second optical member 162.

[0131] Referring to Figure 6 and Figure 7 , a display device 100 according to an exemplary embodiment of the present disclosure includes a substrate 110, a buffer film 111, a gate insulating film 112, an interlayer insulating film 113, a lower protective film 114, an outer coating 115, a bank insulating film 116, a first selection transistor TP1, a second selection transistor TP2, a first light-emitting element ED1, a second light-emitting element ED2, a first optical member 161, a second optical member 162, an optical member protective film 170, and a packaging member 180.

[0132] The substrate 110 may include an insulating material. The substrate 110 may include a transparent material. For example, the substrate 110 may include glass or plastic.

[0133] The buffer film 111 may be disposed on the substrate 110. The buffer film 111 may include an insulating material. For example, the buffer film 111 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The buffer film 111 may have a multilayer structure. For example, the buffer film 111 may have a stacked structure of a film formed of silicon nitride (SiNx) and a film formed of silicon oxide (SiOx).

[0134] The buffer film 111 may be located between the substrate 110 and the driving portion of each pixel PX. The buffer film 111 may prevent contamination of the substrate 110 during the process of forming the driving portion. For example, the top surface of the substrate 110 facing the driving portion of each pixel PX may be covered with the buffer film 111. The driving portion of each pixel PX may be located on the buffer film 111.

[0135] The gate insulating film 112 may be disposed on the buffer film 111. The gate insulating film 112 may include an insulating material. For example, the gate insulating film 112 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The gate insulating film 112 may include a material having a high dielectric constant. For example, the gate insulating film 112 may include a high-K material such as hafnium oxide (HfO). The gate insulating film 112 may have a multilayer structure.

[0136] The gate insulating film 112 may extend between the semiconductor layers 121 and 221 of the select transistors TP1 and TP2 and the gate electrodes 122 and 223. For example, the gate electrodes of the driving transistor and the switching transistor may be insulated from the semiconductor layers of the driving transistor and the switching transistor through the gate insulating film 112. The gate insulating film 112 may cover the semiconductor layer of each pixel PX. The gate electrodes of the driving transistor and the switching transistor may be located on the gate insulating film 112.

[0137] The interlayer insulating film 113 may be disposed on the gate insulating film 112. The interlayer insulating film 113 may include the gate insulating film 112. For example, the interlayer insulating film 113 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The interlayer insulating film 113 may extend between the gate electrode and the source electrode and between the gate electrode and the drain electrode of each of the driving transistor DT and the switching transistor. For example, the source electrode and the drain electrode of each of the driving transistor and the switching transistor may be insulated from the gate electrode through the interlayer insulating film 113. The interlayer insulating film 113 may cover the gate electrode of each of the driving transistor and the switching transistor. The source electrode and the drain electrode of each pixel PX may be located on the interlayer insulating film 113. The gate insulating film 112 and the interlayer insulating film 113 may expose the source region and the drain region of each semiconductor pattern located within each pixel PX.

[0138] The lower protective film 114 may be disposed on the interlayer insulating film 113. The lower protective film 114 may include an insulating material. For example, the lower protective film 114 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The lower protective film 114 may prevent the driving part from being damaged due to external moisture and impact. The lower protective film 114 may extend along the surface of the driving transistor and the switching transistor facing the substrate 110. The lower protective film 114 may contact the interlayer insulating film 113 outside the driving part within each pixel PX.

[0139] The outer coating 115 may be disposed on the lower protective film 114. The outer coating 115 may include an insulating material. The outer coating 115 may include a material different from that of the lower protective film 114. For example, the outer coating 115 may include an organic insulating material. The outer coating 115 may remove the steps caused by the driving portions of each pixel PX. For example, the top surface of the outer coating 115 facing the device substrate 110 may be a flat surface.

[0140] The first selection transistor TP1 and the second selection transistor TP2 may be disposed on the substrate 110. The first selection transistor TP1 may be electrically connected between the drain electrode of the driving transistor DT and the first lower electrode 141 of the first light-emitting element ED1. The second selection transistor TP2 may be electrically connected between the drain electrode of the driving transistor DT and the second lower electrode 151 of the second light-emitting element ED2.

[0141] The first selection transistor TP1 may include a first semiconductor layer 121, a first gate electrode 122, a first source electrode 123, and a first drain electrode 124. The first selection transistor TP1 may have the same structure as the switching transistor and the driving transistor. For example, the first semiconductor layer 121 may be located between the buffer film 111 and the gate insulating film 112, and the first gate electrode 122 may be located between the gate insulating film 112 and the interlayer insulating film 113. The first source electrode 123 and the first drain electrode 124 may be located between the interlayer insulating film 113 and the lower protective film 114. The first gate electrode 122 may overlap the channel region of the first semiconductor layer 121. The first source electrode 123 may be electrically connected to the source region of the first semiconductor layer 121. The first drain electrode 124 may be electrically connected to the drain region of the first semiconductor layer 121.

[0142] The second selection transistor TP2 may include a second semiconductor layer 221, a second gate electrode 223, a second source electrode 225, and a second drain electrode 227. For example, the second semiconductor layer 221 may be on the same layer as the first semiconductor layer 121, the second gate electrode 223 may be on the same layer as the first gate electrode 122, and the second source electrode 225 and the second drain electrode 227 may be on the same layer as the first source electrode 123 and the first drain electrode 124.

[0143] The first light-emitting element ED1 and the second light-emitting element ED2 of each pixel PX may be disposed on the outer coating 115 corresponding to the pixel PX.

[0144] The first light-emitting element ED1 may emit light representing a specific color. For example, the first light-emitting element ED1 may include a first lower electrode 141, a first light-emitting layer 142, and a first upper electrode 143 sequentially stacked on the substrate 110.

[0145] The first lower electrode 141 may include a conductive material. The first lower electrode 141 may include a material having a high reflectivity. For example, the first lower electrode 141 may include a metal such as aluminum (Al) and silver (Ag). The first lower electrode 141 may have a multilayer structure. For example, the first lower electrode 141 may have the following structure: a reflective electrode formed of a metal is located between a transparent electrode formed of a transparent conductive material such as ITO and IZO. The first lower electrode 141 may be electrically connected to the first drain electrode 124 of the first select transistor TP1 through a contact hole penetrating the lower protective film 114 and the outer coating 115.

[0146] The first light-emitting layer 142 may generate light having a luminance corresponding to the voltage difference between the first lower electrode 141 and the first upper electrode 143. For example, the first light-emitting layer 142 may include an emission material layer (EML) containing an emission material. The emission material may include an organic material, an inorganic material, or a hybrid material.

[0147] The first light-emitting layer 142 may have a multilayer structure. For example, the first light-emitting layer 142 may further include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0148] The first upper electrode 143 may include a conductive material. The first upper electrode 143 may include a material different from that of the first lower electrode 141. The transmittance of the first upper electrode 143 may be higher than that of the first lower electrode 141. For example, the first upper electrode 143 may be a transparent electrode formed of a transparent conductive material such as ITO and IZO. Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, the light generated by the first light-emitting layer 142 may be emitted through the first upper electrode 143.

[0149] The second light-emitting element ED2 may implement the same color as the first light-emitting element ED1. The second light-emitting element ED2 may have the same structure as the first light-emitting element ED1. For example, the second light-emitting element ED2 may include a second lower electrode 151, a second light-emitting layer 152, and a second upper electrode 153 sequentially stacked on the substrate 110.

[0150] The second lower electrode 151 may correspond to the first lower electrode 141, the second light-emitting layer 152 may correspond to the first light-emitting layer 142, and the second upper electrode 153 may correspond to the first upper electrode 143. For example, the second lower electrode 151 may be formed for the second light-emitting element ED2 to have the same structure as the first lower electrode 141, and the same applies to the second light-emitting layer 152 and the second upper electrode 153. For example, the first light-emitting element ED1 and the second light-emitting element ED2 may be formed to have the same structure. However, the present disclosure is not limited thereto, and in some cases, at least some components of the first light-emitting element ED1 and the second light-emitting element ED2 may be formed differently.

[0151] The second light-emitting layer 152 may be spaced apart from the first light-emitting layer 142. Accordingly, in the display device according to an exemplary embodiment of the present disclosure, emission due to leakage current may be prevented.

[0152] According to an exemplary embodiment of the present disclosure, in a display device, light may be generated from only one of the first light-emitting layer 142 and the second light-emitting layer 152 according to a user selection or a pre-specified condition.

[0153] The second lower electrode 151 of each pixel PX may be spaced apart from the first lower electrode 141 of the corresponding pixel PX. For example, the bank insulating film 116 may be disposed between the first lower electrode 141 and the second lower electrode 151 of each pixel PX. The bank insulating film 116 may include an insulating material. For example, the bank insulating film 116 may include an organic insulating material. The bank insulating film 116 may include a material different from that of the outer coating 115.

[0154] The second lower electrode 151 of each pixel PX may be insulated from the first lower electrode 141 of the corresponding pixel PX through the bank insulating film 116. For example, the bank insulating film 116 may cover the edges of the first lower electrode 141 and the second lower electrode 151 located within each pixel PX. Accordingly, in the display device 100, an image from the first optical region where the first light-emitting element ED1 of each pixel PX is located or an image from the second optical region where the second light-emitting element ED2 of each pixel PX is located may be provided to the user.

[0155] The first light-emitting layer 142 and the first upper electrode 143 of the first light-emitting element ED1 located within each pixel PX may be stacked on a partial region of the corresponding first lower electrode 141 exposed by the bank insulating film 116. The second light-emitting layer 152 and the second upper electrode 153 of the second light-emitting element ED2 located within each pixel PX may be stacked on a partial region of the corresponding second lower electrode 151 exposed by the bank insulating film 116. For example, the bank insulating film 116 may distinguish a first emission region that emits light from the first light-emitting element ED1 and a second emission region that emits light from the second light-emitting element ED2 within each pixel PX. The size of the second emission region divided within each pixel PX may be smaller than the size of the first emission region.

[0156] The second upper electrode 153 of each pixel PX may be electrically connected to the first upper electrode 143 of the corresponding pixel PX. For example, the voltage applied to the second upper electrode 153 of the second light-emitting element ED2 within each pixel PX may be the same as the voltage applied to the first upper electrode 143 of the first light-emitting element ED1 within the corresponding pixel PX. The second upper electrode 153 of each pixel PX may include the same material as the first upper electrode 143 of the corresponding pixel PX. For example, the second upper electrode 153 of each pixel PX may be formed simultaneously with the first upper electrode 143 of the corresponding pixel PX. The second upper electrode 153 of each pixel PX may extend onto the bank insulating film 116 and directly contact the first upper electrode 143 of the corresponding pixel PX. The brightness of the first optical region and the brightness of the second optical region within each pixel PX may be controlled by the driving current generated in the corresponding pixel PX

[0157] The encapsulation member 180 may be located on the first light-emitting element ED1 and the second light-emitting element ED2 of each pixel PX. The encapsulation member 180 may prevent the light-emitting elements ED1 and ED2 from being damaged due to external moisture and impact. The encapsulation member 180 may have a multi-layer structure. For example, the encapsulation member 180 may include a first encapsulation layer 181, a second encapsulation layer 182, and a third encapsulation layer 183 stacked in sequence, but is not limited thereto. The first encapsulation layer 181, the second encapsulation layer 182, and the third encapsulation layer 183 may include insulating materials. The second encapsulation layer 182 may include a material different from that of the first encapsulation layer 181 and the third encapsulation layer 183. For example, the first encapsulation layer 181 and the third encapsulation layer 183 are inorganic encapsulation layers including inorganic insulating materials, while the second encapsulation layer 182 may include an organic encapsulation layer containing an organic insulating material. Accordingly, the light-emitting elements ED1 and ED2 of the display device 100 can be more effectively prevented from being damaged due to external moisture and impact.

[0158] The first optical member 161 and the second optical member 162 may be disposed on the encapsulation member 180.

[0159] The first optical member 161 may be disposed on the first light-emitting element ED1. The light generated by the first light-emitting element ED1 of each pixel PX may be emitted through the first optical member 161 disposed in the first optical region of the corresponding pixel PX. The first optical member 161 may have a shape in which light is not restricted in at least one direction. For example, the planar shape of the first optical member 161 located within each pixel PX may have a strip shape extending in one direction.

[0160] In this case, the traveling direction of the light emitted from the first optical region of each pixel PX may not be limited to one direction. For example, the content (or image) provided through the first optical region of each pixel PX may be shared with a person adjacent to the user in one direction around the user. Therefore, the content provided by the light emitted through the first optical member 161 will be provided within a first viewing angle range that is wider than the viewing angle of the content provided by the light emitted through the second optical member 162. For example, the content provided by the light emitted through the first optical member 161 may be provided in a sharing mode.

[0161] The second optical member 162 may be disposed on the second light-emitting element ED2. The light generated by the second light-emitting element ED2 of each pixel PX may be emitted through the second optical member 162 disposed in the second optical region of the corresponding pixel PX. The second optical member 162 may limit the traveling direction of the transmitted light to one direction and / or another direction. For example, the planar shape of the optical member 162 located within each pixel PX may have a circular shape.

[0162] In this case, the traveling direction of the light emitted from the second optical region of each pixel PX may be limited to one direction and / or another direction. For example, the content (or image) provided through the second optical region of each pixel PX may not be shared with the people around the user. Therefore, the content provided by the light emitted through the second optical member 162 may be provided within a second viewing angle range that is narrower than the viewing angle of the content provided by the light emitted through the first optical member 161. For example, the content provided by the light emitted through the second optical member 162 may be provided in a private mode.

[0163] The first emission region of each pixel PX may have a shape corresponding to the first optical member 161 of the corresponding pixel PX. For example, the planar shape of the first emission region of each pixel PX may have a strip shape extending in one direction. The first optical member 161 may have a size larger than the first emission region of the corresponding pixel PX. Therefore, the efficiency of the light emitted from the first emission region of the pixel PX can be improved.

[0164] The second emission region of each pixel PX may have a shape corresponding to the second optical member 162 of the corresponding pixel PX. For example, the planar shape of the second light-emitting region of each pixel PX may have a circular shape. The second optical member 162 may have a size larger than that of the second emission region of the corresponding pixel PX. Therefore, the efficiency of the light emitted from the second emission region of the pixel PX can be improved.

[0165] The optical member protective film 170 may be located on the first optical member 161 and the second optical member 162 of the pixel PX. The optical member protective film 170 may include an insulating material. For example, the optical member protective film 170 may include an organic insulating material. The refractive index of the optical member protective film 170 may be smaller than the refractive indices of the first optical member 161 and the second optical member 162 within each pixel PX. Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, the light passing through the first optical member 161 and the second optical member 162 of each pixel PX may not be reflected toward the substrate 110 due to the difference in the refractive index of the optical member protective film 170.

[0166] Figure 8 is a circuit diagram showing an example of a selection signal generation circuit included in Figure 2 the display device.

[0167] Meanwhile, Figure 8 the first selection signal generation circuit SLC1 shown represents an exemplary embodiment of a selection signal generation circuit corresponding to each of the plurality of selection signal generators SLG included in the display device 100 described with reference to Figures 2 to 3E The selection signal generator SLG including the first selection signal generation circuit SLC1 may provide a selection signal to the pixel PX including the first pixel circuit PC1 described with reference to Figure 4 FIG.

[0168] Referring to Figure 8 FIG., the plurality of transistors included in the first selection signal generation circuit SLC1 may be n-type transistors or p-type transistors. In the case of p-type transistors, the low-level voltage of each control signal is the voltage for turning on the TFT, and the high-level voltage of each control signal may be the voltage for turning off the TFT. Hereinafter, for ease of description, it will be described based on the plurality of transistors T1 to T8 included in the first selection signal generation circuit SLC1 being p-type transistors. However, at least some of the plurality of transistors T1 to T8 included in the first selection signal generation circuit SLC1 may be modified and implemented as n-type transistors.

[0169] The first electrode or the second electrode of the transistor to be described below may refer to the source electrode or the drain electrode. However, the terms "first electrode and second electrode" are merely terms for distinguishing each electrode and do not limit the meaning corresponding to each electrode. In addition, the first electrode of each electrode may not refer to the same electrode.

[0170] The first selection signal generation circuit SLC1 may include a first selection signal output unit SGL1 that generates a first selection signal Ss based on the first control signal to the fourth control signal S_V, S_H, P_V, and P_H, the first power supply voltage VGH, and the second power supply voltage VGL, and a second selection signal output unit SLG2 that generates a second selection signal Ps based on the first control signal to the fourth control signal S_V, S_H, P_V, and P_H, the first power supply voltage VGH, and the second power supply voltage VGL.

[0171] The first power supply voltage VGH and the second power supply voltage VGL are driving voltages for driving the first selection signal generation circuit SLC1, and the voltage level of the second power supply voltage VGL may be lower than the voltage level of the first power supply voltage VGH. For example, the first power supply voltage VGH may be a positive voltage, and the second power supply voltage VGL may be a negative voltage.

[0172] The first selection signal output unit SGL1 may control the voltage of the first output node NC1 to the high-level first power supply voltage VGH or the low-level second power supply voltage VGL, and thus may be configured to output a high-level or low-level first selection signal Ss through the first output node NC1, that is, a first selection signal Ss of an off level or an on level. To this end, the first selection signal output unit SGL1 may include a first transistor T1 to a fourth transistor T4.

[0173] The first transistor T1 may be connected between the second power supply voltage line configured to provide the second power supply voltage VGL and the first output node NC1. For example, the first electrode of the first transistor T1 may be connected to the second power supply voltage line, and the second electrode of the first transistor T1 may be connected to the first output node NC1. The gate electrode of the first transistor T1 may be connected to the first control signal line providing the first control signal S_V. When the first control signal S_V of an on level (e.g., low level) is provided, the first transistor T1 may be turned on to electrically connect the first output node NC1 and the second power supply voltage line. In this case, the second power supply voltage VGL is provided to the first output node NC1, and thus the first selection signal output unit SGL1 may output a low-level first selection signal Ss.

[0174] The second transistor T2 may be connected between a second power voltage line configured to provide a second power voltage VGL and a first output node NC1. For example, a first electrode of the second transistor T2 may be connected to the second power voltage line, and a second electrode of the second transistor T2 may be connected to the first output node NC1. A gate electrode of the second transistor T2 may be connected to a second control signal line providing a second control signal S_H. When the second control signal S_H at a conductive level (e.g., a low level) is provided, the second transistor T2 may be turned on to electrically connect the first output node NC1 and the second power voltage line. In this case, the second power voltage VGL is provided to the first output node NC1, and thus the first selection signal output unit SGL1 may output a first selection signal Ss at a low level.

[0175] The third transistor T3 may be connected between a first power voltage line configured to provide a first power voltage VGH and a first output node NC1. For example, a first electrode of the third transistor T3 may be connected to the fourth transistor T4, and a second electrode of the third transistor T3 may be connected to the first output node NC1. A gate electrode of the third transistor T3 may be connected to a third control signal line providing a third control signal P_V. When the third control signal P_V at a conductive level (e.g., a low level) is provided, the third transistor T3 may be turned on to electrically connect the first output node NC1 and the fourth transistor T4.

[0176] The fourth transistor T4 may be connected between the third transistor T3 and the first power voltage line configured to provide the first power voltage VGH. For example, a first electrode of the fourth transistor T4 may be connected to the first power voltage line, and a second electrode of the fourth transistor T4 may be connected to the first electrode of the third transistor T3. A gate electrode of the fourth transistor T4 may be connected to a fourth control signal line providing a fourth control signal P_H. When the fourth control signal P_H at a conductive level (e.g., a low level) is provided, the fourth transistor T4 may be turned on to electrically connect the third transistor T3 and the first power voltage line.

[0177] The first transistor T1 and the second transistor T2 may be connected in parallel between a second power voltage line configured to provide a second power voltage VGL and a first output node NC1. Accordingly, when at least one of the first transistor T1 and the second transistor T2 is turned on, the first output node NC1 and the second power voltage line configured to provide the second power voltage VGL may be electrically connected, and thus the first selection signal Ss at a low level may be output through the first output node NC1.

[0178] In addition, the third transistor T3 and the fourth transistor T4 can be serially connected between the first power voltage line configured to provide the first power voltage VGH and the first output node NC1. Therefore, when both the third transistor T3 and the fourth transistor T4 are turned on, the first output node NC1 and the first power voltage line configured to provide the first power voltage VGH can be electrically connected, and thus the high-level first selection signal Ss can be output through the first output node NC1.

[0179] In this way, the first transistor T1 and the second transistor T2 can be used as the pull-up unit of the first selection signal output unit SGL1, while the third transistor T3 and the fourth transistor T4 can be used as the pull-down unit of the first selection signal output unit SGL1. For example, the first transistor T1 and the second transistor T2 can be defined as the first pull-up unit, while the third transistor T3 and the fourth transistor T4 can be defined as the first pull-down unit.

[0180] The second selection signal output unit SGL2 can control the voltage of the second output node NC2 to the high-level first power voltage VGH or the low-level second power voltage VGL, and thus is configured to output the high-level or low-level second selection signal Ps through the second output node NC2, that is, the second selection signal Ps of the turn-off level or the turn-on level. To this end, the second selection signal output unit SGL2 can include the fifth transistor T5 to the eighth transistor T8.

[0181] The fifth transistor T5 can be connected between the second power voltage line configured to provide the second power voltage VGL and the second output node NC2. For example, the first electrode of the fifth transistor T5 can be connected to the second power voltage line, and the second electrode of the fifth transistor T5 can be connected to the sixth transistor T6. The gate electrode of the fifth transistor T5 can be connected to the fourth control signal line providing the fourth control signal P_H. When the fourth control signal P_H of the turn-on level (e.g., low level) is provided, the fifth transistor T5 can be turned on to electrically connect the second power voltage line and the sixth transistor T6.

[0182] The sixth transistor T6 can be connected between the fifth transistor T5 and the second output node NC2. For example, the first electrode of the sixth transistor T6 can be connected to the second electrode of the fifth transistor T5, and the second electrode of the sixth transistor T6 can be connected to the second output node NC2. The gate electrode of the sixth transistor T6 can be connected to the third control signal line providing the third control signal P_V. When the third control signal P_V of the turn-on level (e.g., low level) is provided, the sixth transistor T6 can be turned on to electrically connect the fifth transistor T5 and the second output node NC2.

[0183] The seventh transistor T7 can be connected between a first power voltage line configured to provide a first power voltage VGH and a second output node NC2. For example, a first electrode of the seventh transistor T7 can be connected to the first power voltage line, and a second electrode of the seventh transistor T7 can be connected to the second output node NC2. A gate electrode of the seventh transistor T7 can be connected to a first control signal line providing a first control signal S_V. When the first control signal S_V at a conductive level (e.g., a low level) is provided, the seventh transistor T7 can be turned on to electrically connect the second output node NC2 and the first power voltage line. In this case, the first power voltage VGH is provided to the second output node NC2, so that the second selection signal output unit SGL2 can output a second selection signal Ps at a high level.

[0184] The eighth transistor T8 can be connected between a first power voltage line configured to provide a first power voltage VGH and a second output node NC2. For example, a first electrode of the eighth transistor T8 can be connected to the first power voltage line, and a second electrode of the eighth transistor T8 can be connected to the second output node NC2. A gate electrode of the eighth transistor T8 can be connected to a second control signal line providing a second control signal S_H. When the second control signal S_H at a conductive level (e.g., a low level) is provided, the eighth transistor T8 can be turned on to electrically connect the second output node NC2 and the first power voltage line. In this case, the first power voltage VGH is provided to the second output node NC2, so that the second selection signal output unit SGL2 can output a second selection signal Ps at a high level.

[0185] The fifth transistor T5 and the sixth transistor T6 can be connected in series between a second power voltage line configured to provide a second power voltage VGL and the second output node NC2. Thus, when both the fifth transistor T5 and the sixth transistor T6 are turned on, the second output node NC2 and the second power voltage line configured to provide the second power voltage VGL can be electrically connected, so that the second selection signal Ps at a low level can be output through the second output node NC2.

[0186] In addition, the seventh transistor T7 and the eighth transistor T8 can be connected in parallel between a first power voltage line configured to provide a first power voltage VGH and the second output node NC2. Thus, when at least one of the seventh transistor T7 and the eighth transistor T8 is turned on, the second output node NC2 and the first power voltage line configured to provide the first power voltage VGH can be electrically connected, so that the second selection signal Ps at a high level can be output through the second output node NC2.

[0187] In this way, the fifth transistor T5 and the sixth transistor T6 can be used as the pull-up unit of the second selection signal output unit SGL2, while the seventh transistor T7 and the eighth transistor T8 can be used as the pull-down unit of the second selection signal output unit SGL2. For example, the fifth transistor T5 and the sixth transistor T6 can be defined as the second pull-up unit, and the seventh transistor T7 and the eighth transistor T8 can be defined as the second pull-down unit.

[0188] Figure 9 is a diagram for describing Figure 8 an example of the operation of the selection signal generation circuit.

[0189] Figures 10A to 10D is an equivalent circuit diagram for describing Figure 8 an example of the operation of the selection signal generation circuit.

[0190] Referring to Figure 8 and Figure 9 , the first selection signal generation circuit SLC1 can output a low-level first selection signal Ss and a high-level second selection signal Ps based on the first to fourth control signals S_V, S_H, P_V, and P_H, or output a high-level first selection signal Ss and a low-level second selection signal Ps. That is, the first selection signal generation circuit SLC1 can output the first selection signal Ss and the second selection signal Ps with opposite voltage levels.

[0191] For example, still referring to Figure 10A , when the first control signal S_V and the second control signal S_H are at a low level (i.e., conduction level), and the third control signal P_V and the fourth control signal P_H are at a high level (i.e., cutoff level), the first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 can be turned on, and the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be turned off.

[0192] In this case, the second power voltage VGL provided from the second power voltage line is supplied to the first output node NC1 through the turned-on first transistor T1 or the turned-on second transistor T2, so a low-level (i.e., conduction level) first selection signal Ss with the second power voltage VGL can be output. In addition, the first power voltage VGH provided from the first power voltage line is supplied to the second output node NC2 through the turned-on seventh transistor T7 or the turned-on eighth transistor T8, so a high-level (i.e., conduction level) second selection signal Ps with the first power voltage VGH can be output.

[0193] Next, still referring to Figure 10B, when the second control signal S_H and the third control signal P_V are at a low level (i.e., conduction level), and the first control signal S_V and the fourth control signal P_H are at a high level (i.e., cut-off level), the second transistor T2, the third transistor T3, the sixth transistor T6, and the eighth transistor T8 can be turned on, and the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 can be turned off.

[0194] In this case, the second power supply voltage VGL provided from the second power supply voltage line is supplied to the first output node NC1 through the turned-on second transistor T2, so that the first selection signal Ss having a low level (i.e., conduction level) of the second power supply voltage VGL can be output. In addition, the first power supply voltage VGH provided from the first power supply voltage line is supplied to the second output node NC2 through the turned-on eighth transistor T8, so that the second selection signal Ps having a high level (i.e., conduction level) of the first power supply voltage VGH can be output.

[0195] At the same time, even if the third transistor T3 is turned on, the fourth transistor T4 connected in series with the third transistor T3 is turned off, so that the first power supply voltage VGH is not supplied to the first output node NC1. Similarly, even if the sixth transistor T6 is turned on, the fifth transistor T5 connected in series with the sixth transistor T6 is turned off, so that the second power supply voltage VGL is not supplied to the second output node NC2.

[0196] Next, also referring to Figure 10C , when the second control signal S_H and the third control signal P_V are at a high level (i.e., cut-off level), and the first control signal S_V and the fourth control signal P_H are at a low level (i.e., conduction level), the second transistor T2, the third transistor T3, the sixth transistor T6, and the eighth transistor T8 can be turned off, and the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 can be turned on.

[0197] In this case, the second power supply voltage VGL provided from the second power supply voltage line is supplied to the first output node NC1 through the turned-on first transistor T1, so that the first selection signal Ss having a low level (i.e., conduction level) of the second power supply voltage VGL can be output. In addition, the first power supply voltage VGH provided from the first power supply voltage line is supplied to the second output node NC2 through the turned-on seventh transistor T7, so that the second selection signal Ps having a high level (i.e., cut-off level) of the first power supply voltage VGH can be output.

[0198] Meanwhile, even if the fourth transistor T4 is turned on, the third transistor T3 connected in series with the fourth transistor T4 is turned off, so the first power voltage VGH is not supplied to the first output node NC1. Similarly, even if the fifth transistor T5 is turned on, the sixth transistor T6 connected in series with the fifth transistor T5 is turned off, so the second power voltage VGL is not supplied to the second output node NC2.

[0199] Finally, also referring to Figure 10D , when the first control signal S_V and the second control signal S_H are at a high level (i.e., the turn-off level), and the third control signal P_V and the fourth control signal P_H are at a low level (i.e., the turn-on level), the first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 can be turned off, and the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be turned on.

[0200] In this case, the first power voltage VGH supplied from the first power voltage line is supplied to the first output node NC1 through the turned-on third transistor T3 and the turned-on fourth transistor T4 connected in series with each other, so the first selection signal Ss having a high level (i.e., the turn-off level) of the first power voltage VGH can be output. In addition, the second power voltage VGL supplied from the second power voltage line is supplied to the second output node NC2 through the turned-on fifth transistor T5 and the turned-on sixth transistor T6 connected in series with each other, so the second selection signal Ps having a low level (i.e., the turn-on level) of the second power voltage VGL can be output.

[0201] In this way, the first selection signal generation circuit SLC1 can control the driving mode of the pixel PX by being configured to supply the first selection signal Ss and the second selection signal Ps having opposite voltage levels to the pixel PX.

[0202] For example, when the low-level first selection signal Ss and the high-level second selection signal Ps are supplied to the pixel PX, the first selection transistor TP1 is turned on, while the second selection transistor TP2 is turned off, so the first driving current can be supplied to the first light-emitting element ED1. In this case, the first light-emitting element ED1 can provide light through the first optical member 161 at a wide viewing angle as the first viewing angle.

[0203] In addition, when the high-level first selection signal Ss and the low-level second selection signal Ps are supplied to the pixel PX, the first selection transistor TP1 is turned off, while the second selection transistor TP2 is turned on, so the second driving current can be supplied to the second light-emitting element ED2. In this case, the second light-emitting element ED2 can provide light through the second optical member 162 at a narrow viewing angle as the second viewing angle.

[0204] In this manner, the selection signal generator SLG to which the first selection signal generation circuit SLC1 is applied can supply a first selection signal Ss and a second selection signal Ps having opposite voltage levels to the pixel PX to control at least one corresponding pixel PX in the first mode or the second mode.

[0205] Figure 11 is a circuit diagram showing another example of a pixel circuit included in Figure 2 the display device.

[0206] Meanwhile, Figure 11 the second pixel circuit PC2 shown represents another exemplary embodiment of a pixel circuit corresponding to each of the plurality of pixels PX included in the display device 100 described with reference to Figure 2 . For example, Figure 11 shows a modified exemplary embodiment of the exemplary embodiment regarding the selection transistors TP3 and TP4, and thus, in Figure 4 , for the sake of avoiding repetitive description, the description will focus on the differences from the Figure 11 exemplary embodiment. Figure 4

[0207] Referring to Figure 11 , the second pixel circuit PC2 may include a driving transistor DT, a plurality of switching transistors ST1 to ST6, a plurality of selection transistors TP3 and TP4, a storage capacitor Cst, and a plurality of light emitting elements ED1 and ED2.

[0208] The plurality of selection transistors TP3 and TP4 may include: a third selection transistor TP3 configured to generate a current path for a first driving current flowing through the first light emitting element ED1; and a fourth selection transistor TP4 configured to generate a current path for a second driving current flowing through the second light emitting element ED2.

[0209] The third selection transistor TP3 may be connected between the fourth node N4 and the first light emitting element ED1, and the gate electrode of the third selection transistor TP3 may be connected to a selection signal line providing a selection signal MS.

[0210] The fourth selection transistor TP4 may be connected between the fourth node N4 and the second light emitting element ED2, and the gate electrode of the fourth selection transistor TP4 may be connected to a selection signal line providing a selection signal MS.

[0211] The third selection transistor TP3 can be an n-type transistor, and the fourth selection transistor TP4 can be a p-type transistor. Therefore, when a low-level selection signal MS is provided to the selection signal line, in response to the low-level selection signal MS, the third selection transistor TP3 can be turned off, and the fourth selection transistor TP4 can be turned on. Additionally, when a high-level selection signal MS is provided to the selection signal line, in response to the high-level selection signal MS, the third selection transistor TP3 can be turned on, and the fourth selection transistor TP4 can be turned off.

[0212] Therefore, when the pixel PX to which the second pixel circuit PC2 is applied is driven in the first mode as a shared mode, high-level selection signals MS are respectively provided to the gate electrodes of the third selection transistor TP3 and the fourth selection transistor TP4. Thus, the third selection transistor TP3 can be turned on, and the fourth selection transistor TP4 can be turned off. Consequently, a current path for the first drive current flowing through the first light-emitting element ED1 can be formed, and thus the first light-emitting element ED1 can emit light. At the same time, since the turned-off fourth selection transistor TP4 does not generate a second drive current, the second light-emitting element ED2 can refrain from emitting light.

[0213] Moreover, when the pixel PX to which the second pixel circuit PC2 is applied is driven in the second mode as a private mode, low-level selection signals MS are respectively provided to the gate electrodes of the third selection transistor TP3 and the fourth selection transistor TP4. Hence, the third selection transistor TP3 can be turned off, and the fourth selection transistor TP4 can be turned on. As a result, a current path for the second drive current flowing through the second light-emitting element ED2 can be formed, and thus the second light-emitting element ED2 can emit light. Meanwhile, since the turned-off third selection transistor TP3 does not generate a first drive current, the first light-emitting element ED1 can refrain from emitting light.

[0214] The first light-emitting element ED1 can be connected between the third selection transistor TP3 turned on or off by the selection signal MS and the low-potential power line providing the low-potential power voltage VSS. The second light-emitting element ED2 can be connected between the fourth selection transistor TP4 turned on or off by the selection signal MS and the low-potential power line providing the low-potential power voltage VSS.

[0215] In this case, the first light-emitting element ED1 or the second light-emitting element ED2 can be connected to other components (e.g., the driving transistor DT) of the second pixel circuit PC2 through the third selection transistor TP3 or the fourth selection transistor TP4 that is turned on according to the driving mode. For example, the first light-emitting element ED1 can be connected to the driving transistor DT through the third selection transistor TP3 that is turned on in the first mode, and can provide light at a wide viewing angle as the first viewing angle in the first mode (i.e., the sharing mode) through the first driving current. In addition, the second light-emitting element ED2 can be connected to the driving transistor DT through the fourth selection transistor TP4 that is turned on in the second mode, and can provide light at a narrow viewing angle as the second viewing angle in the second mode (i.e., the private mode) through the second driving current. Here, the driving mode can be specified by a user input or determined when a pre-specified condition is satisfied.

[0216] Figure 12 is a circuit diagram showing another example of a selection signal generation circuit included in Figure 2 the display device.

[0217] Meanwhile, Figure 12 the second selection signal generation circuit SLC2 shown shows another exemplary embodiment of a selection signal generation circuit corresponding to each of the plurality of selection signal generators SLG included in the display device 100 described with reference to Figures 2 to 3E The selection signal generator SLG including the second selection signal generation circuit SLC2 can provide a selection signal to the pixel PX including the second pixel circuit PC2 described with reference to Figure 11 .

[0218] Referring to Figure 12 , the plurality of transistors included in the second selection signal generation circuit SLC2 can be n-type transistors or p-type transistors. Hereinafter, for ease of description, it will be described based on the plurality of transistors T9 to T12 included in the second selection signal generation circuit SLC2 being p-type transistors. However, at least some of the plurality of transistors T9 to T12 included in the second selection signal generation circuit SLC2 can be modified and implemented as n-type transistors.

[0219] The second selection signal generation circuit SLC2 can generate a selection signal MS based on the first control signal to the fourth control signals S_V, S_H, P_V, and P_H, the first power voltage VGH, and the second power voltage VGL.

[0220] The second selection signal generation circuit SLC2 can control the voltage of the third output node NC3 to the first power voltage VGH of a high level or the second power voltage VGL of a low level. Therefore, the selection signal MS of a high level or a low level can be output through the third output node NC3. For this purpose, the second selection signal generation circuit SLC2 can include the ninth transistor T9 to the twelfth transistor T12.

[0221] The ninth transistor T9 can be connected between the second power voltage line configured to provide the second power voltage VGL and the third output node NC3. For example, the first electrode of the ninth transistor T9 can be connected to the second power voltage line, and the second electrode of the ninth transistor T9 can be connected to the third output node NC3. The gate electrode of the ninth transistor T9 can be connected to the first control signal line providing the first control signal S_V. When the first control signal S_V of a conductive level (e.g., a low level) is provided, the ninth transistor T9 can be turned on to electrically connect the third output node NC3 and the second power voltage line. In this case, the second power voltage VGL is provided to the third output node NC3, so the second selection signal generation circuit SLC2 can output the selection signal MS of a low level.

[0222] The tenth transistor T10 can be connected between the second power voltage line configured to provide the second power voltage VGL and the third output node NC3. For example, the first electrode of the tenth transistor T10 can be connected to the second power voltage line, and the second electrode of the tenth transistor T10 can be connected to the third output node NC3. The gate electrode of the tenth transistor T10 can be connected to the second control signal line providing the second control signal S_H. When the second control signal S_H of a conductive level (e.g., a low level) is provided, the tenth transistor T10 can be turned on to electrically connect the third output node NC3 and the second power voltage line. In this case, the second power voltage VGL is provided to the third output node NC3, so the second selection signal generation circuit SLC2 can output the selection signal MS of a low level.

[0223] The eleventh transistor T11 can be connected between the first power voltage line configured to provide the first power voltage VGH and the third output node NC3. For example, the first electrode of the eleventh transistor T11 can be connected to the twelfth transistor T12, and the second electrode of the eleventh transistor T11 can be connected to the third output node NC3. The gate electrode of the eleventh transistor T11 can be connected to the third control signal line providing the third control signal P_V. When the third control signal P_V of a conductive level (e.g., a low level) is provided, the eleventh transistor T11 can be turned on to electrically connect the third output node NC3 and the twelfth transistor T12.

[0224] The twelfth transistor T12 may be connected between the eleventh transistor T11 and the first power voltage line that provides the first power voltage VGH. For example, the first electrode of the twelfth transistor T12 may be connected to the first power voltage line, and the second electrode of the twelfth transistor T12 may be connected to the first electrode of the eleventh transistor T11. The gate electrode of the twelfth transistor T12 may be connected to the fourth control signal line that provides the fourth control signal P_H. When the fourth control signal P_H of a conductive level (e.g., a low level) is provided, the twelfth transistor T12 may be turned on to electrically connect the eleventh transistor T11 and the first power voltage line.

[0225] The ninth transistor T9 and the tenth transistor T10 may be connected in parallel between the second power voltage line configured to provide the second power voltage VGL and the third output node NC3. Accordingly, when at least one of the ninth transistor T9 and the tenth transistor T10 is turned on, the third output node NC3 and the second power voltage line configured to provide the second power voltage VGL may be electrically connected, and thus the low-level selection signal MS may be output through the third output node NC3.

[0226] In addition, the eleventh transistor T11 and the twelfth transistor T12 may be connected in series between the first power voltage line configured to provide the first power voltage VGH and the third output node NC3. Accordingly, when both the eleventh transistor T11 and the twelfth transistor T12 are turned on, the third output node NC3 and the first power voltage line configured to provide the first power voltage VGH may be electrically connected, and thus the high-level selection signal MS may be output through the third output node NC3.

[0227] In this way, the ninth transistor T9 and the tenth transistor T10 may be used as the pull-up unit of the second selection signal generation circuit SLC2, and the eleventh transistor T11 and the twelfth transistor T12 may be used as the pull-down unit of the second selection signal generation circuit SLC2. For example, the ninth transistor T9 and the tenth transistor T10 may be defined as the third pull-up unit, and the eleventh transistor T11 and the twelfth transistor T12 may be defined as the third pull-down unit.

[0228] Figure 13 is a diagram for describing Figure 12 an example of the operation of the selection signal generation circuit.

[0229] Figures 14A to 14D is an equivalent circuit diagram for describing Figure 12 an example of the operation of the selection signal generation circuit.

[0230] Referring to Figure 12 and Figure 13, the second selection signal generation circuit SLC2 can output a low-level selection signal MS or a high-level selection signal MS based on the first to fourth control signals S_V, S_H, P_V, and P_H.

[0231] For example, also referring to Figure 14A , when the first control signal S_V and the second control signal S_H are at a low level (i.e., conduction level), and the third control signal P_V and the fourth control signal P_H are at a high level (i.e., cutoff level), the ninth transistor T9 and the tenth transistor T10 can be turned on, and the eleventh transistor T11 and the twelfth transistor T12 can be turned off.

[0232] In this case, the second power supply voltage VGL provided from the second power supply voltage line is supplied to the third output node NC3 through the turned-on ninth transistor T9 or the turned-on tenth transistor T10, so a low-level selection signal MS having the second power supply voltage VGL can be output.

[0233] Next, also referring to Figure 14B , when the second control signal S_H and the third control signal P_V are at a low level (i.e., conduction level), and the first control signal S_V and the fourth control signal P_H are at a high level (i.e., cutoff level), the tenth transistor T10 and the eleventh transistor T11 can be turned on, and the ninth transistor T9 and the twelfth transistor T12 can be turned off.

[0234] In this case, the second power supply voltage VGL provided from the second power supply voltage line is supplied to the third output node NC3 through the turned-on tenth transistor T10, so a low-level selection signal MS having the second power supply voltage VGL can be output.

[0235] At the same time, even if the eleventh transistor T11 is turned on, the twelfth transistor T12 connected in series with the eleventh transistor T11 is turned off, so the first power supply voltage VGH is not supplied to the third output node NC3.

[0236] Next, also referring to Figure 14C , when the second control signal S_H and the third control signal P_V are at a high level (i.e., cutoff level), and the first control signal S_V and the fourth control signal P_H are at a low level (i.e., conduction level), the ninth transistor T9 and the twelfth transistor T12 can be turned on, and the tenth transistor T10 and the eleventh transistor T11 can be turned off.

[0237] In this case, the second power supply voltage VGL provided from the second power supply voltage line is supplied to the third output node NC3 through the turned-on ninth transistor T9, so a low-level selection signal MS having the second power supply voltage VGL can be output.

[0238] Meanwhile, even if the twelfth transistor T12 is turned on, the eleventh transistor T11 connected in series with the twelfth transistor T12 is turned off, so the first power voltage VGH is not supplied to the third output node NC3.

[0239] Finally, also referring to Figure 14D , when the first control signal S_V and the second control signal S_H are at a high level (i.e., the turn-off level), and the third control signal P_V and the fourth control signal P_H are at a low level (i.e., the turn-on level), the ninth transistor T9 and the tenth transistor T10 can be turned off, and the eleventh transistor T11 and the twelfth transistor T12 can be turned on.

[0240] In this case, the first power voltage VGH supplied from the first power voltage line is supplied to the third output node NC3 through the turned-on eleventh transistor T11 and the turned-on twelfth transistor T12 connected in series with each other, so a selection signal MS with a high level of the first power voltage VGH can be output.

[0241] In this way, the second selection signal generation circuit SLC2 can supply a selection signal MS with a high level to the pixel PX in the first mode and supply a selection signal MS with a low level to the pixel PX in the second mode to control the driving mode of the pixel PX.

[0242] For example, when a selection signal MS with a high level is supplied to the pixel PX, the third selection transistor TP3 is turned on and the fourth selection transistor TP4 is turned off, so the first driving current can be supplied to the first light-emitting element ED1. In this case, the first light-emitting element ED1 can emit light through the first optical member 161 at a wide viewing angle as the first viewing angle.

[0243] In addition, when a selection signal MS with a low level is supplied to the pixel PX, the third selection transistor TP3 is turned off and the fourth selection transistor TP4 is turned on, so the second driving current can be supplied to the second light-emitting element ED2. In this case, the second light-emitting element ED2 can emit light through the second optical member 162 at a narrow viewing angle as the second viewing angle.

[0244] In this way, the selection signal generator SLG to which the second selection signal generation circuit SLC2 is applied supplies a selection signal MS with a different voltage level to the pixel PX in each mode, so at least one corresponding pixel PX can be controlled in the first mode or the second mode.

[0245] In addition, as referred to in Figures 11 to 14DAs described above, by commonly connecting the gate electrodes of the selection transistors TP3 and TP4 included in the pixel circuit of the pixel PX to the same selection signal MS and controlling the voltage level of the selection signal MS according to the driving mode, the number of selection signal lines for controlling the selection transistors TP3 and TP4 can be reduced, and the number of transistors in the selection signal generation circuit of the selection signal generator SLG can be reduced. Therefore, the selection signal generation circuit configured to generate the selection signal can be simplified.

[0246] Figure 15 is a circuit diagram showing another example of a selection signal generation circuit included in Figure 2 the display device.

[0247] Meanwhile, Figure 15 the third selection signal generation circuit SLC3 shown shows another exemplary embodiment of the selection signal generation circuit corresponding to each of the plurality of selection signal generators SLG included in the display device 100 described with reference to Figures 2 to 3E The selection signal generator SLG including the third selection signal generation circuit SLC3 can provide a selection signal to the pixel PX including the second pixel circuit PC2 described with reference to Figure 11 Each.

[0248] Referring to Figure 15 , the plurality of transistors included in the third selection signal generation circuit SLC3 can be n-type transistors or p-type transistors. Hereinafter, for convenience of description, it will be described based on the plurality of transistors T13 to T16 included in the third selection signal generation circuit SLC3 being p-type transistors. However, at least some of the plurality of transistors T13 to T16 included in the third selection signal generation circuit SLC3 can be modified and implemented as n-type transistors.

[0249] The third selection signal generation circuit SLC3 can generate a selection signal MS based on the first control signal to the fourth control signals S_V, S_H, P_V, and P_H, the first power voltage VGH, and the second power voltage VGL.

[0250] The third selection signal generation circuit SLC3 can control the voltage of the fourth output node NC4 to the high-level first power voltage VGH or the low-level second power voltage VGL. Therefore, the high-level or low-level selection signal MS can be output through the fourth output node NC4. To this end, the third selection signal generation circuit SLC3 can include the thirteenth transistor T13 to the sixteenth transistor T16.

[0251] The thirteenth transistor T13 can be connected between a second power voltage line configured to provide a second power voltage VGL and a fourth output node NC4. For example, a first electrode of the thirteenth transistor T13 can be connected to the second power voltage line, and a second electrode of the thirteenth transistor T13 can be connected to the fourteenth transistor T14. A gate electrode of the thirteenth transistor T13 can be connected to a fourth control signal line that provides a fourth control signal P_H. When the fourth control signal P_H at an active level (e.g., a low level) is provided, the thirteenth transistor T13 can be turned on to electrically connect the second power voltage line and the fourteenth transistor T14.

[0252] The fourteenth transistor T14 can be connected between the thirteenth transistor T13 and the fourth output node NC4. For example, a first electrode of the fourteenth transistor T14 can be connected to the second electrode of the thirteenth transistor T13, and a second electrode of the fourteenth transistor T14 can be connected to the fourth output node NC4. A gate electrode of the fourteenth transistor T14 can be connected to a third control signal line that provides a third control signal P_V. When the third control signal P_V at an active level (e.g., a low level) is provided, the fourteenth transistor T14 can be turned on to electrically connect the thirteenth transistor T13 and the fourth output node NC4.

[0253] The fifteenth transistor T15 can be connected between a first power voltage line configured to provide a first power voltage VGH and the fourth output node NC4. For example, a first electrode of the fifteenth transistor T15 can be connected to the first power voltage line, and a second electrode of the fifteenth transistor T15 can be connected to the fourth output node NC4. A gate electrode of the fifteenth transistor T15 can be connected to a first control signal line that provides a first control signal S_V. When the first control signal S_V at an active level (e.g., a low level) is provided, the fifteenth transistor T15 can be turned on to electrically connect the fourth output node NC4 and the first power voltage line. In this case, the first power voltage VGH is provided to the fourth output node NC4, so the third selection signal generation circuit SLC3 can output a selection signal MS at a high level.

[0254] The sixteenth transistor T16 may be connected between a first power voltage line configured to provide a first power voltage VGH and a fourth output node NC4. For example, a first electrode of the sixteenth transistor T16 may be connected to the first power voltage line, and a second electrode of the sixteenth transistor T16 may be connected to the fourth output node NC4. A gate electrode of the sixteenth transistor T16 may be connected to a second control signal line providing a second control signal S_H. When the second control signal S_H having a conductive level (e.g., a low level) is provided, the sixteenth transistor T16 may be turned on to electrically connect the fourth output node NC4 and the first power voltage line. In this case, the first power voltage VGH is provided to the fourth output node NC4, and thus the third selection signal generation circuit SLC3 may output a selection signal MS having a high level.

[0255] The thirteenth transistor T13 and the fourteenth transistor T14 may be serially connected between a second power voltage line configured to provide a second power voltage VGL and the fourth output node NC4. Accordingly, when both the thirteenth transistor T13 and the fourteenth transistor T14 are turned on, the fourth output node NC4 and the second power voltage line configured to provide the second power voltage VGL may be electrically connected, and thus the selection signal MS having a low level may be output through the fourth output node NC4.

[0256] In addition, the fifteenth transistor T15 and the sixteenth transistor T16 may be connected in parallel between a first power voltage line configured to provide a first power voltage VGH and the fourth output node NC4. Accordingly, when at least one of the fifteenth transistor T15 and the sixteenth transistor T16 is turned on, the fourth output node NC4 and the first power voltage line configured to provide the first power voltage VGH may be electrically connected, and thus the selection signal MS having a high level may be output through the fourth output node NC4.

[0257] In this manner, the thirteenth transistor T13 and the fourteenth transistor T14 may be used as a pull-up unit of the third selection signal generation circuit SLC3, and the fifteenth transistor T15 and the sixteenth transistor T16 may be used as a pull-down unit of the third selection signal generation circuit SLC3. For example, the thirteenth transistor T13 and the fourteenth transistor T14 may be defined as a fourth pull-up unit, and the fifteenth transistor T15 and the sixteenth transistor T16 may be defined as a fourth pull-down unit.

[0258] Figure 16 is a diagram for describing Figure 15 an example of the operation of a selection signal generation circuit.

[0259] Figures 17A to 17D is an equivalent circuit diagram for describing Figure 15 an example of the operation of a selection signal generation circuit.

[0260] Reference Figure 15 and Figure 16 , the third selection signal generation circuit SLC3 can output a selection signal MS of low level or a selection signal MS of high level based on the first to fourth control signals S_V, S_H, P_V, and P_H.

[0261] For example, still referring to Figure 17A , when the first control signal S_V and the second control signal S_H are at low level (i.e., conduction level), and the third control signal P_V and the fourth control signal P_H are at high level (i.e., cutoff level), the fifteenth transistor T15 and the sixteenth transistor T16 can be turned on, and the thirteenth transistor T13 and the fourteenth transistor T14 can be turned off.

[0262] In this case, the first power voltage VGH provided from the first power voltage line is supplied to the fourth output node NC4 through the turned-on fifteenth transistor T15 and the turned-on sixteenth transistor T16, so a selection signal MS of high level with the first power voltage VGH can be output.

[0263] Next, still referring to Figure 17B , when the second control signal S_H and the third control signal P_V are at low level (i.e., conduction level), and the first control signal S_V and the fourth control signal P_H are at high level (i.e., cutoff level), the fourteenth transistor T14 and the sixteenth transistor T16 can be turned on, and the thirteenth transistor T13 and the fifteenth transistor T15 can be turned off.

[0264] In this case, the first power voltage VGH provided from the first power voltage line is supplied to the fourth output node NC4 through the turned-on sixteenth transistor T16, so a selection signal MS of high level with the first power voltage VGH can be output.

[0265] At the same time, even if the fourteenth transistor T14 is turned on, the thirteenth transistor T13 connected in series with the fourteenth transistor T14 is turned off, so the second power voltage VGL is not supplied to the fourth output node NC4.

[0266] Next, still referring to Figure 17C , when the second control signal S_H and the third control signal P_V are at high level (i.e., cutoff level), and the first control signal S_V and the fourth control signal P_H are at low level (i.e., conduction level), the fourteenth transistor T14 and the sixteenth transistor T16 can be turned off, and the thirteenth transistor T13 and the fifteenth transistor T15 can be turned on.

[0267] In this case, the first power supply voltage VGH supplied from the first power supply voltage line is supplied to the fourth output node NC4 through the turned-on fifteenth transistor T15, and thus a high-level selection signal MS having the first power supply voltage VGH can be output.

[0268] At the same time, even if the thirteenth transistor T13 is turned on, the fourteenth transistor T14 connected in series with the thirteenth transistor T13 is turned off, and thus the second power supply voltage VGL is not supplied to the fourth output node NC4.

[0269] Finally, also referring to Figure 17D , when the first control signal S_V and the second control signal S_H are at a high level (i.e., the turn-off level), and the third control signal P_V and the fourth control signal P_H are at a low level (i.e., the turn-on level), the fifteenth transistor T15 and the sixteenth transistor T16 can be turned off, and the thirteenth transistor T13 and the fourteenth transistor T14 can be turned on.

[0270] In this case, the second power supply voltage VGL supplied from the second power supply voltage line is supplied to the fourth output node NC4 through the turned-on thirteenth transistor T13 and the turned-on fourteenth transistor T14 connected in series with each other, and thus a low-level selection signal MS having the second power supply voltage VGL can be output.

[0271] In this way, the third selection signal generation circuit SLC3 can supply a selection signal MS having a high level to the pixel PX in the first mode and supply a selection signal MS having a low level to the pixel PX in the second mode to control the driving mode of the pixel PX.

[0272] For example, when a high-level selection signal MS is supplied to the pixel PX, the third selection transistor TP3 is turned on and the fourth selection transistor TP4 is turned off, and thus a first driving current can be supplied to the first light-emitting element ED1. In this case, the first light-emitting element ED1 can emit light through the first optical member 161 at a wide viewing angle as a first viewing angle.

[0273] In addition, when a low-level selection signal MS is supplied to the pixel PX, the third selection transistor TP3 is turned off and the fourth selection transistor TP4 is turned on, and thus a second driving current can be supplied to the second light-emitting element ED2. In this case, the second light-emitting element ED2 can emit light through the second optical member 162 at a narrow viewing angle as a second viewing angle.

[0274] In this way, the selection signal generator SLG to which the third selection signal generation circuit SLC3 is applied supplies a selection signal MS having a different voltage level to the pixel PX in each mode, and thus at least one corresponding pixel PX can be controlled in the first mode or the second mode.

[0275] In addition, as described with reference to Figure 11 and Figures 15 to 17D by commonly connecting the gate electrodes of the selection transistors TP3 and TP4 included in the pixel circuit of the pixel PX to the same selection signal MS and controlling the voltage level of the selection signal MS according to the driving mode, the number of selection signal lines for controlling the selection transistors TP3 and TP4 can be reduced, and the number of transistors in the selection signal generation circuit of the selection signal generator SLG can be reduced. Therefore, the selection signal generation circuit configured to generate the selection signal can be simplified.

[0276] Exemplary embodiments of the present disclosure may also be described as follows:

[0277] According to an aspect of the present disclosure, a display device may include: a display panel including a display area and a non-display area surrounding the display area, and including a plurality of pixels and a plurality of selection signal generators disposed on the display area; and a timing controller configured to control the display panel. Each of the plurality of pixels may include: a first light-emitting element; a first optical member configured to refract light from the first light-emitting element; a second light-emitting element configured to emit light of the same color as the first light-emitting element; and a second optical member configured to refract light from the second light-emitting element and having a different shape from the first optical member. Each of the plurality of selection signal generators may control one of the first light-emitting element and the second light-emitting element included in at least one corresponding pixel of the plurality of pixels to emit light.

[0278] Each of the plurality of pixels may further include: a driving transistor configured to generate a first driving current and a second driving current, the first driving current flowing from a high-potential power line configured to provide a high-potential power voltage to a low-potential power line configured to provide a low-potential power voltage through the first light-emitting element, and the second driving current flowing from the high-potential power line to the low-potential power line through the second light-emitting element; a first selection transistor connected between the driving transistor and the first light-emitting element and turned on in response to a first selection signal provided to the first selection signal line; and a second selection transistor connected between the driving transistor and the second light-emitting element and turned on in response to a second selection signal provided to the second selection signal line.

[0279] Each of the plurality of selection signal generators may include: a first selection signal output unit configured to output a first selection signal through a first output node based on a first control signal, a second control signal, a third control signal, a fourth control signal, a first power voltage, and a second power voltage; and a second selection signal output unit configured to output a second selection signal through a second output node based on the first control signal, the second control signal, the third control signal, the fourth control signal, the first power voltage, and the second power voltage.

[0280] The first selection signal output unit may include: a first transistor connected between a second power voltage line providing the second power voltage and the first output node and conducting in response to the first control signal; a second transistor connected between the second power voltage line and the first output node and conducting in response to the second control signal; a third transistor connected between the first output node and a first power voltage line providing the first power voltage and conducting in response to the third control signal; and a fourth transistor connected between the third transistor and the first power voltage line and conducting in response to the fourth control signal.

[0281] The first transistor and the second transistor may be connected in parallel between the second power voltage line and the first output node, and the third transistor and the fourth transistor may be connected in series between the first power voltage line and the first output node.

[0282] The second selection signal output unit may include: a fifth transistor connected between the second power voltage line providing the second power voltage and the second output node and conducting in response to the fourth control signal; a sixth transistor connected between the fifth transistor and the second output node and conducting in response to the third control signal; a seventh transistor connected between the second output node and a first power voltage line providing the first power voltage and conducting in response to the first control signal; and an eighth transistor connected between the second output node and the first power voltage line and conducting in response to the second control signal.

[0283] The fifth transistor and the sixth transistor may be connected in series between the second power voltage line and the second output node, and the seventh transistor and the eighth transistor may be connected in parallel between the first power voltage line and the second output node.

[0284] Each of the plurality of pixels may further include: a driving transistor configured to generate a first driving current and a second driving current, the first driving current flowing from a high-potential power line configured to provide a high-potential power voltage to a low-potential power line configured to provide a low-potential power voltage through a first light-emitting element, and the second driving current flowing from the high-potential power line to the low-potential power line through a second light-emitting element; a third selection transistor connected between the driving transistor and the first light-emitting element and turned on in response to a selection signal provided to a selection signal line; and a fourth selection transistor connected between the driving transistor and the second light-emitting element and turned on in response to the selection signal.

[0285] The third selection transistor may be an n-type transistor, and the fourth selection transistor is a p-type transistor.

[0286] Each of the plurality of selection signal generators outputs a selection signal having a high level or a low level based on a first control signal, a second control signal, a third control signal, a fourth control signal, a first power voltage, and a second power voltage.

[0287] Each of the plurality of selection signal generators may include: a ninth transistor connected between a second power voltage line providing a second power voltage and a third output node and turned on in response to the first control signal; a tenth transistor connected between the second power voltage line and the third output node and turned on in response to the second control signal; an eleventh transistor connected between the third output node and a first power voltage line providing a first power voltage and turned on in response to the third control signal; and a twelfth transistor connected between the eleventh transistor and the first power voltage line and turned on in response to the fourth control signal.

[0288] The ninth transistor and the tenth transistor may be connected in parallel between the second power voltage line and the third output node, and the eleventh transistor and the twelfth transistor may be connected in series between the first power voltage line and the third output node.

[0289] Each of the plurality of selection signal generators may include: a thirteenth transistor connected between a second power voltage line providing a second power voltage and a fourth output node and turned on in response to a fourth control signal; a fourteenth transistor connected between the thirteenth transistor and the fourth output node and turned on in response to a third control signal; a fifteenth transistor connected between the fourth output node and a first power voltage line configured to provide a first power voltage and turned on in response to a first control signal; and a sixteenth transistor connected between the fourth output node and the first power voltage line and turned on in response to a second control signal.

[0290] The thirteenth transistor and the fourteenth transistor may be connected in series between the second power voltage line and the fourth output node, and the fifteenth transistor and the sixteenth transistor may be connected in parallel between the first power voltage line and the fourth output node.

[0291] The plurality of selection signal generators may control any one of a first light-emitting element and a second light-emitting element included in one of the plurality of pixels to emit light.

[0292] Each of the plurality of selection signal generators may control any one of a first light-emitting element and a second light-emitting element included in each of at least two of the plurality of pixels to emit light.

[0293] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be construed as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: A display panel, the display panel including a display area and a non-display area surrounding the display area, and including a plurality of pixels and a plurality of selection signal generators provided on the display area; And A timing controller configured to control the display panel, Wherein each of the plurality of pixels includes: A first light-emitting element; A first optical member configured to refract light from the first light-emitting element; A second light-emitting element configured to emit light of the same color as the first light-emitting element; and A second optical member configured to refract light from the second light-emitting element and having a shape different from that of the first optical member, and Wherein each of the plurality of selection signal generators controls any one of the first light-emitting element and the second light-emitting element included in at least one corresponding pixel of the plurality of pixels to emit light.

2. The display device according to claim 1, Among them, Each of the plurality of pixels further includes: A driving transistor configured to generate a first driving current and a second driving current, the first driving current flowing through the first light-emitting element from a high-potential power line configured to provide a high-potential power voltage to a low-potential power line configured to provide a low-potential power voltage, and the second driving current flowing through the second light-emitting element from the high-potential power line to the low-potential power line; A first selection transistor connected between the driving transistor and the first light-emitting element and turned on in response to a first selection signal provided to a first selection signal line; and A second selection transistor connected between the driving transistor and the second light-emitting element and turned on in response to a second selection signal provided to a second selection signal line.

3. The display device according to claim 2, Among them, Each of the plurality of selection signal generators includes: A first selection signal output unit configured to output the first selection signal through a first output node based on a first control signal, a second control signal, a third control signal, a fourth control signal, a first power voltage, and a second power voltage; and A second selection signal output unit configured to output the second selection signal through a second output node based on the first control signal, the second control signal, the third control signal, the fourth control signal, the first power voltage, and the second power voltage.

4. The display device according to claim 3, Among them, The first selection signal output unit includes: A first transistor connected between a second power voltage line providing the second power voltage and the first output node and turned on in response to the first control signal; A second transistor, connected between the second power voltage line and the first output node and turned on in response to the second control signal; A third transistor, connected between the first output node and a first power voltage line providing the first power voltage and turned on in response to the third control signal; and A fourth transistor, connected between the third transistor and the first power voltage line and turned on in response to the fourth control signal.

5. The display device according to claim 4, Among them, The first transistor and the second transistor are connected in parallel between the second power voltage line and the first output node, and The third transistor and the fourth transistor are connected in series between the first power voltage line and the first output node.

6. The display device according to claim 3, Among them, The second selection signal output unit includes: A fifth transistor, connected between a second power voltage line providing the second power voltage and the second output node and turned on in response to the fourth control signal; A sixth transistor, connected between the fifth transistor and the second output node and turned on in response to the third control signal; A seventh transistor, connected between the second output node and a first power voltage line providing the first power voltage and turned on in response to the first control signal; and An eighth transistor, connected between the second output node and the first power voltage line and turned on in response to the second control signal.

7. The display device according to claim 6, Among them, The fifth transistor and the sixth transistor are connected in series between the second power voltage line and the second output node, and The seventh transistor and the eighth transistor are connected in parallel between the first power voltage line and the second output node.

8. The display device according to claim 1, Among them, Each of the plurality of pixels further includes: A driving transistor configured to generate a first driving current and a second driving current, the first driving current flowing from a high-potential power line configured to provide a high-potential power voltage to a low-potential power line configured to provide a low-potential power voltage through the first light-emitting element, and the second driving current flowing from the high-potential power line to the low-potential power line through the second light-emitting element; A third selection transistor connected between the driving transistor and the first light-emitting element and turned on in response to a selection signal provided to a selection signal line; and A fourth selection transistor connected between the driving transistor and the second light-emitting element and turned on in response to the selection signal.

9. The display device according to claim 8, Among them, The third selection transistor is an n-type transistor, and the fourth selection transistor is a p-type transistor.

10. The display device according to claim 8, Among them, Each of the plurality of selection signal generators outputs the selection signal having a high level or a low level based on a first control signal, a second control signal, a third control signal, a fourth control signal, a first power voltage, and a second power voltage.

11. The display device according to claim 10, Among them, Each of the plurality of selection signal generators includes: A ninth transistor connected between a second power voltage line providing the second power voltage and a third output node and turned on in response to the first control signal; A tenth transistor connected between the second power voltage line and the third output node and turned on in response to the second control signal; An eleventh transistor connected between the third output node and a first power voltage line providing the first power voltage and turned on in response to the third control signal; and A twelfth transistor connected between the eleventh transistor and the first power voltage line and turned on in response to the fourth control signal.

12. The display device according to claim 11, Among them, The ninth transistor and the tenth transistor are connected in parallel between the second power voltage line and the third output node, and The eleventh transistor and the twelfth transistor are connected in series between the first power voltage line and the third output node.

13. The display device according to claim 10, Among them, Each of the plurality of selection signal generators includes: A thirteenth transistor connected between a second power voltage line providing the second power voltage and a fourth output node and turned on in response to the fourth control signal; A fourteenth transistor connected between the thirteenth transistor and the fourth output node and turned on in response to the third control signal; A fifteenth transistor connected between the fourth output node and a first power voltage line configured to provide the first power voltage and turned on in response to the first control signal; and A sixteenth transistor connected between the fourth output node and the first power voltage line and turned on in response to the second control signal.

14. The display device according to claim 13, Among them, The thirteenth transistor and the fourteenth transistor are connected in series between the second power voltage line and the fourth output node, and The fifteenth transistor and the sixteenth transistor are connected in parallel between the first power voltage line and the fourth output node.

15. The display device according to claim 1, Among them, Each of the plurality of selection signal generators controls any one of the first light-emitting element and the second light-emitting element included in one of the plurality of pixels to emit light.

16. The display device according to claim 1, Among them, Each of the plurality of selection signal generators controls any one of the first light-emitting element and the second light-emitting element included in each of at least two of the plurality of pixels to emit light.

17. The display device according to claim 2, Among them, In the first mode, the first light-emitting element is connected to the driving transistor via the turned-on first selection transistor, and provides light at a first viewing angle through the first driving current, wherein, in the second mode, the second light-emitting element is connected to the driving transistor via the turned-on second selection transistor, and provides light at a second viewing angle through the second driving current, and the second viewing angle is narrower than the first viewing angle.

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