Storage device repair method and repair system

Abstract

The present application discloses a repair method and repair system for a storage device, and relates to the field of storage technology. The repair method includes: determining a plurality of first signal lines and a corresponding first quantity in a storage array; the first quantity is the number of failed storage units on the first signal line, and the first quantity of failed storage units on the first signal line is not 0; the first signal line extends along a first direction, and the plurality of first signal lines are arranged at intervals; according to the first number of failed storage units on each first signal line, an arrangement order of signal line addresses of the plurality of first signal lines is set; according to the arrangement order of signal line addresses of the plurality of first signal lines and a preset repair rule, each first signal line is replaced with a first redundant signal line in a redundant storage array to achieve repair. The sorting rate and sorting efficiency of the signal line addresses of the first signal lines are improved, the sorting time of the signal line addresses of the first signal lines is reduced, and the cycle of repairing failed storage units is shortened.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of storage technology, and in particular, to a method for repairing a storage device and a system for repairing a storage device. Background Art

[0002] Dynamic Random Access Memory (DRAM) chips, as storage devices, are now widely used in mobile phones, computers, servers, and other devices due to their simple structure, high integration, and low power consumption, playing a vital role in the consumer electronics sector. During the DRAM chip manufacturing process, failed memory cells may appear in the DRAM chip's memory array. To address this, a portion of the redundant memory array is reserved during DRAM chip design. The redundant memory cells in the redundant memory array are used to replace failed memory cells in the memory array, ensuring the normal operation of the DRAM chip.

[0003] Typically, when using redundant memory cells to repair failed memory cells, row addresses of all word lines in the memory array are sorted according to the number of failed memory cells on each word line in the memory array. Sorting row addresses is time-consuming and inefficient. Summary of the Invention

[0004] The embodiments of the present application provide a repair method and a repair system for a storage device, which can optimize the sorting of row addresses, reduce the sorting time of row addresses, and improve the sorting efficiency of row addresses.

[0005] A method for repairing a storage device, wherein the storage device includes a storage array and a redundant storage array, and the method comprises:

[0006] Determining a plurality of first signal lines in the memory array and a corresponding first number; the first number being the number of failed memory cells on the first signal line, the first number of failed memory cells on the first signal line being non-zero; the first signal lines extending along a first direction, the plurality of first signal lines being arranged at intervals;

[0007] setting an arrangement order of signal line addresses of a plurality of first signal lines according to a first number of failed storage units on each of the first signal lines;

[0008] According to the arrangement order of the signal line addresses of the plurality of first signal lines and a preset repair rule, the first redundant signal lines in the redundant memory array are used to replace each first signal line to achieve repair.

[0009] In one embodiment, setting the arrangement order of the signal line addresses of the plurality of first signal lines according to the first number of failed storage units on each of the first signal lines includes:

[0010] Based on a preset sorting method, signal line addresses of the plurality of first signal lines are sorted according to a first number of failed storage units on each of the first signal lines.

[0011] In one embodiment, based on a preset sorting method, the signal line addresses of the plurality of first signal lines are sorted according to the first number of failed storage units on each of the first signal lines, including:

[0012] Based on a quick sort method, a merge sort method or a bubble sort method, signal line addresses of the plurality of first signal lines are sorted according to a first number of failed storage units on each of the first signal lines.

[0013] In one embodiment, based on a quick sorting method, signal line addresses of a plurality of first signal lines are sorted according to a first number of failed storage units on each of the first signal lines, including:

[0014] Selecting a target signal line from the plurality of first signal lines by a random selection method;

[0015] Taking the first number corresponding to the target signal line as a reference number;

[0016] A first signal line group and a second signal line group are obtained based on the reference number and the first number of failed memory cells on each of the first signal lines, and the signal line address of each of the first signal lines in the first signal line group is arranged to the left of the signal line address of each of the first signal lines in the second signal line group; the first signal line group includes a plurality of first signal lines whose first number of failed memory cells is less than or equal to the reference number, and the second signal line group includes a plurality of first signal lines whose first number of failed memory cells is greater than the reference number;

[0017] Repeat the steps of randomly selecting target signal lines and obtaining the first signal line group and the second signal line group for the two signal line groups until the number of first signal lines in the new signal line group is less than or equal to a preset value, or the first numbers of the first signal lines in the new signal line group are the same; and use the order of the signal line addresses of the first signal lines of each signal line group as the order of the signal line addresses of the multiple first signal lines.

[0018] In one embodiment, the first number of failed memory cells on each first signal line is different, and the steps of repeatedly performing the steps of randomly selecting a target signal line and obtaining the first signal line group and the second signal line group on the two signal line groups include:

[0019] The signal line addresses corresponding to the first signal lines in the new signal line group on the left are sorted until the number of the first signal lines in the new signal line group is equal to one.

[0020] In one embodiment, at least two of the first signal lines have the same first number of failed memory cells, and the steps of repeatedly performing the steps of randomly selecting target signal lines and obtaining the first signal line group and the second signal line group on the two signal line groups include:

[0021] The signal line addresses corresponding to the first signal lines in the new signal line group on the left are sorted until the number of first signal lines in the new signal line group is equal to 1, or the first numbers of the first signal lines in the new signal line group are the same.

[0022] In one embodiment, the method for repairing a storage device further includes:

[0023] Determining that among a plurality of second signal lines in the memory array, the number of failed memory cells on the second signal line is 0; the second signal line is parallel to the first signal line;

[0024] Before setting the arrangement order of the signal line addresses of the plurality of first signal lines, the signal line addresses of the plurality of second signal lines are arranged as a whole on one side of the signal line addresses of the plurality of first signal lines.

[0025] In one embodiment, the first signal line is a word line.

[0026] A repair system for a storage device, wherein the storage device includes a storage array and a redundant storage array, and the repair system includes:

[0027] an acquisition module, configured to determine a plurality of first signal lines in the memory array and a corresponding first number; the first number being the number of failed memory cells on the first signal line, the first number of failed memory cells on the first signal line being non-zero; the first signal lines extending along a first direction, the plurality of first signal lines being arranged at intervals;

[0028] a sorting module connected to the acquisition module, and configured to set a sorting order of signal line addresses of a plurality of first signal lines according to a first number of failed storage units on each of the first signal lines;

[0029] The repair module is connected to the sorting module and is used to replace each first signal line with a first redundant signal line in a redundant memory array to achieve repair according to the sorting order of the signal line addresses of the plurality of first signal lines and a preset repair rule.

[0030] A storage device repair system, comprising:

[0031] Main control device;

[0032] A storage device connected to the main control device, the storage device comprising:

[0033] A memory die, comprising at least one memory module, wherein the memory module comprises a memory array and a redundant memory array;

[0034] The main control device is connected to the storage chip and is used to obtain the failed storage information of the failed storage unit of the storage array, and execute the above-mentioned repair method of the storage device according to the failed storage information to generate repair information, wherein the repair information includes the first redundant signal line and the corresponding information of each first signal line in the redundant storage array.

[0035] In one embodiment, the storage device further includes:

[0036] The control chip is connected to the main control device and the storage chip respectively, and is used to generate a repair signal according to the repair information; the storage chip is used to replace each first signal line with a first redundant signal line according to the repair signal to achieve repair.

[0037] In one embodiment, the memory chip includes a plurality of memory groups, each of which includes a plurality of memory modules; the control chip includes a redundant loading device and a plurality of control devices, the redundant loading device is respectively connected to the main control device and the plurality of control devices, and the plurality of control devices are respectively connected to the plurality of memory groups;

[0038] The redundant loading device is used to generate a plurality of repair control signals according to the repair information; the plurality of repair control signals respectively correspond to the plurality of control devices;

[0039] The control device is used to output corresponding repair signals to the multiple storage modules of the connected storage group according to the repair control signal output by the connected redundant loading device.

[0040] In the repair method of the above-mentioned storage device, multiple first signal lines and corresponding first quantities in the storage array are determined, the first quantity is the number of failed storage units on the first signal line, the first quantity of failed storage units on the first signal line is not 0, and according to the first quantity of failed storage units on each first signal line, the arrangement order of the signal line addresses of the multiple first signal lines is set, thereby improving the sorting rate and sorting efficiency of the signal line addresses of the first signal lines, reducing the sorting time of the signal line addresses of the first signal lines, and shortening the cycle of repairing the failed storage units.

[0041] In the repair system of the above-mentioned storage device, an acquisition module determines that there are multiple first signal lines and corresponding first quantities of failed storage units in the storage array, and a sorting module sets the arrangement order of the signal line addresses of the multiple first signal lines according to the first number of failed storage units on each first signal line, thereby improving the sorting rate and sorting efficiency of the signal line addresses of the first signal lines, reducing the sorting time of the signal line addresses of the first signal lines, and shortening the cycle of the repair module repairing the failed storage units.

[0042] In the repair system of the above-mentioned storage device, during the process of the main control device generating repair information, the main control device first obtains multiple first signal lines and corresponding first quantities of failed storage units in the storage array based on the failed storage information, and sets the arrangement order of the signal line addresses of the multiple first signal lines based on the first number of failed storage units on each first signal line. Since only the signal line addresses of the first signal lines whose first number of failed storage units is not 0 are sorted, the sorting rate and sorting efficiency of the signal line addresses of the first signal lines are improved, the sorting time of the signal line addresses of the first signal lines is reduced, and the time for the main control device to generate repair information is shortened. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0044] Figure 1 This is one of the structural diagrams of the storage device in the embodiment of the present application;

[0045] Figure 2 This is a flowchart of a method for repairing a storage device according to an embodiment of the present disclosure;

[0046] Figure 3 This is a schematic diagram of sorting signal line addresses of a plurality of first signal lines according to a first number of failed memory cells on each first signal line in an embodiment of the present application;

[0047] Figure 4 This is a second schematic diagram of sorting the signal line addresses of a plurality of first signal lines according to the first number of failed memory cells on each first signal line in an embodiment of the present application;

[0048] Figure 5 This is one of the structural diagrams of the repair system for a storage device according to an embodiment of the present disclosure;

[0049] Figure 6 This is a second structural diagram of a repair system for a storage device according to an embodiment of the present disclosure;

[0050] Figure 7 This is the third structural diagram of the repair system for a storage device according to an embodiment of the present disclosure;

[0051] Figure 8 This is a fourth structural diagram of a repair system for a storage device according to an embodiment of the present disclosure;

[0052] Figure 9 This is a fifth structural diagram of a repair system for a storage device according to an embodiment of the present disclosure;

[0053] Figure 10 This is the sixth structural diagram of the repair system for a storage device in an embodiment of the present disclosure.

[0054] Description of reference numerals:

[0055] Acquisition module 102 ; sorting module 104 ; repair module 106 ; main control device 202 ; storage device 204 ; storage die 302 ; control die 304 ; storage group 400 ; storage module 402 ; redundant loading device 404 ; control device 406 . DETAILED DESCRIPTION

[0056] To facilitate understanding of the embodiments of the present application, a more comprehensive description of the embodiments of the present application will be provided below with reference to the accompanying drawings. The accompanying drawings provide preferred embodiments of the embodiments of the present application. However, the embodiments of the present application can be implemented in many different forms and are not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive disclosure of the embodiments of the present application.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the embodiments of the present application pertain. The terms used herein in the description of the embodiments of the present application are intended only to describe specific embodiments and are not intended to limit the embodiments of the present application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0058] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inside", "outside", etc., indicating orientations or positional relationships, are based on the methods or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0059] It should be understood that the terms "first," "second," and the like used herein may be used to describe various elements herein, but these elements are not limited by these terms. These terms are used solely to distinguish a first element from another element. For example, a first signal line may be referred to as a second signal line, and similarly, a second signal line may be referred to as a first signal line, without departing from the scope of this application. The first signal line and the second signal line are both signal lines, but they are not the same signal line.

[0060] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the description of this application, the meaning of "several" is at least one, such as one, two, etc., unless otherwise clearly and specifically defined.

[0061] Figure 1 This is one of the structural diagrams of the storage device in the embodiment of the present application, see Figure 1 The memory device includes a memory array and a redundant memory array; wherein the memory array includes word lines (WL) and bit lines (BL), one of the word lines and the bit lines extends along a first direction X, and the other extends along a second direction Y intersecting the first direction X, and the memory cell is located at the intersection of the word line and the bit line on the plane (for ease of explanation, Figure 1 Indicated by a black dot in the figure, the intersection position is a virtual position). " shows a failed memory cell in a memory array; the redundant memory array includes redundant word lines (YWL) and redundant bit lines (YBL), the redundant word lines and word lines extend in the same direction, and the redundant bit lines and bit lines extend in the same direction. Figure 1 The redundant memory cells in the CMOS are located at the intersection of the redundant word lines and bit lines on the plane ( Figure 1 The intersection is shown as a black dot in the figure (the intersection is a virtual location), and the intersection of the redundant bit line and the word line on the plane. The redundant memory cells in the redundant memory array are used to repair failed memory cells in the memory array. As an example, the word line extends along a first direction X, and multiple word lines are arranged at intervals along a second direction Y. The bit line extends along the second direction Y, and multiple bit lines are arranged at intervals along the first direction X. As an example, Figure 1 For example, a memory array includes n word lines WL0 ˜WLn-1 and a bit lines BL0 ˜BLa-1, and a redundant memory array includes m redundant word lines YWL0 ˜YWLm-1 and b redundant bit lines YBL0 ˜YBLb-1.

[0062] It can be understood that when the redundant memory cells in the redundant memory array repair the failed memory cells in the memory array, the signal line addresses of the word lines and / or bit lines are mapped to the redundant word lines and / or the redundant signal line addresses of the redundant word lines, so that the redundant memory cells in the redundant memory array repair the failed memory cells in the memory array.

[0063] Figure 2 This is one of the flowcharts of the method for repairing a storage device according to the embodiment of the present disclosure, see Figure 2 In this embodiment, a method for repairing a storage device is provided, the method comprising:

[0064] S102: Determine a plurality of first signal lines and corresponding first quantities in a memory array.

[0065] A storage array includes storage cells. Data is written to and read from each storage cell of the storage array. If the read data matches the written data, the storage cell is considered normal. If the read data matches the written data, the storage cell is considered faulty. A faulty storage cell is an abnormal storage cell that needs to be repaired.

[0066] Data is written and read from all memory cells in a memory array to obtain failed memory cells. Based on the failed memory cells, a plurality of first signal lines connected to the failed memory cells and a first number ebit cnt corresponding to each first signal line are obtained, that is, the plurality of first signal lines in the memory array having failed memory cells and the first number of failed memory cells on each first signal line are determined. The first signal lines extend along a first direction, and the plurality of first signal lines are arranged at intervals. Furthermore, the plurality of first signal lines are arranged at intervals in a second direction, and the second direction intersects the first direction.

[0067] It can be understood that the first signal line is a word line or a bit line in the memory array, the first redundant signal line is a redundant bit line and / or a redundant word line, and further, the first signal line is a word line, and the first redundant signal line is a redundant word line.

[0068] The repair method for a storage device of the present application is described as an example, assuming that the first signal line is a word line and the first direction is the extension direction of the word line. The number of failed memory cells on the word line is determined. If the number of failed memory cells on the word line is not zero, the word line is marked as a first signal line, and the number of failed memory cells on the word line is used as the first number ebit cnt corresponding to the first signal line. Furthermore, if the number of failed memory cells on the word line is zero, it is assumed that no failed memory cells exist on the word line, and the word line is marked as a second signal line.

[0069] Specifically, after writing data to multiple memory cells on a word line, the data in the multiple memory cells on the word line are read separately. The memory cells whose read data are inconsistent with the written data are counted. The value obtained by the count is the number of failed memory cells on the word line. If the number of failed memory cells on the word line is not zero, the word line is marked as a first signal line, and the number of failed memory cells on the word line is used as the first number ebitcnt corresponding to the first signal line. According to the above method, the number of failed memory cells on each word line in the memory array is determined separately, and multiple first signal lines in the memory array and the first number corresponding to each first signal line are obtained. Figure 1 After writing data to a memory cells on word line WL0, the data in the a memory cells on word line WL0 are read separately. The memory cells whose read data do not match the written data are counted. The counted value is the number of failed memory cells on word line WL0. If the number of failed memory cells on word line WL0 is not zero, word line WL0 is marked as a first signal line, and the number of failed memory cells on word line WL0 is used as the first number ebit cnt corresponding to the first signal line. According to the above method, the number of failed memory cells on word lines WL1 to WLn-1 is determined respectively, and multiple first signal lines in the memory array having failed memory cells and the first number ebit cnt corresponding to each first signal line are obtained.

[0070] by Figure 1For example, the number of failed memory cells on the word line WL0 is 2, and the number 2 of failed memory cells on the word line WL0 is greater than 0. It is determined that the word line WL0 is the first signal line, and the first number ebit cnt corresponding to the first signal line is 2; the number of failed memory cells on the word line WL1 is 4, and the number 4 of failed memory cells on the word line WL1 is greater than 0. It is determined that the word line WL1 is the first signal line, and the first number ebit cnt corresponding to the first signal line is 4; the number of failed memory cells on the word line WL2 is 3, and the number 3 of failed memory cells on the word line WL2 is greater than 0. It is determined that the word line WL2 is the first signal line, and the first number ebit cnt corresponding to the first signal line is 3; the number of failed memory cells on the word line WL3 is 2, and the number 2 of failed memory cells on the word line WL3 is greater than 0. It is determined that the word line WL3 is the first signal line, and the first number ebit cnt corresponding to the first signal line is cnt is 2; the number of failed memory cells on word line WL4 is 0, determining that word line WL4 is the second signal line, ..., the number of failed memory cells on word line WLn-1 is 1, and the number 1 of failed memory cells on word line WLn-1 is greater than 0, determining that word line WLn-1 is also the first signal line, and the first number ebit cnt corresponding to the first signal line is 1. Assuming that the number of failed memory cells on word lines WL5 to WLn-2 is 0, word lines WL5 to WLn-2 are determined to be second signal lines; five first signal lines (word line WL0, word line WL1, word line WL2, word line WL3, and word line WLn-1) among the n word lines are obtained, as well as a first quantity ebit cnt corresponding to each first signal line (the first quantity ebit cnt corresponding to word line WL0 is 2, the first quantity ebit cnt corresponding to word line WL1 is 4, the first quantity ebit cnt corresponding to word line WL2 is 3, the first quantity ebit cnt corresponding to word line WL3 is 2, and the first quantity ebit cnt corresponding to word line WLn-1 is 1).

[0071] S104 , setting an arrangement order of signal line addresses of a plurality of first signal lines according to a first number of failed memory cells on each first signal line.

[0072] Signal line addresses of the plurality of first signal lines are sorted according to the first number of failed memory cells on each first signal line. The signal line addresses represent positions of the first signal lines in the memory array. After the memory array is formed, the signal line addresses of the first signal lines remain fixed.

[0073] Compared with the process of sorting the signal line addresses of all word lines according to the number of failed memory cells on all word lines of the storage array and screening out the first signal line with failed memory cells in the word line, the number of signal line addresses of the word lines that need to be sorted is reduced. Subsequently, the signal line addresses of multiple first signal lines are sorted according to the first number of failed memory cells on each first signal line, which requires less data and shortens the sorting time, thereby improving the sorting efficiency of the signal line addresses.

[0074] It is understood that the signal line addresses of the first signal lines can be sorted in ascending order of the first number of failed memory cells on each first signal line, or can be sorted in descending order of the first number of failed memory cells on each first signal line. If the first number of failed memory cells on two first signal lines is the same, the order of the signal line addresses of the two first signal lines can be interchanged.

[0075] by Figure 3 For example, according to the first number ebit cnt (2) corresponding to word line WL0, the first number ebit cnt (4) corresponding to word line WL1, the first number ebit cnt (3) corresponding to word line WL2, the first number ebit cnt (2) corresponding to word line WL3 and the first number ebit cnt (1) corresponding to word line WLn-1, the arrangement order of the signal line addresses of word line WL0, word line WL1, word line WL2, word line WL3 and word line WLn-1 is set. Taking WL representing the signal line address of the word line WL, and arranging the first quantities corresponding to the signal line addresses of the word lines WL0, WL1, WL2, WL3, and WLn-1 as the first signal lines in ascending order as an example, the signal line addresses of the multiple first signal lines (word line WL0, WL1, WL2, WL3, and WLn-1) are arranged in the following order: WLn-1, WL0, WL3, WL2, WL1; wherein the first quantities ebit cnt corresponding to the word line WL0 and the word line WL3 are both 2, and therefore, the order of the signal line addresses of the word line WL0 and the word line WL3 can be interchanged. That is, the arrangement order of the signal line addresses of word line WL0, word line WL1, word line WL2, word line WL3 and word line WLn-1 is: WLn-1, WL0, WL3, WL2, WL1, or the arrangement order of the signal line addresses of word line WL0, word line WL1, word line WL2, word line WL3 and word line WLn-1 is: WLn-1, WL3, WL0, WL2, WL1.

[0076] S106 , according to the arrangement order of the signal line addresses of the plurality of first signal lines and a preset repair rule, using the first redundant signal lines in the redundant memory array to replace each first signal line to implement repair.

[0077] After signal line addresses of the plurality of first signal lines are sorted, first redundant signal lines in the remaining memory array are used to replace each first signal line according to the sorting of the signal line addresses and a preset repair rule, so that the redundant memory cells in the redundant memory array repair the failed memory cells on the first signal lines.

[0078] by Figure 1 For example, based on the signal line address order WLn-1, WL3, WL0, WL2, and WL1 of word line WL0, word line WL1, word line WL2, word line WL3, and word line WLn-1, and a preset repair rule, the first redundant signal line (redundant word line YWL0 to redundant word line YWLm-1, or / and redundant bit line YBL0 to redundant bit line YBLb-1) in the redundant memory array is used to replace each first signal line, thereby enabling the redundant memory cells in the redundant memory array to repair the failed memory cells on the first signal line. It is understood that the first redundant signal line can be a redundant word line or a redundant bit line. Furthermore, the first redundant signal line is a redundant word line.

[0079] It can be understood that the preset repair rule refers to the rule of replacing the first signal line with the redundant signal line in the redundant storage array. The failed storage units on the first signal line can be repaired sequentially according to the size of the first number corresponding to the signal line address of the first signal line, or the failed storage units on multiple first signal lines can be repaired simultaneously according to the size of the first number corresponding to the signal line address of the first signal line. This application does not limit this.

[0080] As an example, the preset repair rule is: according to the order from large to small of the first number of failed storage cells corresponding to the first signal line, the signal line address of the first signal line is mapped to the redundant signal line address of the redundant word line of the redundant storage array in sequence, and all storage cells on the first signal line are replaced by the redundant storage cells on the redundant word line to realize the repair of the failed storage cells on the first signal line.

[0081] The repair of failed storage units of a storage device enables the storage device to be used normally. For example, if the storage device repair method provided in the present application is applied to the test of the storage device before mass production, the pass rate and test rate of the mass production of the storage device can be improved; if the storage device repair method provided in the present application is applied to the repair of the storage device during normal operation, the time for each power-on repair can be shortened.

[0082] In the above-mentioned repair method for a storage device, a plurality of first signal lines and corresponding first quantities are determined in a storage array, where the first quantity is the number of failed storage cells on the first signal line, and the first quantity ebit cnt of failed storage cells on the first signal line is not 0. Based on the first quantity of failed storage cells on each first signal line, an arrangement order of signal line addresses of the plurality of first signal lines is set, thereby improving the sorting rate and efficiency of the signal line addresses of the first signal lines, reducing the sorting time of the signal line addresses of the first signal lines, and shortening the cycle for repairing failed storage cells.

[0083] In some embodiments, determining a plurality of first signal lines in a memory array and a corresponding first number ebitcnt includes traversing memory cells on each word line of the memory array to obtain a plurality of word lines (first signal lines) having failed memory cells and the first number ebitcnt corresponding to each word line. By screening the word lines in the memory array having failed memory cells and using them as first signal lines, and then sorting the word line addresses of the word lines having failed memory cells, the word line address sorting time of the word lines in the memory array can be reduced, thereby improving the word line address sorting efficiency of the word lines.

[0084] In some embodiments, determining a plurality of first signal lines in a memory array and a corresponding first number ebitcnt includes traversing memory cells on each bit line of the memory array to obtain a plurality of bit lines (first signal lines) containing failed memory cells and the first number ebitcnt corresponding to each bit line. By screening the bit lines in the memory array containing failed memory cells and using them as first signal lines, and then sorting the bit line addresses of the bit lines containing failed memory cells, the time required to sort the bit line addresses of the bit lines in the memory array can be reduced, thereby improving the efficiency of sorting the bit line addresses of the bit lines.

[0085] In some embodiments, setting an arrangement order of signal line addresses of a plurality of first signal lines based on a first number (ebit cnt) of failed memory cells on each first signal line includes: sorting the signal line addresses of the plurality of first signal lines based on the first number (ebit cnt) of failed memory cells on each first signal line based on a preset sorting method. The preset sorting method is a method for sorting the magnitude of the plurality of first numbers (ebit cnt) corresponding to the plurality of first signal lines. The preset sorting method is used to sort the plurality of first numbers (ebit cnt) corresponding to the plurality of first signal lines. The signal line addresses of the plurality of first signal lines correspond to the plurality of first numbers (ebit cnt) in a one-to-one manner. The signal line addresses corresponding to the first signal lines can be sorted based on the sorting of the first numbers (ebit cnt) corresponding to the first signal lines.

[0086] See also Figure 1, taking the first quantity ebit cnt corresponding to the signal line address as ascending order, and taking the first signal line as a word line as an example, obtain the first quantity ebit cnt of 2 corresponding to the word line WL0, the first quantity ebit cnt of 4 corresponding to the word line WL1, the first quantity ebit cnt of 3 corresponding to the word line WL2, the first quantity ebit cnt of 2 corresponding to the word line WL3, and the first quantity ebit cnt of 1 corresponding to the word line WLn-1; based on a preset sorting method, sort the first quantities ebit cnt of 2, 4, 3, 2, and 1 corresponding to the word line WL0, the word line WL1, the word line WL2, the word line WL3, and the word line WLn-1 in ascending order, respectively, to obtain the first quantities ebit cnt sorted as 1 2 2 3 4; according to the first quantities ebit cnt sorted as 1 2 2 3 4, sort the signal line addresses of the word lines corresponding to the first quantities ebit cnt to obtain the order WLn-1 WL0 WL3 WL2 WL1 or the order WLn-1 Signal line addresses of WL3, WL0, WL2, and WL1. In some embodiments, sorting the signal line addresses of the plurality of first signal lines based on a preset sorting method according to a first number (ebit cnt) of failed storage cells on each of the first signal lines includes sorting the signal line addresses of the plurality of first signal lines based on the first number (ebit cnt) of failed storage cells on each of the first signal lines based on a quick sorting method, a merge sorting method, or a bubble sorting method. Sorting the first number (ebit cnt) of failed storage cells on each of the first signal lines using different sorting methods diversifies the sorting methods of the signal line addresses and eliminates the impact of a single sorting method on the accuracy and efficiency of the signal line address sorting.

[0087] See also Figure 3, arranging the first quantity ebit cnt corresponding to the signal line address in descending order, taking the first signal line as a word line as an example, obtaining the first quantity ebit cnt corresponding to word line WL0=2, the first quantity ebit cnt corresponding to word line WL1=4, the first quantity ebit cnt corresponding to word line WL2=3, the first quantity ebit cnt corresponding to word line WL3=2, and the first quantity ebit cnt corresponding to word line WLn-1=1; based on a quick sorting method, a merge sorting method, or a bubble sorting method, sorting the first quantities ebit cnt corresponding to word line WL0, word line WL1, word line WL2, word line WL3, and word line WLn-1, which are 2, 4, 3, 2, and 1, respectively, in descending order, obtaining a first quantity ebit cnt sorted as 4 3 2 2 1; sorting the signal line addresses of the word lines corresponding to the first quantity ebit cnt according to the first quantity ebit cnt sorted as 4 3 2 2 1, obtaining a sorting order of WL1 WL2 WL0 WL3 WLn-1 or the signal line address in the order of WL1 WL2 WL3 WL0 WLn-1.

[0088] In some embodiments, sorting the signal line addresses of the plurality of first signal lines based on a preset sorting method and a first number (ebit cnt) of failed memory cells on each first signal line includes sorting the signal line addresses of the plurality of first signal lines based on the first number (ebit cnt) of failed memory cells on each first signal line based on a quick sorting method. The quick sorting method can further improve the efficiency of sorting the signal line addresses of the plurality of first signal lines in the memory array, thereby reducing the time required to sort the signal line addresses of the plurality of first signal lines in the memory array by more than 20 times.

[0089] See also Figure 3, taking the first quantity ebit cnt corresponding to the signal line address as arranged in descending order, and taking the first signal line as a word line as an example, obtain the first quantity ebit cnt corresponding to word line WL0=2, the first quantity ebit cnt corresponding to word line WL1=4, the first quantity ebit cnt corresponding to word line WL2=3, the first quantity ebit cnt corresponding to word line WL3=2, and the first quantity ebit cnt corresponding to word line WLn-1=1; based on the quick sorting method, sort the first quantities ebit cnt corresponding to word line WL0, word line WL1, word line WL2, word line WL3 and word line WLn-1 as 2, 4, 3, 2 and 1 respectively in descending order, and obtain the first quantities ebit cnt sorted as 4 3 2 21; according to the first quantity ebit cnt sorted as 4 3 2 2 1, sort the signal line addresses of the word lines corresponding to the first quantity ebit cnt, and obtain the sorting as WL1 WL2 WL0 WL3 WLn-1 or the sorting as WL1WL2 Signal line addresses of WL3 WL0 WLn-1.

[0090] In some embodiments, based on a preset sorting method, the signal line addresses of multiple first signal lines are sorted according to the first number ebit cnt of failed storage units on each first signal line, including: selecting the first signal line corresponding to the signal line address at the first, last or middle position in the sorting of the signal line addresses of the multiple first signal lines as the target signal line; using the first number ebit cnt corresponding to the target signal line as the reference number of the quick sorting method, and sorting the signal line addresses of the multiple first signal lines according to the first number ebit cnt of failed storage units on each first signal line, thereby simplifying the selection of the reference number in the quick sorting method.

[0091] The preset sorting includes ascending sorting, selecting the first signal line corresponding to the signal line address ranked first in the sorting of the signal line addresses of the plurality of first signal lines as the target signal line; using the first number ebitcnt corresponding to the target signal line as the reference number of the quick sorting method; obtaining the first signal line group and the second signal line group based on the reference number and the first number ebit cnt corresponding to the plurality of first signal lines, and arranging the signal line addresses of the first signal lines of the first signal line group to the left of the signal line addresses of the first signal lines of the second signal line group; wherein the first signal line group includes a plurality of first signal lines whose corresponding first number ebit cnt is less than or equal to the reference number, and the second signal line group includes a plurality of first signal lines whose corresponding first number is greater than the reference number; using the first signal line group and the second signal line group as new plurality of first signal lines, repeatedly performing the steps of selecting the first signal line corresponding to the signal line address ranked first in the sorting as the target signal line, and obtaining the first signal line group and the second signal line group, until the number of first signal lines in the new signal line group is less than or equal to the preset value, or the first number ebit cnt corresponding to the first signal line in the new signal line group is less than or equal to the preset value. cnt is the same, and the order of the signal line addresses of the first signal lines of each signal line group is used as the order of the signal line addresses of the plurality of first signal lines.

[0092] Figure 3 This is one of the schematic diagrams of sorting the signal line addresses of a plurality of first signal lines according to the first number of failed memory cells on each first signal line in an embodiment of the present application. In the figure, the signal line addresses corresponding to the first new signal line group on the left are sorted first until the number of first signal lines in the new signal line group is less than or equal to 1. Figure 1 and Figure 3, taking the first number ebit cnt corresponding to the signal line address as ascending order, and taking the word line as an example, the five first signal lines are word line WL0, word line WL1, word line WL2, word line WL3 and word line WLn-1. The initial order of the signal line addresses of word line WL0, word line WL1, word line WL2, word line WL3 and word line WLn-1 is WL0 (2) WL1 (4) WL2 (3) WL3 (2) WLn-1 (1). In the first step, the word line WL0 (first signal line) corresponding to the signal line address WL0 ranked first is selected as the target signal line; the first number ebit cnt corresponding to word line WL0, which is 2, is used as the reference number of the quick sorting method. In the second step, based on the reference number 2, starting from the first number ebit cnt of 4 corresponding to the second sorted signal line address WL1 in the initial sort, search from the left side to the right side for the first first number ebit cnt greater than the reference number 2, that is, the first number ebit cnt of 4 corresponding to WL1. Then, search from the right side to the left side for the first first number ebit cnt less than or equal to the reference number 2, that is, the first number ebit cnt of 1 corresponding to WLn-1. Then, the signal line addresses of the word line WL1 and the word line WLn-1 corresponding to 4 and 1 are swapped to obtain positions in the initial sort, until the first number ebit cnt from the left side to the right side and from the right side to the left side points to the same first number ebit cnt, or there is no first number ebit cnt that has not been compared with the reference number 2. cnt, obtain the first signal line group and the second signal line group, the first signal line group includes a number of first signal lines corresponding to a first number less than or equal to the reference number, the second signal line group includes a number of first signal lines corresponding to a first number greater than the reference number, that is, the first signal line group includes word line WLn-1, word line WL3 and word line WL0, the second signal line group includes word line WL2 and word line WL1, and the signal line address WL0 of word line WL0 corresponding to the reference number is arranged at the end of the signal line addresses corresponding to the number of first signal lines in the first signal line group. At this time, the signal line addresses of the 5 first signal lines in the first signal line group and the second signal line group are arranged as WLn-1 (1) WL3 (2) WL0 (2) WL2 (3) WL1 (4). In the third step, word lines WLn-1, WL3, and WL0 of the first signal line group, and word lines WL2 and WL1 of the second signal line group are respectively used as multiple new first signal lines. Steps 1 and 2 are repeated to perform recursive sorting until the number of first signal lines in the signal line group is less than or equal to 1, or the first numbers ebit cnt corresponding to the first signal lines in the signal line group are the same. The sorting of the signal line addresses of the first signal lines of each signal line group is used as the sorting of the signal line addresses of the multiple first signal lines, thus obtaining the signal line address sorting WLn-1 WL3 WL0 WL2 WL1 of word line WL0, word line WL1, word line WL2, word line WL3, and word line WLn-1.In some embodiments, based on a preset sorting method, signal line addresses of multiple first signal lines are sorted according to a first number (ebit cnt) of failed memory cells on each first signal line. This method includes: randomly selecting a target signal line from the multiple first signal lines; and using the first number corresponding to the target signal line as a reference number for a quick sorting method to sort the signal line addresses of the multiple first signal lines according to the first number of failed memory cells on each first signal line. This method further improves the efficiency of sorting the signal line addresses of the multiple first signal lines in a memory array. As an example, the srand random function is used to select the target signal line.

[0093] In some embodiments, the preset sorting includes ascending sorting, and signal line addresses of the plurality of first signal lines are sorted based on the preset sorting method according to a first number of failed memory cells on each first signal line, including: randomly selecting a target signal line from each first signal line; using the first number corresponding to the target signal line as a reference number; obtaining a first signal line group and a second signal line group based on the reference number and the first number ebit cnt of failed memory cells on each first signal line, and arranging the signal line addresses of each first signal line in the first signal line group to the left of the signal line addresses of each first signal line in the second signal line group; repeating the steps of randomly selecting the target signal line and obtaining the first signal line group and the second signal line group for the two signal line groups until the number of first signal lines in the signal line group is less than or equal to a preset value, or the first number of first signal lines in the signal line groups is the same, and using the sorting of the signal line addresses of each first signal line in each signal line group as the sorting of the signal line addresses of the plurality of first signal lines; wherein the first signal line group includes a plurality of first signal lines whose first number ebit cnt of failed memory cells is less than or equal to the reference number, and the second signal line group includes a plurality of first signal lines whose first number ebit cnt of failed memory cells is greater than the reference number.

[0094] Figure 4 This is a second schematic diagram of sorting the signal line addresses of a plurality of first signal lines according to the first number of failed memory cells on each first signal line in an embodiment of the present application; Figure 4 The left side ax is the target signal line, which means that the first signal line ax is randomly selected from the first new signal line group on the left side as the target signal line. The random selection can be generated by, for example, a random function srand to generate a random number x, where x is any integer between 0 and n, and n is the total number of first signal lines included in the new signal line group. It can be understood that x is Figure 4The new signal line group shown is the number of the array element instead of the signal line address of the first signal line (for example, the row address caddr of the word line WL). It is worth noting that because the signal lines with the number of failed storage cells being 0 account for the majority of all signal lines in the storage array, the signal line address of the first signal line is only a part of all signal line addresses extending in the first direction. In the figure, the signal line addresses corresponding to the first signal lines in the new signal line group on the left are prioritized to be sorted until the number of first signal lines in the new signal line group is equal to 1. It can be understood that when the first numbers of the first signal lines are the same, the signal line addresses corresponding to the first signal lines in the new signal line group on the left are prioritized to be sorted until the number of first signal lines in the new signal line group is equal to 1, or the first numbers of the first signal lines in the new signal line group are the same. See Figure 4 , taking the signal line address corresponding to the first signal line as an example with the first signal line identifier, the multiple first signal lines include 10 first signal lines, and a0 to a9 represent each first signal line. The corresponding relationship between the multiple first signal lines and the multiple first quantities is: a0 is 3, a1 is 1, a2 is 2, a3 is 7, a4 is 9, a5 is 6, a6 is 4, a7 is 5, a8 is 10, and a9 is 8. It is worth noting that, Figure 4The example in which the first numbers of the first signal lines are different is used for explanation, but the present invention is not limited to this. The first numbers of the first signal lines may also be the same, for example, the first numbers of a0 and a2 are both 3; the initial sorting of the signal line addresses of the multiple first signal lines is a0(3) a1(1) a2(2) a3(7) a4(9)a5(6) a6(4) a7(5) a8(10) a9(8); in the first step, the first signal line a5 is randomly selected as the target signal line, and the first number 6 corresponding to the first signal line a5 is the benchmark number of the quick sorting method. In the second step, based on the reference number 6, search for a first number greater than 6 from the left side to the right side of the first number corresponding to the first signal line of the initial sort, and search for a first number less than or equal to 6 from the right side to the left side of the first number corresponding to the first signal line of the initial sort; then, exchange the positions of the signal line addresses of the first signal lines corresponding to them in the initial sort; until the first number corresponding to the same first signal line is pointed to from the left side to the right side and from the right side to the left side, at this time, the order of the signal line addresses of each first signal line is a0(3) a1(1) a2(2) a7(5) a6(4) a5(6) a4(9) a3(7) a8(10) a9(8), and the initial order of the signal line addresses of each first signal line of the first signal line group is a0(3) a1(1) a2(2) a7(5) a6(4) a5(6), and the initial order of the signal line addresses of each first signal line of the second signal line group is a4(9) a3(7) a8(10) a9(8), the signal line addresses of each first signal line of the first signal line group are arranged on the left side of the signal line addresses of each first signal line of the second signal line group. In the third step, the first signal line group and the second signal line group are respectively used as new multiple signal lines, and the first and second steps are repeated; wherein, when the signal line addresses corresponding to the first signal lines are not exchanged, the order of the signal line addresses corresponding to the first signal lines remains unchanged; until the number of first signal lines in the obtained signal line group is equal to 1, the order of the signal line addresses of each first signal line of each signal line group is used as the order of the signal line addresses of the multiple first signal lines, that is, the order of the signal line addresses of the multiple first signal lines is a1(1) a2(2) a0(3) a6(4) a7(5) a5(6) a3(7) a9(8)a4(9) a8(10).

[0095] In some embodiments, the repair method of a storage device further includes: determining that on multiple second signal lines in a storage array, the number of failed storage cells on the second signal line is 0, and the second signal line is parallel to the first signal line; before setting the arrangement order of the signal line addresses of the multiple first signal lines, the signal line addresses of the multiple second signal lines are arranged as a whole on one side of the signal line addresses of the multiple first signal lines, thereby completing the sorting of the signal line addresses of the first signal lines and the second signal lines extending along the first release direction in the storage array.

[0096] It should be understood that although Figure 2 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 2 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0097] Based on the same inventive concept, the present application also provides a storage device repair system, and the parts that are the same as or corresponding to the embodiments of the above-mentioned storage device repair method will not be described in detail below. Figure 5 This is one of the structural diagrams of the repair system of the storage device in the embodiment of the present disclosure, see Figure 5 In this embodiment, a repair system for a storage device is provided. The storage device includes a storage array and a redundant storage array. The repair system includes: an acquisition module 102 , a sorting module 104 , and a repair module 106 .

[0098] The acquisition module 102 is used to determine multiple first signal lines in the storage array and the corresponding first number ebitcnt; the first number ebitcnt is the number of failed storage cells on the first signal line, and the first number ebitcnt of failed storage cells on the first signal line is not 0; the first signal line extends along a first direction, and the multiple first signal lines are arranged at intervals.

[0099] The sorting module 104 is connected to the acquiring module 102 and is configured to set a sorting order of the signal line addresses of the plurality of first signal lines according to a first number ebit cnt of failed storage cells on each first signal line.

[0100] The repair module 106 is connected to the sorting module 104 and is configured to replace each first signal line with a first redundant signal line in the redundant memory array to repair the first signal lines according to the sorting order of the signal line addresses of the first signal lines and a preset repair rule.

[0101] In the repair system of the above-mentioned storage device, the acquisition module 102 determines that there are multiple first signal lines of failed storage cells in the storage array, and the sorting module 104 sets the arrangement order of the signal line addresses of the multiple first signal lines according to the first number of failed storage cells on each first signal line, thereby improving the sorting rate and sorting efficiency of the signal line addresses of the first signal lines, reducing the sorting time of the signal line addresses of the first signal lines, and shortening the cycle of the repair module 106 to repair the failed storage cells.

[0102] Based on the same inventive concept, the present application also provides a storage device repair system. Parts identical or corresponding to the above-mentioned storage device repair method embodiments will not be described in detail below. Figure 6 This is the second structural diagram of the repair system of the storage device in the embodiment of the present disclosure, see Figure 6 In this embodiment, a storage device repair system is provided, including: a main control device 202 and a storage device 204.

[0103] The storage device 204 is connected to the main control device 202. The storage device 204 includes: a storage die 302; the storage die 302 includes at least one storage module 402, and the storage module 402 includes a storage array and a redundant storage array. The main control device 202 is connected to the storage die 302 and is used to obtain failure storage information of a failed storage cell in the storage array and execute the above-mentioned storage device repair method based on the failure storage information to generate repair information. The failure storage information represents the location information of the failed storage cell in the storage array; the repair information includes the corresponding information of the first redundant signal line and each first signal line in the redundant storage array. For example, the main control device 202 can be the host computer of a test machine, or it can be packaged together with the storage device 204 to form a memory, with the main control device 202 serving as the main chip in the memory.

[0104] In the repair system of the above-mentioned storage device, during the process of generating repair information, the main control device 202 first obtains multiple first signal lines and corresponding first quantities ebitcnt of failed storage units in the storage array based on the failed storage information, and sets an arrangement order of signal line addresses of the multiple first signal lines based on the first quantity ebitcnt of failed storage units on each first signal line. Since only the signal line addresses of the first signal lines whose first quantity of failed storage units is not 0 are sorted, the sorting rate and efficiency of the signal line addresses of the first signal lines are improved, the sorting time of the signal line addresses of the first signal lines is reduced, and the time it takes for the main control device 202 to generate repair information is shortened.

[0105] Figure 7 This is the third structural diagram of the repair system of the storage device in the embodiment of the present disclosure, see Figure 7 In some embodiments, the storage device 204 further includes a control die 304. The control die 304 is connected to the main control device 202 and the storage die 302, respectively, and is configured to generate a repair signal based on the repair information. The storage die 302 is configured to replace each first signal line with a first redundant signal line of the redundant storage array to implement repair based on the repair signal. It is understood that the storage die 302 maps the signal line address of the first signal line to the redundant signal line address corresponding to the redundant storage unit based on the repair signal.

[0106] Figure 8 This is a fourth structural diagram of the repair system for the storage device according to the embodiment of the present disclosure, see Figure 8 In some embodiments, the control die 304 includes a redundancy loader 404 and a control device (RTL IP) 406. The redundancy loader 404 is connected to the main control device 202 and the control device 406, respectively, and the control device 406 is connected to the storage module 402. The redundancy loader 404 is used to generate a repair control signal based on the repair information, and the control device 406 is used to output a corresponding repair signal to the connected storage module 402 based on the repair control signal output by the connected redundancy loader 404.

[0107] Figure 9 This is the fifth structural diagram of the repair system of the storage device in the embodiment of the present disclosure, see Figure 9In some embodiments, the storage die 302 includes a storage group 400, and the storage group 400 includes multiple storage modules 402; the control die 304 includes: a redundant loading device 404 and a control device 406; the redundant loading device 404 is connected to the main control device 202 and the control device 406 respectively, and the control device 406 is correspondingly connected to the storage group 400; the redundant loading device 404 is used to generate a repair control signal according to the repair information, and the control device 406 is used to output a corresponding repair signal to the multiple storage modules 402 of the connected storage group 400 according to the repair control signal output by the connected redundant loading device 404.

[0108] Figure 10 This is the sixth structural diagram of the repair system of the storage device in the embodiment of the present disclosure, see Figure 10 In some embodiments, the memory die 302 includes a plurality of memory groups 400 , each memory group 400 includes a plurality of memory modules 402 ; the control die 304 includes a redundant loading device 404 and a plurality of control devices 406 .

[0109] The redundant loading device 404 is connected to the main control device 202 and multiple control devices 406 respectively, and the multiple control devices 406 are respectively connected to the multiple storage groups 400; the redundant loading device 404 is used to generate multiple repair control signals according to the repair information; the multiple repair control signals correspond to the multiple control devices 406 respectively; the control device 406 is used to output corresponding repair signals to the multiple storage modules 402 of the connected storage group 400 according to the repair control signals output by the connected redundant loading device 404.

[0110] The redundant loading device 404 generates a plurality of repair control signals according to the repair information output by the main control device 202, and transmits the plurality of repair control signals to the redundant latch (RDN LATCH) of the corresponding control device (RTL IP) 406 according to the first control information; wherein the first control information includes the first address information RTL_IP_ID representing the address of the control device 406, the first switch information RDN_LDEN for controlling the opening and closing of the redundant loading device 404, and the second switch information for controlling the storage and stopping of the repair control signal; the redundant loading device 404 is used to transmit the repair control signal to the control device 406 corresponding to the first address information RTL_IP_ID according to the first address information RTL_IP_ID when the first switch information RDN_LDEN and the second switch information are simultaneously valid; illustratively, the first switch information is valid when the first switch information is a high level 1, and the second switch information is valid when the second switch information is a high level 1.

[0111] As an example, the second switch information includes row switch information RDN_ROWEN and column switch information RDN_COLEN; the redundant loading device 404 is used to store the row repair information in the redundant latch (RDN LATCH) of the control device (RTL IP) 406 corresponding to the first address information RTL_IP_ID when the first switch information RDN_LDEN and the row switch information RDN_ROWEN are both valid; the redundant loading device 404 is also used to store the column repair information in the redundant latch (RDN LATCH) of the control device (RTL IP) 406 corresponding to the first address information RTL_IP_ID when the first switch information RDN_LDEN and the column switch information RDN_COLEN are both valid. The repair information includes row repair information and column repair information. The row repair information includes a mapping relationship between a redundant word line address corresponding to a redundant memory cell for repairing a failed memory cell in the redundant memory array and a word line address corresponding to the failed memory cell on each first signal line. The redundant word line address is an address of a redundant word line corresponding to the redundant memory cell, and the word line address is an address of a word line corresponding to the failed memory cell. The column repair information includes a mapping relationship between a redundant bit line address corresponding to a redundant memory cell for repairing a failed memory cell in the redundant memory array and a bit line address corresponding to the failed memory cell on each first signal line. The redundant bit line address is an address of a redundant bit line corresponding to the redundant memory cell, and the bit line address is an address of a bit line corresponding to the failed memory cell.

[0112] The control device (RTL IP) 406 outputs a repair signal based on a control instruction and a repair control signal; wherein the control instruction includes at least one of a read instruction, a write instruction, and a refresh instruction; the control device 406 outputs a repair signal based on the control instruction and the repair control signal when the bit line address and / or word line address of the storage unit corresponding to the control instruction matches (is the same as) the bit line address and / or word line address of the failed storage unit.

[0113] Exemplarily, multiple memory groups 400 in a memory die 302 are located on the same wafer. Furthermore, multiple memory modules 402 in a memory group 400 in a memory die 302 are located on multiple wafers arranged in a stacked manner. In some embodiments, the control die 304 further includes a test module; the test module is connected to the main control device 202 and the memory die 302, and is configured to receive test information output by the main control device 202; the main control device 202 is configured to receive failure memory information generated by the memory module 402 in the memory die 302 based on the test information.

[0114] Furthermore, the test module has a BIST circuit, and the test module and the control device are packaged together to form a buffer die in the control die 304 .

[0115] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the above-described method embodiments. Any reference to memory, storage, database, or other media used in the embodiments provided herein may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0116] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0117] The above-described embodiments merely represent several implementation methods of the embodiments of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that a person skilled in the art may make various modifications and improvements without departing from the concept of the embodiments of the present application, and these modifications and improvements fall within the scope of protection of the embodiments of the present application.

Claims

1. A method for repairing a storage device, characterized in that: The storage device includes a storage array and a redundant storage array, and the repair method includes: Determining a plurality of first signal lines in the memory array and a corresponding first number; wherein the first number is the number of failed memory cells on the first signal line, and the first number of failed memory cells on the first signal line is not zero; the first signal lines extend along a first direction, and the plurality of first signal lines are arranged at intervals; setting an arrangement order of signal line addresses of a plurality of first signal lines according to a first number of the failed storage units on each of the first signal lines; According to the arrangement order of the signal line addresses of the plurality of first signal lines and a preset repair rule, the first redundant signal lines in the redundant memory array are used to replace each first signal line to achieve repair; Among them, determining multiple first signal lines and corresponding first quantities in the storage array includes: determining the number of failed storage cells on all signal lines extending along the first direction, and when the number of failed storage cells on a signal line is not 0, marking the signal line as a first signal line, and taking the number of failed storage cells on the signal line as the first quantity corresponding to the first signal line.

2. The repair method according to claim 1, characterized in that: The step of setting an arrangement order of signal line addresses of a plurality of first signal lines according to a first number of failed storage units on each of the first signal lines comprises: Based on a preset sorting method, signal line addresses of the plurality of first signal lines are sorted according to a first number of failed storage units on each of the first signal lines.

3. The repair method according to claim 2, characterized in that: The method of sorting the signal line addresses of the plurality of first signal lines based on a preset sorting method according to a first number of failed storage units on each of the first signal lines includes: Based on a quick sort method, a merge sort method or a bubble sort method, signal line addresses of the plurality of first signal lines are sorted according to a first number of failed storage units on each of the first signal lines.

4. The repair method according to claim 2, characterized in that: The method of sorting the signal line addresses of the plurality of first signal lines based on a preset sorting method according to a first number of failed storage units on each of the first signal lines includes: Selecting a target signal line from the plurality of first signal lines by a random selection method; Taking the first number corresponding to the target signal lines as a reference number of a quick sorting method; A first signal line group and a second signal line group are obtained based on the reference number and the first number of failed memory cells on each of the first signal lines, and the signal line address of each of the first signal lines in the first signal line group is arranged to the left of the signal line address of each of the first signal lines in the second signal line group; the first signal line group includes a plurality of first signal lines whose first number of failed memory cells is less than or equal to the reference number, and the second signal line group includes a plurality of first signal lines whose first number of failed memory cells is greater than the reference number; Repeat the steps of randomly selecting target signal lines and obtaining the first signal line group and the second signal line group for the two signal line groups until the number of first signal lines in the new signal line group is less than or equal to a preset value, or the first numbers of the first signal lines in the new signal line group are the same; and use the order of the signal line addresses of the first signal lines of each signal line group as the order of the signal line addresses of the multiple first signal lines.

5. The repair method according to claim 4, characterized in that: The first number of failed storage units on each of the first signal lines is different, and the steps of repeatedly performing the steps of randomly selecting a target signal line and obtaining a first signal line group and a second signal line group on the two signal line groups include: The signal line addresses corresponding to the first signal lines in the new signal line group on the left are sorted until the number of the first signal lines in the new signal line group is equal to one.

6. The repair method according to claim 4, characterized in that: There are at least two first signal lines with the same first number of failed storage cells, and the steps of repeatedly performing the steps of randomly selecting target signal lines and obtaining the first signal line group and the second signal line group on the two signal line groups include: The signal line addresses corresponding to the first signal lines in the new signal line group on the left are sorted until the number of first signal lines in the new signal line group is equal to 1, or the first numbers of the first signal lines in the new signal line group are the same.

7. The repair method according to claim 1, characterized in that: Also includes: Determining a plurality of second signal lines in the memory array, wherein the number of the failed memory cells on the second signal lines is 0; The second signal line is parallel to the first signal line; Before setting the arrangement order of the signal line addresses of the plurality of first signal lines, the signal line addresses of the plurality of second signal lines are arranged as a whole on one side of the signal line addresses of the plurality of first signal lines.

8. The repair method according to claim 1, characterized in that: The first signal line is a word line.

9. A storage device repair system, characterized in that: The storage device includes a storage array and a redundant storage array, and the repair system includes: an acquisition module, configured to determine a plurality of first signal lines in the memory array and a corresponding first number; the first number being the number of failed memory cells on the first signal line, the first number of failed memory cells on the first signal line being non-zero; the first signal lines extending along a first direction, the plurality of first signal lines being arranged at intervals; a sorting module connected to the acquisition module, and configured to set a sorting order of signal line addresses of a plurality of first signal lines according to a first number of failed storage units on each of the first signal lines; a repair module connected to the sorting module, configured to replace each of the first signal lines with a first redundant signal line in the redundant memory array to perform repair according to the sorting order of the signal line addresses of the plurality of first signal lines and a preset repair rule; Among them, the acquisition module is also used to determine the number of failed storage units on all signal lines extending along the first direction. When the number of failed storage units on a signal line is not 0, the signal line is marked as a first signal line, and the number of failed storage units on the signal line is used as the first quantity corresponding to the first signal line.

10. A storage device repair system, characterized in that: include: Main control device; A storage device connected to the main control device, the storage device comprising: A memory die, comprising at least one memory module, wherein the memory module comprises a memory array and a redundant memory array; The main control device is connected to the storage chip and is used to obtain failure storage information of the failed storage unit of the storage array, and execute the repair method of the storage device according to any one of claims 1 to 6 according to the failure storage information to generate repair information, wherein the repair information includes the first redundant signal line and corresponding information of each first signal line in the redundant storage array.

11. The repair system according to claim 10, characterized in that: The storage device further includes: a control chip, connected to the main control device and the storage chip respectively, and used to generate a repair signal according to the repair information; The memory chip is used to replace each of the first signal lines with a first redundant signal line according to the repair signal to achieve repair.

12. The repair system according to claim 11, characterized in that The storage die includes a plurality of storage groups, each of which includes a plurality of storage modules; the control die includes a redundant loading device and a plurality of control devices, the redundant loading devices are respectively connected to the main control device and the plurality of control devices, and the plurality of control devices are respectively connected to the plurality of storage groups; The redundant loading device is used to generate a plurality of repair control signals according to the repair information; the plurality of repair control signals respectively correspond to the plurality of control devices; The control device is used to output corresponding repair signals to the multiple storage modules of the connected storage group according to the repair control signal output by the connected redundant loading device.

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