Display device

Abstract

A display device according to one embodiment of the present invention includes pixels arranged in a display. The pixel includes: a first electrode extending in a first direction; a second electrode including a first electrode unit separated from the first electrode in a direction intersecting the first direction and extending in the first direction, a second electrode unit extending from the first electrode unit in a second direction, and a third electrode unit, the third electrode unit extends from the second electrode unit in the first direction; a third electrode, at least one region of which is separated from the third electrode unit in a direction intersecting the first direction, and which extends in the first direction; a first light emitting element connected between the first electrode and the second electrode; and a second light emitting element connected between the second electrode and the third electrode.

Description

[0001] This application is a divisional application of a patent application with an application date of July 9, 2019, an application number of 201980088981.0, and an invention title of "Display Device". Technical Field

[0002] Embodiments of the present disclosure relate to a display device. Background Art

[0003] Recently, technologies for manufacturing ultra-small light-emitting elements using materials having a reliable inorganic crystal structure and technologies for manufacturing light-emitting devices using such light-emitting elements have been developed. For example, technologies for manufacturing a plurality of ultra-small light-emitting elements having small sizes corresponding to a range from the nanoscale to the micrometer scale and technologies for using the ultra-small light-emitting elements as light sources for forming various light-emitting devices (e.g., pixels of a display device) have been developed. Summary of the Invention

[0004] Technical Problem

[0005] An object of the present disclosure is to provide a display device including a light-emitting element.

[0006] Technical Solution

[0007] A display device according to an embodiment of the present disclosure may include pixels disposed in a display area. The pixel may include: a first electrode extending in a first direction; a second electrode including a first electrode portion, a second electrode portion, and a third electrode portion, the first electrode portion being spaced apart from the first electrode in a direction crossing the first direction and extending in the first direction, the second electrode portion extending from the first electrode portion in a second direction, and the third electrode portion extending from the second electrode portion in the first direction; a third electrode including at least one region spaced apart from the third electrode portion in a direction crossing the first direction and extending in the first direction; a first light-emitting element connected between the first electrode and the second electrode; and a second light-emitting element connected between the second electrode and the third electrode.

[0008] In an embodiment, the second electrode portion may be disposed between the first electrode and the third electrode.

[0009] In an embodiment, the first electrode may be spaced apart from the first electrode portion with respect to the second direction. The third electrode may be spaced apart from the third electrode portion with respect to the second direction.

[0010] In an embodiment, at least one region of the third electrode and the first electrode may be disposed at positions spaced apart from each other on a straight line with respect to the first direction. The first electrode portion and the third electrode portion may be disposed on a straight line with respect to the first direction.

[0011] In an embodiment, the first electrode and the third electrode portion may be disposed at positions spaced apart from each other in a line with respect to a first direction. At least one region of the third electrode and the first electrode portion may be disposed at positions spaced apart from each other in a line with respect to the first direction.

[0012] In an embodiment, the first light-emitting element may include a P-type end electrically connected to the first electrode and an N-type end electrically connected to the second electrode. The second light-emitting element may include a P-type end electrically connected to the second electrode and an N-type end electrically connected to the third electrode.

[0013] In an embodiment, the display device may further include: a first electrode line electrically connected to the first electrode and configured to be supplied with a first power voltage or a first driving signal; and a second electrode line electrically connected to the third electrode and configured to be supplied with a second power voltage or a second driving signal.

[0014] In an embodiment, the display device may further include: a third light-emitting element including a P-type end electrically connected to the third electrode and an N-type end opposite to the P-type end; and a fourth electrode electrically connected between the N-type end of the third light-emitting element and the second electrode line.

[0015] A display device according to an embodiment of the present disclosure may include a first pixel, the first pixel including a light-emitting element disposed in a plurality of series stages. The first pixel may include: first sub-regions to K-th sub-regions respectively corresponding to the first series stage to the K-th series stage, where K is a natural number of 2 or greater; a first electrode and a second electrode of each series stage in the plurality of series stages, disposed at positions spaced apart from each other in each of the first sub-regions to the K-th sub-regions; first light-emitting elements to K-th light-emitting elements respectively connected between the first electrode and the second electrode in the first sub-regions to the K-th sub-regions; a first electrode line connected to the first electrode of the first sub-region; a second electrode line connected to the second electrode of the K-th sub-region; and at least one intermediate electrode disposed between two consecutive sub-regions of the first sub-regions to the K-th sub-regions and connected to the second electrode of the previous sub-region and the first electrode of the subsequent sub-region. The intermediate electrode may extend in a direction crossing the direction in which the first electrode and the second electrode extend.

[0016] In an embodiment, the first electrode line and the second electrode line may be disposed to face each other, and the first sub-regions to the K-th sub-regions may be disposed between the first electrode line and the second electrode line. Each of the first electrode line and the second electrode line may extend in a direction crossing the direction in which the first electrode and the second electrode extend.

[0017] In an embodiment, the first electrode line, the second electrode line, and the intermediate electrode may be disposed parallel to each other, and at least one sub-region may be disposed between the first electrode line, the second electrode line, and the intermediate electrode.

[0018] In an embodiment, the first sub-region to the Kth sub-region may be continuously arranged in a first direction. The intermediate electrode may extend between two consecutive sub-regions in a second direction intersecting the first direction.

[0019] In an embodiment, the first electrode and the second electrode may extend in the first direction and may be arranged parallel to each other in each of the first sub-region to the Kth sub-region.

[0020] In an embodiment, the first electrode and the second electrode may be arranged at regular intervals in each of the first sub-region to the Kth sub-region.

[0021] In an embodiment, the intermediate electrode may be integrally connected to the second electrode of the previous sub-region and the first electrode of the subsequent sub-region.

[0022] In an embodiment, the intermediate electrode may have a width smaller than the width of each of the first electrode line and the second electrode line.

[0023] In an embodiment, the first electrode line may be supplied with a first power voltage or a first driving signal. The second electrode line may be supplied with a second power voltage or a second driving signal.

[0024] In an embodiment, the first pixel may further include a pixel circuit connected between the first electrode line and a first power supply that supplies the first power voltage.

[0025] In an embodiment, the first electrode and the second electrode may be arranged in the same repeating pattern in each of the first sub-region to the Kth sub-region.

[0026] In an embodiment, in two consecutive sub-regions, the first electrode and the second electrode may be arranged in a symmetric shape based on the intermediate electrode.

[0027] In an embodiment, the display device may further include a second pixel having the same structure as that of the first pixel and arranged adjacent to the first pixel. The first electrode line and the intermediate electrode of the first pixel and the second pixel may be separated from each other between the first pixel and the second pixel.

[0028] In an embodiment, the second electrode lines of the first pixel and the second pixel may be integrally connected to each other.

[0029] In an embodiment, the first pixel may further include at least one reverse light-emitting element, and at least one reverse light-emitting element is connected between the first electrode and the second electrode in at least one of a plurality of series stages in a direction opposite to the light-emitting element. The number of reverse light-emitting elements may be smaller than the number of light-emitting elements.

[0030] In an embodiment, the first pixel may further include at least one of the following elements: a first partition wall disposed under the corresponding first electrode; a second partition wall disposed under the corresponding second electrode; a first contact electrode disposed over the corresponding first electrode and configured to electrically connect a corresponding one of the first electrodes to a first end of at least one light-emitting element; and a second contact electrode disposed over the corresponding second electrode and configured to electrically connect a corresponding one of the second electrodes to a second end of at least one light-emitting element.

[0031] In an embodiment, the display device may further include a bank configured to integrally surround an emission region of the first pixel including a first sub-region to a K-th sub-region.

[0032] Advantageous Effects

[0033] In a display device including a pixel according to an embodiment of the present disclosure, light-emitting elements supplied to an emission region of each pixel can be effectively used to form each light source unit. In addition, the efficiency of power to be used for aligning the light-emitting elements can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1a and Figure 1b are a perspective view and a cross-sectional view, respectively, showing a light-emitting element according to an embodiment of the present disclosure.

[0035] Figure 2a and Figure 2b are a perspective view and a cross-sectional view, respectively, showing a light-emitting element according to an embodiment of the present disclosure.

[0036] Figure 3a and Figure 3b are a perspective view and a cross-sectional view, respectively, showing a light-emitting element according to an embodiment of the present disclosure.

[0037] Figure 4 is a plan view showing a display device according to an embodiment of the present disclosure.

[0038] Figures 5a to 5e are circuit diagrams each showing a pixel according to an embodiment of the present disclosure.

[0039] Figure 6 and Figure 7 are plan views each showing a pixel according to an embodiment of the present disclosure.

[0040] Figure 8 and Figure 9 are plan views each showing a pixel (e.g., modified embodiments related to embodiments of Figure 6 and Figure 7 respectively) according to an embodiment of the present disclosure.

[0041] Figures 10 to 13 are cross-sectional views each showing a pixel according to an embodiment of the present disclosure.

[0042] Figures 14a to 14c are plan views sequentially showing a method of manufacturing a display device according to an embodiment of the present disclosure.

[0043] Figure 15 and Figure 16 are plan views each showing a method of manufacturing a display device according to an embodiment of the present disclosure (e.g., showing different modified embodiments related to Figure 14a embodiments). Detailed Description

[0044] Now, various embodiments of the present disclosure will be described in detail. Since the embodiments of the present disclosure can be variously modified in many different forms, specific examples of the various embodiments of the present disclosure are shown in the drawings and described below. However, the present disclosure is not limited to the following embodiments and can be modified into various forms.

[0045] In the drawings, some elements not directly related to the features of the present disclosure may be omitted to clearly explain the present disclosure. In addition, the sizes, ratios, etc. of some elements in the drawings may be slightly exaggerated. It should be noted that, throughout the drawings, the same reference numerals are used to denote the same or similar elements, and repeated descriptions will be omitted.

[0046] It will be understood that, although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. It will also be understood that when the terms "comprising", "including", "having", etc. are used in this specification, it indicates the presence of the stated features, wholes, steps, operations, elements, components, and / or combinations thereof, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or combinations thereof. In addition, when a first component or part is disposed on a second component or part, the first component or part may not only be directly located on the second component or part, but also a third component or part may be located therebetween. In addition, the terms "position", "direction", etc. used in the following description are defined in relative terms, and it should be noted that they may be changed to opposite positions or directions according to the viewing angle or direction. In addition, as long as not specifically mentioned in the sentence, the singular form may also include the plural form.

[0047] Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a and Figure 3b are a perspective view and a cross-sectional view showing a light-emitting element LD according to an embodiment of the present disclosure. AlthoughFigures 1a to 3b A cylindrical rod-shaped light-emitting element LD is shown, but the type and / or shape of the light-emitting element LD according to the present disclosure are not limited thereto.

[0048] Referring to Figure 1a and Figure 1b The light-emitting element LD according to an embodiment of the present disclosure may include a first-conductive-type semiconductor layer 11 (also referred to as a "first semiconductor layer"), a second-conductive-type semiconductor layer 13 (also referred to as a "second semiconductor layer"), and an active layer 12 disposed between the first-conductive-type semiconductor layer 11 and the second-conductive-type semiconductor layer 13. For example, the light-emitting element LD may include the first-conductive-type semiconductor layer 11, the active layer 12, and the second-conductive-type semiconductor layer 13 continuously stacked in the longitudinal direction.

[0049] In an embodiment, the light-emitting element LD may be provided in the form of a rod extending in one direction. If the direction along which the light-emitting element LD extends is defined as the longitudinal direction, the light-emitting element LD may have a first end and a second end with respect to the longitudinal direction.

[0050] In an embodiment, one of the first-conductive-type semiconductor layer 11 and the second-conductive-type semiconductor layer 13 may be disposed on the first end of the light-emitting element LD. The other of the first-conductive-type semiconductor layer 11 and the second-conductive-type semiconductor layer 13 may be disposed on the second end of the light-emitting element LD.

[0051] In an embodiment, the light-emitting element LD may be a rod-shaped light-emitting diode manufactured in the form of a rod. In this specification, the term "rod-shaped" includes rod-like shapes such as cylindrical and prismatic shapes and strip shapes that extend in a longitudinal manner (i.e., having an aspect ratio greater than 1), and the cross-sectional shape thereof is not limited to a specific shape. For example, the length L of the light-emitting element LD may be greater than its diameter D (or the width of its cross-section).

[0052] In an embodiment, the light-emitting element LD may have a small size ranging from the nanoscale to the microscale. For example, each light-emitting element LD may have a diameter D and / or a length L ranging from the nanoscale to the microscale. However, in the present disclosure, the size of the light-emitting element LD is not limited thereto. For example, the size of the light-emitting element LD may be changed in various ways according to the design conditions of various devices (e.g., a display device that uses a light-emitting device using the light-emitting element LD as a light source).

[0053] The first-conductivity-type semiconductor layer 11 may include, for example, at least one N-type semiconductor layer. For example, the first-conductivity-type semiconductor layer 11 may include an N-type semiconductor layer including any one of semiconductor materials such as InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a first-conductivity dopant such as Si, Ge, or Sn. However, the material for forming the first-conductivity-type semiconductor layer 11 is not limited thereto, and the first-conductivity-type semiconductor layer 11 may be formed of various other materials.

[0054] The active layer 12 may be disposed on the first-conductivity-type semiconductor layer 11 and may have a single quantum well structure or a multi-quantum well structure. In an embodiment, a cladding layer (not shown) doped with a conductive dopant may be formed above and / or below the active layer 12. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. In an embodiment, a material such as AlGaN or AlInGaN may be used to form the active layer 12, and various other materials may be used to form the active layer 12.

[0055] If a voltage equal to or greater than a threshold voltage is applied to each of opposite ends of the light-emitting element LD, the light-emitting element LD may emit light through recombination of electron-hole pairs in the active layer 12. Since the light emission of the light-emitting element LD can be controlled based on the foregoing principle, the light-emitting element LD can be used as a light source for various light-emitting devices and pixels of a display device.

[0056] The second-conductivity-type semiconductor layer 13 may be disposed on the active layer 12 and may include a semiconductor layer having a type different from that of the first-conductivity-type semiconductor layer 11. For example, the second-conductivity-type semiconductor layer 13 may include at least one P-type semiconductor layer. For example, the second-conductivity-type semiconductor layer 13 may include a P-type semiconductor layer including any one of semiconductor materials such as InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a second-conductivity dopant such as Mg. However, the material for forming the second-conductivity-type semiconductor layer 13 is not limited thereto, and the second-conductivity-type semiconductor layer 13 may be formed of various other materials.

[0057] In an embodiment, the light-emitting element LD may further include an insulating film INF disposed on the surface of the light-emitting element LD. The insulating film INF may be formed on the surface of the light-emitting element LD to surround at least the outer circumferential surface of the active layer 12, and may further surround a predetermined region of the first conductive-type semiconductor layer 11 and the second conductive-type semiconductor layer 13. Here, the insulating film INF may allow opposite ends of the light-emitting element LD having different polarities to be exposed to the outside. For example, the insulating film INF may expose one end of each of the first conductive-type semiconductor layer 11 and the second conductive-type semiconductor layer 13 disposed on the respective opposite ends of the light-emitting element LD with respect to the longitudinal direction. For example, it may expose two base sides of a cylinder (in Figure 1a and Figure 1b , the top surface and the bottom surface of the light-emitting element LD) without covering the two base sides.

[0058] In an embodiment, the insulating film INF may include at least one insulating material such as silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), and titanium dioxide (TiO2), but is not limited thereto. In other words, the material forming the insulating film INF is not limited to a specific material, and the insulating film INF may be formed of various known insulating materials.

[0059] In an embodiment, in addition to the first conductive-type semiconductor layer 11, the active layer 12, the second conductive-type semiconductor layer 13, and / or the insulating film INF, the light-emitting element LD may further include additional other components. For example, the light-emitting element LD may further include one or more fluorescent layers, one or more active layers, one or more semiconductor layers, and / or one or more electrode layers disposed on one end of the first conductive-type semiconductor layer 11, the active layer 12, and / or the second conductive-type semiconductor layer 13.

[0060] For example, as Figure 2a and Figure 2b shown, the light-emitting element LD may further include at least one electrode layer 14 disposed on one end of the second conductive-type semiconductor layer 13. In an embodiment, as Figure 3a and Figure 3b shown, the light-emitting element LD may further include at least one electrode layer 15 disposed on one end of the first conductive-type semiconductor layer 11.

[0061] Each of the electrode layers 14 and 15 may be an ohmic contact electrode, but is not limited thereto. Each of the electrode layers 14 and 15 may include a metal or a metal oxide. For example, each of the electrode layers 14 and 15 may be formed of a transparent electrode material (such as chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), their oxides or alloys, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO)) alone or in combination. In an embodiment, the electrode layers 14 and 15 may be substantially transparent or translucent. Thus, the light generated from the light-emitting element LD can be emitted to the outside after passing through the electrode layers 14 and 15.

[0062] In an embodiment, the insulating film INF may at least partially surround the outer circumferential surfaces of the electrode layers 14 and 15, or may not surround the outer circumferential surfaces. In other words, the insulating film INF may be selectively formed on the surfaces of the electrode layers 14 and 15. In addition, the insulating film INF may be formed to expose the opposite ends of the light-emitting element LD having different polarities. For example, at least one region of each of the electrode layers 14 and 15 may be exposed. Optionally, in an embodiment, the insulating film INF may not be provided.

[0063] If the insulating film INF is provided on the surface of the light-emitting element LD, specifically, on the surface of the active layer 12, it is possible to prevent the active layer 12 from being short-circuited with at least one electrode (for example, at least one of the contact electrodes connected to the opposite ends of the light-emitting element LD) not shown. Therefore, the electrical stability of the light-emitting element LD can be ensured. In the description of each embodiment of the present disclosure, the term "connected (or coupled)" may generally refer to physical and / or electrical connection (or coupling). In addition, the term "connected (or coupled)" may generally refer to direct and / or indirect connection (or coupling) and integral or non-integral connection.

[0064] In addition, due to the insulating film INF formed on the surface of the light-emitting element LD, the occurrence of defects on the surface of the light-emitting element LD can be minimized, thereby improving the lifespan and efficiency of the light-emitting element LD. Additionally, if the insulating film INF is formed on each light-emitting element LD, even when a plurality of light-emitting elements LD are arranged adjacent to each other, it is possible to prevent the light-emitting elements LD from being undesirably short-circuited.

[0065] In an embodiment of the present disclosure, a surface treatment process may be performed to manufacture the light-emitting element LD. For example, each light-emitting element LD may be surface-treated so that when a plurality of light-emitting elements LD are mixed with a fluid solution (or solvent) and then supplied to each emission region (for example, the emission region of each pixel), the light-emitting elements LD can be uniformly dispersed rather than unevenly aggregated in the solution.

[0066] In a non-limiting embodiment related thereto, the insulating film INF itself may be formed of a hydrophobic film using a hydrophobic material, or an additional hydrophobic film formed of a hydrophobic material may be formed on the insulating film INF. In an embodiment, the hydrophobic material may be a fluorine-containing material to exhibit hydrophobicity. In an embodiment, the hydrophobic material may be applied to the light-emitting element LD in the form of a self-assembled monolayer (SAM). In this case, the hydrophobic material may include octadecyltrichlorosilane, fluoroalkyltrichlorosilane, perfluoroalkyltriethoxysilane, etc. In addition, the hydrophobic material may be a commercially available fluorine-containing material (such as Teflon TM or Cytop TM ) or a corresponding material.

[0067] The light-emitting device including the above-described light-emitting element LD can be used not only in a display device but also in various devices that require a light source. For example, at least one ultra-small light-emitting element LD (e.g., a plurality of ultra-small light-emitting elements LD each having a size ranging from the nanoscale to the microscale) may be disposed in each pixel region of the display panel to form a light source (or a light source unit) of the corresponding pixel using the ultra-small light-emitting element LD. In addition, the application field of the light-emitting element LD according to the present disclosure is not limited to a display device. For example, the light-emitting element LD can also be used in other types of devices that require a light source, such as a lighting device.

[0068] Figure 4 is a plan view showing a display device according to an embodiment of the present disclosure. In an embodiment, Figure 4 shows a display device, specifically, shows a display panel PNL provided in the display device, as an example of a device that can use the light-emitting element LD described with reference to Figures 1a to 3b as a light source. For example, each pixel unit PXU of the display panel PNL and each pixel for forming the pixel unit PXU may include a plurality of light-emitting elements LD.

[0069] For illustrative purposes, Figure 4 simply shows the structure of the display panel PNL according to an embodiment focused on the display area DA. In some embodiments, although not shown, at least one driving circuit (e.g., at least one of a scan driver and a data driver) and / or a plurality of lines may be further provided in the display panel PNL.

[0070] Referring to Figure 4, a display panel PNL according to an embodiment of the present disclosure may include a substrate layer BSL and a plurality of pixels disposed on the substrate layer BSL. In an embodiment, the pixels may include a first pixel PXL1 configured to emit light of a first color, a second pixel PXL2 configured to emit light of a second color, and / or a third pixel PXL3 configured to emit light of a third color. In the following embodiments, the term "pixel PXL" or "a plurality of pixels PXL" will be used to collectively refer to any one pixel or two or more pixels among the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3.

[0071] Specifically, the display panel PNL and the substrate layer BSL for forming the display panel PNL may include a display area DA for displaying an image and a non-display area NDA formed in a predetermined area other than the display area DA. The pixels PXL may be disposed in the display area DA on the substrate layer BSL.

[0072] In an embodiment, the display area DA may be disposed in a central area of the display panel PNL, and the non-display area NDA may be disposed in a peripheral area of the display panel PNL in such a manner as to surround the display area DA. The positions of the display area DA and the non-display area NDA are not limited thereto, and their positions may be changed. The display area DA may form a screen on which an image is displayed.

[0073] The substrate layer BSL may form a substrate of the display panel PNL. In an embodiment, the substrate layer BSL may be a rigid or flexible substrate or film, and its material or properties are not particularly limited. For example, the substrate layer BSL may be a rigid substrate made of glass or strengthened glass, a flexible substrate (or film) formed of plastic or metal, or at least one insulating layer, and its material and / or properties are not particularly limited.

[0074] In addition, the substrate layer BSL may be transparent, but the present disclosure is not limited thereto. For example, the substrate layer BSL may be a transparent, semi-transparent, opaque, or reflective substrate.

[0075] A region on the substrate layer BSL can be defined as a display area DA where pixels PXL are disposed, and another region thereof can be defined as a non-display area NDA. For example, the substrate layer BSL can include a display area DA and a non-display area NDA disposed around the display area DA. The display area DA includes a plurality of pixel regions in which corresponding pixels PXL are formed. Each pixel region can generally refer to a pixel circuit region in which a pixel circuit of a corresponding pixel PXL is formed and / or an emission region in which a light-emitting element constituting the light source (or light source unit) of the pixel PXL and the first electrode and the second electrode connected thereto are disposed. Various lines and / or internal circuits connected to the pixels PXL in the display area DA can be disposed in the non-display area NDA.

[0076] A plurality of pixels PXL are dispersed and disposed in the display area DA. For example, the plurality of pixels PXL can be regularly arranged in the display area DA in a stripe or pentile (or called PenTile) arrangement manner or the like. The arrangement structure of the pixels PXL is not limited thereto, and the pixels PXL can be arranged in the display area DA in various structures and / or schemes.

[0077] In an embodiment, two or more kinds of pixels PXL that emit different colors of light can be disposed in the display area DA. For example, a first pixel PXL1 configured to emit light of a first color, a second pixel PXL2 configured to emit light of a second color, and a third pixel PXL3 configured to emit light of a third color can be disposed in the display area DA. At least one first pixel PXL1, at least one second pixel PXL2, and at least one third pixel PXL3 disposed adjacent to each other can form a pixel unit PXU that can emit different colors of light.

[0078] In an embodiment, each first pixel PXL1 can be a red pixel that emits red light, each second pixel PXL2 can be a green pixel that emits green light, and each third pixel PXL3 can be a blue pixel that emits blue light. In an embodiment, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can include light-emitting elements related to the first color, light-emitting elements related to the second color, and light-emitting elements related to the third color as light sources, so that the pixels can emit light of the first color, the second color, and the third color, respectively. In an embodiment, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can each have a light-emitting element configured to emit light of the same color, and can each include a color filter and a light conversion layer having different colors and disposed on the corresponding light-emitting element to emit light of the first color, the second color, and the third color, respectively.

[0079] However, there is no particular limitation on the color, type, and / or number of pixels PXL forming each pixel unit PXU. For example, the color of light to be emitted from each pixel PXL can be changed in various ways.

[0080] Each pixel PXL can include at least one light source driven by a predetermined control signal (e.g., a scan signal and a data signal) and / or a predetermined power supply (e.g., a first power supply and a second power supply). For example, each pixel PXL can include a light-emitting element LD according to Figures 1a to 3b any one of the embodiments, e.g., at least one ultra-small rod-shaped light-emitting element LD having a small size corresponding to the nanometer to micrometer scale. However, in the embodiments of the present disclosure, the type of the light-emitting element LD that can be used as the light source of the pixel PXL is not limited thereto. For example, in an embodiment, each pixel PXL can include a light-emitting element having a core-shell structure and manufactured by a growth method. In an embodiment, the light-emitting element having a core-shell structure can be an ultra-small core-shell light-emitting element having a small size corresponding to the nanometer to micrometer scale, but the size of the light-emitting element having a core-shell structure is not limited.

[0081] In an embodiment, each pixel PXL can be formed by an active pixel. However, the type, structure, and / or driving scheme of the pixel PXL that can be applied to the display device according to the present disclosure are not particularly limited. For example, each pixel PXL can have the same structure as the pixels of a passive or active light-emitting display device having various known structures and / or operable in various known driving schemes.

[0082] Figures 5a to 5e are circuit diagrams each showing a pixel PXL according to an embodiment of the present disclosure. For example, Figures 5a to 5e shows different embodiments of the pixel PXL that can be applied to an active display device. However, the type of the pixel PXL and the display device to which the embodiments of the present disclosure can be applied is not limited thereto. In an embodiment, Figures 5a to 5e each pixel PXL shown in Figure 4 can be any one of the pixels PXL provided on the Figures 5a to 5e display panel PNL. The pixels PXL can have substantially the same or similar structures. For example, Figure 4 each pixel PXL shown in

[0083] Referring to Figure 5a, a pixel PXL according to an embodiment of the present disclosure may include a light source unit LSU configured to generate light having a luminance corresponding to a data signal. The pixel PXL may further include a pixel circuit PXC configured to drive the light source unit LSU.

[0084] In an embodiment, the light source unit LSU may include a plurality of light emitting elements LD electrically connected to each other between a first power supply VDD supplying a first power voltage and a second power supply VSS supplying a second power voltage. For example, the light source unit LSU may include a first electrode ET1 connected to the first power supply VDD, a second electrode ET2 connected to the second power supply VSS, and a plurality of light emitting elements LD connected in parallel to each other in the same direction between the first electrode ET1 and the second electrode ET2. In an embodiment, the first electrode ET1 may be an anode electrode, and the second electrode ET2 may be a cathode electrode.

[0085] In an embodiment, each light emitting element LD may include a P-type end connected to the first power supply VDD through the first electrode ET1 and an N-type end connected to the second power supply VSS through the second electrode ET2. In an embodiment, the light emitting elements LD may be connected in parallel in the forward direction between the first electrode ET1 and the second electrode ET2. Thus, each light emitting element LD connected in the forward direction between the first power supply VDD and the second power supply VSS may form an effective light source. A group of effective light sources may form the light source unit LSU of the pixel PXL.

[0086] In an embodiment, the first power supply VDD and the second power supply VSS may have different potentials so that the light emitting element LD can emit light. For example, the first power supply VDD may be set as a high-potential power supply, and the second power supply VSS may be set as a low-potential power supply. Here, at least during the emission period of the pixel PXL, the potential difference between the first power supply VDD and the second power supply VSS may be set to be equal to or greater than the threshold voltage of the light emitting element LD.

[0087] In an embodiment, a first end (e.g., P-type end) of the light emitting element LD forming each light source unit LSU may be commonly connected to the pixel circuit PXC through an electrode of the light source unit LSU (e.g., the first electrode ET1 (also referred to as "first pixel electrode") of each pixel PXL), and may be connected to the first power supply VDD through the pixel circuit PXC and the first power line PL1. A second end (e.g., N-type end) of the light emitting element LD may be commonly connected to the second power supply VSS through another electrode of the light source unit LSU (e.g., the second electrode ET2 (also referred to as "second pixel electrode") of each pixel PXL) and the second power line PL2.

[0088] The light-emitting element LD of the light source unit LSU can emit light having a luminance corresponding to the drive current supplied thereto through the pixel circuit PXC. For example, during each frame period, the pixel circuit PXC can supply a drive current corresponding to the gray value of the data of the corresponding frame to the light source unit LSU. The drive current supplied to the light source unit LSU can be divided into portions flowing to the light-emitting elements LD connected in the forward direction. Therefore, each light-emitting element LD can emit light having a luminance corresponding to the current applied thereto, so that the light source unit LSU can emit light having a luminance corresponding to the drive current.

[0089] In an embodiment, the light source unit LSU may further include at least one ineffective light source in addition to the light-emitting elements LD forming each effective light source. For example, at least one reverse light-emitting element LDrv may be further connected between the first electrode ET1 and the second electrode ET2 of the light source unit LSU.

[0090] Each reverse light-emitting element LDrv, together with the light-emitting elements LD forming the effective light source, may be connected in parallel with each other between the first electrode ET1 and the second electrode ET2, and each reverse light-emitting element LDrv may be connected between the first electrode ET1 and the second electrode ET2 in a direction opposite to that of the light-emitting element LD. For example, the N-type end of the reverse light-emitting element LDrv may be connected to the first power supply VDD via the first electrode ET1. The P-type end of the reverse light-emitting element LDrv may be connected to the second power supply VSS via the second electrode ET2. Even when a predetermined drive voltage (e.g., a normal-direction drive voltage) is applied between the first electrode ET1 and the second electrode ET2, the reverse light-emitting element LDrv remains ineffective. Therefore, substantially no current flows through the reverse light-emitting element LDrv.

[0091] In an embodiment, in the step of aligning the light-emitting element LD between the first electrode ET1 and the second electrode ET2 to form each light source unit LSU, the alignment of the light-emitting element LD supplied to each pixel region (e.g., the emission region of each pixel PXL) in any one direction (e.g., the forward direction) and the biasing can be controlled by adjusting the alignment signal (or alignment voltage) to be applied to the first electrode ET1 and the second electrode ET2 or by forming a magnetic field. In this case, at least one reverse light-emitting element LDrv connected in the reverse direction can be further connected between the first electrode ET1 and the second electrode ET2 of each pixel PXL together with a plurality of light-emitting elements LD connected in the forward direction. In an embodiment, in the case where the light-emitting element LD is biased and aligned to increase the number of light-emitting elements LD connected between the first electrode ET1 and the second electrode ET2 of each pixel PXL in the forward direction, the number of reverse light-emitting elements LDrv connected between the first electrode ET1 and the second electrode ET2 in the reverse direction can be less than the number of light-emitting elements LD connected in the forward direction. For example, the number of reverse light-emitting elements LDrv connected between the first electrode ET1 and the second electrode ET2 in the reverse direction can be 30% or less of the number of light-emitting elements LD connected in the forward direction.

[0092] The pixel circuit PXC can be connected to the scan line Si and the data line Dj corresponding to the pixel PXL. For example, if the pixel PXL is provided in the i-th row (i is a natural number) and the j-th column (j is a natural number) of the display area DA, the pixel circuit PXC of the pixel PXL can be connected to the i-th scan line Si and the j-th data line Dj of the display area DA. In an embodiment, the pixel circuit PXC can include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0093] The first transistor (also referred to as the “driving transistor”) T1 is connected between the first power supply VDD and the light source unit LSU. The gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 can control the driving current to be supplied to the light source unit LSU in response to the voltage of the first node N1.

[0094] The second transistor (also referred to as the “switching transistor”) T2 can be connected between the data line Dj and the first node N1. The gate electrode of the second transistor T2 is connected to the scan line Si. When a scan signal having a gate-on voltage (e.g., a low-level voltage) is supplied from the scan line Si, the second transistor T2 is turned on to electrically connect the first node N1 to the data line Dj.

[0095] During each frame period, a data signal corresponding to a frame is supplied to the data line Dj. The data signal is transmitted to the first node N1 via the second transistor T2. Thus, a voltage corresponding to the data signal is charged into the storage capacitor Cst.

[0096] One electrode of the storage capacitor Cst is connected to the first power supply VDD, and the other electrode thereof is connected to the first node N1. The storage capacitor Cst can be charged with a voltage corresponding to the data signal to be supplied to the first node N1 during each frame period.

[0097] Although in Figure 5a the transistors (e.g., the first transistor T1 and the second transistor T2) included in the pixel circuit PXC have been shown to be formed of P-type transistors, the present disclosure is not limited thereto. In other words, at least one of the first transistor T1 and the second transistor T2 can be changed to an N-type transistor.

[0098] For example, as shown in Figure 5b both the first transistor T1 and the second transistor T2 can be formed of N-type transistors. In this case, the gate conduction voltage of the scan signal for writing the data signal supplied to the data line Dj into the pixel PXL during each frame period can be a high-level voltage. Similarly, the voltage of the data signal for turning on the first transistor T1 can be a voltage having a level opposite to that of Figure 5a the embodiment. For example, in Figure 5b the embodiment, as the grayscale value to be expressed increases, a data signal having a higher voltage can be supplied.

[0099] Except that the connection positions of some circuit elements and the voltage levels of control signals (e.g., the scan signal and the data signal) change according to the change of the transistor type, Figure 5b the pixel PXL shown in Figure 5a is substantially similar in structure and operation to the pixel PXL shown in Figure 5b Therefore, a detailed description of the pixel PXL in

[0100] The structure of the pixel circuit PXC is not limited to the embodiments shown in Figure 5a and Figure 5b In other words, the pixel circuit PXC can be formed of a known pixel circuit that can have various structures and / or can be operated by various driving schemes. For example, the pixel circuit PXC can be constructed in the same manner as the embodiment shown in Figure 5c will be omitted.

[0101] Refer to Figure 5c, the pixel circuit PXC can be connected not only to the scan line Si in the corresponding horizontal line, but also to at least one other scan line (or control line). For example, the pixel circuit PXC of the pixel PXL provided in the i-th row of the display area DA can also be connected to the (i - 1)-th scan line Si-1 and / or the (i + 1)-th scan line Si+1. In an embodiment, the pixel circuit PXC can be connected not only to the first power supply VDD and the second power supply VSS, but also to a third power supply. For example, the pixel circuit PXC can also be connected to the initialization power supply Vint. In an embodiment, the pixel circuit PXC can include a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst.

[0102] The first transistor T1 can be connected between the first power supply VDD and the light source unit LSU. For example, the first electrode (e.g., source electrode) of the first transistor T1 can be connected to the first power supply VDD through the fifth transistor T5 and the first power line PL1, and the second electrode (e.g., drain electrode) of the first transistor T1 can be connected to the first electrode (e.g., the first contact electrode and / or the first pixel electrode of the corresponding pixel PXL) of the light source unit LSU via the sixth transistor T6. The gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 can control the drive current to be supplied to the light source unit LSU in response to the voltage of the first node N1.

[0103] The second transistor T2 is connected between the data line Dj and the first electrode of the first transistor T1. The gate electrode of the second transistor T2 is connected to the corresponding scan line Si. When a scan signal having a gate-on voltage is supplied from the scan line Si, the second transistor T2 can be turned on to electrically connect the data line Dj to the first electrode of the first transistor T1. Therefore, if the second transistor T2 is turned on, the data signal supplied from the data line Dj can be transmitted to the first transistor T1.

[0104] The third transistor T3 is connected between the other electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 is connected to the corresponding scan line Si. When a scan signal having a gate-on voltage is supplied from the scan line Si, the third transistor T3 can be turned on to electrically connect the first transistor T1 in the form of a diode.

[0105] The fourth transistor T4 may be connected between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 is connected to the previous scan line, for example, the (i-1)-th scan line Si-1. When a scan signal having a gate-on voltage is supplied to the (i-1)-th scan line Si-1, the fourth transistor T4 may be turned on, so that the voltage of the initialization power supply Vint can be transmitted to the first node N1. In an embodiment, when the first transistor T1 is a P-type transistor, the voltage of the initialization power supply Vint for initializing the gate voltage of the first transistor T1 may be the lowest voltage of the data signal or less.

[0106] The fifth transistor T5 is connected between the first power supply VDD and the first transistor T1. The gate electrode of the fifth transistor T5 is connected to the corresponding emission control line, for example, the i-th emission control line Ei. When an emission control signal having a gate-off voltage (e.g., a high-level voltage) is supplied to the i-th emission control line Ei, the fifth transistor T5 may be turned off and may be turned on in other cases.

[0107] The sixth transistor T6 is connected between the first transistor T1 and the light source unit LSU. The gate electrode of the sixth transistor T6 is connected to the corresponding emission control line, for example, the i-th emission control line Ei. When an emission control signal having a gate-off voltage is supplied to the i-th emission control line Ei, the sixth transistor T6 may be turned off and may be turned on in other cases.

[0108] The seventh transistor T7 is connected between the second node N2 and the initialization power supply Vint, and the first electrode of the light source unit LSU (e.g., the first pixel electrode ET1 of the corresponding pixel PXL) is connected to the second node N2. The gate electrode of the seventh transistor T7 is connected to any one of the scan lines of the subsequent stage (subsequent horizontal pixel column), for example, connected to the (i + 1)-th scan line Si+1. When a scan signal having a gate-on voltage is supplied to the (i + 1)-th scan line Si+1, the seventh transistor T7 may be turned on, so that the voltage of the initialization power supply Vint can be supplied to the first electrode of the light source unit LSU. In this case, during each initialization period in which the voltage of the initialization power supply Vint is transmitted to the light source unit LSU, the voltage of the first electrode of the light source unit LSU can be initialized. The control signal for controlling the operation of the seventh transistor T7 may be changed in various ways. For example, in an embodiment, the gate electrode of the seventh transistor T7 may be connected to the scan line of the corresponding horizontal row, i.e., the i-th scan line Si. In this case, when a scan signal having a gate-on voltage is supplied to the i-th scan line Si, the seventh transistor T7 may be turned on, so that the voltage of the initialization power supply Vint can be supplied to the first electrode of the light source unit LSU.

[0109] The storage capacitor Cst can be connected between the first power supply VDD and the first node N1. The storage capacitor Cst can store a voltage corresponding to both the data signal applied to the first node N1 and the threshold voltage of the first transistor T1 during each frame period.

[0110] Although in Figure 5c , the transistors (e.g., the first transistor T1 to the seventh transistor T7) included in the pixel circuit PXC have been shown to be formed of P-type transistors, the present disclosure is not limited thereto. For example, at least one of the first transistor T1 to the seventh transistor T7 can be changed to an N-type transistor.

[0111] Although Figures 5a to 5c an embodiment is shown in which all the effective light sources (i.e., the light-emitting elements LD) constituting each light source unit LSU are connected in parallel with each other, the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, as Figure 5d and Figure 5e shown, the light source unit LSU of each pixel PXL can be configured to include a series structure. In the description of the embodiments below, Figure 5d and Figure 5e the detailed description of components similar or identical to the components (e.g., the pixel circuit PXC) of the Figures 5a to 5c embodiment will be omitted.

[0112] Referring to Figure 5d , the light source unit LSU can include a plurality of light-emitting elements connected in series with each other. For example, the light source unit LSU can include a first light-emitting element LD1, a second light-emitting element LD2, and a third light-emitting element LD3 that are connected in series in the forward direction between the first power supply VDD and the second power supply VSS and constitute each effective light source. Hereinafter, when specifying a specific light-emitting element among the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3, the corresponding light-emitting element will be referred to as the first light-emitting element LD1, the second light-emitting element LD2, or the third light-emitting element LD3. The term "light-emitting element LD" or "plurality of light-emitting elements LD" will be used to arbitrarily specify at least one light-emitting element among the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3, or to commonly specify the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3.

[0113] The P-type terminal of the first light-emitting element LD1 can be connected to the first power supply VDD through the first electrode ET1 of the light source unit LSU. The N-type terminal of the first light-emitting element LD1 can be connected to the P-type terminal of the second light-emitting element LD2. The P-type terminal of the second light-emitting element LD2 can be connected to the N-type terminal of the first light-emitting element LD1. The N-type terminal of the second light-emitting element LD2 can be connected to the P-type terminal of the third light-emitting element LD3. The P-type terminal of the third light-emitting element LD3 can be connected to the N-type terminal of the second light-emitting element LD2. The N-type terminal of the third light-emitting element LD3 can be connected to the second power supply VSS through the second electrode ET2 of the light source unit LSU and the second power line PL2. In this way, the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be connected in series between the first electrode ET1 and the second electrode ET2 of the light source unit LSU.

[0114] Although an embodiment in which the light-emitting elements LD are connected to have a three-stage series structure is shown in Figure 5d , the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, two light-emitting elements LD can be connected to have a two-stage series structure, or four or more light-emitting elements LD can be connected to have a four-stage or more series structure.

[0115] When it is assumed that the same brightness is expressed using light-emitting elements LD having the same conditions (e.g., the same size and / or number), in the light source unit LSU having a structure in which the light-emitting elements LD are connected in series, compared with the light source unit LSU having a structure in which the light-emitting elements LD are connected in parallel, the voltage to be applied between the first electrode ET1 and the second electrode ET2 can increase, and the amount of driving current flowing into the light source unit LSU can decrease. Therefore, when the light source unit LSU of each pixel PXL is formed of a series structure, as the display device is driven, the panel current flowing through the display panel PNL can decrease. Therefore, power consumption can be reduced.

[0116] In an embodiment, at least one series stage can include a plurality of light-emitting elements LD connected in parallel with each other. In this case, the light source unit LSU can be formed of a series / parallel combination structure. For example, the light source unit LSU can be constructed as shown in the embodiment of Figure 5e .

[0117] Referring to Figure 5e, each series stage of the light source unit LSU may include a plurality of light emitting elements LD connected in parallel with each other. For example, the light source unit LSU may include a plurality of first light emitting elements LD1 provided in the first series stage (also referred to as the "first stage" or "first row") and a plurality of second light emitting elements LD2 provided in the second series stage (also referred to as the "second stage" or "second row") after the first series stage. In addition, the light source unit LSU may selectively further include at least one series stage after the second series stage. For example, the light source unit LSU may further include a plurality of third light emitting elements LD3 provided in the third series stage (referred to as the "third stage" or "third row") after the second series stage. In an embodiment, at least one series stage may further include at least one reverse light emitting element LDrv, but the present disclosure is not limited thereto. For example, each pixel PXL may also include at least one reverse light emitting element LDrv connected in a direction opposite to the direction of the light emitting element LD in at least one of the plurality of series stages. In an embodiment, when the light emitting elements LD are aligned by controlling an alignment signal (or alignment voltage) or forming a magnetic field such that the light emitting elements LD supplied to each pixel region (e.g., the emission region of each pixel PXL) are biased in any one direction (e.g., the forward direction), the number of reverse light emitting elements LDrv provided in each pixel PXL may be less than the number of effective light sources (i.e., light emitting elements LD) provided in the forward direction in the pixel PXL.

[0118] The first light emitting elements LD1 may be connected in parallel with each other between the first electrode ET1[1] and the second electrode ET2[1] of the first series stage. The second light emitting elements LD2 may be connected in parallel with each other between the first electrode ET1[2] and the second electrode ET2[2] of the second series stage. The third light emitting elements LD3 may be connected in parallel with each other between the first electrode ET1[3] and the second electrode ET2[3] of the third series stage.

[0119] In an embodiment, the first electrodes ET1[1] to ET1[3] and the second electrodes ET2[1] to ET2[3] provided in each series stage may form sub-electrodes (or also referred to as "separated electrodes") that are dispersed and provided in the light source unit LSU. Hereinafter, the term "first electrode ET1" (also referred to as "first sub-electrode") will be used to arbitrarily designate at least one of the first electrodes ET1[1] to ET1[3] (also referred to as "first sub-electrodes") provided in each series stage, or to collectively designate the first electrodes ET1[1] to ET1[3] provided in each series stage. Similarly, the term "second electrode ET2" (also referred to as "second sub-electrode") will be used to arbitrarily designate at least one of the second electrodes ET2[1] to ET2[3] (also referred to as "second sub-electrodes") provided in each series stage, or to collectively designate the second electrodes ET2[1] to ET2[3] provided in each series stage.

[0120] Thus, in the case of constructing the light source unit LSU of each pixel PXL by connecting a plurality of light emitting elements LD in a series / parallel combination structure, the driving current / voltage conditions can be easily controlled to correspond to the specifications of a desired product. For example, when assuming that light emitting elements LD having the same conditions (e.g., the same size and / or number) are used and the same brightness is represented, compared with the driving current of the light source unit LSU having a structure in which all the light emitting elements LD are connected in parallel with each other as shown in the embodiment of Figures 5a to 5c the light source unit LSU in which the light emitting elements LD are connected in a series / parallel combination structure can reduce the driving current, and compared with the driving voltage of the light source unit LSU having a structure in which all the light emitting elements LD are connected in series as shown in the embodiment of Figure 5d the driving voltage to be applied to the opposite ends of the light source unit LSU can be reduced. In the case where all the light emitting elements LD are connected in series, if at least one of the light emitting elements LD connected in series with each other is not completely connected in the forward direction, the path along which the driving current can flow in the pixel PXL is blocked, thereby possibly causing a black dot defect. On the other hand, in the case where the light emitting elements LD are connected to each other in a series / parallel combination structure, even if some of the light emitting elements LD in each series stage are not completely connected in the forward direction or a defect occurs in some of the light emitting elements LD, the driving current is allowed to flow through the other light emitting elements LD of the corresponding series stage. Therefore, defects of the pixel PXL can be prevented or reduced.

[0121] As shown in the foregoing embodiments, the pixel PXL according to an embodiment of the present disclosure may include a pixel circuit PXC and / or a light source unit LSU that may have various structures. The structure applicable to the pixel PXL of the present disclosure is not limited to Figures 5a to 5eThe embodiments shown in, and each pixel PXL can have various well-known structures. For example, the pixel circuit PXC included in each pixel PXL can be formed of well-known pixel circuits that can have various structures and / or can be operated by various driving schemes. In an embodiment of the present disclosure, each pixel PXL can be constructed in a passive light-emitting display device or the like. In this case, the pixel circuit PXC can be omitted, and each of the first electrode ET1 and the second electrode ET2 of the light source unit LSU can be directly connected to the scan line Si, the data line Dj, the power line, and / or the control line.

[0122] Figure 6 and Figure 7 are plan views each showing a pixel PXL according to an embodiment of the present disclosure. For example, Figure 6 and Figure 7 show different embodiments of a pixel unit PXU including Figure 4 a first pixel PXL1, a second pixel PXL2, and a third pixel PXL3. For example, Figure 6 and Figure 7 show different embodiments related to the shape and arrangement structure of the first electrode ET1 and the second electrode ET2.

[0123] In an embodiment, Figure 6 and Figure 7 each pixel PXL shown in can be any one of the pixel PXLs shown in Figures 5a to 5e For example, Figure 6 and Figure 7 each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 shown in can be a pixel PXL including a plurality of light-emitting elements LD connected in a series / parallel combination structure as shown in the embodiment of Figure 5e .

[0124] In an embodiment, the pixels PXL provided in the display area ( Figure 4 DA of ) can have substantially the same or similar structures. For example, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can have substantially the same structure. Therefore, hereinafter, the structure of each pixel PXL will be described based on the first pixel PXL1.

[0125] In an embodiment, Figure 6 and Figure 7 show the structure of each pixel PXL centered on the light source unit LSU of the pixel PXL. Here, each pixel PXL can further include circuit elements for controlling each light source unit LSU (for example, forming Figures 5a to 5e(at least one circuit element of the pixel circuit PXC). In an embodiment, the circuit element may be disposed on a layer different from the layer of the light source unit LSU. For example, the circuit element may be disposed in a pixel circuit layer on one surface of the base substrate layer ( Figure 4 BSL), and the light source unit LSU may be disposed in a display element layer, and the display element layer is disposed on the pixel circuit layer.

[0126] In addition, Figure 6 and Figure 7 illustrates an embodiment in which each light source unit LSU is connected to a predetermined power line (e.g., the first power line PL1 and / or the second power line PL2), a circuit element (e.g., at least one circuit element forming the pixel circuit PXC), and / or a signal line (e.g., the scan line Si and / or the data line Dj) through the first contact hole CH1 and the second contact hole CH2, but the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, at least one of the first electrode ET1 and the second electrode ET2 of each pixel PXL may be directly connected to a predetermined power line and / or a signal line without using, for example, a contact hole and / or an intermediate line.

[0127] Referring to Figures 4 to 7 , each pixel PXL (e.g., the first pixel PXL1) according to an embodiment of the present disclosure may include a plurality of light emitting elements LD disposed in a plurality of series stages. For example, each pixel PXL may include a first light emitting element to a Kth light emitting element LD respectively disposed in a first series stage to a Kth (K is a natural number of 2 or more) series stage. In an embodiment, the first light emitting element to the Kth light emitting element LD may be respectively disposed in a first sub-region to a Kth sub-region. For example, each pixel PXL may include a first sub-region to a Kth sub-region corresponding to the first series stage to the Kth (K is a natural number of 2 or more) series stage, and a first light emitting element to a Kth light emitting element LD respectively disposed in the first sub-region to the Kth sub-region.

[0128] For example, when the pixel PXL includes a plurality of light-emitting elements LD (e.g., first light-emitting element LD1 to third light-emitting element LD3) arranged in three series stages (e.g., first series stage, second series stage, and third series stage) and constituting each light source unit LSU, the pixel PXL may include a first sub-region SAR1 corresponding to the first series stage and in which at least one first light-emitting element LD1 is provided, a second sub-region SAR2 corresponding to the second series stage and in which at least one second light-emitting element LD2 is provided, and a third sub-region SAR3 corresponding to the third series stage and in which at least one third light-emitting element LD3 is provided. Hereinafter, the term "sub-region SAR" or "plural sub-regions SAR" will be used to arbitrarily specify at least one of the first sub-region SAR1, the second sub-region SAR2, and the third sub-region SAR3, or to commonly specify a plurality of sub-regions.

[0129] In addition, each pixel PXL may include a first electrode ET1 and a second electrode ET2 disposed at positions spaced apart from each other in each of the first sub-region to the Kth sub-region SAR of each series stage. For example, each pixel PXL may include a first electrode ET1[1] and a second electrode ET2[1] disposed at positions spaced apart from each other in the first sub-region SAR1 of the first series stage, a first electrode ET1[2] and a second electrode ET2[2] disposed at positions spaced apart from each other in the second sub-region SAR2 of the second series stage, and a first electrode ET1[3] and a second electrode ET2[3] disposed at positions spaced apart from each other in the third sub-region SAR3 of the third series stage.

[0130] At least one effective light source may be connected between the first electrode ET1 and the second electrode ET2 of each series stage. For example, a plurality of light-emitting elements LD may be connected between the first electrode ET1 and the second electrode ET2 of each series stage in the forward direction. In other words, in this embodiment, each sub-region SAR may be a region including the first electrode ET1 and the second electrode ET2 constituting each series stage and at least one light-emitting element LD electrically connected between the first electrode ET1 and the second electrode ET2.

[0131] In addition, each pixel PXL may further include a plurality of electrode lines. For example, each pixel PXL may further include a first electrode line MLI1 connected to the first electrode of the first series stage (e.g., the first electrode ET1[1] of the first sub-region SAR1), a second electrode line MLI2 connected to the second electrode of the last series stage (e.g., the second electrode ET2[3] of the third sub-region SAR3), and at least one intermediate electrode SLI disposed between two consecutive sub-regions SAR.

[0132] In an embodiment, first sub-regions to K-th sub-regions SAR (e.g., first sub-region SAR1 to third sub-region SAR3) corresponding to the first series stage to the K-th series stage (e.g., the first series stage to the third series stage) may be continuously provided in the emission region EMA of the corresponding pixel PXL. For example, the emission region EMA of each pixel PXL may include the first sub-region to the K-th sub-region SAR continuously provided in the first direction DR1. In an embodiment, the first direction DR1 may be a vertical direction (or column direction), but the present disclosure is not limited thereto. For example, in an embodiment, the first direction DR1 may be a horizontal direction (or row direction). Optionally, in an embodiment, the first direction DR1 may be a diagonal direction.

[0133] For example, if each light source unit LSU includes a plurality of light-emitting elements LD dispersed in three series stages, the emission region EMA in which the light source unit LSU is provided may be divided into three sub-regions SAR with respect to the first direction DR1. In other words, the emission region EMA of each pixel PXL may include a plurality of sub-regions SAR in which the light-emitting elements LD of the series stages of the light source unit LSU constituting the pixel PXL are provided, as well as the first electrode ET1 and the second electrode ET2. In an embodiment, each emission region EMA may further include a region formed between the sub-regions SAR.

[0134] For example, the emission region EMA may include a first sub-region SAR1, a second sub-region SAR2, and a third sub-region SAR3 continuously provided in the first direction DR1, and a region formed between the first sub-region SAR1, the second sub-region SAR2, and the third sub-region SAR3 (e.g., a region in which each intermediate electrode SLI is provided).

[0135] In an embodiment, the emission region EMA of each pixel PXL may refer to a region in which the light-emitting element LD forming at least the light source unit LSU of the corresponding pixel PXL is provided. The emission region EMA may be defined by a bank structure (also referred to as a "pixel defining layer") or the like. For example, a light-shielding bank including an opening for exposing the emission region EMA of each pixel PXL may be provided between the pixels PXL.

[0136] In the first sub-region SAR1, at least one first electrode ET1[1] of the first series stage, at least one second electrode ET2[1] of the first series stage spaced apart from the first electrode ET1[1] of the first series stage, and at least one first light-emitting element (e.g., a plurality of first light-emitting elements connected in parallel to each other) LD1 electrically connected between the first electrode ET1[1] of the first series stage and the second electrode ET2[1] of the first series stage can be provided. Similarly, in the second sub-region SAR2, at least one first electrode ET1[2] of the second series stage, at least one second electrode ET2[2] of the second series stage spaced apart from the first electrode ET1[2] of the second series stage, and at least one second light-emitting element (e.g., a plurality of second light-emitting elements connected in parallel to each other) LD2 electrically connected between the first electrode ET1[2] of the second series stage and the second electrode ET2[2] of the second series stage can be provided. In addition, in the case where the pixel PXL further includes a third sub-region SAR3 corresponding to the third series stage, in the third sub-region SAR3, at least one first electrode ET1[3] of the third series stage, at least one second electrode ET2[3] of the third series stage spaced apart from the first electrode ET1[3] of the third series stage, and at least one third light-emitting element (e.g., a plurality of third light-emitting elements connected in parallel to each other) LD3 electrically connected between the first electrode ET1[3] of the third series stage and the second electrode ET2[3] of the third series stage can be provided.

[0137] The first electrode ET1 and the second electrode ET2 of each series stage can be provided at positions spaced apart from each other in each corresponding sub-region SAR. In an embodiment, the first electrode ET1 and the second electrode ET2 of each series stage can be regularly arranged in each corresponding sub-region SAR, but the present disclosure is not limited thereto.

[0138] In an embodiment, the first electrode ET1 and the second electrode ET2 can have a bar shape extending in any one direction in each sub-region SAR. For example, both the first electrode ET1 and the second electrode ET2 can have a bar shape extending in the first direction DR1 in the corresponding sub-region SAR, and can be provided parallel to each other. For example, the first electrode ET1 and the second electrode ET2 of each series stage can extend in the first direction DR1 in each corresponding sub-region SAR, and can be continuously or alternately provided at positions spaced apart from each other in the second direction DR2 intersecting the first direction DR1. In an embodiment, the first electrode ET1 and the second electrode ET2 can be provided at regular intervals in each sub-region SAR. Therefore, the light-emitting elements LD can be more regularly aligned in each sub-region SAR.

[0139] However, the shapes, orientations, and / or relative arrangement structures of the first electrode ET1 and the second electrode ET2 are not limited thereto and can be changed in various ways. For example, in an embodiment, the first electrode ET1 and the second electrode ET2 of each series stage can be arranged at positions spaced apart from each other in a double helix structure or the like.

[0140] Each first electrode ET1 can be electrically connected to a first electrode line (also referred to as "first main electrode line" or "first main alignment line") MLI1 or the second electrode ET2 of the previous series stage. For example, the first electrode ET1[1] of the first series stage as the first series stage can be integrally or non-integrally connected to the first electrode line MLI1. In an embodiment, when the first electrode ET1[1] of the first series stage and the first electrode line MLI1 are integrally connected to each other, the first electrode ET1[1] of the first series stage and the first electrode line MLI1 can be regarded as different regions of one electrode, one line, or one pattern.

[0141] The first electrode ET1 of each of the other series stages can be electrically connected to the second electrode ET2 of the previous series stage. For example, the first electrode ET1[2] of the second series stage can be integrally or non-integrally connected to the second electrode ET2[1] of the first series stage. The first electrode ET1[3] of the third series stage can be integrally or non-integrally connected to the second electrode ET2[2] of the second series stage.

[0142] Each second electrode ET2 can be electrically connected to the first electrode ET1 of the subsequent series stage or a second electrode line (also referred to as "second main electrode line" or "second main alignment line") MLI2. For example, the second electrode ET2[1] of the first series stage can be connected to the first electrode ET1[2] of the second series stage. The second electrode ET2[2] of the second series stage can be connected to the first electrode ET1[3] of the third series stage. When each light source unit LSU includes only two series stages, the second electrode ET2[2] of the second series stage can be integrally or non-integrally connected to the second electrode line MLI2.

[0143] The second electrode ET2[3] of the last Kth series stage (for example, the third series stage) can be integrally or non-integrally connected to the second electrode line MLI2. In an embodiment, when the second electrode ET2[3] of the third series stage and the second electrode line MLI2 are integrally connected to each other, the second electrode ET2[3] of the third series stage and the second electrode line MLI2 can be regarded as different regions of one electrode, one line, or one pattern.

[0144] In an embodiment, the first electrode ET1 and the second electrode ET2 may be disposed in each emission area EMA in a regular pattern. In addition, the respective numbers of the first electrode ET1 and the second electrode ET2 disposed in each sub-area SAR are not particularly limited. For example, each sub-area SAR may include one or more first electrodes ET1 and second electrodes ET2, and the respective numbers of the first electrode ET1 and the second electrode ET2 may be the same as or different from each other.

[0145] In an embodiment, as Figure 6 shown, the first electrode ET1 and the second electrode ET2 may be disposed in two consecutive sub-areas SAR in a shape in which the first electrode ET1 and the second electrode ET2 are symmetric with each other based on an intermediate electrode SLI disposed between the two sub-areas SAR. For example, in the first sub-area SAR1, two first series-stage first electrodes ET1[1] may be disposed, and one first series-stage second electrode ET2[1] parallel to the first series-stage first electrodes ET1[1] may be disposed between the first series-stage first electrodes ET1[1]. In the second sub-area SAR2, one second series-stage first electrode ET1[2] integrally connected to the one first series-stage second electrode ET2[1] may be disposed to be symmetric with the first series-stage second electrode ET2[1] based on a first intermediate electrode SLI1 disposed between the first sub-area SAR1 and the second sub-area SAR2, and two second series-stage second electrodes ET2[2] may be disposed on opposite sides of the one second series-stage first electrode ET1[2] such that the two second series-stage second electrodes ET2[2] are symmetric with the two first series-stage first electrodes ET1[1] based on the first intermediate electrode SLI1. Similarly, in the third sub-area SAR3, two third series-stage first electrodes ET1[3] integrally connected to the two second series-stage second electrodes ET2[2] may be disposed to be symmetric with the two second series-stage second electrodes ET2[2] based on a second intermediate electrode SLI2 disposed between the second sub-area SAR2 and the third sub-area SAR3, and one third series-stage second electrode ET2[3] may be disposed between the two third series-stage first electrodes ET1[3] such that the one third series-stage second electrode ET2[3] is symmetric with the one second series-stage first electrode ET1[2] based on the second intermediate electrode SLI2.

[0146] In an embodiment, as Figure 7As shown in the figure, the first electrode ET1 and the second electrode ET2 can be arranged in the same repeating pattern in each sub-region SAR. For example, in each of the first sub-region SAR1 to the third sub-region SAR3, two first electrodes ET1 can be arranged, and one second electrode ET2 can be arranged between the two first electrodes ET1 such that the second electrode ET2 is parallel to the first electrode ET1. In other words, the shapes and arrangement structures of the first electrode ET1 and the second electrode ET2 can be changed in various ways according to the embodiments.

[0147] At least one light-emitting element LD (e.g., a plurality of light-emitting elements LD) can be connected between the first electrode ET1 and the second electrode ET2 of each series stage. For example, a plurality of first light-emitting elements LD1 can be connected in parallel between the first electrode ET1[1] and the second electrode ET2[1] of the first series stage. Similarly, a plurality of second light-emitting elements LD2 can be connected in parallel between the first electrode ET1[2] and the second electrode ET2[2] of the second series stage, and a plurality of third light-emitting elements LD3 can be connected in parallel between the first electrode ET1[3] and the second electrode ET2[3] of the third series stage.

[0148] In an embodiment, each light-emitting element LD can be a light-emitting element made of a material having an inorganic crystal structure and having an ultra-small size (e.g., ranging from the nanoscale to the microscale). For example, as Figures 1a to 3b shown in the figure, each light-emitting element LD can be an ultra-small rod-shaped light-emitting element having a size ranging from the nanoscale to the microscale. The size, type, shape, etc. of the light-emitting element LD can be changed in various ways.

[0149] Although Figure 6 and Figure 7 show that in the region where a pair of first electrode ET1 and second electrode ET2 are arranged to face each other, each light-emitting element LD is uniformly horizontally arranged along the second direction DR2 between the first electrode ET1 and the second electrode ET2, the present disclosure is not limited thereto. For example, at least one of the light-emitting elements LD can be arranged and / or connected in a diagonal direction between the first electrode ET1 and the second electrode ET2. Optionally, although not shown in Figure 6 and Figure 7 at least one light-emitting element that is not fully connected between the first electrode ET1 and the second electrode ET2 (e.g., an invalid light source other than the reverse light-emitting element LDrv) can be further arranged in each sub-region SAR and / or in the region surrounding the sub-region SAR.

[0150] In an embodiment, the light-emitting element LD may be prepared in a predetermined solution in a diffused form and then supplied to the emission area EMA of each pixel PXL by an inkjet scheme or the like. For example, the light-emitting element LD may be mixed with a volatile solvent and supplied to each emission area EMA. Here, if a predetermined alignment signal (or alignment voltage) is applied to the first electrode ET1 and the second electrode ET2, an electric field is formed between the first electrode ET1 and the second electrode ET2, whereby the light-emitting element LD may be aligned between the first electrode ET1 and the second electrode ET2. After aligning the light-emitting element LD, the solvent may be removed by a volatilization scheme or other schemes. In this way, the light-emitting element LD may be reliably disposed between the first electrode ET1 and the second electrode ET2.

[0151] Each light-emitting element LD may include a first end EP1 connected to the first electrode ET1 of a corresponding series stage and a second end EP2 connected to the second electrode ET2 of the corresponding series stage. In an embodiment, the first end EP1 may be a P-type end, and the second end EP2 may be an N-type end.

[0152] In an embodiment, each light-emitting element LD may be connected between the first electrode ET1 and the second electrode ET2 of each series stage in the forward direction. For example, the first end EP1 of each light-emitting element LD may be directly connected to the first electrode ET1 of any one series stage or may be connected to the first electrode ET1 of any one series stage through at least one contact electrode. Similarly, the second end EP2 of each light-emitting element LD may be directly connected to the second electrode ET2 of any one series stage or may be connected to the second electrode ET2 of any one series stage through at least one contact electrode. The light-emitting element LD connected between the first electrode ET1 and the second electrode ET2 of each series stage in the forward direction may form an effective light source of the corresponding series stage.

[0153] Although not shown in Figure 6 and Figure 7 , at least one series stage may further include at least one reverse light-emitting element ( Figures 5a to 5e LDrv of

[0154] connected between the first electrode ET1 and the second electrode ET2 in a direction opposite to the direction of the light-emitting element LD constituting the corresponding effective light source (e.g., in the reverse direction). For example, at least one sub-region SAR may include at least one reverse light-emitting element LDrv connected between the first electrode ET1 and the second electrode ET2 in the reverse direction. At least one reverse light-emitting element LDrv may be kept disabled in the pixel PXL.During a period in which a display device is operated, the first electrode line MLI1 may be supplied with a voltage of a first power supply VDD (e.g., a first power voltage) or a first driving signal (e.g., a scan signal, a data signal, or other predetermined control signal). In an embodiment, the first electrode line MLI1 may be electrically connected to a first contact hole CH1, a predetermined circuit element (e.g., at least one transistor forming a pixel circuit PXC), a power line (e.g., a first power line PL1), and / or a signal line (e.g., a scan line Si, a data line Dj, or a predetermined control line). For example, the first electrode line MLI1 may be electrically connected to a predetermined circuit element disposed therebelow through the first contact hole CH1 and may be connected to the first power line PL1 through the circuit element. For example, each pixel PXL may further include a pixel circuit PXC connected between the first electrode line MLI1 and the first power supply VDD. In an embodiment, the pixel circuit PXC may be disposed below each light source unit LSU and may be connected to the first electrode line MLI1 of the light source unit LSU through the first contact hole CH1. In an embodiment, the first electrode line MLI1 may be connected to a signal line supplied with a predetermined first driving signal via the first contact hole CH1 or the like. In an embodiment, the first electrode line MLI1 may be directly connected to the first power line PL1 or a predetermined signal line without using the first contact hole CH1 and / or the circuit element. In this case, the first electrode line MLI1 may be connected to the first power line PL1 or a predetermined signal line integrally or non-integrally.

[0155] In an embodiment, the first electrode line MLI1 connected to the first electrode ET1[1] of the first series stage of each pixel PXL may be first manufactured to be commonly connected to a plurality of pixels PXL, and a first alignment signal (or a first alignment voltage) may be supplied in a step of aligning the light emitting element LD. Thereafter, the first electrode line MLI1 between the pixels PXL may be disconnected so that the pixels PXL may be manufactured to be operable individually. For example, the first electrode line MLI1 may be disconnected between a first pixel PXL1 and a second pixel PXL2 adjacent to each other, between a second pixel PXL2 and a third pixel PXL3 adjacent to each other, and between pixel units PXU adjacent to each other so that the corresponding pixels PXL may be separated from each other to be operable individually. In other words, in an embodiment, the first electrode line MLI1 of the pixel PXL may be separated from each other between adjacent pixels PXL.

[0156] During a period in which the display device is operated, the second electrode line MLI2 may be supplied with the voltage of the second power supply VSS (e.g., the second power voltage) or a second driving signal (e.g., a scan signal, a data signal, or other predetermined control signal). In an embodiment, the second electrode line MLI2 may be electrically connected to the second contact hole CH2, a predetermined circuit element (e.g., at least one transistor forming the pixel circuit PXC), a power line (e.g., the second power line PL2), and / or a signal line (e.g., the scan line Si, the data line Dj, or a predetermined control line). For example, the second electrode line MLI2 may be connected to the second power line PL2 disposed therebelow through the second contact hole CH2. In an embodiment, the second electrode line MLI2 may be directly connected to the second power line PL2 or a predetermined signal line without using, for example, the second contact hole CH2 and / or a circuit element. In this case, the second electrode line MLI2 may be connected to the second power line PL2 or a predetermined signal line integrally or non-integrally.

[0157] In an embodiment, the second electrode line MLI2 of the second electrode ET2[3] connected to the last series stage (e.g., the third series stage) of each pixel PXL may be commonly connected to a plurality of pixels PXL. For example, the second electrode lines MLI2 of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be integrally connected to each other. In an embodiment, the second electrode lines MLI2 of a plurality of pixel units PXU may be integrally connected to each other.

[0158] In the step of aligning the light-emitting element LD, a predetermined second alignment signal (or second alignment voltage) may be supplied to the second electrode line MLI2. During a period in which the display device is actually driven, the voltage of the second power supply VSS or a predetermined second driving signal may be supplied to the second electrode line MLI2.

[0159] In an embodiment, the first electrode line MLI1 and the second electrode line MLI2 may be arranged to face each other, and the first sub-region to the K-th sub-region SAR (e.g., the first sub-region SAR1 to the third sub-region SAR3) of each pixel PXL is disposed between the first electrode line MLI1 and the second electrode line MLI2. For example, the first electrode line MLI1 of each pixel PXL may be arranged adjacent to the first sub-region SAR1 and connected to the first electrode ET1[1] of the first series stage provided in the first sub-region SAR1. The second electrode line MLI2 of each pixel PXL may be arranged adjacent to the last sub-region SAR (e.g., the third sub-region SAR3) and connected to the second electrode ET2[3] of the third series stage provided in the third sub-region SAR3. For example, the first electrode line MLI1 and the second electrode line MLI2 of each pixel PXL may be respectively arranged above the first sub-region SAR1 and below the third sub-region SAR3, and electrically connected to the first electrode ET1[1] of the first sub-region SAR1 and the second electrode ET2[3] of the third sub-region SAR3, respectively.

[0160] For example, the first electrode line MLI1 and the second electrode line MLI2 may be arranged parallel to each other, and the first sub-region to the K-th sub-region SAR of each pixel PXL is disposed between the first electrode line MLI1 and the second electrode line MLI2. For example, each of the first electrode line MLI1 and the second electrode line MLI2 may extend in a second direction DR2 that intersects the first direction DR1 along which the first electrode ET1 and the second electrode ET2 respectively extend. For example, each of the first electrode line MLI1 and the second electrode line MLI2 may extend in a direction perpendicular to the direction along which the first electrode ET1 and the second electrode ET2 respectively extend. In an embodiment, the second direction DR2 may be a horizontal direction (or row direction), but the present disclosure is not limited thereto. For example, in an embodiment, the second direction DR2 may be a vertical direction (or column direction). Alternatively, in an embodiment, the second direction DR2 may be a diagonal direction.

[0161] The electrode line MLI including the first electrode line MLI1 and the second electrode line MLI2 of each pixel PXL may be a main alignment line that is supplied with a predetermined alignment signal to be applied to each light source unit LSU in a step of aligning the light-emitting elements LD in each pixel PXL to manufacture a display device, and is disposed on a path along which an alignment current corresponding to the alignment signal flows. In addition, the electrode line MLI may be a main drive / power line that is supplied with a predetermined drive voltage in a step of driving the display device (e.g., when using the display device) in response to a data signal of each frame to be applied to each light source unit LSU, and is disposed on a path along which a drive current of each pixel PXL flows.

[0162] Each intermediate electrode SLI can be electrically connected to both the second electrode ET2 in the previous sub-region SAR and the first electrode ET1 in the subsequent sub-region SAR among two consecutive sub-regions SAR. For example, in the case where each pixel PXL includes a light source unit LSU formed by three series stages, the pixel PXL may include a first intermediate electrode SLI1 and a second intermediate electrode SLI2. The first intermediate electrode SLI1 is disposed between the first sub-region SAR1 and the second sub-region SAR2 and is electrically connected to the second electrode ET2[1] of the first sub-region SAR1 and the first electrode ET1[2] of the second sub-region SAR2. The second intermediate electrode SLI2 is disposed between the second sub-region SAR2 and the third sub-region SAR3 and is electrically connected to the second electrode ET2[2] of the second sub-region SAR2 and the first electrode ET1[3] of the third sub-region SAR3.

[0163] In an embodiment, each intermediate electrode SLI can be integrally connected to the second electrode ET2 of the previous sub-region SAR and the first electrode ET1 of the subsequent sub-region SAR. In this case, in the step of forming the first electrode ET1 and the second electrode ET2 of each series stage, the intermediate electrode SLI can be formed simultaneously between the series stages. Therefore, each intermediate electrode SLI can be formed between consecutive series stages without a separate additional process of forming the intermediate electrode SLI. According to the foregoing embodiment, the process of manufacturing the pixel PXL and the display device including the pixel PXL can be simplified, and its manufacturing efficiency can be improved.

[0164] In an embodiment, each intermediate electrode SLI can be disposed between the first electrode line MLI1 and the second electrode line MLI2, and can be spaced apart from each of the first electrode line MLI1 and the second electrode line MLI2, and at least one sub-region SAR is disposed therebetween. For example, the first electrode line MLI1, the second electrode line MLI2, and at least one intermediate electrode SLI of each pixel PXL can be disposed parallel to each other, and at least one sub-region SAR is disposed therebetween.

[0165] For example, in the same manner as the first electrode line MLI1 and the second electrode line MLI2, each intermediate electrode SLI can extend in a direction intersecting the direction in which the first electrode ET1 and the second electrode ET2 extend. For example, each intermediate electrode SLI can extend in the second direction DR2 between two consecutive sub-regions SAR.

[0166] In an embodiment, the intermediate electrode SLI of each series stage may be formed in a form commonly connected to a plurality of pixels PXL, and a predetermined intermediate stage alignment signal (or intermediate alignment voltage) may be supplied in the step of aligning the light-emitting element LD. For example, the first intermediate electrode SLI1 of the first pixel PXL1 may be formed in a form commonly connected to the first intermediate electrodes SLI1 of the second pixel PXL2 and the third pixel PXL3, and a predetermined first intermediate stage alignment signal (or first intermediate alignment voltage) may be supplied in the step of aligning the light-emitting element LD. The second intermediate electrode SLI2 of the first pixel PXL1 may be formed in a form commonly connected to the second intermediate electrodes SLI2 of the second pixel PXL2 and the third pixel PXL3, and a predetermined second intermediate stage alignment signal (or second intermediate alignment voltage) may be supplied in the step of aligning the light-emitting element LD.

[0167] In other words, the intermediate electrode SLI may be formed to directly apply a predetermined alignment voltage between consecutive series stages in the step of aligning the light-emitting element LD. Due to the intermediate electrode SLI, even in the step of aligning the light-emitting element LD, an alignment signal may be applied to the light source unit LSU using a series structure for each pixel PXL. Therefore, the alignment current flowing through the display panel PNL can be reduced, so that the efficiency of the energy (electric power, or power) required for aligning the light-emitting element LD can be improved.

[0168] Since the alignment current flowing through the first electrode line MLI1 and the second electrode line MLI2 is reduced, the voltage drop (IR drop) occurring in the first electrode line MLI1 and the second electrode line MLI2 is reduced, so that the line width of the first electrode line MLI1 and / or the second electrode line MLI2 can be reduced. In addition, the capacity of an amplifier (not shown) of a power supply for applying the alignment signal can be reduced.

[0169] In addition, in the case where the intermediate electrode SLI is formed such that the light-emitting element LD can be biased and aligned between the first electrode ET1 and the second electrode ET2 while applying a predetermined alignment voltage between series stages, in the step of aligning the light-emitting element LD during the process of manufacturing the display device, the direction of the alignment voltage / current to be applied to the first electrode ET1 and the second electrode ET2 may match the direction of the driving voltage / current to be applied to the first electrode ET1 and the second electrode ET2 in the step of actually driving the display device. Therefore, when actually driving the display device, the light-emitting element LD can be biased and aligned in a direction corresponding to the forward direction. According to an embodiment of the present disclosure, the number of light-emitting elements LD connected between the first electrode ET1 and the second electrode ET2 in the forward direction for each pixel PXL can be increased. Therefore, the light-emitting elements LD supplied to the emission area EMA of each pixel PXL can be effectively used to form each light source unit LSU.

[0170] Except for the nodes where the first electrode ET1 and the second electrode ET2 are connected in series between the corresponding series stages, different from the first electrode line MLI1 and the second electrode line MLI2, each intermediate electrode SLI may not form a substantial current path. Therefore, each intermediate electrode SLI may be formed to have a width smaller than the widths of the first electrode line MLI1 and the second electrode line MLI2. For example, when the first electrode line MLI1 and the second electrode line MLI2 have a first width W1 and a second width W2 respectively, each intermediate electrode SLI may have a third width W3 smaller than each of the first width W1 and the second width W2. In an embodiment, the first width W1 and the second width W2 may be the same as or different from each other. In the case where the width of each intermediate electrode SLI is reduced, the capacity of the amplifier of the power supply for applying a predetermined alignment signal may be further reduced in the step of aligning the light-emitting element LD.

[0171] After the alignment of the light-emitting element LD is completed, the intermediate electrodes SLI between the pixels PXL may be disconnected and separated. For example, the intermediate electrodes SLI of the corresponding series stages may be disconnected from each other between the first pixel PXL1 and the second pixel PXL2 adjacent to each other, between the second pixel PXL2 and the third pixel PXL3 adjacent to each other, and between the pixel units PXU adjacent to each other. Therefore, the pixels PXL may be separated in a form that can be individually controlled.

[0172] In Figure 6 and Figure 7 In the description of the embodiment of, although in the previous description, the first electrode ET1 and the second electrode ET2 have been described as being separate components due to the corresponding series stages, overall, with respect to the electrodes of each pixel PXL, at least two electrodes provided in multiple series stages may be considered as different regions of a single electrode. For example, the second electrode ET2[1] of the first series stage, the first intermediate electrode SLI1, and the first electrode ET1[2] of the second series stage, which are integrally connected to each other, may be considered as the first electrode portion, the second electrode portion, and the third electrode portion of a single electrode (for example, referred to as the "second electrode"). Similarly, the second electrode ET2[2] of the second series stage, the second intermediate electrode SLI2, and the first electrode ET1[3] of the third series stage, which are integrally connected to each other, may be considered as the first electrode portion, the second electrode portion, and the third electrode portion of another single electrode (for example, referred to as the "third electrode").

[0173] In this regard, the structure of the electrodes provided in the emission area EMA of each pixel PXL will be described. Each pixel PXL may include: at least one first electrode (e.g., the first electrode ET1[1] of the first series stage), electrically connected to the first electrode line MLI1 and extending in the first direction DR1; at least one second electrode, including a first electrode portion and a third electrode portion (e.g., the second electrode ET2[1] of the first series stage and the first electrode ET1[2] of the second series stage) that are spaced apart from the first electrode and both extend in the first direction DR1, and a second electrode portion (e.g., the first intermediate electrode SLI1) that extends in the second direction DR2 between the first electrode and the third electrode; and at least one third electrode (e.g., the second electrode ET2[2] of at least the second series stage), spaced apart from the first electrode and the second electrode and having at least one region extending in the first direction DR1. In addition, each pixel PXL may include at least one first light-emitting element LD1 electrically connected between the first electrode and the second electrode and at least one second light-emitting element LD2 electrically connected between the second electrode and the third electrode.

[0174] In an embodiment, the first electrode portion (the second electrode ET2[1] of the first series stage) of the second electrode may extend in the first direction DR1 and may be spaced apart from the first electrode (the first electrode ET1[1] of the first series stage) with respect to a direction (e.g., the second direction DR2) intersecting the first direction DR1. For example, the first electrode portion of the second electrode may be disposed parallel to the first electrode.

[0175] In an embodiment, the second electrode portion (the first intermediate electrode SLI1) of the second electrode may extend in the second direction DR2 from the first electrode portion (e.g., the lower end region of the first electrode portion). In an embodiment, the second electrode portion of the second electrode may be disposed at a position spaced apart from the first electrode and the third electrode between the first electrode and the third electrode, but the present disclosure is not limited thereto.

[0176] In an embodiment, the third electrode portion (the first electrode ET1[2] of the second series stage) of the second electrode may extend in the first direction DR1 from the second electrode portion. In an embodiment, the first electrode portion and the third electrode portion of the second electrode may be disposed on a line along the first direction DR1, but the present disclosure is not limited thereto. For example, as Figure 6 shown, both the first electrode portion and the third electrode portion of the second electrode may have a structure extending on a line along the first direction DR1. In an embodiment, both the first electrode portion and the third electrode portion of the second electrode may extend in the first direction DR1, but may not be disposed on a line. For example, as Figure 7As shown, both the first electrode portion and the third electrode portion of the second electrode can be bent (or folded) at the node with the second electrode portion.

[0177] Similarly, the third electrode can include a first electrode portion and a third electrode portion that are spaced apart from the first and second electrodes and both extend in the first direction DR1 (e.g., the second electrode ET2[2] of the second series stage and the first electrode ET1[3] of the third series stage), and a second electrode portion that extends in the second direction between the first electrode portion and the third electrode portion (e.g., the second intermediate electrode SLI2). However, in the case where each pixel PXL includes only two series stages, the third electrode can include only the first electrode portion and / or the second electrode portion.

[0178] In an embodiment, the first electrode portion (the second electrode ET2[2] of the second series stage) of the third electrode can extend in the first direction DR1 and can be spaced apart from the third electrode portion (the first electrode ET1[2] of the second series stage) of the second electrode with respect to a direction (e.g., the second direction DR2) that intersects the first direction DR1. For example, the first electrode portion of the third electrode can be disposed parallel to the third electrode portion of the second electrode.

[0179] In an embodiment, the second electrode portion (the second intermediate electrode SLI2) of the third electrode can extend in the second direction DR2 from the first electrode portion (e.g., the lower end region of the first electrode portion). In an embodiment, the second electrode portion of the third electrode can be disposed at a position spaced apart from the second and fourth electrodes between the second and fourth electrodes, but the present disclosure is not limited thereto.

[0180] In an embodiment, the third electrode portion (the first electrode ET1[3] of the third series stage) of the third electrode can extend in the first direction DR1 from the second electrode portion. In an embodiment, the first electrode portion and the third electrode portion of the third electrode can be disposed in a line along the first direction DR1, but the present disclosure is not limited thereto. For example, as Figure 6 shown, both the first electrode portion and the third electrode portion of the third electrode can have a structure that extends in a line along the first direction DR1. In an embodiment, both the first electrode portion and the third electrode portion of the third electrode can extend in the first direction DR1, but may not be disposed in a line. For example, as Figure 7 shown, both the first electrode portion and the third electrode portion of the third electrode can be bent at the node with the second electrode portion.

[0181] The third electrode may be electrically connected to the second electrode line MLI2. In an embodiment, when each pixel PXL includes only two series stages, the third electrode may be directly connected to the second electrode line MLI2. In an embodiment, when each pixel PXL includes three or more series stages, at least one electrode and / or light-emitting element may be connected between the third electrode and the second electrode line MLI2. For example, each pixel PXL may further include at least one third light-emitting element LD3 electrically connected between the third electrode and the second electrode line MLI2 and a fourth electrode (e.g., the second electrode ET2[3] of the third series stage) electrically connected between the third light-emitting element LD3 and the second electrode line MLI2.

[0182] In an embodiment, at least one region of the first electrode and at least one region of the third electrode may be disposed at positions spaced apart from each other on a line. For example, as Figure 6 shown, the first electrode portions of the first electrode and the third electrode may be disposed on a line along the first direction DR1 and may be disposed at positions spaced apart from each other, and the second electrode portion of the second electrode is disposed therebetween. In this case, the first electrode portion and the third electrode portion of the second electrode may be disposed on a line along the first direction DR1. For example, the first electrode portion and the third electrode portion of the second electrode may be spaced apart from the first electrode portions of the first electrode and the third electrode by the same distance in the second direction DR2. The shape, structure, and / or relative disposition relationship of the electrodes disposed in each pixel PXL may be changed according to the embodiment.

[0183] For example, in an embodiment, as Figure 7 shown, the third electrode portions of the first electrode and the second electrode may be disposed on a line at positions spaced apart from each other along the first direction DR1. In this case, the first electrode portion of the second electrode and at least one region of the third electrode (e.g., the first electrode portion of the third electrode) may be disposed on a line at positions spaced apart from each other.

[0184] At least one first light-emitting element LD1 may be electrically connected between the first electrode and the second electrode. At least one second light-emitting element LD2 may be electrically connected between the second electrode and the third electrode. In addition, when each pixel PXL further includes a fourth electrode, at least one third light-emitting element LD3 may be electrically connected between the third electrode and the fourth electrode.

[0185] In an embodiment, the first light-emitting element LD1 may be connected between the first electrode and the first electrode portion of the second electrode. The second light-emitting element LD2 may be connected between the third electrode portion of the second electrode and the first electrode portion of the third electrode. Similarly, the third light-emitting element LD3 may be connected between the third electrode portion of the third electrode and the fourth electrode.

[0186] The first light-emitting element LD1 can be connected between the first electrode and the second electrode in the forward direction. For example, the first end (e.g., P-type end) EP1 of the first light-emitting element LD1 can be electrically connected to the first electrode. The second end (e.g., N-type end opposite to the P-type end) EP2 of the first light-emitting element LD1 can be electrically connected to the second electrode.

[0187] Similarly, the second light-emitting element LD2 can be connected between the second electrode and the third electrode in the forward direction. The third light-emitting element LD3 can be connected between the third electrode and the fourth electrode in the forward direction. For example, the first end (e.g., P-type end) EP1 of the second light-emitting element LD2 can be electrically connected to the second electrode. The second end (e.g., N-type end opposite to the P-type end) EP2 of the second light-emitting element LD2 can be electrically connected to the third electrode. Additionally, the first end (e.g., P-type end) EP1 of the third light-emitting element LD3 can be electrically connected to the third electrode. The second end (e.g., N-type end opposite to the P-type end) EP2 of the third light-emitting element LD3 can be electrically connected to the fourth electrode.

[0188] In other words, according to the viewpoint, the corresponding electrodes and / or electrode portions can be designated by different names or terms. In addition, a plurality of electrodes or electrode portions connected integrally or non-integrally with each other, etc. can be regarded as a single element or separate elements separated from each other. Therefore, the structure of the pixel PXL according to the embodiment of the present disclosure can be interpreted in a narrow sense for each sub-region SAR or pixel PXL, or in a broad sense for each pixel unit PXU or display area DA.

[0189] Figures 8 to 9 are all plan views showing a pixel PXL according to an embodiment of the present disclosure (e.g., showing modified embodiments related to the embodiments of Figure 6 and Figure 7 respectively). In the description of the embodiments of Figure 8 and Figure 9 , the detailed description of the structures similar or identical to those of Figure 6 and Figure 7 will be omitted.

[0190] Refer to Figure 8 and Figure 9, each pixel PXL may also selectively include a first contact electrode CE1 and a second contact electrode CE2 disposed above the first electrode ET1 and the second electrode ET2, respectively. For example, each first contact electrode CE1[1] of the first series stage may be disposed on each corresponding first electrode ET1[1] of the first series stage. Each second contact electrode CE2[1] of the first series stage may be disposed on each corresponding second electrode ET2[1] of the first series stage. Similarly, each first contact electrode CE1[2] of the second series stage may be disposed on each corresponding first electrode ET1[2] of the second series stage. Each second contact electrode CE2[2] of the second series stage may be disposed on each corresponding second electrode ET2[2] of the second series stage. Each first contact electrode CE1[3] of the third series stage may be disposed on each corresponding first electrode ET1[3] of the third series stage. Each second contact electrode CE2[3] of the third series stage may be disposed on each corresponding second electrode ET2[3] of the third series stage.

[0191] In an embodiment, the first contact electrode CE1 may be formed to have a separate pattern above the first electrode ET1 of each series stage. The first contact electrode CE1 may electrically connect each first electrode ET1 to a first end EP1 of at least one light-emitting element LD adjacent to the first electrode ET1.

[0192] Similarly, the second contact electrode CE2 may be formed to have a separate pattern above the second electrode ET2 of each series stage. The second contact electrode CE2 may electrically connect each second electrode ET2 to a second end EP2 of at least one light-emitting element LD adjacent to the second electrode ET2.

[0193] Since the first contact electrode CE1 and the second contact electrode CE2 are formed, the light-emitting element LD can be more reliably connected between the first electrode ET1 and the second electrode ET2.

[0194] In addition, each pixel PXL may also selectively include a first partition wall PW1 (also referred to as "first wall" or "first bank") and a second partition wall PW2 (also referred to as "second wall" or "second bank") disposed below the first electrode ET1 and the second electrode ET2, respectively.

[0195] In an embodiment, the first partition wall PW1 may be disposed to have a separate pattern below the first electrode ET1 of each series stage. If the first partition wall PW1 is disposed below the first electrode ET1, the first electrode ET1 may protrude upward in the region where the first partition wall PW1 is disposed. Therefore, the light emitted from the first end EP1 of the light-emitting element LD facing the first electrode ET1 can be controlled to travel more effectively in the front direction of the display device.

[0196] Similarly, the second partition wall PW2 can be configured to have separate patterns respectively under the second electrodes ET2 of each series stage. If the second partition wall PW2 is disposed under the second electrode ET2, the second electrode ET2 can protrude upward in the region where the second partition wall PW2 is provided therein. Accordingly, the light emitted from the second end EP2 of the light-emitting element LD facing the second electrode ET2 can be controlled to travel more effectively in the front direction of the display device.

[0197] In addition, the display device may further include a bank BNK that defines and / or divides the emission area EMA of each pixel PXL. For example, the bank BNK may be disposed between the emission areas EMA of the pixels PXL to integrally surround each emission area EMA of each pixel PXL including the sub-region SAR. For example, the bank BNK may include a plurality of openings corresponding to the respective emission areas EMA of the pixels PXL and may be formed in a grid shape in the display area DA. In an embodiment, the bank BNK may include a light-shielding material and / or a reflective opaque material such that light leakage between adjacent pixels PXL can be prevented.

[0198] According to Figures 6 to 9 each embodiment shown in

[0199] the light-emitting elements LD supplied to the emission areas EMA of each pixel PXL can be connected at least in a series structure. For example, the light-emitting elements LD supplied to the emission areas EMA of each pixel PXL can be connected in a series / parallel combination structure to form each light source unit LSU. Accordingly, not only can each pixel PXL be reliably driven, but also the driving current flowing through the display panel PNL can be reduced. Accordingly, the power consumption efficiency can be improved.

[0200] In addition, since each intermediate electrode SLI is formed between consecutive series stages, the directions of the alignment voltage / current to be applied to the first electrode ET1 and the second electrode ET2 in the step of aligning the light-emitting element LD can match the directions of the drive voltage / current to be applied to the first electrode ET1 and the second electrode ET2 in the step of actually driving the display device. Therefore, in the case where the light-emitting element LD is biased and aligned between the first electrode ET1 and the second electrode ET2, the number of light-emitting elements LD connected in the forward direction between the first electrode ET1 and the second electrode ET2 of each pixel PXL can be increased.

[0201] In an embodiment, in the step of aligning the light-emitting element LD, the light-emitting elements supplied to the emission region EMA can be controlled to be aligned and biased in any one direction (e.g., in the direction corresponding to the forward direction during operation) by adjusting the alignment signal (or alignment voltage) to be applied to the first electrode ET1 and the second electrode ET2 or by forming a magnetic field. For example, in the step of aligning the light-emitting element LD, when adjusting the waveform of the alignment signal or forming a magnetic field in each emission region EMA, the number of light-emitting elements LD oriented in the forward direction such that each of their first ends EP1 is oriented toward the first electrode ET1 and each of their second ends EP2 is oriented toward the second electrode ET2 can be controlled to be greater than the number of reverse light-emitting elements LDrv oriented such that each of their first ends EP1 is oriented toward the second electrode ET2 and each of their second ends EP2 is oriented toward the first electrode ET1. For example, the light-emitting element LD can be aligned by controlling the process conditions such that the ratio of the number of light-emitting elements LD oriented in the forward direction to the number of reverse light-emitting elements LDrv oriented in the direction opposite to that of the light-emitting element LD becomes approximately 80:20. Therefore, the number of light-emitting elements LD among the light-emitting elements supplied to the emission region EMA of each pixel PXL that can be used as effective light sources to form each light source unit LSU can be increased. That is, according to the foregoing embodiments, the application efficiency of the light-emitting element LD can be improved. In addition, since the number of light-emitting elements LD connected in the forward direction in each series stage is increased, it is possible to prevent the phenomenon that the alignment / drive current does not flow in any one series stage because there is no light-emitting element LD aligned in the forward direction in the series stage, or to prevent the alignment / drive current from concentrating on a small number of light-emitting elements LD aligned in the forward direction. Therefore, each pixel PXL can be reliably driven.

[0202] Figures 10 to 13 are cross-sectional views each showing a pixel PXL according to an embodiment of the present disclosure. For example, Figures 10 to 13 shows corresponding to Figure 8Different embodiments of the cross-section of the first pixel PXL1 of the line I-I'. In the embodiments, the structures of the second pixel PXL2 and the third pixel PXL3 may be substantially the same as or similar to the structure of the first pixel PXL1. Hereinafter, reference will be made to Figures 10 to 13 and Figures 4 to 9 to describe embodiments of the cross-section structure of each pixel PXL.

[0203] Referring to Figures 4 to 13 , according to an embodiment of the present disclosure, the pixel PXL and the display device including the pixel PXL may include a display element layer DPL, and the display element layer DPL includes a plurality of light-emitting elements LD provided in the emission area EMA of each pixel PXL on one surface of the substrate layer BSL. In addition, the pixel PXL and the display device including the pixel PXL may also selectively include a pixel circuit layer PCL. For example, the pixel PXL and the display device including the pixel PXL may also include a pixel circuit layer PCL provided between the substrate layer BSL and the display element layer DPL.

[0204] In an embodiment, the pixel circuit layer PCL may include at least one circuit element electrically connected to the light-emitting element LD. For example, the pixel circuit layer PCL may include at least one circuit element forming the pixel circuit PXC of each pixel PXL.

[0205] For example, the pixel circuit layer PCL may include a plurality of transistors T and storage capacitors Cst provided in each pixel area and forming the corresponding pixel circuit PXC, and may also include at least one power line and / or signal line connected to the pixel circuit PXC and / or the light source unit LSU. Here, in the case where the pixel circuit PXC is omitted and each light source unit LSU is directly connected to the first power line PL1 and the second power line PL2 (or a predetermined signal line), the pixel circuit layer PCL may be omitted. For the sake of illustration, Figures 10 to 13 only one transistor T among the circuit elements and lines provided on the pixel circuit layer PCL is representatively shown. Here, the planar / cross-section structure of the pixel circuit layer PCL may be changed in various ways. The position and cross-section structure of each transistor T may be changed in various ways according to the embodiments.

[0206] In addition, the pixel circuit layer PCL may include a plurality of insulating layers provided between the corresponding electrodes and / or lines. In an embodiment, the pixel circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, and a passivation layer PSV continuously stacked on one surface of the substrate layer BSL. In some embodiments, the pixel circuit layer PCL may also include at least one light-shielding pattern (not shown) provided under at least some of the transistors T.

[0207] The buffer layer BFL can prevent impurities from diffusing into each circuit element. The buffer layer BFL can be formed of a single layer, or can be formed of a multi-layer having at least two layers. In the case where the buffer layer BFL has a multi-layer structure, the corresponding layers can be formed of the same material or different materials. In an embodiment, the buffer layer BFL can be omitted.

[0208] In an embodiment, each transistor T can include a semiconductor layer SCL, a gate electrode GE, and a first transistor electrode TE1 and a second transistor electrode TE2. Although Figures 10 to 13 an embodiment is shown in which each transistor T includes a first transistor electrode TE1 and a second transistor electrode TE2 formed separately from the semiconductor layer SCL, the present disclosure is not limited thereto. For example, in an embodiment, the first transistor electrode TE1 and / or the second transistor electrode TE2 in at least one transistor T provided in each pixel region can be integrally formed with the corresponding semiconductor layer SCL.

[0209] The semiconductor layer SCL can be provided on the buffer layer BFL. For example, the semiconductor layer SCL can be provided between the gate insulating layer GI and the substrate layer BSL on which the buffer layer BFL is formed. The semiconductor layer SCL can include a first region in contact with each first transistor electrode TE1, a second region in contact with each second transistor electrode TE2, and a channel region provided between the first region and the second region. In an embodiment, one of the first region and the second region can be a source region, and the other can be a drain region.

[0210] In an embodiment, the semiconductor layer SCL can be a semiconductor pattern formed of polycrystalline silicon, amorphous silicon, an oxide semiconductor, etc. The channel region of the semiconductor layer SCL can be an intrinsic semiconductor that is an undoped semiconductor pattern. Each of the first region and the second region of the semiconductor layer SCL can be a semiconductor pattern doped with a predetermined impurity.

[0211] The gate electrode GE can be provided on the semiconductor layer SCL, and the gate insulating layer GI is interposed therebetween. For example, the gate electrode GE can be provided between the gate insulating layer GI and the interlayer insulating layer ILD, and can overlap at least one region of the semiconductor layer SCL.

[0212] The first transistor electrode TE1 and the second transistor electrode TE2 can be disposed on each semiconductor layer SCL, and at least one interlayer insulating layer ILD is disposed therebetween. For example, the first transistor electrode TE1 and the second transistor electrode TE2 can be disposed on respective different ends of the semiconductor layer SCL, and the gate insulating layer GI and the interlayer insulating layer ILD are disposed therebetween. The first transistor electrode TE1 and the second transistor electrode TE2 can be electrically connected to each semiconductor layer SCL. For example, the first transistor electrode TE1 and the second transistor electrode TE2 can be connected to the first region and the second region of the semiconductor layer SCL through corresponding contact holes penetrating through the gate insulating layer GI and the interlayer insulating layer ILD. In an embodiment, any one of the first transistor electrode TE1 and the second transistor electrode TE2 can be a source electrode, and the other can be a drain electrode.

[0213] At least one transistor T disposed in the pixel circuit PXC can be connected to at least one pixel electrode. For example, Figure 5e Any one (e.g., the drain electrode) of the first transistor electrode TE1 and the second transistor electrode TE2 of the first transistor T1 shown in can be electrically connected to the first electrode ET1[1] of the first series stage of the corresponding pixel PXL through a contact hole (e.g., the first contact hole CH1) penetrating through the passivation layer PSV and through a first electrode line MLI1 disposed above the passivation layer PSV.

[0214] In an embodiment, at least one signal line and / or power line connected to each pixel PXL can be disposed on the same layer as a layer of an electrode in each circuit element forming the pixel circuit PXC. For example, the scan line Si of each pixel PXL can be disposed on the same layer as the layer of the gate electrode GE. The data line Dj of each pixel PXL can be disposed on the same layer as the layer of the first transistor electrode TE1 and the second transistor electrode TE2 of the transistor T. In addition, the first power line PL1 and / or the second power line PL2 can be disposed on the same layer as the layer of the gate electrode GE of the transistor T or the first transistor electrode TE1 and the second transistor electrode TE2.

[0215] In an embodiment, the display element layer DPL may include a light source unit LSU for each pixel PXL. For example, the display element layer DPL may include a plurality of first electrodes ET1 and second electrodes ET2 disposed in an emission area EMA of each pixel PXL, and a plurality of light-emitting elements LD disposed between the first electrode ET1 and the second electrode ET2. In addition, the display element layer DPL may selectively include a first partition wall PW1 and a second partition wall PW2 configured to cause a predetermined area of the first electrode ET1 and the second electrode ET2 to protrude upward, and a first contact electrode CE1 and a second contact electrode CE2 configured to more reliably connect the light-emitting element LD between the first electrode ET1 and the second electrode ET2. Additionally, the display element layer DPL may include, for example, at least one conductive layer and / or insulating layer.

[0216] In an embodiment, the display element layer DPL may include a first partition wall PW1, a second partition wall PW2, a first electrode ET1, a second electrode ET2, a first insulating layer INS1, a light-emitting element LD, an insulating pattern INP, a first contact electrode CE1, a second contact electrode CE2, and a second insulating layer INS2 that are continuously provided and / or formed above the substrate layer BSL and / or the pixel circuit layer PCL.

[0217] The first partition wall PW1 and the second partition wall PW2 may be disposed at positions spaced apart from each other in the emission area of each pixel PXL. The first partition wall PW1 and the second partition wall PW2 may protrude from the substrate layer BSL and / or the pixel circuit layer PCL in the height direction of the substrate layer BSL. In an embodiment, the first partition wall PW1 and the second partition wall PW2 may have substantially the same height, but the present disclosure is not limited thereto.

[0218] In an embodiment, the first partition wall PW1 may be disposed between the substrate layer BSL and / or the pixel circuit layer PCL and each first electrode ET1. The first partition wall PW1 may be disposed adjacent to the first end EP1 of the light-emitting element LD. For example, one side surface of each first partition wall PW1 may be positioned adjacent to and configured to face the first end EP1 of the light-emitting element LD.

[0219] In an embodiment, the second partition wall PW2 may be disposed between the substrate layer BSL and / or the pixel circuit layer PCL and the second electrode ET2. The second partition wall PW2 may be disposed adjacent to the second end EP2 of the light-emitting element LD. For example, one side surface of the second partition wall PW2 may be positioned adjacent to and configured to face the second end EP2 of the light-emitting element LD.

[0220] In an embodiment, each of the first partition wall PW1 and the second partition wall PW2 may have various shapes. In an embodiment, asFigure 10 and Figure 12 As shown in Figure 12 , the first partition wall PW1 and the second partition wall PW2 may have a trapezoidal cross section whose width gradually decreases upward. In this case, each of the first partition wall PW1 and the second partition wall PW2 may have an inclined surface on at least one side. In an embodiment, as shown in Figure 11 and Figure 13 As shown in Figure 13 , the first partition wall PW1 and the second partition wall PW2 may have a semi-circular or semi-elliptical cross section whose width gradually decreases upward. In this case, each of the first partition wall PW1 and the second partition wall PW2 may have a curved surface on at least one side surface. At least one electrode and / or insulating layer provided above the first partition wall PW1 and the second partition wall PW2 may have a curved surface in a region corresponding to the first partition wall PW1 and the second partition wall PW2.

[0221] In other words, the shape of each of the first partition wall PW1 and the second partition wall PW2 may be changed in various ways without being particularly limited. In an embodiment, at least one of the first partition wall PW1 and the second partition wall PW2 may be omitted or changed in position.

[0222] Each of the first partition wall PW1 and the second partition wall PW2 may include an insulating material having at least one inorganic material and / or organic material. For example, the first partition wall PW1 and the second partition wall PW2 may include at least one inorganic layer containing various known inorganic insulating materials (such as silicon nitride (SiN x )) or silicon oxide (SiO x ). Optionally, the first partition wall PW1 and the second partition wall PW2 may include at least one organic layer and / or a photoresist layer containing various known organic insulating materials, or may form a single-layer or multi-layer insulator containing a combination of organic / inorganic materials. In an embodiment of the present disclosure, the constituent materials of the first partition wall PW1 and the second partition wall PW2 may be changed in various ways.

[0223] In an embodiment, each of the first partition wall PW1 and the second partition wall PW2 may be used as a reflector. For example, the first partition wall PW1 and the second partition wall PW2 together with the first electrode ET1 and the second electrode ET2 provided on the first partition wall PW1 and the second partition wall PW2 may be used as a reflector for guiding the light emitted from each light-emitting element LD in a desired direction, thereby improving the light efficiency of the pixel PXL.

[0224] The first electrode ET1 and the second electrode ET2 may be respectively provided above the first partition wall PW1 and the second partition wall PW2. The first electrode ET1 and the second electrode ET2 may be provided at positions spaced apart from each other in each pixel region (particularly, each emission region EMA).

[0225] In an embodiment, the first electrode ET1 and the second electrode ET2 respectively disposed above the first partition wall PW1 and the second partition wall PW2 may have shapes corresponding to the respective shapes of the first partition wall PW1 and the second partition wall PW2. For example, the first electrode ET1 and the second electrode ET2 may have inclined surfaces or curved surfaces respectively corresponding to the first partition wall PW1 and the second partition wall PW2, and protrude in the height direction of the substrate layer BSL.

[0226] Each of the first electrode ET1 and the second electrode ET2 may include at least one conductive material. For example, each of the first electrode ET1 and the second electrode ET2 may include at least one metal among various metal materials (including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), copper (Cu), etc. or alloys thereof), at least one of conductive oxides (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), antimony zinc oxide (AZO), indium tin zinc oxide (ITZO), tin oxide (SnO2)) and conductive polymers (such as PEDOT), but the present disclosure is not limited thereto. For example, each of the first electrode ET1 and the second electrode ET2 may include other conductive materials such as carbon nanotubes and graphene. In other words, each of the first electrode ET1 and the second electrode ET2 may include at least one of various conductive materials to have conductivity, and the constituent materials thereof are not particularly limited. In addition, each of the first electrode ET1 and the second electrode ET2 may have the same conductive material or at least one different conductive material.

[0227] Each of the first electrode ET1 and the second electrode ET2 may have a single-layer structure or a multi-layer structure. For example, each of the first electrode ET1 and the second electrode ET2 may include at least one reflective electrode layer. Each of the first electrode ET1 and the second electrode ET2 may also selectively include at least one of at least one transparent electrode layer disposed above and / or below the reflective electrode layer and at least one conductive cover layer covering the upper portion of the reflective electrode layer and / or the transparent electrode layer.

[0228] In an embodiment, the reflective electrode layer of each of the first electrode ET1 and the second electrode ET2 may be formed of a conductive material having a uniform reflectivity. For example, the reflective electrode layer may include at least one of various metal materials (including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), copper (Cu), etc. or alloys thereof), but the present disclosure is not limited thereto. In other words, the reflective electrode layer may be formed of various reflective conductive materials. Each of the first electrode ET1 and the second electrode ET2 including the reflective electrode layer may enable the light emitted from the opposite ends (i.e., the first end EP1 and the second end EP2) of each light-emitting element LD to travel in the direction of the displayed image (e.g., in the forward direction). Specifically, if the first electrode ET1 and the second electrode ET2 respectively have inclined or curved surfaces corresponding to the shapes of the first partition wall PW1 and the second partition wall PW2 and are respectively arranged to face the first end EP1 and the second end EP2 of the light-emitting element LD, the light emitted from the first end EP1 and the second end EP2 of each light-emitting element LD can be reflected by the first electrode ET1 and the second electrode ET2, and thus can travel more reliably in the forward direction of the display panel PNL (e.g., in the upward direction of the substrate layer BSL). Accordingly, the efficiency of the light emitted from the light-emitting element LD can be improved.

[0229] In addition, the transparent electrode layer of each of the first electrode ET1 and the second electrode ET2 may be formed of various transparent conductive materials. For example, the transparent electrode layer may include ITO, IZO, or ITZO, but the present disclosure is not limited thereto. In an embodiment, each of the first electrode ET1 and the second electrode ET2 may have a three-layer structure having a stacked structure of ITO / Ag / ITO. Thus, if both the first electrode ET1 and the second electrode ET2 are formed of a multilayer structure including at least two layers, the voltage drop caused by signal delay (RC delay) can be minimized. Therefore, a desired voltage can be effectively transmitted to the light-emitting element LD.

[0230] Further, if each of the first electrode ET1 and the second electrode ET2 includes a conductive cover layer covering the reflective electrode layer and / or the transparent electrode layer, the reflective electrode layers of the first electrode ET1 and the second electrode ET2 can be prevented from being damaged due to defects caused during the manufacturing process of the pixel PXL. However, the conductive cover layer may be selectively included in the first electrode ET1 and the second electrode ET2 and may be omitted according to the embodiment. In addition, the conductive cover layer may be considered as a component of each of the first electrode ET1 and the second electrode ET2, or as a separate component provided on the first electrode ET1 and the second electrode ET2.

[0231] The first insulating layer INS1 may be disposed on a predetermined region of the first electrode ET1 and the second electrode ET2. For example, the first insulating layer INS1 may be formed to cover a predetermined region of the first electrode ET1 and the second electrode ET2, and may include openings to expose other predetermined regions of the first electrode ET1 and the second electrode ET2. For example, the first insulating layer INS1 may expose the first electrode ET1 and the second electrode ET2 in a predetermined first contact portion CNT1 and a second contact portion CNT2, respectively. In some embodiments, the first insulating layer INS1 may be omitted. In this case, the light-emitting element LD may be directly disposed on one end of each of the passivation layer PSV and / or the first electrode ET1 and the second electrode ET2.

[0232] In an embodiment, the first insulating layer INS1 may be mainly formed to cover the entire surface of the first electrode ET1 and the second electrode ET2. After supplying the light-emitting element LD and aligning the light-emitting element LD on the first insulating layer INS1, the first insulating layer INS1 may be partially opened to expose the first electrode ET1 and the second electrode ET2 in corresponding predetermined regions (e.g., corresponding first contact portion CNT1 and second contact portion CNT2) on the first partition wall PW1 and the second partition wall PW2. In an embodiment, the first insulating layer INS1 may be patterned in the form of a separate pattern that is partially disposed under the light-emitting element LD after the supply and alignment of the light-emitting element LD have been completed.

[0233] In other words, the first insulating layer INS1 may be disposed between the first electrode ET1 and the second electrode ET2 and the light-emitting element LD, and may expose at least one region of each of the first electrode ET1 and the second electrode ET2. After forming the first electrode ET1 and the second electrode ET2, the first insulating layer INS1 may be formed to cover the first electrode ET1 and the second electrode ET2, so that damage to the first electrode ET1 and the second electrode ET2 can be prevented or metal precipitation in subsequent processes can be prevented. In addition, the first insulating layer INS1 may stably support each light-emitting element LD.

[0234] The first insulating layer INS1 may be formed of a single layer or multiple layers, and may include at least one inorganic insulating material and / or organic insulating material. For example, the first insulating layer INS1 may include various organic / inorganic insulating materials including silicon nitride (SiN x ), silicon oxide (SiO x ), aluminum oxide (Al2O3), etc. There is no particular limitation on the constituent material of the first insulating layer INS1.

[0235] A plurality of light emitting elements LD may be supplied to each pixel region (specifically, an emission region EMA in which a first insulating layer INS1 is formed for each pixel PXL) and aligned in each pixel region (specifically, an emission region EMA in which a first insulating layer INS1 is formed for each pixel PXL). For example, a plurality of light emitting elements LD may be supplied to each emission region EMA by an inkjet method or the like, and the light emitting elements LD may be directionally aligned between a first electrode ET1 and a second electrode ET2 by a predetermined alignment voltage (or alignment signal) applied to the first electrode ET1 and the second electrode ET2.

[0236] In an embodiment, at least some of the light emitting elements LD may be disposed horizontally between a pair of first electrodes ET1 and second electrodes ET2 such that opposite ends (i.e., a first end EP1 and a second end EP2) of each light emitting element LD with respect to its longitudinal direction overlap with the pair of first electrodes ET1 and second electrodes ET2. In addition, in an embodiment, some other light emitting elements LD may be disposed diagonally between a pair of first electrodes ET1 and second electrodes ET2. In an embodiment, at least some of the light emitting elements LD may be disposed between a pair of first electrodes ET1 and second electrodes ET2 such that at least some of the light emitting elements LD do not overlap with the first electrodes ET1 and second electrodes ET2, and may be connected to the first electrode ET1 and the second electrode ET2 through a first contact electrode CE1 and a second contact electrode CE2, respectively.

[0237] An insulating pattern INP may be disposed on a predetermined region of the light emitting element LD. For example, the insulating pattern INP may expose the first end EP1 and the second end EP2 of the light emitting element LD, and may be disposed only partially above a predetermined region of the light emitting element LD including a corresponding central region of the light emitting element LD. The insulating pattern INP may be formed in an independent pattern in each emission region EMA, but the present disclosure is not limited thereto. According to an embodiment, the insulating pattern INP may be omitted. In this case, opposite ends of the first contact electrode CE1 and the second contact electrode CE2 may be directly disposed on the light emitting element LD.

[0238] The insulating pattern INP may be formed of a single layer or multiple layers, and may include at least one inorganic insulating material and / or organic insulating material. For example, the insulating pattern INP may include various organic / inorganic insulating materials including silicon nitride (SiN x ), silicon oxide (SiO x ), aluminum oxide (Al2O3), a photoresist (PR) material, etc. The constituent material of the insulating pattern INP is not particularly limited.

[0239] After the alignment of the light-emitting element LD has been completed, an insulating pattern INP is formed on the light-emitting element LD so that the light-emitting element LD can be prevented from being removed from the alignment position. In addition, when there is a space between the first insulating layer INS1 and the light-emitting element LD, the space can be filled with an insulating material introduced therein during the process of forming the insulating pattern INP. Therefore, the light-emitting element LD can be supported more stably.

[0240] Opposite ends of the light-emitting element LD not covered by the insulating pattern INP (i.e., the first end EP1 and the second end EP2) can be covered by the first contact electrode CE1 and the second contact electrode CE2, respectively. For example, corresponding ends of the first contact electrode CE1 and the second contact electrode CE2 can be disposed on the first end EP1 and the second end EP2 of the light-emitting element LD at positions spaced apart from each other, with the insulating pattern INP therebetween.

[0241] In an embodiment, as Figure 10 and Figure 11 shown, the first contact electrode CE1 and the second contact electrode CE2 can be formed simultaneously on the same layer on one surface of the substrate layer BSL. Therefore, the process of manufacturing the pixel PXL and the display device including the pixel PXL can be simplified. For example, compared with the case of forming the first contact electrode CE1 and the second contact electrode CE2 through corresponding mask processes, the number of mask processes required to form the pixel PXL can be reduced, and the first contact electrode CE1 and the second contact electrode CE2 can be formed more easily.

[0242] In an embodiment, as Figure 12 and Figure 13 shown, the first contact electrode CE1 and the second contact electrode CE2 can be formed continuously on different layers on one surface of the substrate layer BSL. An additional third insulating layer INS3 can be provided between the first contact electrode CE1 and the second contact electrode CE2. In other words, the positions and the relative setting relationship of the first contact electrode CE1 and the second contact electrode CE2 can be changed in various ways.

[0243] In addition, the first contact electrode CE1 and the second contact electrode CE2 may be respectively disposed above the first electrode ET1 and the second electrode ET2 to cover the exposed areas of the first electrode ET1 and the second electrode ET2 (e.g., the first contact portion CNT1 and the second contact portion CNT2). For example, the first contact electrode CE1 and the second contact electrode CE2 may be respectively disposed on at least a predetermined area of the first electrode ET1 and the second electrode ET2 to contact the first electrode ET1 and the second electrode ET2 in the first contact portion CNT1 and the second contact portion CNT2, respectively. Accordingly, the first contact electrode CE1 and the second contact electrode CE2 may be electrically connected to the first electrode ET1 and the second electrode ET2, respectively. The first electrode ET1 and the second electrode ET2 may be electrically connected to the first end EP1 and the second end EP2 of the light-emitting element LD through the first contact electrode CE1 and the second contact electrode CE2, respectively.

[0244] In an embodiment, the first contact electrode CE1 and the second contact electrode CE2 may be formed of various transparent conductive materials. For example, the first contact electrode CE1 and the second contact electrode CE2 may include at least one of various transparent conductive materials including ITO, IZO, and ITZO, and may be substantially transparent or semi-transparent to satisfy a predetermined transmittance. Accordingly, the light emitted from the light-emitting element LD through the first end EP1 and the second end EP2 may pass through the first contact electrode CE1 and the second contact electrode CE2 and be emitted from the display device.

[0245] The second insulating layer INS2 may be disposed on the first contact electrode CE1 and the second contact electrode CE2. For example, the second insulating layer INS2 may be formed and / or disposed on the entire surface of the display area DA of the substrate layer BSL on which the first partition wall PW1 and the second partition wall PW2, the first electrode ET1 and the second electrode ET2, the light-emitting element LD, the insulating pattern INP, and the first contact electrode CE1 and the second contact electrode CE2 are formed, such that the second insulating layer INS2 may cover the first partition wall PW1 and the second partition wall PW2, the first electrode ET1 and the second electrode ET2, the light-emitting element LD, the insulating pattern INP, and the first contact electrode CE1 and the second contact electrode CE2. The second insulating layer INS2 may include at least one inorganic layer and / or organic layer.

[0246] In an embodiment, the second insulating layer INS2 may include a thin film encapsulation layer having a multilayer structure, but the present disclosure is not limited thereto. In some embodiments, at least one outer coating and / or a packaging substrate, etc. may be further disposed above the second insulating layer INS2.

[0247] In an embodiment, the second insulating layer INS2 may be formed of a single layer or multiple layers and may include at least one inorganic insulating material and / or organic insulating material. For example, the second insulating layer INS2 may include various known organic / inorganic insulating materials including silicon nitride (SiN x ), silicon oxide (SiO x ), etc. There is no particular limitation on the constituent material of the second insulating layer INS2.

[0248] Figures 14a to 14c FIGS. are plan views sequentially showing a method of manufacturing a display device according to an embodiment of the present disclosure (for example, an embodiment showing a method of manufacturing a display device including a pixel unit PXU including Figure 8 ). In Figures 14a to 14c , in order to more clearly show the connection / disconnection structure of the electrode lines MLI between the pixels PXL, the illustration of the bank BNK will be omitted.

[0249] Referring to Figures 4 to 14a , a first electrode ET1 and a second electrode ET2 of the pixel PXL, a first electrode line MLI1 and a second electrode line MLI2, and an intermediate electrode SLI, etc. may be formed on a substrate layer BLS (or on a substrate layer BLS on which a pixel circuit layer PCL is formed). A plurality of light-emitting elements LD may be supplied to an emission region EMA on which the first electrode ET1 and the second electrode ET2, the first electrode line MLI1 and the second electrode line MLI2, and the intermediate electrode SLI are formed for each pixel PXL. By applying a predetermined alignment signal between the first electrode line MLI1 and the second electrode line MLI2 and the intermediate electrode SLI, the light-emitting element LD can be aligned between the first electrode ET1 and the second electrode ET2. In the step of aligning the light-emitting element LD, the first electrode line MLI1 and the second electrode line MLI2 may be main alignment lines through which an alignment current corresponding to the alignment signal flows, and the intermediate electrode SLI may be a sub-alignment line for directly applying a predetermined alignment signal between series stages.

[0250] In an embodiment, the first electrode line MLI1 and the second electrode line MLI2 and the intermediate electrode SLI may be first commonly connected to a plurality of pixels PXL. For example, the first electrode line MLI1 of the first pixel PXL1 may be integrally formed with the first electrode line MLI1 of the second pixel PXL2 and the third pixel PXL3. The second electrode line MLI2 of the first pixel PXL1 may be integrally formed with the second electrode line MLI2 of the second pixel PXL2 and the third pixel PXL3. For example, the first electrode line MLI1 may be first formed to have a closed state rather than an open state in an open line region MLIda between the first pixel PXL1 to the third pixel PXL3.

[0251] Similarly, each intermediate electrode SLI of the first pixel PXL1 can be integrally formed with the corresponding intermediate electrodes SLI of the second pixel PXL2 and the third pixel PXL3 (e.g., the intermediate electrodes SLI disposed between the same row or consecutive series stages in the same order). For example, the first intermediate electrode SLI1 disposed between the first series stage and the second series stage of the first pixel PXL1 can be integrally formed with the first intermediate electrode SLI1 disposed between the first series stage and the second series stage of the second pixel PXL2 and the third pixel PXL3. The second intermediate electrode SLI2 disposed between the second series stage and the third series stage of the first pixel PXL1 can be integrally formed with the second intermediate electrode SLI2 disposed between the second series stage and the third series stage of the second pixel PXL2 and the third pixel PXL3. For example, each intermediate electrode SLI can be first formed in the open line region SLIda between the first pixel PXL1 to the third pixel PXL3 to have a closed state instead of an open state.

[0252] In an embodiment, since a predetermined alignment signal is supplied through the first electrode line MLI1, the second electrode line MLI2, and the intermediate electrode SLI, a predetermined alignment voltage can be directly applied between the first electrode ET1 and the second electrode ET2 of each series stage. For example, since the first alignment signal generator SG1, the second alignment signal generator SG2, and the third alignment signal generator SG3 (or different output channels of a single signal generator) are respectively connected between the first electrode line MLI1 and the first intermediate electrode SLI1, between the first intermediate electrode SLI1 and the second intermediate electrode SLI2, and between the second intermediate electrode SLI2 and the second electrode line MLI2, a predetermined AC voltage can be applied to each series stage.

[0253] Referring to Figure 14a and Figure 14b , after the alignment of the light emitting element LD has been completed, the first electrode line MLI1 is disconnected in the open line region MLIda between adjacent pixels PXL, so that the first electrode lines MLI1 of the pixels PXL can be separated from each other. In addition, with respect to the intermediate electrode SLI, the intermediate electrode SLI is disconnected in the open line region SLIda between adjacent pixels PXL, so that the intermediate electrodes SLI of the pixels PXL can be separated from each other.

[0254] Referring to Figure 14c , each first contact electrode CE1 can be formed on each corresponding first electrode ET1 and the first end EP1 adjacent thereto of the light emitting element LD. Each second contact electrode CE2 can be formed on each corresponding second electrode ET2 and the second end EP2 adjacent thereto of the light emitting element LD. Therefore, the light emitting element LD can be reliably connected between the first electrode ET1 and the second electrode ET2.

[0255] In an embodiment, the steps may be performed in the reverse order Figure 14b of separating the first electrode line MLI1 and the intermediate electrode SLI shown in Figure 14c and forming the first contact electrode CE1 and the second contact electrode CE2 shown in. For example, in an embodiment of the present disclosure, after the alignment of the light-emitting element LD is completed, the first contact electrode CE1 and the second contact electrode CE2 are respectively formed on the first end EP1 and the second end EP2 of the light-emitting element LD, and thereafter, the first electrode line MLI1 and the intermediate electrode SLI may be separated between the pixels PXL.

[0256] In addition, in an embodiment, when each pixel PXL does not include the first contact electrode CE1 and the second contact electrode CE2, the process of forming the first contact electrode CE1 and the second contact electrode CE2 may be omitted. In this case, each first electrode ET1 may be directly connected to the first end EP1 of an adjacent light-emitting element LD, and each second electrode ET2 may be directly connected to the second end EP2 of an adjacent light-emitting element LD.

[0257] Figures 15 to 16 are plan views each showing a method of manufacturing a display device according to an embodiment of the present disclosure (for example, showing different modified embodiments related to the embodiment of Figure 14a ). In the description of the embodiments of Figure 15 and Figure 16 , the detailed description of the structures similar or identical to those of the embodiment of Figure 14a will be omitted.

[0258] Referring to Figure 15 , the shapes and / or arrangement structures of the first electrode ET1 and the second electrode ET2 may be changed in various ways according to the embodiment. In an embodiment, although the shapes and / or arrangement structures of the first electrode ET1 and the second electrode ET2 are changed, the light-emitting element LD may be aligned between the first electrode ET1 and the second electrode ET2 of each series stage in a manner substantially the same as that of the embodiment of Figure 14a . For example, in the embodiment of Figure 15 , a predetermined AC voltage may also be applied to each series stage by connecting an alignment signal generator (for example, a first alignment signal generator SG1, a second alignment signal generator SG2, and a third alignment signal generator SG3) between the first electrode line MLI1 and the first intermediate electrode SLI1, between the first intermediate electrode SLI1 and the second intermediate electrode SLI2, and between the second intermediate electrode SLI2 and the second electrode line MLI2, respectively.

[0259] Referring to Figure 16, in the step of aligning the light-emitting element LD, the AC voltage output from a single alignment signal generator SG can be distributed and supplied to a plurality of series stages through a power transformer TRF. For example, the power transformer TRF can be connected between the alignment signal generator SG configured to output a predetermined AC voltage and the first electrode line MLI1, the second electrode line MLI2, and the intermediate electrode SLI. In an embodiment, the power transformer TRF can include output coils corresponding to the respective series stages. For example, the power transformer TRF can include an input coil Li connected to the alignment signal generator SG and a first coil Lo1, a second coil Lo2, and a third coil Lo3 respectively connected to the opposite ends of the first series stage, the second series stage, and the third series stage. In other words, the method of applying the alignment signal can be changed in various ways according to the embodiments. For example, a predetermined alignment signal can be supplied to the first electrode ET1 and the second electrode ET2 of each series stage through various power systems and / or power supply methods.

[0260] In the various embodiments of the present disclosure described above, in the steps of aligning and driving the light-emitting element LD, a series structure can be used in the same way. For example, in the two steps of alignment and driving, the light-emitting element LD can be connected in a series / parallel combination structure. Therefore, the power efficiency for aligning the light-emitting element LD can be improved, and the light-emitting element LD aligned (e.g., biased alignment) between the first electrode ET1 and the second electrode ET2 can be used more effectively to form each light source unit LSU. In addition, by applying at least a series structure to each light source unit LSU, the alignment / driving current flowing through the display panel PNL can be reduced, so that the capacity of the amplifier provided at the output terminal of the power supply (e.g., the power system for applying a predetermined alignment signal) used when aligning the light-emitting element LD and the width of the first electrode line MLI1 and / or the second electrode line MLI2 can be selectively reduced.

[0261] Although the spirit and scope of the present disclosure are described through detailed embodiments, it should be noted that the above embodiments are merely descriptive and should not be considered restrictive. Those skilled in the art should understand that various changes, substitutions, and modifications can be made without departing from the scope of the disclosure defined by the claims.

[0262] The scope of the present disclosure is not limited by the specific implementation manners of this specification and should be defined by the appended claims. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present disclosure.

Claims

1. A display device, the display device including pixels disposed in a display area, the pixels including: A first electrode extending in a first direction; A second electrode including a first electrode portion, a second electrode portion, and a third electrode portion, the first electrode portion being spaced apart from the first electrode in a second direction intersecting the first direction and extending in the first direction, the second electrode portion extending from the first electrode portion in the second direction, and the third electrode portion extending from the second electrode portion in the first direction; A third electrode including at least one region spaced apart from the third electrode portion in the second direction intersecting the first direction and extending in the first direction; A first light-emitting element connected between the first electrode and the second electrode; And A second light-emitting element connected between the second electrode and the third electrode, Wherein the at least one region of the third electrode and the first electrode are disposed at positions spaced apart from each other on a line with respect to the first direction, and the first electrode portion and the third electrode portion are disposed on a line with respect to the first direction, or The first electrode and the third electrode portion are disposed at positions spaced apart from each other on a line with respect to the first direction, and the at least one region of the third electrode and the first electrode portion are disposed at positions spaced apart from each other on a line with respect to the first direction.

2. The display device according to claim 1, wherein The second electrode portion is disposed between the first electrode and the third electrode.

3. The display device according to claim 1, Among them, The first electrode is spaced apart from the first electrode portion with respect to the second direction, and Wherein the third electrode is spaced apart from the third electrode portion with respect to the second direction.

4. The display device according to claim 1, Among them, The first light-emitting element includes a P-type end electrically connected to the first electrode and an N-type end electrically connected to the second electrode, and Wherein the second light-emitting element includes a P-type end electrically connected to the second electrode and an N-type end electrically connected to the third electrode.

5. The display device according to claim 1, the display device further including: A first electrode line electrically connected to the first electrode and configured to be supplied with a first power voltage or a first driving signal; And A second electrode line electrically connected to the third electrode and configured to be supplied with a second power voltage or a second driving signal.

6. The display device according to claim 5, the display device further including: A third light-emitting element including a P-type end electrically connected to the third electrode and an N-type end opposite to the P-type end; And A fourth electrode electrically connected between the N-type end of the third light-emitting element and the second electrode line.

7. A display device, the display device including a first pixel, the first pixel including light-emitting elements disposed in a plurality of series stages, Among them, The first pixel including: A first sub-region to a Kth sub-region, corresponding to a first series stage to a Kth series stage respectively, K being a natural number of 2 or greater; The first electrode and the second electrode of each of the plurality of series stages extend in a first direction in each of the first sub-region to the K-th sub-region and are disposed at positions spaced apart from each other in a second direction intersecting the first direction; The first light-emitting element to the K-th light-emitting element are respectively connected between the first electrode and the second electrode in the first sub-region to the K-th sub-region; The first electrode line is connected to the first electrode of the first sub-region; The second electrode line is connected to the second electrode of the K-th sub-region; and At least one intermediate electrode is disposed between two consecutive sub-regions among the first sub-region to the K-th sub-region and is connected to the second electrode of the previous sub-region and the first electrode of the subsequent sub-region, wherein the at least one intermediate electrode extends in the second direction intersecting the first direction along which the first electrode and the second electrode extend, wherein the second electrode in the subsequent sub-region and the first electrode in the previous sub-region are disposed at positions spaced apart from each other in a line with respect to the first direction, and the first electrode in the subsequent sub-region and the second electrode in the previous sub-region are disposed in a line with respect to the first direction, or the first electrode in the subsequent sub-region and the first electrode in the previous sub-region are disposed at positions spaced apart from each other in a line with respect to the first direction, and the second electrode in the subsequent sub-region and the second electrode in the previous sub-region are disposed in a line with respect to the first direction and are spaced apart from each other.

8. The display device according to claim 7, Among them, The first electrode line and the second electrode line are disposed to face each other, and the first sub-region to the K-th sub-region are disposed between the first electrode line and the second electrode line, and wherein each of the first electrode line and the second electrode line extends in the second direction intersecting the first direction along which the first electrode and the second electrode extend.

9. The display device according to claim 8, wherein, The first electrode line, the second electrode line, and the at least one intermediate electrode are disposed parallel to each other, and at least one sub-region is disposed between the first electrode line, the second electrode line, and the at least one intermediate electrode.

10. The display device according to claim 7, Among them, The first sub-region to the K-th sub-region are continuously disposed in the first direction, and wherein the at least one intermediate electrode extends between the two consecutive sub-regions in the second direction intersecting the first direction.

11. The display device according to claim 10, wherein, The first electrode and the second electrode extend in the first direction and are disposed parallel to each other in each of the first sub-region to the K-th sub-region.

12. The display device according to claim 11, wherein, The first electrode and the second electrode are disposed at regular intervals in each of the first sub-region to the K-th sub-region.

13. The display device according to claim 7, wherein, The at least one intermediate electrode is integrally connected to the second electrode of the previous sub-region and the first electrode of the subsequent sub-region.

14. The display device according to claim 7, wherein, The at least one intermediate electrode has a width smaller than the width of each of the first electrode line and the second electrode line.

15. The display device according to claim 7, Among them, wherein the first electrode line is supplied with a first power voltage or a first driving signal, and wherein the second electrode line is supplied with a second power voltage or a second driving signal.

16. The display device according to claim 15, wherein, The first pixel further includes a pixel circuit connected between the first electrode line and a first power supply that supplies the first power voltage.

17. The display device according to claim 7, wherein, The first electrode and the second electrode are arranged in the same repeating pattern in each of the first sub-region to the K-th sub-region.

18. The display device according to claim 7, wherein, In the two consecutive sub-regions, the first electrode and the second electrode are arranged in a symmetric shape based on the at least one intermediate electrode.

19. The display device according to claim 7, the display device further includes a second pixel having the same structure as that of the first pixel and arranged adjacent to the first pixel, Among them, wherein the first electrode line and the at least one intermediate electrode of the first pixel and the first electrode line and the at least one intermediate electrode of the second pixel are separated from each other between the first pixel and the second pixel.

20. The display device according to claim 19, wherein, The second electrode line of the first pixel and the second electrode line of the second pixel are integrally connected to each other.

21. The display device according to claim 7, Among them, the first pixel further includes at least one reverse light-emitting element, the at least one reverse light-emitting element is connected between the first electrode and the second electrode in a direction opposite to that of the light-emitting element in at least one of the plurality of series stages, and wherein the number of reverse light-emitting elements is less than the number of light-emitting elements.

22. The display device according to claim 7, wherein, The first pixel further includes at least one of the following elements: a first partition wall disposed under the corresponding first electrode; a second partition wall disposed under the corresponding second electrode; a first contact electrode disposed above the corresponding first electrode and all configured to electrically connect a corresponding one of the first electrodes to a first end of at least one light-emitting element; and a second contact electrode disposed above the corresponding second electrode and all configured to electrically connect a corresponding one of the second electrodes to a second end of at least one light-emitting element.

23. The display device according to claim 7, the display device further includes a bank configured to integrally surround an emission region of the first pixel including the first sub-region to the K-th sub-region.

Images