Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device, relates to the technical field of display, and aims to improve the display quality. The display panel comprises a substrate, a plurality of pixel driving circuits, a planarization layer and a plurality of sub-pixels. The planarization layer comprises a via hole located in the transparent area, and the via hole exposes a part of the pixel driving circuit. The plurality of sub-pixels includes anodes extending from the light emitting region to the transparent region and electrically connected to the pixel driving circuit through the hole. The display panel further comprises a plurality of film layers located between the substrate and the planarization layer, the multiple film layers are all located in the light emitting area, at least one film layer in the multiple film layers is further located in the climbing area and comprises a first part located in the climbing area, the anode comprises a second part located in the climbing area, and the second part is located in the climbing area. The orthographic projection of the second part on the substrate is not overlapped with the orthographic projection of the first part on the substrate. The display panel can be used for displaying pictures.

Description

Technical Field

[0001] This application relates to the field of display technologies, and in particular, to a display panel and a display device. Background Art

[0002] In a display panel of an Organic Light-Emitting Diode (OLED), there is a significant height difference between the transparent region and the light-emitting region. During the leveling process of the planarization material, the planarization layer climbs on the region (ramping region) between the transparent region and the light-emitting region, and the slope angle of the slope formed by the planarization layer in the ramping region is relatively large. As a result, the anode is prone to drilling fracture problems in the ramping region, forming a dark spot cluster, which reduces the display quality of the display panel. Summary of the Invention

[0003] This application provides a display panel and a display device, aiming to improve the display quality.

[0004] To achieve the above object, the embodiments of this application provide the following technical solutions:

[0005] On the one hand, a display panel is provided. The display panel includes a display area, the display area includes a plurality of light-emitting regions and a plurality of transparent regions, and a ramping region located between the light-emitting region and the transparent region. The display panel includes a substrate, a plurality of pixel driving circuits, a planarization layer, and a plurality of sub-pixels. The plurality of pixel driving circuits are disposed on the substrate. The planarization layer is disposed on a side of the pixel driving circuit away from the substrate and is located in the light-emitting region, the ramping region, and the transparent region. The planarization layer includes a slope surface in the ramping region, and the planarization layer further includes a via hole in the transparent region, and the via hole exposes a part of the pixel driving circuit. The plurality of sub-pixels are disposed on a side of the planarization layer away from the substrate. At least one sub-pixel is provided in one light-emitting region. One sub-pixel includes two secondary sub-pixels, and the secondary sub-pixel includes an anode. The anode extends from the light-emitting region through the ramping region to the transparent region and is electrically connected to the pixel driving circuit through the via hole. Wherein, the display panel further includes a plurality of film layers located between the substrate and the planarization layer. The plurality of film layers are all located in the light-emitting region, and at least one of the plurality of film layers is further located in the ramping region. At least one film layer includes a first portion in the ramping region. The anode includes a second portion in the ramping region, and the orthographic projection of the second portion on the substrate does not overlap with the orthographic projection of the first portion on the substrate.

[0006] The display area of the display panel provided by the present application includes a plurality of light-emitting areas, a plurality of transparent areas, and a ramp area located between the light-emitting area and the transparent area. The display panel further includes a substrate, and a plurality of pixel driving circuits, a planarization layer, and a plurality of sub-pixels sequentially disposed on the substrate. The plurality of sub-pixels are disposed in the light-emitting area, one sub-pixel includes two secondary sub-pixels, each secondary sub-pixel includes an anode, the planarization layer includes vias disposed in the transparent area, and the anode is electrically connected to the pixel driving circuit through the vias. The pixel driving circuit is configured to transmit an anode signal to the anode to drive the secondary sub-pixel to emit light.

[0007] Moreover, the display panel further includes a plurality of film layers located between the substrate and the planarization layer. The plurality of film layers are all located in the light-emitting area, and at least one of the plurality of film layers is further located in the ramp area. At least one film layer includes a first portion located in the ramp area, and the anode includes a second portion located in the ramp area. The orthographic projection of the second portion on the substrate does not overlap with the orthographic projection of the first portion on the substrate.

[0008] It can be understood that, along the direction perpendicular to the substrate, among the plurality of film layers located below the planarization layer in the light-emitting area, at least one film layer is in the ramp area, and in the ramp area, this film layer is not located below the anode, that is, by reducing the thickness of the foregoing film layer in the ramp area to reduce the slope gradient difference, thereby extending the ramp distance of the planarization layer in the ramp area to reduce the slope angle, making the slope of the planarization layer located below the anode smoother, improving the problem of drilling and cracking of the anode in the ramp area, avoiding the formation of dark spots on the display panel, and improving the display quality of the display panel.

[0009] In some embodiments, at least one of the plurality of film layers is a conductive layer. The conductive layer includes a first portion located in the ramp area, and the orthographic projection of the second portion on the substrate does not overlap with the orthographic projection of the first portion on the substrate.

[0010] In some embodiments, the conductive layer is a gate conductive layer, and the first portion is an auxiliary electrode. The plurality of film layers further include a source-drain conductive layer disposed between the gate conductive layer and the planarization layer. The source-drain conductive layer includes a data line passing through the ramp area, and the data line is electrically connected to the auxiliary electrode.

[0011] In some embodiments, the conductive layer is a source-drain conductive layer, and the first portion at least includes a first data segment and a second data segment. The orthographic projection of the second portion on the substrate is located between the orthographic projection of the first data segment on the substrate and the orthographic projection of the second data segment on the substrate. The plurality of film layers further include a gate conductive layer disposed between the substrate and the source-drain conductive layer. The gate conductive layer includes a data connection line located in the ramp area, and the data connection line connects the first data segment and the second data segment.

[0012] In some embodiments, at least one of the multiple film layers is a dielectric layer, and the dielectric layer includes a first part located in the ramp region. The orthographic projection of the second part on the substrate does not overlap with the orthographic projection of the first part on the substrate.

[0013] In some embodiments, the first part includes a through trench, and the orthographic projection of the second part on the substrate overlaps with the orthographic projection of the trench on the substrate.

[0014] In some embodiments, the multiple film layers include a buffer layer, a gate insulating layer, a gate conductive layer, an interlayer insulating layer, a source-drain conductive layer, and a passivation layer that are stacked in sequence. The dielectric layer is one of the buffer layer, the gate insulating layer, the interlayer insulating layer, or the passivation layer.

[0015] In some embodiments, the multiple film layers include a buffer layer, a gate insulating layer, a gate conductive layer, an interlayer insulating layer, a source-drain conductive layer, and a passivation layer that are stacked in sequence. The gate conductive layer includes a first part located in the ramp region. The first part is an auxiliary electrode. The orthographic projection of the second part on the substrate does not overlap with the orthographic projection of the first part on the substrate. The source-drain conductive layer includes a data line passing through the ramp region, and the data line is electrically connected to the auxiliary electrode. The interlayer insulating layer includes a trench located in the ramp region, and the orthographic projection of the second part on the substrate overlaps with the orthographic projection of the trench on the substrate.

[0016] In some embodiments, the multiple film layers include a buffer layer, a gate insulating layer, a gate conductive layer, an interlayer insulating layer, a source-drain conductive layer, and a passivation layer that are stacked in sequence. The source-drain conductive layer includes a first part located in the ramp region. The first part includes at least a first data segment and a second data segment. The orthographic projection of the second part on the substrate is located between the orthographic projection of the first data segment on the substrate and the orthographic projection of the second data segment on the substrate. The gate conductive layer includes a data connection line located in the ramp region, and the data connection line connects the first data segment and the second data segment. The passivation layer includes a trench located in the ramp region, and the orthographic projection of the second part on the substrate overlaps with the orthographic projection of the trench on the substrate.

[0017] On the other hand, a display device is provided, which includes the display panel in any of the above embodiments and a controller electrically connected to the display panel.

[0018] The above display device has the same structure and beneficial technical effects as the display panel provided in some of the above embodiments, and will not be elaborated here. Description of the Drawings

[0019] To more clearly illustrate the technical solutions in this application, the following will briefly introduce the accompanying drawings required for use in some embodiments of this application. Obviously, the accompanying drawings in the following description are only the accompanying drawings of some embodiments of this application. For those of ordinary skill in the art, other accompanying drawings can also be obtained based on these drawings. In addition, the accompanying drawings in the following description can be regarded as schematic diagrams and do not represent the actual sizes of the products or the actual processes of the methods involved in the embodiments of this application.

[0020] Figure 1 Structural diagram of the display device provided by the embodiment of this application;

[0021] Figures 2 to 4 For Figure 1 Partial enlarged view of multiple film layers of the display panel in at N;

[0022] Figure 5 For Figure 4 Partial cross-sectional view of the display panel along the section line A-A' in ;

[0023] Figures 6 to 8 Another partial enlarged view of multiple film layers of the display panel provided by the embodiment of this application at N;

[0024] Figure 9 For Figure 8 Partial cross-sectional view of the display panel along the section line A-A' in ;

[0025] Figure 10 Another partial enlarged view of multiple film layers of the display panel provided by the embodiment of this application at N. Detailed implementation manners

[0026] The following will clearly and completely describe the technical solutions in some embodiments of this application in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all of the embodiments. Based on the embodiments provided by this application, all other embodiments obtained by those of ordinary skill in the art fall within the scope of protection of this application.

[0027] Unless otherwise required by the context, in the entire specification and claims, the term "comprising" is interpreted as an open and inclusive meaning, that is, "including, but not limited to".

[0028] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of this application, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0029] In describing some embodiments, the expression "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral one; it can be directly connected or indirectly connected through an intermediate medium. For example, in describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical contact or electrical contact with each other.

[0030] In addition, the use of "based on" implies openness and inclusiveness, because a process, step, calculation, or other action "based on" one or more of the stated conditions or values may, in practice, be based on additional conditions or values beyond those stated.

[0031] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can be that the layer or element is directly on the other layer or substrate, or there can be an intermediate layer between the layer or element and the other layer or substrate.

[0032] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of regions are exaggerated for clarity. Thus, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include shape deviations caused, for example, by manufacturing. For example, an etched region shown as rectangular will typically have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0033] Embodiments of the present application provide a display device, which can be an Organic Light-Emitting Diode (OLED). Figure 1 This is a structural diagram of the display device provided by the embodiments of the present application.

[0034] See Figure 1 , the display device 100 includes a display panel 10 and a controller 20 electrically connected to the display panel 10. The controller 20 can be disposed on the non-display side of the display panel 10 and is used to control the display panel 10 to perform screen display.

[0035] The above display device 100 can be any device that displays images whether in motion (e.g., video) or stationary (e.g., still images), and whether text or otherwise. More specifically, it is contemplated that the embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photos, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0036] Figures 2 to 4 is Figure 1 a partial enlarged view of a plurality of film layers of the display panel in [N]; Figure 5 is Figure 4 a partial cross-sectional view of the display panel along the section line A-A'.

[0037] See Figure 2 , the display panel 10 includes a display area 11, the display area 11 includes a plurality of light-emitting areas 12 and a plurality of transparent areas 13, and a ramp area 14 located between the light-emitting area 12 and the transparent area 13. For example, along the direction X, the transparent areas 13 are located on opposite sides of the light-emitting area 12, and the ramp area 14 is located between the light-emitting area 12 and the transparent area 13.

[0038] See Figures 2 to 5 , the display panel 10 further includes a substrate 1, a plurality of pixel driving circuits 2, a planarization layer 3, and a plurality of sub-pixels 4.

[0039] Exemplarily, see Figure 5 , the thickness range of the substrate 1 is 50um to 1000um, and the substrate 1 can be Corning glass, or Asahi Glass, or can also be transparent materials such as quartz glass, etc.

[0040] Exemplarily, see Figure 5 , the display panel 10 further includes a light-shielding layer M1 and a buffer layer 20 disposed on the substrate 1. A metal can be deposited on the substrate 1 by a magnetron sputtering device, and through photolithography, wet etching patterning, and stripping the photoresist on the metal surface, the pattern of the light-shielding layer M1 can be obtained.

[0041] Then, a buffer layer 20 is deposited by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. The material of the buffer layer 20 includes SiN x , SiO x or SiO x N y or one or more of them. The thickness range of the buffer layer 20 is 150 nm to 500 nm.

[0042] Refer to Figure 4 and Figure 5 , a plurality of pixel driving circuits 2 are disposed on the substrate 1, and the pixel driving circuits 2 are located on the side of the light-shielding layer M1 away from the substrate 1. Refer to Figure 2 , the light-shielding layer M1 extends from the light-emitting region 12 through the ramp region 14 to the transparent region 13. The pixel driving circuit 2 includes a plurality of thin film transistors located in the light-emitting region 12. The plurality of thin film transistors include driving transistors. In the light-emitting region 12, the light-shielding layer M1 can block the light from the back of the display panel 10 to prevent the light from irradiating the driving transistors and causing the threshold voltage drift thereof. Moreover, the source or drain of the driving transistor is electrically connected to the light-shielding layer M1, and the anode signal output by the driving transistor can be transmitted to the transparent region 13 through the light-shielding layer M1.

[0043] Exemplarily, the process of forming the plurality of pixel driving circuits 2 includes the following steps S1 to S4:

[0044] Step S1: An oxide is deposited on the buffer layer 20 by using a magnetron sputtering device as the active layer of the thin film transistor. After photolithography and wet etching for patterning, the photoresist on the metal surface is stripped to obtain the active layer located in the light-emitting region 12. The above-mentioned oxide can be an amorphous oxide such as IGZO, ZnON, ITZO, etc.

[0045] Step S2: Refer to Figure 2 and Figure 5 , a gate insulating film is deposited by using a chemical vapor deposition method. The magnetron sputtering device is used again to deposit a gate conductive film on the gate insulating film. The metal thickness is 200 nm to 1000 nm. The composition of the gate conductive film can be Al, Mo, Cr, Cu, Ti, etc. After photolithography and wet etching processes, the gate pattern is defined to form the gate conductive layer M2. At the same time, the photoresist is not stripped, and the gate insulating film is etched by using the photoresist on the gate conductive layer M2 as a mask to form the gate insulating layer 21.

[0046] Step S3: Refer to Figure 5, any one of NH3, N2, and H2 gases is used to conductivize the exposed IGZO to reduce the ohmic contact resistance between the active layer and the source-drain conductive layer. The interlayer insulating layer 22 is deposited by plasma enhanced chemical vapor deposition process. The patterns of the deposited interlayer insulating holes and contact holes are defined by photolithography process. The contact holes between the source and drain electrodes of the driving transistor and the active layer, and the contact hole connecting one of the source or drain electrodes to the light-shielding layer M1 are obtained by dry etching process. The interlayer insulating layer 22 is SiN x or SiO x single-layer or multi-layer structure.

[0047] Step S4: Refer to Figure 3 and Figure 5 , the source-drain conductive film is deposited by magnetron sputtering process. The deposited metal can be Al, Mo, Cr, Cu, Ti, etc. The thickness of the source-drain conductive film is 200nm - 1000nm. The source-drain conductive layer M3 is obtained by photolithography and wet etching processes. The source-drain conductive layer M3 can be a two-layer or three-layer copper structure such as MoNb / Cu, MTD / Cu, MoNb / Cu / MTD, MoNb / Cu / ITO, or MoTD / Cu / ITO.

[0048] Exemplarily, continue to refer to Figure 3 , the pixel driving circuit 2 further includes a transfer electrode 25 disposed in the transparent region 13. For example, the transfer electrode 25 can be located in the source-drain conductive layer M3. In the transparent region 13, the transfer electrode 25 penetrates through the interlayer insulating layer 22 and is electrically connected to the light-shielding layer M1.

[0049] Exemplarily, refer to Figure 5 , the display panel 10 further includes a passivation layer 23 covering the pixel driving circuit 2. Exemplarily, the passivation layer 23 is deposited by chemical vapor deposition method. The material of the passivation layer 23 is silicon oxide, and the film thickness of the passivation layer 23 is 4000A - 5000A.

[0050] Continue to refer to Figure 5 , the planarization layer 3 is disposed on the side of the pixel driving circuit 2 away from the substrate 1, and the planarization layer 3 is located in the light-emitting region 12, the ramp region 14, and the transparent region 13.

[0051] Exemplarily, the planarization material is deposited by the slit method to form the planarization layer 3. The planarization material is pre-baked, exposed, developed and cured to form patterns in the light-emitting region 12, the ramp region 14, and the transparent region 13. After drying at 230°C to remove water and organic solvents, the planarization layer 3 is obtained. The film thickness of the planarization layer 3 is 2.0um - 3.5um.

[0052] Continue to refer to Figure 5, below the planarization layer 3, the thickness of the display panel 10 in the transparent area 13 is smaller than the thickness in the light-emitting area 12, and there is a height difference between the transparent area 13 and the light-emitting area 12. Since the planarization material has fluidity, during the process of forming the planarization layer 3, the planarization layer 3 will climb in the area between the transparent area 13 and the light-emitting area 12 (that is, the aforementioned climbing area 14). Therefore, the planarization layer 3 will form a slope 30 located in the climbing area 14.

[0053] Furthermore, the planarization layer 3 further includes a via hole 31 located in the transparent area 13 , and the via hole 31 exposes part of the pixel driving circuit 2 , for example, the via hole 31 exposes the switching electrode 25 , and the conductive film layer located above the via hole 31 can be electrically connected to the switching electrode 25 through the via hole 31 .

[0054] See also Figure 4 , multiple sub-pixels 4 are arranged on the side of the planarization layer 3 away from the substrate 1, and one light-emitting area 12 is provided with at least one sub-pixel 4. One sub-pixel 4 includes two secondary sub-pixels, and the two secondary sub-pixels are respectively a first secondary sub-pixel (A secondary sub-pixel) and a second secondary sub-pixel (B secondary sub-pixel).

[0055] Exemplarily, the number of sub-pixels 4 provided in a light-emitting area 12 may be one, two, three or four, and the present application does not impose any limitation thereto.

[0056] For example, a light-emitting area 12 is provided with four sub-pixels 4, and the four sub-pixels 4 are respectively a red sub-pixel, a white sub-pixel, a green sub-pixel, and a blue sub-pixel. It can be understood that the colors of the two secondary sub-pixels included in each sub-pixel are also the same. For example, the red sub-pixel and the white sub-pixel are located on one side of the transparent area 13, and the green sub-pixel and the blue sub-pixel are located on the other side of the transparent area 13.

[0057] Continue to see Figure 4 and Figure 5 Each secondary sub-pixel includes an anode M4, and the anode M4 extends from the light-emitting area 12 through the climbing area 14 to the transparent area 13. Exemplarily, the process of forming the anode M4 includes the following steps S5 to S7:

[0058] Step S5: depositing an anode layer of indium tin oxide (ITO) by a magnetron sputtering process, and obtaining an anode pattern by a patterning process. The anode layer of indium tin oxide is used for array testing (AT) and maintenance.

[0059] Step S6: depositing an auxiliary electrode layer by magnetron sputtering, the auxiliary electrode layer is a triple layer of ITO / Cu / MoNb, Cu can also be replaced by Al, Mo, etc., the thickness of the auxiliary electrode layer is 6000nm~8000nm, and the auxiliary electrode pattern is obtained by patterning and etching process.

[0060] Step S7: Deposit an anode layer by magnetron sputtering. The anode layer is a three-layer structure of Cu / MoNb / ITO. An anode pattern can be obtained using a patterning process.

[0061] See Figure 4 and Figure 5 , anode M4 extends from the light-emitting region 12 through the ramp region 14 to the transparent region 13. And in the transparent region 13, anode M4 is electrically connected to the pixel driving circuit 2 through the via hole 31. For example, anode M4 is electrically connected to the transfer electrode 25 of the pixel driving circuit 2 through the via hole 31. The anode signal from the driving transistor is transmitted to anode M4 through the light-shielding layer M1 and the transfer electrode 25 to drive each sub-pixel to emit light.

[0062] In the related art, below the planarization layer, the thickness of the display panel in the transparent region is smaller than that in the light-emitting region and the ramp region. There is a height difference between the transparent region and the light-emitting region and the ramp region. During the leveling process of the planarization material, the planarization layer will form a large slope angle in the ramp region, which may easily cause the anode above the planarization layer in the ramp region to be drilled and fractured, forming dark spots and affecting the display quality of the display panel.

[0063] Among them, see Figure 5 , the display panel 10 further includes a plurality of film layers 6 located between the substrate 1 and the planarization layer 3. Exemplarily, the plurality of film layers 6 include a buffer layer 20, a gate insulating layer 21, a gate conductive layer M2, an interlayer insulating layer 22, a source-drain conductive layer M3, and a passivation layer 23. These film layers 6 are all located in the light-emitting region 12, and at least one of the plurality of film layers 6 is also located in the ramp region 14.

[0064] See Figure 4 and Figure 5 , at least one of the plurality of film layers 6 includes a first portion 61 located in the ramp region 14. Exemplarily, the source-drain conductive layer M3 includes a first portion 61 located in the ramp region 14. For example, the first portion 61 is a data line for transmitting data signals.

[0065] The anode M4 includes a second portion 52 located in the ramp region 14. The orthographic projection of the second portion 52 on the substrate 1 does not overlap with the orthographic projection of the first portion 61 on the substrate 1. It can be understood that along the direction perpendicular to the substrate 1 (direction Z), among the plurality of film layers 6 below the planarization layer 3 in the light-emitting region 12, at least one film layer also extends into the ramp region 14, and the portion of this film layer located in the ramp region 14 is not located below the anode M4.

[0066] The display area 11 of the display panel 10 provided in this application includes a plurality of light-emitting areas 12, a plurality of transparent areas 13, and a ramp area 14 located between the light-emitting area 12 and the transparent area 13. The display panel 10 further includes a substrate 1, and a plurality of pixel driving circuits 2, a planarization layer 3, and a plurality of sub-pixels 4 sequentially disposed on the substrate 1. The plurality of sub-pixels 4 are disposed in the light-emitting area 12. One sub-pixel 4 includes two secondary sub-pixels, and each secondary sub-pixel includes an anode M4. The planarization layer 3 includes a via 31 disposed in the transparent area 13. The anode M4 is electrically connected to the pixel driving circuit 2 through the via 31. The pixel driving circuit 2 is configured to transmit an anode signal to the anode M4 to drive the secondary sub-pixel to emit light.

[0067] Moreover, the display panel 10 further includes a plurality of film layers 6 located between the substrate 1 and the planarization layer 3. The plurality of film layers 6 are all located in the light-emitting area 12, and at least one of the plurality of film layers 6 is further located in the ramp area 14. At least one film layer includes a first portion 61 located in the ramp area 14. The anode M4 includes a second portion 52 located in the ramp area 14. The orthographic projection of the second portion 52 on the substrate 1 does not overlap with the orthographic projection of the first portion 61 on the substrate 1.

[0068] It can be understood that along the direction perpendicular to the substrate 1 (direction Z), among the plurality of film layers 6 located below the planarization layer 3 in the light-emitting area 12, at least one film layer is in the ramp area 14, and in the ramp area 14, this film layer is not located below the anode M4. That is, by reducing the thickness of the aforementioned film layer in the ramp area 14 to reduce the slope gradient difference, thereby extending the ramp distance of the planarization layer 3 in the ramp area 14 to reduce the slope angle, making the slope surface 30 of the planarization layer 3 located below the anode M4 smoother, improving the problem of drilling and cracking of the anode M4 in the ramp area 14, avoiding the formation of dark spots on the display panel 10, and improving the display quality of the display panel 10.

[0069] In some embodiments, referring to Figures 2 to 5 ..., at least one of the plurality of film layers 6 is a conductive layer. The conductive layer includes a first portion 61 located in the ramp area 14. The orthographic projection of the second portion 52 on the substrate 1 does not overlap with the orthographic projection of the first portion 61 on the substrate 1. It can be understood that along the direction Z, the conductive layer located below the planarization layer 3 in the light-emitting area 12 is in the ramp area 14, and in the ramp area 14, the conductive layer is not located below the anode M4. That is, by reducing the thickness of the conductive layer in the ramp area 14 to reduce the slope gradient difference, thereby extending the ramp distance of the planarization layer 3 in the ramp area 14 to reduce the slope angle, making the slope surface 30 of the planarization layer 3 located below the anode M4 smoother, improving the problem of drilling and cracking of the anode M4 in the ramp area 14, avoiding the formation of dark spots on the display panel 10, and improving the display quality of the display panel 10.

[0070] In some embodiments, referring to Figures 3 to 5, the above-mentioned conductive layer is the source-drain conductive layer M3. The first part 61 at least includes a first data line segment 241 and a second data line segment 242, and the first data line segment 241 and the second data line segment 242 are discontinuous. The orthographic projection of the second part 52 on the substrate 1 is located between the orthographic projection of the first data line segment 241 on the substrate 1 and the orthographic projection of the second data line segment 242 on the substrate 1. That is, along the Z direction, the source-drain conductive layer M3 in the light-emitting region 12 below the planarization layer 3 is in the ramp region 14, and in the ramp region 14, the source-drain conductive layer M3 is not located below the anode M4. That is, by reducing the thickness of the source-drain conductive layer M3 in the ramp region 14, the slope gradient difference is reduced, thereby extending the ramp distance of the planarization layer 3 in the ramp region 14 to reduce the slope angle, so that the slope surface 30 of the planarization layer 3 is smoother, improving the problem of drilling fracture of the anode M4 in the ramp region 14, avoiding the formation of dark spots on the display panel 10, and improving the display quality of the display panel 10.

[0071] The multiple film layers 6 further include a gate conductive layer M2 disposed between the substrate 1 and the source-drain conductive layer M3. The gate conductive layer M2 includes a data connection line 220 located in the ramp region 14. The data connection line 220 connects the first data line segment 241 and the second data line segment 242 through a plurality of small holes 243, so that the source-drain conductive layer M3 located in the ramp region 14 can propagate data signals.

[0072] Figures 6 to 8 It is a partial enlarged view of the multiple film layers of another display panel provided by the embodiment of the present application at N; Figure 9 is Figure 8 a partial cross-sectional view of the display panel in along the section line A-A'.

[0073] In some embodiments, referring to Figures 6 to 9 , the conductive layer is the gate conductive layer M2, and the first part 61 is a part of the gate conductive layer M2 and is an auxiliary electrode.

[0074] Referring to Figure 6 and Figure 8 , in the ramp region 14, the gate conductive layer M2 below the second part 52 is removed to reduce the thickness of the film layer below the second part 52. Referring to Figure 7 , the source-drain conductive layer M3 is disposed through the ramp region 14. Referring to Figure 8 and Figure 9, the orthographic projection of the second part 52 on the substrate 1 does not overlap with the orthographic projection of the first part 61 on the substrate 1. That is, along the Z direction, the gate conductive layer M2 in the light-emitting region 12 below the planarization layer 3 is within the ramp region 14, and within the ramp region 14, the gate conductive layer M2 is not located below the anode M4. That is, by reducing the thickness of the gate conductive layer M2 in the ramp region 14, the slope gradient difference is reduced, thereby extending the ramp distance of the planarization layer 3 in the ramp region 14 to reduce the slope angle, making the slope surface 30 of the planarization layer 3 below the anode M4 smoother, improving the problem of drilling fracture generated by the anode M4 in the ramp region 14, avoiding the formation of dark spots on the display panel 10, and improving the display quality of the display panel 10.

[0075] See Figure 7 , the multiple film layers 6 further include a source-drain conductive layer M3 disposed between the gate conductive layer M2 and the planarization layer 3. The source-drain conductive layer M3 includes a data line 240 passing through the ramp region. The data line 240 is electrically connected to the auxiliary electrode (the first part 61) through a plurality of small holes 243. The auxiliary electrode is used to reduce the ohmic resistance of the data line 240, thereby reducing the voltage loss on the source-drain conductive layer M3.

[0076] In some embodiments, see Figure 5 and Figure 9 , at least one of the multiple film layers 6 is a dielectric layer. The dielectric layer includes a first part 61 in the ramp region 14. The orthographic projection of the second part 52 on the substrate 1 does not overlap with the orthographic projection of the first part 61 on the substrate 1. That is, along the Z direction, the dielectric layer in the light-emitting region 12 below the planarization layer 3 is within the ramp region 14, and within the ramp region 14, the dielectric layer is not located below the anode M4. That is, by reducing the thickness of the dielectric layer in the ramp region 14, the slope gradient difference is reduced, thereby extending the ramp distance of the planarization layer 3 in the ramp region 14 to reduce the slope angle, making the slope surface 30 of the planarization layer 3 below the anode M4 smoother, improving the problem of drilling fracture generated by the anode M4 in the ramp region 14, avoiding the formation of dark spots on the display panel 10, and improving the display quality of the display panel 10.

[0077] Exemplarily, the dielectric layer is one of the buffer layer 20, the gate insulating layer 21, the interlayer insulating layer 22, or the passivation layer 23.

[0078] In the embodiments of the present application, for example Figure 5 as shown, the above dielectric layer is the passivation layer 23. Along the Z direction, between the second part 52 and the data connection line 220, there is no passivation layer 23 provided, and this dielectric layer is located below the anode M4 in the light-emitting region 12. By reducing the thickness of this dielectric layer in the ramp region 14, the slope gradient difference is reduced, thereby extending the ramp distance of the planarization layer 3 in the ramp region 14 to reduce the slope angle of the slope surface 30.

[0079] For another example Figure 9 As shown, the dielectric layer is the gate insulating layer 21 and the interlayer insulating layer 22. Along the direction Z, the gate insulating layer 21 and the interlayer insulating layer 22 are not provided between the second part 52 and the data line 240, while the gate insulating layer 21 and the interlayer insulating layer 22 are located under the anode M4 of the light-emitting region 12. By reducing the thickness of the dielectric layer in the ramp region 14, the slope gradient difference is reduced, so as to extend the ramp distance of the planarization layer 3 in the ramp region 14 and reduce the slope angle of the slope surface 30.

[0080] In some embodiments, referring to Figure 10 , the first part 61 includes a through groove 610. The orthographic projection of the second part 52 on the substrate 1 overlaps with the orthographic projection of the groove 610 on the substrate 1, that is, along the direction Z, the groove 610 is provided under the second part 52 to reduce the thickness of the film layer located under the second part 52, make the slope surface 30 of the planarization layer 3 gentle, improve the problem of drilling fracture of the anode M4 in the ramp region 14, avoid the formation of dark spots on the display panel 10, and improve the display quality of the display panel 10.

[0081] In some embodiments, referring to Figures 2 to 5 , the multiple film layers 6 include a buffer layer 20, a gate insulating layer 21, a gate conductive layer M2, an interlayer insulating layer 22, a source-drain conductive layer M3, and a passivation layer 23 stacked in sequence. The source-drain conductive layer M3 includes a first part 61 located in the ramp region 14. The first part 61 at least includes a first data line segment 241 and a second data line segment 242, and the first data line segment 241 and the second data line segment 242 are not continuous. The orthographic projection of the second part 52 on the substrate 1 is located between the orthographic projection of the first data line segment 241 on the substrate 1 and the orthographic projection of the second data line segment 242 on the substrate 1. That is, along the direction Z, the source-drain conductive layer M3 is not provided under the second part 52, that is, the source-drain conductive layer M3 is not provided under the planarization layer 3 in the ramp region 14, while the source-drain conductive layer M3 is provided under the planarization layer 3 in the light-emitting region 12, so that the film layer thickness in the light-emitting region 12 is greater than the film layer thickness in the ramp region 14.

[0082] Moreover, the gate conductive layer M2 includes a data connection line 220 located in the ramp region 14. The data connection line 220 connects the first data segment 241 and the second data segment 242, enabling the source-drain conductive layer M3 (data line) located in the ramp region 14 to propagate data signals. Since no source-drain conductive layer M3 is provided below the second portion 52, there is no need to insulate and isolate the source-drain conductive layer M3. A trench 610 can be formed in the passivation layer 23 located in the ramp region 14. The orthographic projection of the second portion 52 on the substrate 1 overlaps with the orthographic projection of the trench 610 on the substrate 1, that is, the passivation layer 23 located in the trench 610 is removed, and a planarization layer 3 is directly provided above the interlayer insulating layer 22 located in the ramp region 14. By reducing the thickness of the passivation layer 23 in the ramp region 14, the slope gradient difference is reduced, thereby extending the ramp distance of the planarization layer 3 in the ramp region 14 to reduce the slope angle of the slope surface 30.

[0083] Since no source-drain conductive layer M3 and passivation layer 23 are provided between the second portion 52 and the data connection line 220, while a source-drain conductive layer M3 and a passivation layer 23 are provided below the planarization layer 3 located in the light-emitting region 12, the slope gradient difference between the light-emitting region 12 and the ramp region 14 is further reduced, thereby reducing the stepped film thickness step difference from the light-emitting region 12 to the ramp region 14, making the slope surface 30 of the planarization layer 3 smoother, improving the problem of drilling fracture of the anode M4 in the ramp region 14, avoiding the formation of dark spots on the display panel 10, and improving the display quality of the display panel 10.

[0084] In some embodiments, referring to Figures 6 to 9 , the multiple film layers 6 include a buffer layer 20, a gate insulating layer 21, a gate conductive layer M2, an interlayer insulating layer 22, a source-drain conductive layer M3, and a passivation layer 23 stacked in sequence. The gate conductive layer M2 includes a first portion 61 located in the ramp region 14. The gate conductive layer M2 is patterned to form the first portion 61, and the first portion 61 is an auxiliary electrode. The orthographic projection of the second portion 52 on the substrate 1 does not overlap with the orthographic projection of the first portion 61 on the substrate 1, that is, along the Z direction, no gate conductive layer M2 is provided below the second portion 52, and there is no need to provide a gate insulating layer 23 below the second portion either. That is, the gate conductive layer M2 and the gate insulating layer 23 located below the planarization layer 3 in the light-emitting region 12 are within the ramp region 14, and within the ramp region 14, the gate conductive layer M2 and the gate insulating layer 23 are not located below the anode M4. That is, by reducing the thickness of the gate conductive layer M2 and the gate insulating layer 23 in the ramp region 14, the slope gradient difference is reduced, making the slope surface 30 of the planarization layer 3 smoother, improving the problem of drilling fracture of the anode M4 in the ramp region 14, avoiding the formation of dark spots on the display panel 10, and improving the display quality of the display panel 10.

[0085] The source-drain conductive layer M3 includes a data line 240 passing through the ramp region 14. The data line 240 is electrically connected to an auxiliary electrode (the first part 61) through a plurality of small holes 243. The auxiliary electrode is used to reduce the ohmic resistance of the data line 240, thereby reducing voltage loss. The interlayer insulating layer 22 includes a trench 610 located in the ramp region 14. The orthographic projection of the second part 52 on the substrate 1 overlaps with the orthographic projection of the trench 610 on the substrate 1. That is, along the direction Z, the interlayer insulating layer 22 below the second part 52 is removed to reduce the film thickness below the second part 52, thereby reducing the slope gradient difference between the light-emitting region 12 and the ramp region 14, making the slope surface 30 of the planarization layer 3 gentle, improving the problem of drilling fracture of the anode M4 in the ramp region 14, avoiding the formation of dark spots on the display panel 10, and improving the display quality of the display panel 10.

[0086] As described above, the above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present application, thinking of changes or substitutions, should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A display panel, characterized in that, It includes a display area, the display area includes a plurality of light-emitting areas and a plurality of transparent areas, and a ramp area located between the light-emitting area and the transparent area; The display panel includes: A substrate; A plurality of pixel driving circuits disposed on the substrate; A planarization layer disposed on a side of the pixel driving circuit away from the substrate and located in the light-emitting area, the ramp area and the transparent area. The planarization layer includes a slope surface located in the ramp area; the planarization layer further includes a via hole located in the transparent area, and the via hole exposes a part of the pixel driving circuit; A plurality of sub-pixels disposed on a side of the planarization layer away from the substrate. At least one sub-pixel is provided in one light-emitting area; one sub-pixel includes two secondary sub-pixels, and the secondary sub-pixel includes an anode; the anode extends from the light-emitting area through the ramp area to the transparent area and is electrically connected to the pixel driving circuit through the via hole; Wherein, the display panel further includes a plurality of film layers located between the substrate and the planarization layer. The plurality of film layers are all located in the light-emitting area, and at least one of the plurality of film layers is further located in the ramp area. The at least one film layer includes a first part located in the ramp area; The anode includes a second part located in the ramp area, and a positive projection of the second part on the substrate does not overlap with a positive projection of the first part on the substrate.

2. The display panel according to claim 1, wherein At least one of the plurality of film layers is a conductive layer, and the conductive layer includes the first part located in the ramp area; A positive projection of the second part on the substrate does not overlap with a positive projection of the first part on the substrate.

3. The display panel according to claim 2, wherein The conductive layer is a gate conductive layer, and the first part is an auxiliary electrode; The plurality of film layers further includes a source-drain conductive layer disposed between the gate conductive layer and the planarization layer. The source-drain conductive layer includes a data line passing through the ramp area, and the data line is electrically connected to the auxiliary electrode.

4. The display panel according to claim 2, wherein, The conductive layer is a source-drain conductive layer, and the first part at least includes a first data segment and a second data segment; A positive projection of the second part on the substrate is located between a positive projection of the first data segment on the substrate and a positive projection of the second data segment on the substrate; The plurality of film layers further includes a gate conductive layer disposed between the substrate and the source-drain conductive layer. The gate conductive layer includes a data connection line located in the ramp area, and the data connection line connects the first data segment and the second data segment.

5. The display panel according to claim 1, wherein At least one of the plurality of film layers is a dielectric layer, and the dielectric layer includes the first part located in the ramp area; A positive projection of the second part on the substrate does not overlap with a positive projection of the first part on the substrate.

6. The display panel according to claim 5, wherein The first part includes a through groove; A positive projection of the second part on the substrate overlaps with a positive projection of the groove on the substrate.

7. The display panel according to claim 5 or 6, characterized in that, The plurality of film layers include a buffer layer, a gate insulating layer, a gate conductive layer, an interlayer insulating layer, a source-drain conductive layer and a passivation layer stacked in sequence. The dielectric layer is one of the buffer layer, the gate insulating layer, the interlayer insulating layer or the passivation layer.

8. The display panel according to claim 1, wherein The multiple film layers include a buffer layer, a gate insulating layer, a gate conductive layer, an interlayer insulating layer, a source / drain conductive layer, and a passivation layer that are stacked in sequence; The gate conductive layer includes the first part located in the ramp area, the first part being an auxiliary electrode, and the second part has a non-overlapping projection on the substrate with the projection of the first part on the substrate; the source / drain conductive layer includes a data line passing through the ramp area, and the data line is electrically connected to the auxiliary electrode; The interlayer insulating layer includes a trench located in the ramp area, and the projection of the second part on the substrate overlaps with the projection of the trench on the substrate.

9. The display panel according to claim 1, wherein The multiple film layers include a buffer layer, a gate insulating layer, a gate conductive layer, an interlayer insulating layer, a source / drain conductive layer, and a passivation layer that are stacked in sequence; The source / drain conductive layer includes the first part located in the ramp area, the first part at least including a first data segment and a second data segment; the projection of the second part on the substrate is located between the projection of the first data segment on the substrate and the projection of the second data segment on the substrate; the gate conductive layer includes a data connection line located in the ramp area, and the data connection line connects the first data segment and the second data segment; The passivation layer includes a trench located in the ramp area, and the projection of the second part on the substrate overlaps with the projection of the trench on the substrate.

10. A display device, characterized in that, Comprising: A display panel according to any one of claims 1 to 9; A controller electrically connected to the display panel.

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