Pixel circuit board, display device, and method for manufacturing pixel circuit board

Abstract

In a pixel circuit substrate (200), a first electrode (11) is formed below a first insulating film (21), a second electrode (12) is formed on the first insulating film (21), a second insulating film (22) is formed on the second electrode (12), the etching rate of the first insulating film (21) is lower than the etching rate of the second insulating film (22), and the etching rate of the first insulating film (21) is lower than the etching rate of the second insulating film (22). A first contact hole (31) that overlaps the second electrode (12) in plan view is formed in the second insulating film (22), and a second contact hole (32) that overlaps the first electrode (11) is formed in the second insulating film (22).

Description

Technical Field

[0001] The present invention relates to a pixel circuit substrate, a display device, and a method for manufacturing a pixel circuit substrate. Background Art

[0002] Patent Document 1 discloses a semiconductor device including: a capacitor element including a nitride film in a capacitor insulating film, a diffusion layer, and a silicide layer formed on the diffusion layer, the nitride film covering the silicide layer.

[0003] Prior Art Documents Patent Documents Patent Document 1: Japanese Patent Application Laid-Open No. 2003-282726 Summary of the Invention Technical Problem to be Solved by the Invention In the semiconductor device described in Patent Document 1, when designing the electrodes and contact holes of the capacitor element to meet the requirements of high resolution, the design of the contact holes exceeds the alignment accuracy limit, resulting in problems such as the contact holes extending beyond the electrodes. As a result, the two electrodes of the capacitor are short-circuited, and the function of the capacitor element is impaired.

[0004] The pixel circuit substrate according to one aspect of the present disclosure is completed in view of the above problems, and an object thereof is to provide a pixel circuit substrate and related technologies that can reduce the possibility of the contact holes extending beyond the electrodes of the capacitor element and can achieve high resolution.

[0005] Solution to the Problem The pixel circuit substrate according to one aspect of the present disclosure has a plurality of pixel circuits, the pixel circuit including a first electrode and a second electrode forming a capacitor, and including a first insulating film and a second insulating film, the first electrode being formed on a layer lower than the first insulating film, the second electrode being formed on the first insulating film, the second insulating film being formed on the second electrode, the etching rate of the first insulating film with respect to a prescribed etchant being less than the etching rate of the second insulating film with respect to the prescribed etchant, a first contact hole and a second contact hole being formed in the second insulating film, the first contact hole overlapping the second electrode in a plan view, and the second contact hole overlapping the first electrode in a plan view.

[0006] In addition, the display device according to one aspect of the present disclosure includes: the pixel circuit substrate according to one aspect of the present disclosure; and a light-emitting element layer located on the pixel circuit substrate.

[0007] In addition, in a method for manufacturing a pixel circuit substrate according to an aspect of the present disclosure, the pixel circuit substrate has a pixel circuit, and the pixel circuit includes a first electrode and a second electrode that form a capacitor. The method for manufacturing the pixel circuit substrate includes: a step of forming the first electrode; a step of forming a first insulating film on the first electrode; a step of forming a second electrode on the first insulating film; a step of forming a second insulating film on the second electrode; a step of etching the second insulating film using an etchant to form a first contact hole that overlaps the second electrode in a top view; and a step of etching the second insulating film using an etchant to form a second contact hole that overlaps the first electrode in a top view. The etching rate of the first insulating film with respect to the etchant is less than the etching rate of the second insulating film with respect to the etchant.

[0008] Advantages of the Invention According to an aspect of the present disclosure, it is possible to provide a pixel circuit substrate and related technologies that can reduce the possibility of a contact hole extending beyond an electrode of a capacitor element and can achieve high resolution. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 FIG. is a cross-sectional view for explaining an outline of a display device 500 including a pixel circuit substrate 200 according to an aspect of the present disclosure.

[0010] Figure 2 FIG. is a cross-sectional view for explaining an outline of a display device 501 including a pixel circuit substrate 201 according to an aspect of the present disclosure.

[0011] Figure 3 FIG. is a cross-sectional view for explaining an outline of a capacitor (capacitance element) 101 included in a pixel circuit substrate according to an aspect of the present disclosure.

[0012] Figure 4 FIG. is a top view for explaining an outline of a capacitor (capacitance element) 101 included in a pixel circuit substrate according to an aspect of the present disclosure.

[0013] Figure 5 FIG. is a cross-sectional view for explaining an outline of a capacitor (capacitance element) 102 included in a pixel circuit substrate according to an aspect of the present disclosure.

[0014] Figure 6 FIG. is a cross-sectional view for explaining an outline of a capacitor (capacitance element) 103 included in a pixel circuit substrate according to an aspect of the present disclosure.

[0015] Figure 7 FIG. is a cross-sectional view for explaining an outline of a capacitor (capacitance element) 104 included in a pixel circuit substrate according to an aspect of the present disclosure.

[0016] Figure 8 It is a cross-sectional view showing an overview of the second electrode 12a of a capacitor (capacitive element) included in a pixel circuit substrate related to one aspect of the present disclosure.

[0017] Figure 9 It is a diagram showing an overview of a process of forming a first electrode 11, a process of forming a first insulating film 21, and a process of forming a second electrode 12b included in a method of manufacturing a pixel circuit substrate related to one aspect of the present disclosure.

[0018] Figure 10 It is a diagram showing an overview of a process of etching in a state where a second electrode 12b is protected by a resist 700 included in a method of manufacturing a pixel circuit substrate related to one aspect of the present disclosure.

[0019] Figure 11 It is a diagram showing an overview of a process of forming a first contact hole 31 and a process of forming a second contact hole 32 included in a method of manufacturing a pixel circuit substrate related to one aspect of the present disclosure.

[0020] Figure 12 It is a diagram showing an overview of a capacitor 105 included in a pixel circuit substrate manufactured by a method of manufacturing a pixel circuit substrate related to one aspect of the present disclosure. Detailed Description

[0021] <Display device 500> Figure 1 It is a cross-sectional view for explaining an overview of a display device 500 related to one aspect of the present disclosure. The display device 500 related to one aspect of the present disclosure includes: a pixel circuit substrate 200 related to one aspect of the present disclosure; and a light-emitting element layer 300 located on the pixel circuit substrate.

[0022] As Figure 1 shown, the pixel circuit substrate 200 includes a capacitor (capacitive element) 100 in a first pixel circuit. A bottom coating 41, a semiconductor film SC, a gate insulating film GI, insulating films IL1, IL2, and IL3 are formed on a main substrate 40, and an organic insulating film (also referred to as a planarization film) 42 is formed on the insulating film IL3. Here, the capacitor 100 includes: a first electrode 11 provided between the gate insulating film GI and the insulating film IL1, a second electrode 12 provided between the insulating film IL2 and the insulating film IL3, and a third electrode 13 provided on a second insulating film 22. In addition, a first insulating film 21 of the capacitor 100 is formed on a part of the insulating film IL2, a third insulating film 23 is formed on a part of the insulating film (inorganic insulating film) IL1, and the second insulating film 22 is formed to have the same film as the insulating film TGI of a top-gate type oxide semiconductor transistor.

[0023] The capacitor 100 is a capacitor having a multilayer structure, and the multilayer structure includes a first electrode 11 as a gate electrode, a second electrode 12, and a third electrode 13 as a top gate electrode.

[0024] Since the etching rate of the first insulating film 21 with respect to a specified etchant in the capacitor 100 of the pixel circuit substrate 200 is smaller than that of the second insulating film 22, a short circuit between the first electrode 11 and the second electrode 12 is avoided as described later.

[0025] The pixel circuit substrate 200 includes, for example, a top gate transistor including a semiconductor film SC. The semiconductor film SC may be, for example, a polysilicon semiconductor film. The top gate transistor may use the first electrode 11 of the capacitor 100 as the gate electrode of the top gate transistor and may be electrically connected to a high potential side power supply line (not shown) via the third electrode 13. The top gate transistor is electrically connected to an anode E1 included in the light emitting element layer 300 via a metal film MS. In the pixel circuit substrate 200, the top gate transistor including the semiconductor film SC can function as a light emission control transistor. Figure 1 A part of the shown metal film MS may also be dummy.

[0026] In addition, the pixel circuit substrate 200 includes a top gate oxide semiconductor transistor. The top gate oxide semiconductor transistor includes an oxide semiconductor film SZ and a top gate electrode TGE, and a top gate insulating film TGI in the oxide semiconductor transistor is formed as the same layer as the second insulating film 22. The oxide semiconductor transistor may be electrically connected to a control terminal (gate terminal) of the transistor including the semiconductor film SC and an initialization signal line (not shown) via a metal film MT, for example. In the pixel circuit substrate 200, the top gate transistor including the oxide semiconductor film SZ can function as an initialization transistor.

[0027] The oxide semiconductor film SZ may include, for example, an oxide containing at least one of indium (In), gallium (Ga), and zinc (Zn), and the oxide semiconductor film SZ may also include indium gallium zinc oxide (InGaZnO). It may include at least one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiNx). Silicon dioxide (SiO2) is formed by a vapor phase growth method using a mixed gas including silane (SiH4) and oxygen (O2). Silicon nitride (SiN) is formed by a mixed gas including silane (SiH4), ammonia (NH3), and nitrogen (N2). Silicon oxynitride is formed by a mixed gas including silane (SiH4), ammonia (NH3), oxygen (O2), and nitrogen (N2).

[0028] The light-emitting element layer 300 includes a light-emitting element EL including an anode E1, a cathode E2, and an EL layer, and may also include a sealing layer (not shown). The anode E1 may be a pixel electrode divided by an insulating bank BK, and the cathode E2 may be a common electrode shared by a plurality of light-emitting elements EL.

[0029] The light-emitting element EL may include a plurality of light-emitting elements having an OLED (light-emitting diode including an organic light-emitting layer) layer or a QLED (light-emitting diode including a light-emitting quantum dot) layer.

[0030] <Display device 501> Figure 2 It is a cross-sectional view for explaining the outline of the display device 501 according to one aspect of the present disclosure. The display device 501 according to one aspect of the present disclosure includes: a pixel circuit substrate 201 according to one aspect of the present disclosure; and a light-emitting element layer 300 located on the pixel circuit substrate.

[0031] As Figure 2 shown, the pixel circuit substrate 201 includes a capacitor 100' in the first pixel circuit, and a bottom coating 41, a semiconductor film SC, a gate insulating film GI, insulating films IL1, IL2, and IL3 are formed on the main substrate 40, and an organic insulating film (also referred to as a planarization film) 42 is formed on the insulating film IL3. Here, the capacitor 100' includes a first electrode 11' provided on the insulating film IL1 and a second electrode 12' provided on the insulating film IL3. In addition, in the capacitor 100', a first insulating film 21 is formed on a part of the insulating film IL2, a third insulating film 23 is formed on a part of the insulating film IL1, a second insulating film 22 is formed on a part of the insulating film IL3, and the third insulating film 23 is formed to have the same film as the insulating film TGI of the top-gate type oxide semiconductor transistor. In addition, components having the same function are denoted by the same reference numerals, and their descriptions are omitted.

[0032] The capacitor 101 has a multilayer structure including a first electrode 11', a second electrode 12' as a top gate electrode, and a gate electrode GE.

[0033] Since the etching rate of the first insulating film 21 with respect to a specified etchant in the capacitor 100' of the pixel circuit substrate 201 is smaller than that of the second insulating film 22', a short circuit between the first electrode 11' and the second electrode 12' is avoided as described later.

[0034] In the pixel circuit substrate 201, the capacitor 100' may be configured to include the gate electrode GE of a transistor having a semiconductor film SC as an electrode, and the capacitor 100' is electrically connected to a high-potential side power supply line (not shown).

[0035] In addition, the pixel circuit substrate 201 includes a top-gate oxide semiconductor transistor having an oxide semiconductor film SZ and a top-gate electrode TGE, and a top-gate insulating film TGI in the oxide semiconductor transistor is formed as the same layer as the second insulating film 22'. Between the top-gate electrode TGE and the top-gate insulating film TGI, a part of an insulating film IL2 is formed as the same layer as the first insulating film 21'. A part of this insulating film IL2 may constitute a part of the gate insulating film in the oxide semiconductor transistor, but is not limited thereto. It is also possible that there is no insulating film IL2 between the top-gate electrode TGE and the top-gate insulating film TGI.

[0036] Hereinafter, a more specific embodiment of the capacitor included in the pixel circuit substrate according to one embodiment of the present invention will be described.

[0037] 〔Capacitor (capacitance element) 101〕As Figure 3 shown, the capacitor (capacitance element) 101 includes a first electrode 11, a second electrode 12, a third electrode 13, and a fourth electrode 14 as electrodes, and includes a first insulating film 21, a second insulating film 22, and a third insulating film 23.

[0038] In the capacitor 100, the first electrode 11 is formed on a layer lower than the first insulating film 21, and the second electrode 12 is formed on the first insulating film 21. In addition, the third electrode 13 and the fourth electrode 14 are formed on a layer higher than the second insulating film 22. The second electrode 12 and the third electrode 13 are connected via a first contact hole 31 penetrating the second insulating film 22, and the first electrode 11 and the fourth electrode 14 are connected via a second contact hole 32 penetrating the first insulating film 21, the second insulating film 22, and the third insulating film 23. Thus, a capacitance (electrostatic capacitance) is formed between the first electrode 11 and the second electrode 12 in the capacitor 100.

[0039] In the capacitor 100, the etching rate of the first insulating film 21 with respect to a predetermined etchant is less than the etching rate of the second insulating film 22 located above the first insulating film 21 with respect to the same etchant. Thus, even if the etchant is supplied to a position deviated from the second electrode 12 at a part of the end of the first contact hole 31, the time required to penetrate the insulating films 21, 22, and 23 through the first contact hole 31 can be extended by the first insulating film 21. Therefore, the design alignment accuracy of the contact hole can be increased when designing the capacitor, and further, the design of a high-resolution pixel circuit substrate can be achieved.

[0040] Each of the first electrode 11, the second electrode 12, the third electrode 13, and the fourth electrode 14 only needs to contain a conductive material such as titanium (Ti) or aluminum (Al), and these electrodes can be formed by a known method such as sputtering.

[0041] The etching rate of the insulating material included in the first insulating film 21 is not limited as long as it is smaller than the etching rate of the insulating material included in the second insulating film 22. However, as a specified etching rate, when dry etching is performed using a fluorine-based gas (e.g., PFC), it is preferably in the range of greater than 0 nm / minute and 120 nm / minute or less, and more preferably in the range of greater than 0 nm / minute and 60 nm / minute or less. Since the etching rate of the insulating material included in the first insulating film 21 is selected to be a smaller value in the range of greater than 0 nm / minute and 120 nm / minute or less, the time difference between (i) the time required to form the first contact hole 31 that penetrates the second insulating film 22 with a thickness t2 and (ii) the time required to form the second contact hole 32 that penetrates the first, second, and third insulating films 21, 22, and 23 with a total thickness ta, as shown in Figure 1 can be increased. Here, the first contact hole 31 and the second contact hole 32 are provided between the first electrode 11 and the third electrode 13 (and the fourth electrode 14). Thus, when forming the first contact hole 31 and the second contact hole 32 by, for example, a known etching method, as shown in Figure 3 , even if a part of the end portion of the first contact hole 31 extends beyond the second electrode 12, the time margin required for the etchant for forming the first contact hole 31 to reach the first electrode 11 can be increased. Therefore, the risk of short circuit of the capacitor 101 in which the first contact hole 31 contacts the first electrode 11 can be reduced. Therefore, the design alignment accuracy of the first contact hole 31 and the second contact hole 32 can be increased. As a result, as shown in Figure 4 , the area 11A of the first electrode 11 in a plan view of the capacitor 101 and the area 12A of the second electrode 12 in a plan view can be reduced. Therefore, high resolution of the capacitor 101 can be achieved.

[0042] In addition, for example, in the plan view shown in Figure 3 , the width w1 of the first electrode 11 and the width w2 of the second electrode 12 can be reduced. For example, it is sufficient that the width w1 of the first electrode 11 is larger than the width w2 of the second electrode 12, but it is not limited thereto. The width w1 is, for example, in the range of 0.01 µm to 20 µm, and more preferably in the range of 0.1 µm to 10 µm. In addition, for example, it is sufficient that the width w2 of the second electrode 12 is smaller than the width w1 of the first electrode 11, and there is no limitation. For example, as long as it is in the range of 0.01 µm to 20 µm, and more preferably in the range of 0.1 µm to 10 µm. The capacitor 101 can design the width w1 of the first electrode 11 in the range of 0.01 µm to 20 µm and the width w2 of the second electrode 12 in the range of 0.01 µm to 20 µm.

[0043] The etching rate of the insulating material contained in the second insulating film 22 is preferably in the range of 120 nm / min to 600 nm / min, more preferably in the range of 180 nm / min to 600 nm / min.

[0044] The third insulating film 23 can select the same insulating material as the second insulating film 22 as described later. The etching rate of the insulating material contained in the third insulating film 23 is the same as that of the insulating material contained in the second insulating film 22, so its description is omitted.

[0045] The capacitance of the capacitor 101 is designed according to the following items: (1) the area 11A of the first electrode 11 when viewed from above and the area 12A of the second electrode 12 when viewed from above, (2) the thickness t1 of the first insulating film 21 provided between the first electrode 11 and the second electrode 12 and the thickness t3 of the third insulating film 23 provided between the first electrode 11 and the second electrode 12, (3) the type of insulating material contained in the first insulating film 21 and the type of insulating material contained in the third insulating film.

[0046] For the capacitor 101, by adjusting the etching rate of the first insulating film 21 with respect to a specified etchant and the thickness t1 of the first insulating film 21, it is only necessary to design the time difference between the etching time required to form the first contact hole 31 and the etching time required to form the second contact hole 32. In addition, the capacitance of the capacitor 101 can be designed according to the thickness t1 and type of the insulating material contained in the first insulating film 21, and the thickness t3 and type of the insulating material contained in the third insulating film 23. When the total thickness tc of the thickness t1 of the insulating material and the thickness t3 of the insulating material occupies the space between the first electrode 11 and the second electrode 12, the capacitance of the capacitor can be designed accordingly.

[0047] In addition, in the case of Figure 1 the pixel circuit substrate 200 shown, where the first electrode 11 is used as the gate electrode and the third electrode 13 is used as the top gate electrode, the area of the third electrode 13 when viewed from above, the thickness t2 of the second insulating film 22, and the type of insulating material contained in the second insulating film 22 should also be designed.

[0048] Although not limited, the capacitor included in the pixel circuit substrate according to one embodiment of the present disclosure may have an electrostatic capacitance of, for example, 0.1 to 1000 fF (femtofarad), preferably about 1 to 100 fF (femtofarad).

[0049] The thickness t1 of the first insulating film 21 is preferably in the range of 1 nm to 200 nm, more preferably in the range of 10 nm to 100 nm. The thicker the thickness t1 of the first insulating film 21 within the range of 1 nm to 200 nm, the longer the etching time of the first insulating film 21 can be extended, and the design alignment accuracy of the contact holes 31 and 32 can be increased.

[0050] The thickness t2 of the second insulating film 22 is preferably in the range of 10 nm to 1000 nm, more preferably in the range of 10 nm to 800 nm. The thinner the thickness t2 of the second insulating film 22 within the range of 10 nm to 1000 nm, the shorter the etching time of the second insulating film 22 can be shortened, and the design alignment accuracy of the contact holes 31 and 32 can be increased.

[0051] The thickness t3 of the third insulating film 23 is preferably in the range of 1 nm to 1000 nm, more preferably in the range of 10 nm to 500 nm. Since the thickness t3 of the third insulating film 23 is within the range of 1 nm to 1000 nm, the capacitance in the capacitor 101 can be designed between the first electrode 11 and the second electrode 12 together with the first insulating film 21.

[0052] As described above, in order to increase the design alignment accuracy of the contact holes 31 and 32, for example, the combination of the first insulating film 21 and the second insulating film 22 is preferably: the first insulating film 21 is selected from at least one of a silicon nitride film, an aluminum oxide film, a lanthanum oxide film, a hafnium oxide film, and a gadolinium oxide film, and the second insulating film 22 includes, for example, a silicon oxide film.

[0053] As described above, in order to increase the design alignment accuracy of the contact holes, for example, the combination of the first insulating film 21 and the second insulating film 22 is preferably: the first insulating film 21 is selected from at least one of a silicon nitride film, an aluminum oxide film, a lanthanum oxide film, a hafnium oxide film, and a gadolinium oxide film, and the second insulating film 22 includes a silicon oxide film.

[0054] The silicon nitride film, the aluminum oxide film, the lanthanum oxide film, the hafnium oxide film, the gadolinium oxide film, and the silicon oxide film can be formed by a known method such as plasma chemical vapor deposition (CVD method), for example. The etching rate can be adjusted to the above range according to the manufacturing conditions of these insulating material films. In addition, the relative dielectric constant of these insulating material films can be adjusted according to the manufacturing conditions to adjust the insulation.

[0055] In addition, examples of the conductive material filled in the contact holes 31 and 32 can include molybdenum (Mo), copper (Cu), aluminum (Al), tungsten (W), etc.

[0056] It is preferable that either one of the third electrode 13 and the fourth electrode 14 is electrically connected to, for example, a high-potential side power supply line (not shown) or a gate electrode of a driving transistor (not shown).

[0057] 〔Capacitor 102〕The capacitor included in the pixel circuit substrate according to one embodiment of the present disclosure is not limited to the above embodiment. For example, as Figure 5 shown, the capacitor (capacitance element) 102 includes a first electrode 11, a second electrode 12, a third electrode 13, and a fourth electrode 14 as electrodes, and includes a first insulating film 21a, a second insulating film 22, and a third insulating film 23 as insulating films.

[0058] In the capacitor 102, the first electrode 11 is formed on a layer lower than the first insulating film 21a, and the second electrode 12 is formed on the first insulating film 21a. In addition, in the capacitor 102, a third electrode 13 and a fourth electrode 14 are formed on a layer higher than the second insulating film 22, and the second electrode 12 and the third electrode 13 are connected via a first contact hole 31 penetrating the second insulating film 22, and the first electrode 11 and the fourth electrode 14 are connected via a second contact hole 32 penetrating the second insulating film 22 and the third insulating film 23. Here, the second contact hole 32 is not formed so as to penetrate the first insulating film 21a formed in an island shape on the third insulating film 23.

[0059] In the capacitor 102, the etching rate of the first insulating film 21a is lower than the etching rate of the second insulating film 22 located above the first insulating film 21a with respect to the same etchant. Thus, even if the etchant is supplied to a position deviated from the second electrode 12 at a part of the end of the first contact hole 31, the time required for the first contact hole 31 to penetrate the insulating films 21a, 22, and 23 can be extended through the first insulating film 21a.

[0060] The etching rate of the first insulating film 21a, its thickness t1, and the type of the insulating material are the same as those of the capacitor 101, and thus the description thereof is omitted.

[0061] There is no limitation as long as the width w3 of the first insulating film 21a is smaller than the width w1 of the first electrode 11 and larger than the width w2 of the second electrode 12. For example, it may be within the range of 0.01 μm to 20 μm, and more preferably within the range of 0.1 μm to 10 μm. In this way, the time required for the etchant of the contact hole 31 formed so as to extend beyond the second electrode 12 to reach the first electrode 11 can be extended. Therefore, when designing the contact hole 31 and the contact hole 32, the alignment accuracy can be increased, thereby achieving a high resolution of the pixel circuit substrate including the capacitor 102.

[0062] As long as the area of the first insulating film 21a in plan view is smaller than the area 11A of the first electrode 11 in plan view shown in Figure 4 and larger than the area 12A of the second electrode 12 in plan view based on the width w3 of the first insulating film 21a.

[0063] In addition, when the first electrode 11 is used as the gate electrode and the third electrode 13 is used as the top gate electrode, the capacitance of the capacitor should also be designed in terms of the area of the third electrode 13 when viewed from above, the thickness t2 of the second insulating film 22, and the type of insulating material included in the second insulating film 22. This is also common to the capacitor of the pixel circuit substrate according to one embodiment of the present disclosure.

[0064] There is no limitation on the capacitor 102 as long as the width w3 of the first insulating film 21a is smaller than the width w1 of the first electrode 11 and larger than the width w2 of the second electrode 12. For example, it may be within the range of 0.01 μm to 20 μm, and more preferably within the range of 0.1 μm to 10 μm. Here, by selecting a larger value within the range of 0.01 μm to 20 μm for the width w3 of the first insulating film 21a, it is possible to effectively prevent the contact hole 31 from extending beyond the second electrode 12 and reaching the first electrode 11 due to the first insulating film 21a. Thus, it is possible to extend the time required for the etchant of the contact hole 31 formed to extend beyond the second electrode 12 to reach the first electrode 11. In addition, in the capacitor 102, when the width w3 of the first insulating film 21a is within the range of 0.01 μm to 20 μm, the smaller the width, the more easily the contact hole 32 can be formed without contacting the first insulating film 21a. Therefore, when designing the contact hole 31 and the contact hole 32, the alignment accuracy can be increased, thereby achieving a high resolution of the pixel circuit substrate including the capacitor 102.

[0065] 〔Capacitor 103〕The capacitor included in the pixel circuit substrate according to one embodiment of the present disclosure is not limited to the above embodiment. For example, as Figure 6 shown, the capacitor 103 includes a first electrode 11, a second electrode 12, a third electrode 13, and a fourth electrode 14 as electrodes, and includes a first insulating film 21b and a second insulating film 22 as insulating films.

[0066] In the capacitor 103, the first electrode 11 is formed on a layer lower than the first insulating film 21b, and the second electrode 12 is formed on the first insulating film 21b. In addition, the third electrode 13 and the fourth electrode 14 are formed on a layer higher than the second insulating film 22 in the capacitor 103. The second electrode 12 and the third electrode 13 are connected via a first contact hole 31 penetrating the second insulating film 22, and the first electrode 11 and the fourth electrode 14 are connected via a second contact hole 32 penetrating the second insulating film 22. Here, the second contact hole 32 is not formed so as to penetrate the first insulating film 21b formed in an island shape on the first electrode 11.

[0067] In the capacitor 103, the etching rate of the first insulating film 21b is lower than the etching rate of the second insulating film 22 located above the first insulating film 21b with respect to the same etchant. Thus, even if the etchant is supplied to a position offset from the second electrode 12 at a part of the end of the first contact hole 31, the first insulating film 21b can be used to extend the time required until the first contact hole 31 penetrates the insulating films 21b and 22, and the second contact hole 32 can be rapidly formed in the second insulating film 22.

[0068] In the capacitor 103, the etching rate of the first insulating film 21b, its thickness t1 and width w3, and the type of insulating material are the same as those of the capacitor 102, and thus their description is omitted.

[0069] The width of the capacitor 103 is not limited as long as the width w3 of the first insulating film 21b is smaller than the width w1 of the first electrode 11 and larger than the width w2 of the second electrode 12. For example, it suffices to be in the range of 0.01 μm to 20 μm, and more preferably in the range of 0.1 μm to 10 μm. In this way, the time required for the etchant of the contact hole 31 formed so as to extend beyond the second electrode 12 to reach the first electrode 11 can be extended. Therefore, when designing the contact hole 31 and the contact hole 32, the alignment accuracy can be increased, thereby achieving high resolution of the pixel circuit substrate including the capacitor 103.

[0070] In addition, for the capacitor 103, as long as the area ratio of the first insulating film 21b when viewed from above is Figure 4 smaller than the area 11A of the first electrode 11 when viewed from above and larger than the area 12A of the second electrode 12 when viewed from above as shown.

[0071] The capacitor 103 does not include the third insulating film 23. In the capacitor 103, the thickness t1 of the first insulating film 21b corresponds to the film thickness tc of the insulating material between the first electrode 11 and the second electrode 12. By adjusting the thickness tc, the etching time required to form the contact holes 31 and 32 and the capacitance between the first electrode 11 and the second electrode 12 can be adjusted.

[0072] In addition, by designing the type and thickness t1 of the insulating material included in the first insulating film 21b and the type and thickness ta of the insulating material included in the second insulating film 22 in the capacitor 103, the first contact hole 31 and the second contact hole 32 can also be formed simultaneously, for example.

[0073] 〔Capacitor 104〕The capacitor included in the pixel circuit substrate according to one aspect of the present disclosure is not limited to the above aspect. For example, as Figure 7As shown, the capacitor 104 includes a first electrode 11, a second electrode 12, a third electrode 13, and a fourth electrode 14 as electrodes, and includes a first insulating film 21 and a second insulating film 22 as insulating films.

[0074] In addition, in the capacitor 104, the first electrode 11 is formed on a layer lower than the first insulating film 21, and the second electrode 12 is formed on the first insulating film 21. Further, in the capacitor 104, the third electrode 13 and the fourth electrode 14 are formed on a layer higher than the second insulating film 22, and the second electrode 12 and the third electrode 13 are connected via a first contact hole 31 penetrating the second insulating film 22, and the first electrode 11 and the fourth electrode 14 are connected via a second contact hole 32 penetrating the second insulating film 22c.

[0075] In the capacitor 104, the etching rate of the first insulating film 21 is lower than the etching rate of the second insulating film 22 located on the upper layer of the first insulating film 21 with respect to the same etchant. Thus, even if the etchant is supplied to a position deviated from the second electrode 12 at a part of the end of the first contact hole 31, the first insulating film 21 can be passed through, and the time required for the first contact hole 31 to penetrate the insulating film 21 can be extended.

[0076] In the capacitor 104, the etching rate of the first insulating film 21, its thickness t1 and width w3, and the type of insulating material are the same as those of the capacitor 103, and thus the description thereof is omitted.

[0077] Similar to the capacitor 103, in the capacitor 104, the thickness t1 of the first insulating film 21 corresponds to the thickness tc of the insulating material film between the first electrode 11 and the second electrode 12. By adjusting the thickness tc, the etching time required to form the contact holes 31 and 32 and the capacitance between the first electrode 11 and the second electrode 12 can be adjusted.

[0078] 〔Modification Example〕The capacitor included in the pixel circuit board according to one embodiment of the present disclosure is not limited to the above embodiment. The capacitor included in the pixel circuit board according to one modification example may also include the second electrode 12a shown in place of the second electrode included in any one of the above capacitors 101, 102, 103, and 104. Figure 8 The second electrode 12a includes a stacked film having a multilayer structure in which metal films 121, 122, and 123 are stacked.

[0079] When the second electrode 12a is formed on the first insulating film 21 through patterning using photolithography and etching, the etchant sometimes etches its end portion. Due to this etching, a sharp conical shape can be formed on the end faces of the metal films 121, 122, and 123 from the upper surface side of the outer peripheral end portion of the second electrode 12a.

[0080] In the second electrode 12a, the metal films 121 and 123 can each be formed of a metal such as titanium (Ti) or molybdenum (Mo), and the metal film 122 can be formed of aluminum (Al). The second electrode 12a improves the poor contact with the conductive material filled in the contact hole by having the metal film 121 on its upper surface, and improves the conductivity between the second electrode 12a and the conductive material filled in the contact hole by having the metal film 122.

[0081] 〔Other method〕In addition, the capacitor included in the pixel circuit substrate according to one embodiment of the present disclosure is not limited to the above method. For example, the pixel circuit substrate according to one embodiment of the present disclosure has a plurality of first pixel circuits and a plurality of second pixel circuits. It is also possible that in at least one pixel circuit (first pixel circuit), the first contact hole is provided at the end face of the first electrode, and in other pixel circuits (second pixel circuits), the first contact hole is provided on the upper surface of the first electrode.

[0082] <Manufacturing method of pixel circuit substrate> As Figures 9 to 12 shown, the manufacturing method of the pixel circuit substrate according to one embodiment of the present disclosure includes: a step of forming the first electrode 11; a step of forming the first insulating film 21 on the first electrode 11; a step of forming the second electrode 12b on the first insulating film 21; a step of forming the second insulating film 22 on the second electrode 12b; a step of etching the second insulating film 22 using an etchant to form a first contact hole 31 that overlaps the second electrode 12b in a top view; and a step of etching the second insulating film 22 using an etchant to form a second contact hole 32 that overlaps the first electrode 11 in a top view. The etching rate of the first insulating film with respect to the etchant is smaller than that of the second insulating film.

[0083] Figure 9 An intermediate of the pixel circuit substrate formed by the step of forming the first electrode 11, the step of forming the first insulating film 21 on the first electrode 11, and the step of forming the second electrode 12b on the first insulating film 21 is illustrated. A third insulating film 23 is formed between the first electrode 11 and the first insulating film 21 (step of forming the third insulating film) between the step of forming the first electrode 11 and the step of forming the first insulating film 21 on the first electrode 11. The first electrode 11 can also be formed, for example, on the gate insulating film of a substrate having a gate insulating film (not shown).

[0084] In the process of forming the first electrode 11 and the process of forming the second electrode 12b on the first insulating film 21, the first electrode 11 and the second electrode 12b can be formed by known physical deposition methods such as sputtering, vacuum evaporation, and ion plating, respectively. In addition, the first electrode 11 and the second electrode 12b can be formed into a multilayer structure having, for example, a titanium layer, an aluminum layer, etc., respectively.

[0085] In addition, in the process of forming the first insulating film 21 on the first electrode 11, the first insulating film 21 can be formed into a silicon nitride film, an aluminum oxide film, a lanthanum oxide film, a hafnium oxide film, and a gadolinium oxide film by film formation methods such as plasma chemical vapor deposition (CVD method) and sintering method. For example, silicon oxide (SiO2) is formed by a vapor growth method using a mixed gas containing silane (SiH4) and oxygen (O2). The silicon nitride film (SiN) is formed from a mixed gas containing silane (SiH4), ammonia (NH3), and nitrogen (N2). The silicon oxynitride film can be formed from a mixed gas containing silane (SiH4), ammonia (NH3), oxygen (O2), and nitrogen (N2). In addition, the aluminum oxide film can be formed from a mixed gas containing a metal alkoxide of aluminum (A1), oxygen (O2), and / or nitrogen (N2). The lanthanum oxide film, the hafnium oxide film, and the gadolinium oxide film can be formed by coating an organic solvent containing the oxide film material and sintering it.

[0086] The etching rate of the first insulating film 21 can also be adjusted by adjusting conditions such as film formation / sintering temperature in the process of forming the first insulating film 21 on the first electrode 11.

[0087] As Figure 10 shown, the manufacturing method of the pixel circuit board according to one embodiment of the present disclosure includes an etching process in a state where the second electrode 12b is covered with a resist 700 between the process of forming the second electrode 12b and the process of forming the second insulating film 22.

[0088] When the second electrode 12b is etched in a state where the second electrode 12b is covered with the resist 700, as Figure 10 shown, the periphery of the second electrode 12b is etched together with the second electrode 12b, and there is a case where the thickness of the periphery of the second electrode 12b in the first insulating film 21d becomes thin. According to the manufacturing method of the pixel circuit board according to one embodiment of the present disclosure, by forming the second electrode 12b on the first insulating film 21d having a small etching rate, it is possible to prevent not only the occurrence of a short circuit when forming a contact hole described later, but also the thinning of the thickness of the periphery of the second electrode 12b such as the first insulating film 21d.

[0089] As Figure 11As shown, in the method for manufacturing a pixel circuit substrate according to an aspect of the present disclosure, the second insulating film 22 is formed by a step of forming the second insulating film 22 on the second electrode 12b, and the second insulating film 22 is etched using an etchant.

[0090] The step of forming the second insulating film 22 is the same as the step of forming the first insulating film 21. For example, the second insulating film 22, which is a silicon oxide film, a silicon nitride film, an aluminum oxide film, a lanthanum oxide film, a hafnium oxide film, or a gadolinium oxide film, is formed by plasma chemical vapor deposition (CVD method), sintering method, etc., and preferably can be formed as a silicon oxide film. As described above, the silicon oxide film is formed by vapor growth using a mixed gas containing silane (SiH4) and oxygen (O2).

[0091] In the step of forming the second insulating film 22, for example, by adjusting the mixed gas ratio, temperature conditions, etc. in the CVD method, the etching rate of the second insulating film 22 can be adjusted to be greater than the etching rate of the first insulating film 21d.

[0092] As Figure 11 shown, in the method for manufacturing a pixel circuit substrate according to an aspect of the present disclosure, the second insulating film 22 is formed by a step of forming the second insulating film 22 on the second electrode 12b, and the second insulating film 22 is etched using an etchant. The etching can be either a dry etching method or a wet etching method, but in order to reduce the possibility of electrode corrosion caused by the etchant, a dry etching method such as a plasma etching method is preferred.

[0093] Examples of the etchant used for etching include noble gases such as argon (Ar) and helium (He); halogenated carbon gases such as perfluorocarbon gas (PFC) and hydrofluorocarbon gas (HFC); hydrocarbon gases such as methane; hydrofluoric acid (HF); chlorine gas; oxygen gas; hydrogen gas, etc. PFC is preferably used as the specified etchant. In addition, the specified etchant means an etchant used in common for forming contact holes in the first, second, and third insulating films, and it should be noted that it is not limited to PFC.

[0094] In addition, in each of the processes of forming the first contact hole 31 and the process of forming the second contact hole 32, conditions other than the etching time required, such as the supply amount and temperature of the etchant, can be designed according to the types of insulating materials included in the first insulating film 21 and the second insulating film 22 and the type of etchant used. The supply amount and temperature of the etchant in the process of forming the first contact hole 31 and the process of forming the second contact hole 32 can be the same. In the manufacturing method of the pixel circuit substrate according to one embodiment of the present disclosure, since the etching rate of the first insulating film 21 is designed to be smaller than that of the second insulating film 22 in advance, for example, by keeping the supply amount and temperature of the etchant the same, it is possible to easily design the conditions for forming the first contact hole 31 and the second contact hole 32, which is also one of the advantages of this manufacturing method.

[0095] In addition, the first contact hole 31 and the second contact hole 32 can be formed simultaneously, or the first contact hole 31 and the second contact hole 32 can be formed continuously and separately.

[0096] Figure 12 In the capacitor 105 which is manufactured by the manufacturing method of the pixel circuit substrate according to one embodiment of the present disclosure and has the first insulating film 21d through so-called reprocessing etching, the first insulating film 21d also falls within the scope of the pixel circuit substrate of one aspect of the present disclosure, and the first insulating film 21d includes a thin film portion where the film thickness at the peripheral portion of the second electrode 12b is smaller than the overlapping portion overlapping with the second electrode 12b.

[0097] The present disclosure is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present invention. Further, new technical features can be formed by combining the technical means disclosed in each embodiment.

[0098] Description of Reference Numerals 11, 11' First electrode 12, 12', 12a, 12b Second electrode 13, 13' Third electrode 14 Fourth electrode 21, 21', 21a, 21b, 21c, 21d First insulating film 22, 22' Second insulating film 23 Third insulating film 31, 32 Contact hole (pixel circuit) 100, 100', 101, 102, 103, 104, 105 Capacitor (capacitance element) SC Semiconductor film (top-gate transistor) SZ oxide semiconductor film (top-gate type oxide semiconductor transistor) 300 light-emitting element layer 200, 201 pixel circuit substrates 500, 501 display devices.

Claims

1. A pixel circuit substrate having a plurality of pixel circuits, the pixel circuits including a first electrode and a second electrode forming a capacitor, wherein the pixel circuit substrate comprises a first insulating film and a second insulating film, the first electrode is formed on a layer lower than the first insulating film, the second electrode is formed on the first insulating film, the second insulating film is formed on the second electrode, the etching rate of the first insulating film with respect to a specified etchant is less than the etching rate of the second insulating film with respect to the specified etchant, a first contact hole and a second contact hole are formed in the second insulating film, the first contact hole overlapping the second electrode in a plan view, and the second contact hole overlapping the first electrode in a plan view.

2. The pixel circuit substrate according to claim 1, wherein a third electrode is formed on a layer higher than the second insulating film, the second electrode and the third electrode are connected via the first contact hole penetrating the second insulating film.

3. The pixel circuit substrate according to claim 2, wherein a fourth electrode is formed on a layer higher than the second insulating film, the first electrode and the fourth electrode are connected via the second contact hole.

4. The pixel circuit substrate according to claim 3, wherein the second contact hole penetrates the first insulating film and the second insulating film.

5. The pixel circuit substrate according to any one of claims 1 to 4, wherein a third insulating film is provided, the first insulating film is formed on the first electrode with the third insulating film therebetween.

6. The pixel circuit substrate according to any one of claims 1 to 4, wherein the second insulating film contacts the first electrode and the second electrode.

7. The pixel circuit substrate according to any one of claims 1 to 6, wherein the first insulating film is in an island shape.

8. The pixel circuit substrate according to any one of claims 1 to 7, wherein in a plan view, the first contact hole overlaps an end surface of the second electrode.

9. The pixel circuit substrate according to any one of claims 1 to 8, wherein the first insulating film includes an overlapping portion overlapping the second electrode and a thin film portion having a smaller film thickness than the overlapping portion.

10. The pixel circuit substrate according to any one of claims 1 to 9, wherein one of the first insulating film and the second insulating film contains at least one of a silicon nitride film, an aluminum oxide film, a lanthanum oxide film, a hafnium oxide film, and a gadolinium oxide film, the other of the first insulating film and the second insulating film is a silicon oxide film.

11. The pixel circuit substrate according to any one of claims 1 to 10, wherein a top-gate type transistor is included, one of the first electrode and the second electrode is electrically connected to a gate electrode of the transistor, and the other is electrically connected to a high-potential side power supply line.

12. The pixel circuit substrate according to claim 11, wherein the first insulating film is formed on an inorganic insulating film covering the gate electrode of the transistor.

13. The pixel circuit substrate according to any one of claims 1 to 11, characterized in that it includes a top-gate type oxide semiconductor transistor, the first insulating film and the gate insulating film are formed on the same layer, and the gate insulating film is in contact with the gate electrode of the oxide semiconductor transistor.

14. The pixel circuit substrate according to any one of claims 1 to 13, characterized in that the second electrode has a conical shape with a sharp upper end.

15. The pixel circuit substrate according to claim 14, characterized in that the second electrode is a laminated film including an aluminum layer.

16. The pixel circuit substrate according to claim 15, characterized in that in a plan view, the first contact hole overlaps with an end face of the aluminum layer.

17. The pixel circuit substrate according to any one of claims 1 to 16, characterized in that a plurality of the pixel circuits include a first pixel circuit and a second pixel circuit, in the first pixel circuit, in a plan view, the first contact hole overlaps with an end face of the second electrode, in the second pixel circuit, in a plan view, the first contact hole does not overlap with an end face of the second electrode.

18. A display device, characterized in that, It includes: the pixel circuit substrate according to any one of claims 1 to 17; and a light-emitting element layer located above the pixel circuit substrate.

19. A method for manufacturing a pixel circuit substrate, the pixel circuit substrate having a pixel circuit, the pixel circuit including a first electrode and a second electrode forming a capacitor, the method for manufacturing the pixel circuit substrate is characterized by including: a step of forming the first electrode; a step of forming a first insulating film on the first electrode; a step of forming a second electrode on the first insulating film; a step of forming a second insulating film on the second electrode; a step of etching the second insulating film using an etchant to form a first contact hole that overlaps with the second electrode in a plan view; and a step of etching the second insulating film using an etchant to form a second contact hole that overlaps with the first electrode in a plan view, the etching rate of the etchant on the first insulating film is less than the etching rate of the etchant on the second insulating film.

20. The method for manufacturing a pixel circuit substrate according to claim 19, characterized in that between the step of forming the second electrode and the step of forming the second insulating film, it includes a step of performing etching in a state where the second electrode is covered with a resist.

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