Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel comprises a display area and a peripheral area surrounding the display area, the peripheral area comprises a wiring area, and the wiring area is located on one side of the display area; wherein the wiring area is provided with an input area and a dummy area, the dummy area and the input area are sequentially arranged in the direction away from the display area, the input area is provided with a plurality of input protrusions, the dummy area is provided with a plurality of dummy protrusions, and the display panel further comprises a substrate and a plurality of signal lines located on the substrate. According to the integrated circuit, the first spacer region is arranged between the plurality of input bulges and the plurality of dummy bulges, and at most one of the plurality of signal lines passes through the first spacer region, so that cracks generated on the inorganic insulating layer in the binding process of the integrated circuit can be reduced or avoided, and further, defects caused by the cracks in the inorganic insulating layer can be avoided.

Description

Display panel and display device Technical Field

[0001] At least one embodiment of the present disclosure relates to a display panel and a display device. Background Art

[0002] With the expansion of applications of flexible organic light-emitting diode (OLED) screens, foldable products have gradually occupied the market in recent years.

[0003] Summary of the Invention

[0004] At least one embodiment of the present disclosure provides a display panel and a display device.

[0005] At least one embodiment of the present disclosure provides a display panel, comprising a display area and a peripheral area surrounding the display area, the peripheral area comprising a wiring area, the wiring area being located on one side of the display area; wherein the wiring area has an input area and a dummy area, the dummy area and the input area being arranged in sequence in a direction away from the display area, the input area having a plurality of input protrusions, the dummy area having a plurality of dummy protrusions, the display panel further comprising a base substrate and a plurality of signal lines located on the base substrate, a first spacing area being provided between the plurality of input protrusions and the plurality of dummy protrusions, and at most one of the plurality of signal lines passing through the first spacing area.

[0006] For example, according to the display panel provided by at least one embodiment of the present disclosure, one of the plurality of signal lines passes through the first spacer.

[0007] For example, according to the display panel provided by at least one embodiment of the present disclosure, the multiple signal lines include a crack detection line and a source test line, the crack detection line is located in the peripheral area, the crack detection line is configured to detect cracks in the display panel, the source test line is configured to perform a source test, and one of the crack detection line and the source test line passes through the first spacing area.

[0008] For example, according to the display panel provided by at least one embodiment of the present disclosure, one of the crack detection line and the source test line includes an extension portion, the extension portion passes through the first spacer area, and the minimum distance between the extension portion and the input area is smaller than the minimum distance between the extension portion and the dummy area.

[0009] For example, according to the display panel provided by at least one embodiment of the present disclosure, the minimum distance between the extension portion and the input area is 14 to 17 micrometers.

[0010] For example, according to the display panel provided by at least one embodiment of the present disclosure, the wiring area also includes an output area, the output area is located on a side of the dummy area away from the input area, the output area has a plurality of output protrusions, the plurality of input protrusions and the plurality of output protrusions on the display panel are all configured to be connected to an integrated circuit, the display panel also includes a plurality of connection protrusions, the plurality of connection protrusions are located on a side of the wiring area away from the display area, the plurality of connection protrusions are configured to be connected to a flexible circuit board, at least part of the plurality of input protrusions are arranged in a row along a first direction, and at least part of the plurality of dummy protrusions are arranged in a column along a second direction, the first direction and the second direction are both parallel to the base substrate, and the first direction intersects with the second direction.

[0011] For example, according to the display panel provided by at least one embodiment of the present disclosure, none of the plurality of signal lines passes through the first spacer.

[0012] For example, according to the display panel provided by at least one embodiment of the present disclosure, the multiple signal lines include a crack detection line and a source test line, the crack detection line is located in the peripheral area, the crack detection line is configured to detect cracks in the display panel, the source test line is configured to perform a source test line, the multiple connection protrusions include a first connection protrusion and a second connection protrusion, the two ends of the crack detection line are respectively connected to the first connection protrusion and the second connection protrusion, the wiring area is located in the area enclosed by the crack detection line, and the wiring area is spaced apart from the crack detection line.

[0013] For example, according to the display panel provided by at least one embodiment of the present disclosure, the multiple connecting protrusions also include a third connecting protrusion and a fourth connecting protrusion, the third connecting protrusion is connected to the first connecting protrusion, the fourth connecting protrusion is connected to the second connecting protrusion, and the third connecting protrusion and the fourth connecting protrusion are respectively connected to the two input protrusions in the input area.

[0014] For example, according to a display panel provided in at least one embodiment of the present disclosure, the display panel further includes a first test pad and a second test pad, the first test pad is connected to the first connecting protrusion, the second test pad is connected to the second connecting protrusion, and the first test pad and the second test pad are configured to be connected to a test component for crack detection.

[0015] For example, according to the display panel provided by at least one embodiment of the present disclosure, the multiple dummy protrusions include a first dummy protrusion and a second dummy protrusion, the first dummy protrusion and the second dummy protrusion are adjacent to each other in the second direction, and the source test line passes through the area between the first dummy protrusion and the second dummy protrusion.

[0016] For example, in the display panel provided by at least one embodiment of the present disclosure, the first dummy protrusion is located at an end of the dummy area close to the input area.

[0017] For example, according to the display panel provided by at least one embodiment of the present disclosure, the multiple output protrusions are arranged in a matrix of M rows and N columns along the first direction and the second direction, the matrix includes M rows of output protrusions and N columns of output protrusions, the output protrusion in the i-th row is farther away from the dummy area than the output protrusion in the i+1-th row, N and M are both positive integers, i is less than or equal to M-1, one end of the source test line is connected to one of the multiple output protrusions, and the other end of the source test line is connected to one of the multiple connection protrusions in the display panel.

[0018] For example, according to the display panel provided by at least one embodiment of the present disclosure, the source test line does not pass through the dummy area, and the source test line avoids the first spacer area.

[0019] For example, according to the display panel provided by at least one embodiment of the present disclosure, one end of the source test line is connected to one end of one of the plurality of output bumps in the first row away from the dummy area and extends to a position away from the wiring area for wiring.

[0020] For example, according to the display panel provided by at least one embodiment of the present disclosure, one end of the source test line is connected to one end of one of the multiple output protrusions in the Mth row of output protrusions close to the dummy area, and there is a second spacer area between the multiple output protrusions and the multiple dummy protrusions, and the source test line passes through the second spacer area.

[0021] For example, according to the display panel provided by at least one embodiment of the present disclosure, the multiple signal lines also include multiple first signal lines, at least part of the first signal lines extend along the first direction, and the first signal lines are located between the input area and the output area, and the first signal lines include a first stacked structure in a direction perpendicular to the base substrate.

[0022] For example, according to at least one embodiment of the present disclosure, a display panel is provided, which includes a base substrate, and a first conductive pattern, a second conductive pattern, a third conductive pattern, a fourth conductive pattern and a fifth conductive pattern arranged in sequence on the base substrate, the first conductive pattern is closer to the base substrate than the second conductive pattern, the multiple signal lines also include multiple second signal lines, at least part of the second signal lines extend along the second direction, the multiple second signal lines are located on one side of the wiring area in the first direction, and one end of the second signal line is connected to the connection protrusion in the display panel, the first signal line is located in the third conductive pattern or in the fifth conductive pattern, and the second signal line is located in the fourth conductive pattern.

[0023] For example, according to the display panel provided by at least one embodiment of the present disclosure, the second signal line includes a second stacked structure in a direction perpendicular to the base substrate.

[0024] For example, according to the display panel provided by at least one embodiment of the present disclosure, the first stacked structure and / or the second stacked structure includes a Ti / Al / Ti structure.

[0025] For example, according to at least one embodiment of the present disclosure, a display panel is provided, wherein the display panel further includes an organic pattern, the organic pattern includes an opening, wherein the display panel further includes a supporting structure located in the opening, the supporting structure includes an organic material.

[0026] For example, according to a display panel provided by at least one embodiment of the present disclosure, the organic pattern includes a first organic pattern, a second organic pattern and a third organic pattern, and the first organic pattern, the second organic pattern and the third organic pattern are stacked in sequence along a direction perpendicular to the base substrate, the first organic pattern is closer to the base substrate than the second organic pattern, the first organic pattern includes a first opening, the second organic pattern includes a second opening, and the third organic pattern includes a third opening, and the display panel includes an opening area exposed by the first opening, the second opening and the third opening, wherein the display panel also includes a plurality of support structures located in the opening area.

[0027] For example, in the display panel provided according to at least one embodiment of the present disclosure, the supporting structure is located between the first signal line and the input protrusion, and the supporting structure includes a first organic structure, a second organic structure, and a third organic structure stacked in sequence along a direction perpendicular to the base substrate, the first organic structure is located in the first organic pattern, the second organic structure is located in the second organic pattern, and the third organic structure is located in the third organic pattern.

[0028] For example, according to the display panel provided by at least one embodiment of the present disclosure, the orthographic projection of the first organic structure on the base substrate falls within the orthographic projection of the second organic structure on the base substrate, and the orthographic projection of the second organic structure on the base substrate falls within the orthographic projection of the third organic structure on the base substrate.

[0029] For example, in the display panel provided by at least one embodiment of the present disclosure, the second organic structure covers the first organic structure, and the third organic structure covers the second organic structure.

[0030] At least one embodiment of the present disclosure also provides a display panel, comprising a display area and a peripheral area surrounding the display area, the peripheral area comprising a wiring area, the wiring area being located on one side of the display area; the display panel further comprising a base substrate and a plurality of signal lines located on the base substrate, the plurality of signal lines comprising a crack detection line and a source test line, the crack detection line being located in the peripheral area and surrounding the display area, the crack detection line being configured to detect cracks in the display panel, the source test line being configured to perform a source test, wherein the wiring area has an input area and a dummy area, the dummy area and the input area being arranged in sequence in a direction away from the display area, the input area having a plurality of input protrusions, the dummy area having a plurality of dummy protrusions, a first spacing area being provided between the plurality of input protrusions and the plurality of dummy protrusions, and at most one of the crack detection line and the source test line passing through the first spacing area.

[0031] For example, according to the display panel provided by at least one embodiment of the present disclosure, the wiring area also includes an output area, the output area is located on a side of the dummy area away from the input area, the output area has a plurality of output protrusions, the plurality of input protrusions and the plurality of output protrusions on the display panel are all configured to be connected to an integrated circuit, the display panel also includes a plurality of connection protrusions, the plurality of connection protrusions are located on a side of the wiring area away from the display area, the plurality of connection protrusions are configured to be connected to a flexible circuit board, at least part of the plurality of input protrusions are arranged in a row along a first direction, and at least part of the plurality of dummy protrusions are arranged in a column along a second direction, the first direction and the second direction are both parallel to the base substrate, and the first direction intersects with the second direction.

[0032] For example, according to the display panel provided by at least one embodiment of the present disclosure, the multiple connecting protrusions include a first connecting protrusion and a second connecting protrusion, the two ends of the crack detection line are respectively connected to the first connecting protrusion and the second connecting protrusion, the wiring area is located in the area enclosed by the crack detection line, and the wiring area is spaced apart from the crack detection line.

[0033] For example, according to the display panel provided by at least one embodiment of the present disclosure, the source test line does not pass through the dummy area, and the source test line avoids the first spacer area.

[0034] An embodiment of the present disclosure further provides a display device, comprising any of the above-mentioned display panels. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0036] FIG. 1 is a schematic diagram showing a display panel failing crack detection.

[0037] FIG2 is a schematic diagram of a simulation model of a display panel.

[0038] FIG3 is a schematic diagram of simulation results of the simulation model in FIG2 .

[0039] FIG4 is a schematic diagram of a partial structure of a display panel.

[0040] FIG. 5A is a schematic diagram showing simulation results of a display panel.

[0041] FIG. 5B is a schematic diagram showing simulation results of another display panel.

[0042] FIG. 6 is a schematic diagram showing simulation results of another display panel.

[0043] FIG7 is a schematic diagram of a display panel (after IC binding) provided by an embodiment of the present disclosure.

[0044] FIG8 is a schematic diagram of a wiring area of ​​a display panel provided by an embodiment of the present disclosure.

[0045] FIG9 is a schematic diagram of a partial structure of a display panel.

[0046] FIG. 10 is a schematic diagram of the overall structure of the display panel corresponding to FIG. 9 .

[0047] FIG. 11 is a partially enlarged schematic diagram corresponding to the display panel of FIG. 9 .

[0048] FIG12 is a schematic diagram of a wiring area of ​​another display panel provided by an embodiment of the present disclosure.

[0049] FIG. 13 is a schematic diagram of the overall structure of the display panel corresponding to FIG. 12 .

[0050] FIG14 is a schematic diagram of a wiring area of ​​another display panel provided by an embodiment of the present disclosure.

[0051] FIG. 15 is a schematic diagram of the overall structure of the display panel corresponding to FIG. 14 .

[0052] FIG16 is a schematic diagram of a wiring area of ​​another display panel provided by an embodiment of the present disclosure.

[0053] FIG. 17 is a schematic diagram of the overall structure of the display panel corresponding to FIG. 16 .

[0054] FIG18 is a schematic diagram of the overall structure of another display panel provided by an embodiment of the present disclosure.

[0055] FIG19 is a schematic diagram of the overall structure of another display panel provided by an embodiment of the present disclosure.

[0056] FIG20 is a schematic diagram of a partial structure of a display panel.

[0057] FIG21 is a schematic diagram of a partial structure of another display panel provided in an embodiment of the present disclosure.

[0058] FIG. 22 is a schematic diagram of a support structure provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0059] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0060] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0061] With the application of flexible OLEDs in foldable products, screen quality needs to be further improved in terms of image quality and flicker. For OLED display products, upgrading from low-temperature polysilicon (LTPS) to low-temperature polycrystalline-oxide (LTPO) can meet the higher image quality requirements of foldable products. In the display field, compared to 40nm IC chips, 28nm IC chips are smaller in size and consume less power, making the gradual use of 28nm IC chips an industry trend.

[0062] FIG. 1 is a schematic diagram showing a display panel failing crack detection.

[0063] As shown in Figure 1, during the production of foldable products, the production line consistently experienced 3%-7% of display panel crack detection (PCD) failures (Not Good, NG) on the production line. Analysis revealed that cracks are caused by the integrated circuit (IC) bonding process. For example, the area of ​​the display panel that bonds to the IC is provided with an input bump BP1 and a dummy bump BP3. The crack detection line PCD passes through the area between the input bump BP1 and the dummy bump BP3. When a crack extends through this area, the display panel cracks in this area. The crack will cause the crack detection line in the area used to bond the IC to break, leading to a failure in the display panel crack detection. Therefore, the display panel crack detection failure issue is essentially caused by cracks in the IC bonding process.

[0064] During research, the inventors of this application discovered that for foldable LTPO display panels, crack detection failures caused by the bonding process continued to occur, with obvious cracks visible under a microscope. The NG rate fluctuated between batches by approximately 3%-7%. Failure to detect cracks caused by the IC bonding process poses two risks for OLED screens: ① If the display panel crack detection has already failed, cracks in other locations around the display panel will not be detected; ② Since the essence of failing the display panel crack detection is the presence of cracks in the display panel, there is a risk of further spread and deterioration over time or due to reliability issues, thereby affecting the normal display of the screen. In other words, cracks in the display panel may cause related defects caused by the cracks, and these defects are not limited to NG crack detection on the display panel.

[0065] Figure 2 is a schematic diagram of a simulation model of a display panel; Figure 3 is a schematic diagram of the simulation results of the simulation model in Figure 2; Figure 4 is a schematic diagram of the local structure of a display panel; Figure 5A is a schematic diagram of the simulation results of a display panel; Figure 5B is a schematic diagram of the simulation results of another display panel.

[0066] As shown in Figure 2, for the packaging area of ​​the display panel, for example, the COP (Chip on Pi) area, the simulation model built includes an input protrusion BP1 and a dummy protrusion BP3. The crack detection line PCD and the source test line ST both pass through the area of ​​the display panel between the input protrusion BP1 and the dummy protrusion BP3, and the simulation model simplifies the structure in this area. For example, the area of ​​the display panel between the input protrusion BP1 and the dummy protrusion BP3 is located in the lower left corner of the display panel. For example, the input protrusion BP1 and the dummy protrusion BP3 are both located in the area of ​​the display panel used for binding with the IC. The input protrusion BP1 serves as a conductive structure of the display panel and is connected to the IC; the dummy protrusion BP3 is not connected to the IC. For example, the display panel may also include other conductive structures (for example, output protrusions) to connect to the IC.

[0067] Figure 3 shows that the strain distribution in the simulation model is uneven. Region A0 of the display panel, located between input bump BP1 and dummy bump BP3, exhibits significantly greater strain, leading to a higher risk of cracks in region A0. This simulation result closely matches the crack-initiating regions of the actual product, demonstrating its authenticity.

[0068] For example, the simulation model shown in FIG2 may correspond to the display panel 001 shown in FIG4. For example, as shown in FIG4, the crack detection line PCD is closer to the input bump BP1 than the source test line ST, and both the crack detection line PCD and the source test line ST pass through the area between the input bump BP1 and the dummy bump BP3. The minimum distance L0 between the portion of the crack detection line PCD passing through the area and the input bump BP1 is 58 microns.

[0069] As shown in Figures 4 and 5A, in the region between input bump BP1 and dummy bump BP3, when the minimum distance L0 between crack detection line PCD and input bump BP1 is 58 microns, the area of ​​display panel 001 with the greatest strain is region A1, with the maximum strain value in region A1 being approximately 31‰. The portion of display panel 001 traversed by source test line ST has location A2 with the greatest strain, reaching approximately 8.1‰. In other words, source test line ST passes through a location in display panel 001 where the inorganic layer "climbs" and experiences significant strain.

[0070] The display panel corresponding to FIG5B differs from the display panel corresponding to FIG5A in that the minimum distance between the crack detection line PCD and the input bump BP1 is different. For example, referring to FIG4 , the crack detection line PCD and the source test line ST both pass through the area between the input bump BP1 and the dummy bump BP3. The minimum distance L0 between the portion of the crack detection line PCD passing through this area and the input bump BP1 can be 14 microns. In this case, as shown in FIG5B , the area of ​​the display panel with the greatest strain is area A3, with the maximum strain value in area A3 being approximately 16‰. The portion of the display panel 001 passed by the source test line ST has a location A4 with the greatest strain, and the strain value at location A4 is approximately 4.0‰.

[0071] It can be seen that by reducing the minimum distance L0 between the portion of the crack detection line PCD passing through the area between the input bump BP1 and the dummy bump BP3 and the input bump BP1, the strain value of the display panel is reduced.

[0072] FIG. 6 is a schematic diagram showing simulation results of another display panel.

[0073] For example, as shown in Figure 6, in the display panel, three signal lines are set in the area between the input protrusion and the dummy protrusion, namely, the crack detection line PCD, the data writing control signal line M1 and the light control signal line M2. The crack detection line PCD, the data writing control signal line M1 and the light control signal line M2 all pass through the area between the input protrusion and the dummy protrusion, and the minimum distance between the part of the light control signal line M2 passing through the area and the input protrusion is 22 microns.

[0074] Figure 6 shows that the display panel exhibits the highest strain in region A5, with the maximum strain value in region A5 being approximately 27.9‰. The portion of the display panel traversed by the crack detection line PCD has a location A6 with the highest strain, with a strain value of approximately 5.2‰. While this display panel exhibits better simulation results than display panel 001, the overall strain value of the display panel remains high.

[0075] The simulation results above show that the wiring pattern in the display panel's IC-bonding area (for example, the area between the input bump and the dummy bump) is crucial, as it influences the force distribution on the display panel. Therefore, optimizing the wiring pattern in the display panel's IC-bonding area is crucial to reduce the probability of NG crack detection in the display panel.

[0076] At least one embodiment of the present disclosure provides a display panel and a display device.

[0077] At least one embodiment of the present disclosure provides a display panel, comprising: a display area and a peripheral area surrounding the display area, the peripheral area including a wiring area, the wiring area being located on one side of the display area; the wiring area having an input area and a dummy area, the dummy area and the input area being arranged in sequence in a direction away from the display area, the input area having a plurality of input protrusions, the dummy area having a plurality of dummy protrusions, the display panel further comprising a base substrate and a plurality of signal lines located on the base substrate, a first spacing area being provided between the plurality of input protrusions and the plurality of dummy protrusions, and at most one of the plurality of signal lines passing through the first spacing area.

[0078] The embodiments of the present disclosure optimize the arrangement of signal lines within the first spacing area of ​​the display panel so that at most one of the multiple signal lines passes through the first spacing area, which can significantly reduce the strain value within the first spacing area, thereby reducing the deformation of the display panel and achieving the effect of reducing or eliminating cracks caused by the binding process.

[0079] The display panel and the display device provided by the embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0080] FIG7 is a schematic diagram of a display panel (after IC binding) provided by an embodiment of the present disclosure.

[0081] As shown in FIG7 , the display panel 01 includes a display area 100 and a peripheral area 300 surrounding the display area 100. For example, the display area 100 includes a plurality of sub-pixels SP arranged in an array along a first direction X and a second direction Y. For example, the embodiments of the present disclosure utilize an example in which the peripheral area 300 surrounds the display area 100, but the invention is not limited thereto. The peripheral area 300 may be located on at least one side of the display area 100. For example, the peripheral area 300 may be located on at least one of the left side, right side, top side, and bottom side of the display area 100.

[0082] As shown in Figure 7 , the peripheral region 300 includes a wiring region 200, and the wiring region 200 is located on one side of the display region 100. That is, the wiring region 200 is located on one side of the plurality of sub-pixels SP. Figure 7 uses the example of the wiring region 200 being located on the lower side of the display region 100. The wiring region 200 is part of the peripheral region 300. For clarity, Figure 7 does not show all structures and wiring of the display panel 01.

[0083] 7 , the display panel 01 further includes a base substrate BS and a plurality of signal lines 50 located on the base substrate BS. For example, the plurality of signal lines 50 are located in the peripheral area 300. For example, the signal lines 50 can be connected to scan lines located in the display area 100.

[0084] For example, as shown in FIG7 , the plurality of signal lines 50 may include a crack detection line PCD and a source test line ST. The crack detection line PCD is located in the peripheral area 300 and surrounds the display area 100. The crack detection line PCD is configured to detect cracks in the display panel 01, and the source test line ST is configured to perform a source test.

[0085] As shown in FIG7 , the wiring area 200 includes an input area 201 and a dummy area 203. The dummy area 203 and the input area 201 are arranged sequentially in a direction away from the display area 100. For example, the input area 201 and the dummy area 203 are arranged sequentially in the second direction Y, and the dummy area 203 is located on the side of the input area 201 closer to the display area 100. The input area 201 has a plurality of input protrusions BP1, and the dummy area 203 has a plurality of dummy protrusions BP3. For example, the wiring area 200 also includes an output area 202. In an embodiment of the present disclosure, the division of the output area 201, the input area 202, and the dummy area 203 can be based on a line connecting the outermost edges of the protrusions located therein.

[0086] For example, as shown in FIG7 , at least some of the plurality of input bumps BP1 are arranged in a row along the first direction X, and at least some of the plurality of dummy bumps BP3 are arranged in a column along the second direction Y. For example, in some embodiments, at least some of the plurality of input bumps BP1 may also be arranged in multiple rows along the first direction X, and at least some of the plurality of dummy bumps BP3 may also be arranged in multiple columns along the second direction Y.

[0087] For example, the first direction X and the second direction Y are both parallel to the base substrate BS, and the first direction X intersects the second direction Y. For example, the first direction X is perpendicular to the second direction Y.

[0088] For example, as shown in FIG7 , output region 202 is located on a side of dummy region 203 away from input region 201 and includes a plurality of output bumps BP2. The plurality of input bumps BP1 and the plurality of output bumps BP2 on display panel 01 are configured to connect to integrated circuit 88. For example, dummy bump BP3 can balance stress during the bonding process of integrated circuit 88. Display panel 01 also includes a plurality of connection bumps BP4 located on a side of wiring region 200 away from display region 100. These connection bumps BP4 are configured to connect to flexible printed circuit board 99.

[0089] For example, as shown in FIG7 , the display panel 01 includes multiple conductive structures and multiple connection structures, such as bumps. For example, the multiple conductive structures may include an input bump BP1, a dummy bump BP3, and an output bump BP2. The multiple connection structures may include a connection bump BP4. FIG7 also shows an integrated circuit 88 and a flexible circuit board 99. For example, the integrated circuit 88 and the flexible circuit board 99 may be separately bonded to the display panel. For example, the integrated circuit 88 may be bonded to the conductive structures on the display panel 01, such as the input bump BP1 and the output bump BP2. For example, the flexible circuit board 99 may be bonded to the connection structures on the display panel, such as the connection bump BP4. For example, the bumps on the display panel 01 bonded to the flexible circuit board 99 may be connected to the bumps on the display panel 01 bonded to the integrated circuit 88. For example, the integrated circuit 88 may be a 28nm IC chip, which has a smaller size and lower power consumption.

[0090] For example, as shown in Figure 7, the two ends of the crack detection line PCD can be connected to connection bumps BP4, which are then connected to two input bumps BP1. For example, a resistance can be detected to determine whether the crack detection line PCD is broken. If the crack detection line PCD is intact, its resistance is normal. If the crack detection line PCD is broken, its resistance will be very high.

[0091] Figure 7 also shows data lines DL. Data lines DL are configured to provide data signals, such as data voltages, to subpixels SP. The number of data lines DL is not limited to that shown in Figure 7 and can be determined as needed. One end of a source test line ST is connected to a data line DL via output bump BP1, and the other end of the source test line ST is connected to a connection structure BP4. Figure 7 shows two source test lines ST, which are respectively connected to connection bumps 721 and 722. Connection bumps 721 and 722 can be connected to conductive structures on the flexible printed circuit board 99.

[0092] For example, as shown in Figure 7, the source test line ST is primarily used to test whether the data line DL connected to it is functioning properly. For example, the waveform on the data line DL connected to it can be tested via the source test line ST. If the display panel displays an abnormality, a source test can be performed to determine whether a problem with the data line DL is causing the display abnormality.

[0093] As shown in FIG7 , a first spacer G1 is provided between the plurality of input bumps BP1 and the plurality of dummy bumps BP3, and at most one of the plurality of signal lines 50 in the display panel 01 passes through the first spacer G1. For example, one of the plurality of signal lines 50 passes through the first spacer G1, or none of the plurality of signal lines 50 passes through the first spacer G1.

[0094] For example, as shown in FIG7 , at most one of the crack detection line PCD and the source test line ST passes through the first spacer G1. That is, at most one of the crack detection line PCD and the source test line ST passes through the first spacer G1. For example, neither the crack detection line PCD nor the source test line ST passes through the first spacer G1.

[0095] In the embodiment of the present disclosure, the signal line (eg, the crack detection line PCD or the source test line ST) not passing through the first spacer G1 indicates that the signal line avoids the first spacer G1 .

[0096] This arrangement effectively improves the stress distribution within the first spacer region G1 and reduces the maximum strain within the first spacer region G1, thereby alleviating or preventing cracks in the inorganic insulating layer during the integrated circuit bonding process. This, in turn, avoids defects caused by cracks in the inorganic insulating layer. For example, cracks in the inorganic insulating layer can prevent the display panel crack detection line from breaking, thereby preventing the display panel from failing crack detection.

[0097] The embodiments of the present disclosure optimize the wiring of signal lines in the COP region of the display panel to reduce the strain value of the COP region (eg, the first spacer G1 ) and avoid defects caused by cracks in the inorganic insulating layer of the display panel.

[0098] FIG8 is a schematic diagram of a wiring area of ​​a display panel provided by an embodiment of the present disclosure.

[0099] For example, as shown in Figures 7 and 8, one of the plurality of signal lines 50 passes through the first spacer region G1. For example, one of the plurality of signal lines 50 located in the peripheral region 300 passes through the first spacer region G1. For example, the signal line 50 passing through the first spacer region G1 can be one of the crack detection line PCD and the source test line ST, or can be another signal line 50 in addition to the crack detection line PCD and the source test line ST. The embodiments of the present disclosure do not limit the type of the signal line 50 passing through the first spacer region G1.

[0100] For example, as shown in Figures 7 and 8, the inorganic insulating layer of the display panel includes at least a portion located in the first spacer area G1. By allowing only one signal line 50 to pass through the first spacer area G1, the strain value in the first spacer area G1 can be effectively reduced, thereby avoiding defects caused by cracks in the inorganic insulating layer in the display panel 01.

[0101] For example, as shown in FIG8 , the crack detection line PCD or the source test line ST passes through the first spacer G1, and the crack detection line PCD or the source test line ST passing through the first spacer G1 includes an extension 40. The extension 40 extends along the first direction X and passes through the first spacer G1. For example, the extension 40 may be a portion of the crack detection line PCD or the source test line ST, and the portion is located between the input region 201 and the dummy region 203 in the second direction Y.

[0102] For example, as shown in FIG8 , in the second direction Y, the dummy area 203, the extension portion 40, and the input area 201 are arranged in sequence, and the minimum distance L1 between the extension portion 40 and the input area 201 is smaller than the minimum distance L2 between the extension portion 40 and the dummy area 203. In other words, in the second direction Y, the extension portion 40 is located between the input area 201 and the dummy area 203, and the extension portion 40 is closer to the input area 201.

[0103] For example, as shown in FIG8 , in the second direction Y, the minimum distance L1 between the extension portion 40 and the input region 201 is 1 / 5 to 1 / 2 of the minimum distance L2 between the extension portion 40 and the dummy region 203, such as at least one of 1 / 5 to 1 / 4, 1 / 5 to 1 / 3, 1 / 4 to 1 / 3, and 1 / 3 to 1 / 2. For example, the extension portion 40 can be as close to the input region 201 as possible to avoid passing through the middle of the first spacer region G1.

[0104] Such a configuration can prevent the extension portion 40 from passing through the area of ​​the first spacer region G1 where cracks are prone to occur (for example, the area between the middle of the first spacer region G1 and the dummy region 203), and effectively reduce the strain value in the first spacer region G1, thereby avoiding defects caused by cracks in the inorganic insulating layer in the display panel 02.

[0105] For example, as shown in Figure 8, in the second direction Y, the minimum distance between the extension portion 40 and the input area 201 can be 14 to 17 microns, such as 14 to 15 microns, 14 to 16 microns, 15 to 16 microns, 15 to 17 microns, or 16 to 17 microns, which can be set according to design requirements.

[0106] FIG9 is a schematic diagram of a partial structure of a display panel; FIG10 is a schematic diagram of the overall structure of the display panel corresponding to FIG9; and FIG11 is a schematic diagram of a partial enlargement of the display panel corresponding to FIG9.

[0107] For example, as shown in FIG9 , the signal line passing through the first spacer region G1 can be a source test line ST. For example, one end of the source test line ST is connected to the input bump BP1 in the input region 201, and one end of the source test line ST can be connected to the connection bump. The portion of the source test line ST located between the dummy region 203 and the input region 201 (i.e., the extension portion 40) extends substantially along the edge of the input region 201, thereby avoiding excessive bending in the extension region 40 and facilitating balanced stress distribution between the dummy region 203 and the input region 201. For other structures of the display panel shown in FIG9 , reference can be made to the relevant descriptions of FIG7 and FIG8 in the above embodiments, and will not be repeated here.

[0108] For example, as shown in Figure 10, the display panel may include a gathering area W1, a gathering area W2, a wiring area 200, a pad area W3 and a test area W4 arranged in sequence along the second direction Y. For example, a plurality of signal lines respectively connected to a plurality of scan lines in the display area are gathered in the gathering area W1, and then gathered in the gathering area W2. A plurality of connecting protrusions are provided in the pad area W3 to connect to the flexible circuit board. A plurality of test pads are provided in the test area W4. By connecting the test pads to the test components, the status of the signal lines corresponding to the test pads can be detected. For example, the display panel may also include a first voltage signal line VDD and a second voltage signal line VSS. For example, the first voltage signal line VDD can be a power signal line, and the second voltage signal line VSS can be grounded.

[0109] For example, as shown in FIG11 , along the second direction Y, the display panel may include a signal line S1, a signal line S2, an initialization signal line VIN3, an initialization signal line VIN2, an initialization signal line VIN1, a signal line S3, a signal line S4, a signal line S5, a signal line S6, a signal line S7, and a signal line S8. For example, the initialization signal line VIN3, the initialization signal line VIN2, and the initialization signal line VIN1 may each transmit an initialization signal. For example, the signal line S1, the signal line S2, the signal line S3, the signal line S4, the signal line S5, the signal line S6, the signal line S7, and the signal line S8 may each be configured to transmit a different control signal.

[0110] 11 , the display panel further includes test pads AT, and a plurality of signal lines located between the input area 201 and the output area 202 are respectively connected to the test pads AT. The test pads AT are configured to be connected to a test component for signal detection.

[0111] For example, as shown in Figure 7, the plurality of connection bumps BP4 include a first connection bump BP41 and a second connection bump BP42, and the two ends of the crack detection line PCD are connected to the first connection bump BP41 and the second connection bump BP42, respectively. The wiring area 200 is located within the area surrounded by the crack detection line PCD, and the wiring area 200 is spaced apart from the crack detection line PCD.

[0112] For example, as shown in FIG7 , in the first direction X, the first connection bump BP41 and the second connection bump BP42 are respectively located on either side of the wiring area 200. In the second direction Y, the first connection bump BP41 and the second connection bump BP42 are both located on the side of the wiring area 200 away from the display area 100. For example, the first connection bump BP41 and the second connection bump BP42 do not overlap with the wiring area 200. For example, the crack detection line PCD surrounds the wiring area 200. This arrangement allows the crack detection line PCD to avoid the wiring area 200, thereby avoiding the first spacer G1 in the wiring area 200. As a result, the crack detection line PCD does not pass through the first spacer G1, thereby reducing the strain value in the first spacer G1, reducing the problem of NG in crack detection of the display panel 01, and avoiding defects caused by cracks in the inorganic insulating layer of the display panel 01.

[0113] For example, as shown in Figure 7, the multiple connection bumps BP4 in the display panel 01 also include a third connection bump BP43 and a fourth connection bump BP44, the third connection bump BP43 is connected to the first connection bump BP41, the fourth connection bump BP44 is connected to the second connection bump BP44, the third connection bump BP43 and the fourth connection bump BP44 are respectively connected to the two input bumps BP1 in the input area 201, so that the crack detection line PCD can be electrically connected to the two input bumps BP1 in the input area 201.

[0114] For example, as shown in FIG7 , in the first direction X, the third connection bump BP43 and the fourth connection bump BP44 may be located between the first connection bump BP41 and the second connection bump BP44, with the third connection bump BP43 being closer to the wiring region 200 than the first connection bump BP41, and the fourth connection bump BP44 being closer to the wiring region 200 than the second connection bump BP44. This facilitates connection between the third connection bump BP43 and the fourth connection bump BP44 and the input bump BP1 in the wiring region 200. For example, the third connection bump BP43 and the fourth connection bump BP44 may be connected to two adjacent input bumps BP1 in the wiring region 200, respectively. For example, the two input bumps BP1 respectively connected to the third connection bump BP43 and the fourth connection bump BP44 are both far away from the first spacer area G1. For example, the two input bumps BP1 respectively connected to the third connection bump BP43 and the fourth connection bump BP44 can be located in the middle of the input area 201, so as to reduce the strain value in the first spacer area G1 and reduce the display panel crack detection NG problem.

[0115] Of course, in some embodiments of the present disclosure, the third connection protrusion BP43 may also be located on the side of the first connection protrusion BP41 away from the input area 201, and the fourth connection protrusion BP44 may also be located on the side of the second connection protrusion BP44 away from the input area 201, which can be specifically set according to the space of the layout.

[0116] For example, as shown in Figure 7, the display panel 01 also includes a first test pad ET1 and a second test pad ET2, the first test pad ET1 is connected to the first connection protrusion BP41, and the second test pad ET2 is connected to the second connection protrusion BP42, and the first test pad ET1 and the second test pad ET2 are configured to be connected to the test component for crack detection.

[0117] For example, as shown in FIG7 , the first test pad ET1 can be connected to the first connection bump BP41 via a wire, and the second test pad ET2 can be connected to the second connection bump BP42 via a wire, so that the first test pad ET1 and the second test pad ET2 can be connected to the crack detection line PCD. For example, the test component can include probes, and the probes can be connected to the first test pad ET1 and the second test pad ET2 respectively to detect the resistance of the crack detection line PCD, thereby determining whether the crack detection line PCD is broken.

[0118] FIG12 is a schematic diagram of a wiring area of ​​another display panel provided in an embodiment of the present disclosure; FIG13 is a schematic diagram of the overall structure of the display panel corresponding to FIG12 .

[0119] For example, as shown in FIG12 , neither the crack detection line PCD nor the source test line ST may pass through the first spacer G1. For example, the crack detection line PCD may adopt the routing method shown in FIG7 , but the embodiments of the present disclosure are not limited thereto. For example, as shown in FIG12 , the source test line ST may be located on a side of at least one dummy bump BP3 away from the input region 201 to avoid the first spacer G1.

[0120] For example, as shown in FIG12 , the plurality of dummy bumps BP3 may include a first dummy bump BP31 and a second dummy bump BP32 , wherein the first dummy bump BP31 and the second dummy bump BP32 are adjacent to each other in the second direction Y, and the source test line ST passes through the area between the first dummy bump BP31 and the second dummy bump BP32 . Thus, the source test line ST can bypass the first spacer G1 to reduce the maximum strain value of the first spacer G1 and reduce the problem of NG in crack detection of the display panel 03 .

[0121] For example, as shown in FIG12 , a plurality of dummy bumps BP3 are arranged sequentially in the second direction Y, and a first dummy bump BP31 is located at an end of the dummy area 203 close to the input area 201. For example, a plurality of dummy bumps BP3 may be arranged sequentially in one column or multiple columns in the second direction Y, and the embodiments of the present disclosure are not limited thereto. For example, in the second direction Y, the first dummy bump BP31 is closer to the input area 201 than the second dummy bump BP32. For example, in the second direction Y, the first dummy bump BP31 may be the dummy bump in the dummy area 203 that is closest to the input area 201. For example, the first dummy bump BP31 and the second dummy bump BP32 being adjacent to each other in the second direction Y means that no other dummy bump BP3 is provided between the first dummy bump BP31 and the second dummy bump BP32 in the second direction Y.

[0122] With this configuration, the source test line ST can avoid the first spacing region G1 while minimizing the intersection between the source test line ST and other signal lines passing through the dummy region 203 , thereby reducing the risk of signal crosstalk and making the layout more reasonable.

[0123] For example, as shown in FIG12 , a plurality of output bumps BP2 are arranged in a matrix of M rows and N columns along a first direction X and a second direction Y. The matrix includes M rows of output bumps BP2 and N columns of output bumps BP2. For example, the output bump BP2 in the i-th row is further away from the dummy region 203 than the output bump BP2 in the i+1-th row, where N and M are both positive integers and i is less than or equal to M-1. For example, the output bump BP2 in the first row is further away from the dummy region 203 than the output bump BP2 in the second row. For example, the output bump BP2 in the M-th row is closer to the dummy region 203 than the output bump BP2 in the M-1-th row.

[0124] For example, as shown in Figures 12 and 13, one end of the source test line ST is connected to one of the output bumps BP2, and the other end of the source test line ST is connected to one of the connection bumps BP4 in the display panel 03. The source test line ST extends from the output region 202 to a region near the test pad AT, and then extends along the first direction X to a region near the dummy region 203. The source test line ST passes through the dummy region 203 and the region between two adjacent dummy bumps BP3 in the dummy region 203, and then connects to the connection bump BP4.

[0125] Regarding other structures in the display panel shown in FIG. 12 and FIG. 13 , reference may be made to the relevant descriptions regarding FIG. 7 and FIG. 8 in the above embodiments, and no further details are given here.

[0126] FIG14 is a schematic diagram of a wiring area of ​​another display panel provided in an embodiment of the present disclosure; FIG15 is a schematic diagram of the overall structure of the display panel corresponding to FIG14 .

[0127] For example, as shown in FIG14 , the difference between the display panel 04 and the display panel 03 in FIG12 is that the wiring method of the source test line ST is different, and the rest of the structures are the same or substantially the same. For details, please refer to the relevant description of the above embodiment, which will not be repeated here.

[0128] For example, as shown in FIG14 , the arrangement of the crack detection line PCD in the display panel 04 can be similar to that of the display panel 01 shown in FIG7 . The source test line ST in the display panel 04 does not pass through the dummy region 203, and the source test line ST avoids the first spacer region G1. For example, in the first direction X, a portion of the source test line ST is located on one side of the dummy region 203, and a gap exists between the source test line ST and the dummy region 203. For example, in the first direction X, the minimum distance between the source test line ST and the dummy region 203 is smaller than the minimum distance between the source test line ST and the input region 201, and a gap exists between the source test line ST and the first spacer region G1. Consequently, the source test line ST can avoid the first spacer region G1, thereby improving stress distribution within the first spacer region G1 and reducing the risk of cracks on the source test line ST within the first spacer region G1.

[0129] For example, as shown in Figures 14 and 15 , one end of a source test line ST is connected to one end of one of the output bumps BP2 in the first row of output bumps BP2 in the output region 202, away from the dummy region 203. The source test line ST is then extended to a location away from the wiring region 200 for routing. For example, one end of the source test line ST is connected to one end of the dummy region 203 of one of the output bumps BP2 in the first row of output bumps BP2. The source test line ST then extends in a first direction X toward a region away from the test pad AT, away from the wiring region 200. Furthermore, the source test line ST extends along a second direction Y. This arrangement facilitates connection of one end of the source test line ST to the output bump BP2, avoids overlap between the source test line ST and other output bumps BP2 in the output region 202, reduces the risk of signal crosstalk, and facilitates layout.

[0130] FIG16 is a schematic diagram of a wiring area of ​​another display panel provided in an embodiment of the present disclosure; FIG17 is a schematic diagram of the overall structure of the display panel corresponding to FIG16 .

[0131] For example, as shown in FIG16 , the difference between the display panel 05 and the display panel 04 in FIG14 is that the wiring method of the source test line ST is different, and the rest of the structures are the same or substantially the same. For details, please refer to the relevant description of the above embodiment, which will not be repeated here.

[0132] For example, as shown in FIG16 , one end of the source test line ST can be connected to one end of one of the output bumps BP2 in the Mth row of output bumps BP2, which is near the dummy region 203. A second spacer G2 is provided between the multiple output bumps BP2 and the multiple dummy bumps BP3, and the source test line ST passes through the second spacer G2. For example, one end of the source test line ST can be connected to one of the output bumps BP2 in the Mth row of output bumps BP2, and connected to the end of the output bump BP2 near the dummy region 203. This configuration helps avoid overlap between the source test line ST and other output bumps BP2 in the output region 202, thereby reducing the risk of signal crosstalk and facilitating layout.

[0133] For example, as shown in Figures 16 and 17, the source test line ST extends along the edge of the output area 202 near the dummy area 203, passes through the second spacer area G2, then extends to one side of the dummy area 203, and then extends along the second direction Y, ultimately connecting to the connection bump of the display panel 05. Thus, the source test line ST can avoid the dummy area 203 and the first spacer area G1, thereby improving the stress distribution in the first spacer area G1 and reducing the problem of the source test line ST being broken in the first spacer area G1.

[0134] For example, as shown in FIG16 , multiple signal lines 50 in the display panel 05 do not pass through the first spacing area G1, that is, any signal line 50 does not pass through the first spacing area G1. This can improve the stress distribution in the first spacing area G1 and reduce the problem of any signal line 50 breaking in the first spacing area G1.

[0135] For example, for the display panels shown in Figures 15 and 17, after the source test line ST is led out from the output area 202, it can be connected to the connection protrusion of the display panel after avoiding the dummy area 203, and the position of the connection protrusion can refer to the connection protrusion BP4 in Figure 13, that is, it is located on the side of the input area 201 away from the output area 202.

[0136] FIG18 is a schematic diagram of the overall structure of another display panel provided by an embodiment of the present disclosure; FIG19 is a schematic diagram of the overall structure of another display panel provided by an embodiment of the present disclosure.

[0137] For example, as shown in FIG18 , the plurality of signal lines 50 further include a plurality of first signal lines 510. At least portions of the first signal lines 510 extend along the first direction X, and the first signal lines 510 are located between the input region 201 and the output region 202. For example, the first signal lines 510 pass through the dummy region 203. For example, the first signal lines 510 pass through the region between two adjacent dummy bumps BP2. For example, the first signal lines 510 can be any one of the signal lines S1, S2, the initialization signal line VIN3, the initialization signal line VIN2, the initialization signal line VIN1, the signal line S3, the signal line S4, the signal line S5, the signal line S6, the signal line S7, and the signal line S8 shown in FIG11 .

[0138] For example, as shown in FIG18 , the first signal line 510 includes a first stacked structure in a direction perpendicular to the substrate. For example, the first stacked structure may be a Ti / Al / Ti structure in a direction perpendicular to the substrate, but the embodiments of the present disclosure are not limited thereto. The first signal line 510 may have such a structure to reduce the resistance per unit area of ​​the first signal line 510. For example, the resistance per unit area of ​​the first signal line 510 using the first stacked structure may be 0.004 to 0.006 Ω / μm. 2 , such as 0.005Ω / μm 2 , thereby facilitating reduction of the load of the first signal line 510. In the embodiment of the present disclosure, the unit area resistance of a signal line refers to the resistance per square micrometer of the projected area of ​​the signal line on the substrate.

[0139] For example, as shown in FIG18 , the plurality of signal lines 50 further include a plurality of second signal lines 520. At least a portion of the second signal lines 520 extends along the second direction Y. The plurality of second signal lines 520 are located on one side of the wiring region 200 in the first direction X, and one end of the second signal line 520 is connected to a connection bump BP4 in the display panel. For example, one end of the second signal line 520 can be connected to the first signal line 510, and the other end of the second signal line 520 can be connected to the connection bump BP4. For example, the first signal line 510 can be connected to the second signal line 520 via a via extending through the insulating layer.

[0140] For example, as shown in FIG18 , the second signal line 520 includes a second stacked structure in a direction perpendicular to the base substrate. For example, the second stacked structure may also be a Ti / Al / Ti structure in a direction perpendicular to the base substrate, but the embodiments of the present disclosure are not limited thereto. For example, the second stacked structure may also be the same as the first stacked structure, or the second stacked structure may also be different from the first stacked structure. The second signal line 520 adopts such a structure to reduce the unit area resistance of the second signal line 520. For example, the unit area resistance of the second signal line 520 using the second stacked structure may be 0.004 to 0.006 Ω / μm. 2 , such as 0.005Ω / μm 2 , which is beneficial to reducing the load of the second signal line 520.

[0141] For example, as shown in FIG18 , a display panel may include a base substrate, and a first conductive pattern 610, a second conductive pattern 620, a third conductive pattern 630, a fourth conductive pattern 640, and a fifth conductive pattern 650 sequentially disposed on the base substrate, wherein the first conductive pattern 610 is closer to the base substrate than the second conductive pattern 620. For example, the second conductive pattern 620 is located between the first conductive pattern 610 and the third conductive pattern 630. For example, an inorganic insulating layer may be disposed between the first conductive pattern 610 and the second conductive pattern 620. For example, the inorganic insulating layer may be a passivation layer, but is not limited thereto.

[0142] For example, as shown in FIG18 , the first conductive pattern 610 and the second conductive pattern 620 may be made of the same material, such as molybdenum. For example, the third conductive pattern 630 , the fourth conductive pattern 640 , and the fifth conductive pattern 650 may be made of the same material, such as a Ti / Al / Ti structure, but are not limited thereto.

[0143] For example, as shown in FIG. 18 , the first signal line 510 may be located in the third conductive pattern 630 , but embodiments of the present disclosure are not limited thereto.

[0144] For example, as shown in FIG19 , the difference between the display panel 07 and the display panel 06 in FIG18 is that the wiring method of the first signal line 510 is different, and the rest of the structures are the same or roughly the same. For details, please refer to the relevant description of the above embodiment, which will not be repeated here.

[0145] For example, as shown in FIG. 19 , the first signal line 510 may also be located in the fifth conductive pattern 650 to reduce the resistance per unit area of ​​the first signal line 510 .

[0146] For example, as shown in FIG. 18 and FIG. 19 , the second signal line 520 may be located in the fourth conductive pattern 640 to reduce the resistance per unit area of ​​the second signal line 520 .

[0147] FIG20 is a schematic diagram of a partial structure of a display panel.

[0148] For example, as shown in FIG20 , compared with the display panel 02 shown in FIG8 , the display panel 08 further includes an organic pattern 700 , and the remaining structures are the same or substantially the same, and are not described again herein.

[0149] For example, as shown in FIG. 20 , the organic pattern 700 includes an opening 750 that exposes the wiring region 200. The organic pattern 700 is removed within the region defined by the opening 750. For example, the wiring region 200 includes a flat region T1, and no support structure (e.g., dummy bump BP3) is provided in the flat region T1. Therefore, the strain and pressure in the flat region T1 are relatively high, making it prone to defects such as cracks.

[0150] FIG21 is a schematic diagram of a partial structure of another display panel provided in an embodiment of the present disclosure; FIG22 is a schematic diagram of a supporting structure provided in an embodiment of the present disclosure.

[0151] For example, as shown in FIG21 , compared with the display panel 08 shown in FIG20 , the display panel 09 further includes a supporting structure, and the remaining structures are the same or substantially the same, and are not described again here.

[0152] 21 , the display panel 09 further includes a support structure 800 located in the opening 750, and the support structure 800 includes an organic material. For example, the support structure 800 is located in the flat region T1, thereby supporting the structures located in the region and reducing the strain and pressure in the flat region T1.

[0153] For example, as shown in FIG22 , the organic pattern 800 may include a first organic pattern 710, a second organic pattern 720, and a third organic pattern 730. The first organic pattern 710, the second organic pattern 720, and the third organic pattern 730 are sequentially stacked in a direction perpendicular to the base substrate, with the first organic pattern 710 being closer to the base substrate than the second organic pattern 720. For example, the second organic pattern 720 is located between the first organic pattern 710 and the third organic pattern 730. For example, the first organic pattern 710, the second organic pattern 720, and the third organic pattern 730 may include the same insulating material.

[0154] For example, as shown in FIG22 , the first organic pattern 710 includes a first opening 701, the second organic pattern 720 includes a second opening 702, and the third organic pattern 730 includes a third opening 703. For example, the first opening 701, the second opening 702, and the third opening 703 include overlapping areas. The display panel 09 includes an opening area 750 exposed by the first opening 701, the second opening 702, and the third opening 703, and the display panel 09 also includes a plurality of support structures 800 located in the opening area 750. For example, the support structure 800 is located in the flat area T1, so that it can support the structure located in the area to reduce the strain and pressure of the flat area T1. For example, the support structure 800 can be made of the same material as the first organic pattern 710, the second organic pattern 720, and the third organic pattern 730, and the embodiments of the present disclosure are not limited to this.

[0155] For example, as shown in FIG. 21 and FIG. 22 , the support structure 800 is located between the first signal line 510 and the input bump BP1 . For example, the support structure 800 may be located between the crack detection line PCD and the input bump BP1 .

[0156] For example, as shown in FIG22 , the support structure 800 includes a first organic structure 810, a second organic structure 820, and a third organic structure 830, which are sequentially stacked along a direction perpendicular to the base substrate. The first organic structure 810 is located within the first organic pattern 710, the second organic structure 820 is located within the second organic pattern 720, and the third organic structure 830 is located within the third organic pattern 730. For example, the first organic structure 810 is part of the first organic pattern 710, the second organic structure 820 is part of the second organic pattern 720, and the third organic structure 830 is part of the third organic pattern 730. Consequently, the first organic structure 810, the second organic structure 820, and the third organic structure 830 are no longer required to form the first organic structure 810, the second organic structure 820, and the third organic structure 830, thereby simplifying the fabrication process of the first organic structure 810, the second organic structure 820, and the third organic structure 830.

[0157] For example, as shown in FIG22 , the orthographic projection of the first organic structure 810 on the substrate falls within the orthographic projection of the second organic structure 820 on the substrate, and the orthographic projection of the second organic structure 820 on the substrate falls within the orthographic projection of the third organic structure 830 on the substrate. For example, the orthographic projection area of ​​the second organic structure 820 can be larger than the orthographic projection area of ​​the first organic structure 810, and the orthographic projection area of ​​the third organic structure 830 can be larger than the orthographic projection area of ​​the second organic structure 820.

[0158] For example, as shown in FIG22 , the second organic structure 820 may cover the first organic structure 810, and the third organic structure 830 may cover the second organic structure 820. For example, the outer surface of the first organic structure 810 may be completely covered by the second organic structure 820, and the outer surface of the second organic structure 820 may be completely covered by the third organic structure 830. This arrangement facilitates patterning of the second organic structure 820 and the third organic structure 830, simplifying the fabrication process of the support structure 800.

[0159] An embodiment of the present disclosure further provides another display panel.

[0160] As shown in FIG7 , the display panel 01 includes a display area 100 and a peripheral area 300 surrounding the display area 100. For example, the display area 100 includes a plurality of sub-pixels SP arranged in an array along a first direction X and a second direction Y. For example, the embodiments of the present disclosure utilize an example in which the peripheral area 300 surrounds the display area 100, but the invention is not limited thereto. The peripheral area 300 may be located on at least one side of the display area 100. For example, the peripheral area 300 may be located on at least one of the left side, right side, top side, and bottom side of the display area 100.

[0161] As shown in Figure 7 , the peripheral region 300 includes a wiring region 200, and the wiring region 200 is located on one side of the display region 100. That is, the wiring region 200 is located on one side of the plurality of sub-pixels SP. Figure 7 uses the example of the wiring region 200 being located on the lower side of the display region 100. The wiring region 200 is part of the peripheral region 300. For clarity, Figure 7 does not show all structures and wiring of the display panel 01.

[0162] 7 , the display panel 01 further includes a base substrate BS and a plurality of signal lines 50 located on the base substrate BS. For example, the plurality of signal lines 50 are located in the peripheral area 300. For example, the signal lines 50 can be connected to scan lines located in the display area 100.

[0163] For example, as shown in FIG7 , the plurality of signal lines 50 include a crack detection line PCD and a source test line ST. The crack detection line PCD is located in the peripheral area 300 and surrounds the display area 100. The crack detection line PCD is configured to detect cracks in the display panel 01, and the source test line ST is configured to perform a source test.

[0164] As shown in FIG7 , the wiring area 200 includes an input area 201 and a dummy area 203. The dummy area 203 and the input area 201 are sequentially arranged in a direction away from the display area 100. For example, the input area 201 and the dummy area 203 are sequentially arranged in the second direction Y, and the dummy area 203 is located on a side of the input area 201 closer to the display area 100. The input area 201 has a plurality of input bumps BP1, and the dummy area 203 has a plurality of dummy bumps BP3.

[0165] For example, as shown in FIG7 , the wiring region 200 further includes an output region 202. The output region 202 is located on a side of the dummy region 203 away from the input region 201 and includes a plurality of output bumps BP2. The plurality of input bumps BP1 and the plurality of output bumps BP2 on the display panel 01 are configured to connect to the integrated circuit 88. For example, the dummy bumps BP3 can balance stress during the bonding process of the integrated circuit 88. The display panel 01 further includes a plurality of connection bumps BP4 located on a side of the wiring region 200 away from the display region 100. The plurality of connection bumps BP4 are configured to connect to the flexible circuit board 99.

[0166] For example, as shown in FIG7 , the display panel 01 includes multiple conductive structures and multiple connection structures, such as bumps. For example, the multiple conductive structures may include an input bump BP1, a dummy bump BP3, and an output bump BP2. The multiple connection structures may include a connection bump BP4. FIG7 also shows an integrated circuit 88 and a flexible circuit board 99. For example, the integrated circuit 88 and the flexible circuit board 99 may be separately bonded to the display panel. For example, the integrated circuit 88 may be bonded to the conductive structures on the display panel 01, such as the input bump BP1 and the output bump BP2. For example, the flexible circuit board 99 may be bonded to the connection structures on the display panel, such as the connection bump BP4. For example, the bumps on the display panel 01 bonded to the flexible circuit board 99 may be connected to the bumps on the display panel 01 bonded to the integrated circuit 88. For example, the integrated circuit 88 may be a 28nm IC chip, which has a smaller size and lower power consumption.

[0167] For example, as shown in Figure 7, the two ends of the crack detection line PCD can be connected to connection bumps BP4, which are then connected to two input bumps BP1. For example, a resistance can be detected to determine whether the crack detection line PCD is broken. If the crack detection line PCD is intact, its resistance is normal. If the crack detection line PCD is broken, its resistance will be very high.

[0168] Figure 7 also shows data lines DL. Data lines DL are configured to provide data signals, such as data voltages, to subpixels SP. The number of data lines DL is not limited to that shown in Figure 7 and can be determined as needed. One end of a source test line ST is connected to a data line DL via output bump BP1, and the other end of the source test line ST is connected to a connection structure BP4. Figure 7 shows two source test lines ST, which are respectively connected to connection bumps 721 and 722. Connection bumps 721 and 722 can be connected to conductive structures on the flexible printed circuit board 99.

[0169] For example, as shown in Figure 7, the source test line ST is primarily used to test whether the data line DL connected to it is functioning properly. For example, the waveform on the data line DL connected to it can be tested via the source test line ST. If the display panel displays an abnormality, a source test can be performed to determine whether a problem with the data line DL is causing the display abnormality.

[0170] As shown in FIG7 , a first spacer G1 is provided between the plurality of input bumps BP1 and the plurality of dummy bumps BP3. At most one of the crack detection line PCD and the source test line ST passes through the first spacer G1. That is, one of the crack detection line PCD and the source test line ST may pass through the first spacer G1. For example, neither the crack detection line PCD nor the source test line ST passes through the first spacer G1.

[0171] In the embodiment of the present disclosure, the signal line (eg, the crack detection line PCD or the source test line ST) not passing through the first spacer G1 indicates that the signal line avoids the first spacer G1 .

[0172] This arrangement effectively improves the stress distribution within the first spacer region G1 and reduces the maximum strain within the first spacer region G1, thereby alleviating or preventing cracks in the inorganic insulating layer during the integrated circuit bonding process. This, in turn, avoids defects caused by cracks in the inorganic insulating layer. For example, cracks in the inorganic insulating layer can prevent the display panel crack detection line from breaking, thereby preventing the display panel from failing crack detection.

[0173] For example, as shown in FIG7 , at least some of the plurality of input bumps BP1 are arranged in a row along the first direction X, and at least some of the plurality of dummy bumps BP3 are arranged in a column along the second direction Y. For example, in some embodiments, at least some of the plurality of input bumps BP1 may also be arranged in multiple rows along the first direction X, and at least some of the plurality of dummy bumps BP3 may also be arranged in multiple columns along the second direction Y.

[0174] For example, as shown in Figure 7, the plurality of connection bumps BP4 include a first connection bump BP41 and a second connection bump BP42, and the two ends of the crack detection line PCD are connected to the first connection bump BP41 and the second connection bump BP42, respectively. The wiring area 200 is located within the area surrounded by the crack detection line PCD, and the wiring area 200 is spaced apart from the crack detection line PCD.

[0175] For example, as shown in FIG7 , in the first direction X, the first connection bump BP41 and the second connection bump BP42 are respectively located on both sides of the wiring area 200. In the second direction Y, the first connection bump BP41 and the second connection bump BP42 are both located on a side of the wiring area 200 away from the display area 100. For example, the first connection bump BP41 and the second connection bump BP42 do not overlap with the wiring area 200. For example, the crack detection line PCD surrounds the wiring area 200.

[0176] With such a setting, the crack detection line PCD can avoid the wiring area 200, thereby avoiding the first spacing area G1 in the wiring area 200, so that the crack detection line PCD does not pass through the first spacing area G1, thereby reducing the strain value in the first spacing area G1, reducing the NG problem of crack detection of the display panel 01, and avoiding defects caused by cracks in the inorganic insulating layer in the display panel 01.

[0177] For example, as shown in Figure 7, the multiple connection bumps BP4 in the display panel 01 also include a third connection bump BP43 and a fourth connection bump BP44, the third connection bump BP43 is connected to the first connection bump BP41, the fourth connection bump BP44 is connected to the second connection bump BP44, the third connection bump BP43 and the fourth connection bump BP44 are respectively connected to the two input bumps BP1 in the input area 201, so that the crack detection line PCD can be electrically connected to the two input bumps BP1 in the input area 201.

[0178] 7 , the source test line ST may not pass through the first isolation region G1 . For example, the source test line ST may avoid the first isolation region G1 .

[0179] For example, as shown in FIG12 , the plurality of dummy bumps BP3 may include a first dummy bump BP31 and a second dummy bump BP32 , wherein the first dummy bump BP31 and the second dummy bump BP32 are adjacent to each other in the second direction Y, and the source test line ST passes through the area between the first dummy bump BP31 and the second dummy bump BP32 . Thus, the source test line ST can bypass the first spacer G1 to reduce the maximum strain value of the first spacer G1 and reduce the problem of NG in crack detection of the display panel 03 .

[0180] For example, as shown in FIG12 , a plurality of output bumps BP2 are arranged in a matrix of M rows and N columns along a first direction X and a second direction Y. The matrix includes M rows of output bumps BP2 and N columns of output bumps BP2. For example, the output bump BP2 in the i-th row is further away from the dummy region 203 than the output bump BP2 in the i+1-th row, where N and M are both positive integers and i is less than or equal to M-1. For example, the output bump BP2 in the first row is further away from the dummy region 203 than the output bump BP2 in the second row. For example, the output bump BP2 in the M-th row is closer to the dummy region 203 than the output bump BP2 in the M-1-th row.

[0181] For example, as shown in Figures 14 and 15, one end of the source test line ST is connected to one end of one of the multiple output bumps BP2 in the first row of output bumps BP2 in the output area 202 away from the dummy area 203, and the source test line ST extends to a position away from the wiring area 200 for wiring.

[0182] For example, as shown in Figure 16, one end of the source test line ST can be connected to one end of one of the multiple output bumps BP2 in the M-th row of output bumps BP2 close to the dummy area 203, and a second spacing area G2 is provided between the multiple output bumps BP2 and the multiple dummy bumps BP3, and the source test line ST passes through the second spacing area G2.

[0183] Therefore, the source test line ST can avoid the first isolation region G1 to improve stress distribution in the first isolation region G1 and reduce the problem of the source test line ST being broken in the first isolation region G1.

[0184] The various components or structures in the embodiments of the present disclosure may be arranged in order of appearance, without being restricted to the names with ordinal numbers given in the specification.

[0185] Embodiments of the present disclosure further provide a display device comprising any of the above-described display panels. For example, the display panel may be a foldable display panel, and the display device may be a foldable display device. Of course, the display panel may also be a non-foldable display panel, and the display device may also be a non-foldable display device.

[0186] For example, the display device includes an OLED or a product including an OLED. For example, the display device includes any product or component with a display function, such as a television, a digital camera, a mobile phone, a watch, a tablet computer, a laptop computer, a navigation system, etc., which includes the above-mentioned display panel.

[0187] It should be noted that, for the sake of clarity, the thickness of layers or regions in the drawings used to describe the embodiments of the present disclosure are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or intervening elements may be present.

[0188] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel, comprising: a display area and a peripheral area surrounding the display area, the peripheral area including a wiring area located on one side of the display area; wherein, the wiring area has an input area and a dummy area, the dummy area and the input area are arranged in sequence in a direction away from the display area, the input area has a plurality of input protrusions, and the dummy area has a plurality of dummy protrusions, the display panel further includes a substrate and a plurality of signal lines located on the substrate, there is a first spacer area between the plurality of input protrusions and the plurality of dummy protrusions, and at most one of the plurality of signal lines passes through the first spacer area.

2. The display panel according to claim 1, wherein one of the plurality of signal lines passes through the first spacer area.

3. The display panel according to claim 1 or 2, wherein, the plurality of signal lines include a crack detection line and a source test line, the crack detection line is located in the peripheral area, the crack detection line is configured to detect cracks in the display panel, the source test line is configured to perform a source test, and one of the crack detection line and the source test line passes through the first spacer area.

4. The display panel according to claim 3, wherein, one of the crack detection line and the source test line includes an extension portion, the extension portion passes through the first spacer area, and the minimum distance between the extension portion and the input area is less than the minimum distance between the extension portion and the dummy area.

5. The display panel according to claim 4, wherein, the minimum distance between the extension portion and the input area is 14 to 17 micrometers.

6. The display panel according to claim 1, wherein, the wiring area further includes an output area located on a side of the dummy area away from the input area, the output area has a plurality of output protrusions, the plurality of input protrusions and the plurality of output protrusions on the display panel are both configured to be connected to an integrated circuit, the display panel further includes a plurality of connection protrusions located on a side of the wiring area away from the display area, the plurality of connection protrusions are configured to be connected to a flexible circuit board, at least a part of the plurality of input protrusions are arranged in a row in a first direction, at least a part of the plurality of dummy protrusions are arranged in a column in a second direction, both the first direction and the second direction are parallel to the substrate, and the first direction intersects the second direction.

7. The display panel according to claim 6, wherein, none of the plurality of signal lines passes through the first spacer area.

8. The display panel according to claim 7, wherein, the plurality of signal lines include a crack detection line and a source test line, the crack detection line is located in the peripheral area, the crack detection line is configured to detect cracks in the display panel, the source test line is configured to perform a source test line, the plurality of connection protrusions include a first connection protrusion and a second connection protrusion, and two end portions of the crack detection line are respectively connected to the first connection protrusion and the second connection protrusion. The wiring area is located within the area surrounded by the crack detection line, and the wiring area is spaced apart from the crack detection line.

9. The display panel according to claim 8, wherein, the plurality of connection protrusions further include a third connection protrusion and a fourth connection protrusion, the third connection protrusion is connected to the first connection protrusion, the fourth connection protrusion is connected to the second connection protrusion, and the third connection protrusion and the fourth connection protrusion are respectively connected to two of the input protrusions in the input area.

10. The display panel according to claim 9, further comprising a first test pad and a second test pad, the first test pad is connected to the first connection protrusion, the second test pad is connected to the second connection protrusion, and the first test pad and the second test pad are configured to be connected to a test component for crack detection.

11. The display panel according to any one of claims 7-10, wherein, the plurality of dummy protrusions include a first dummy protrusion and a second dummy protrusion, the first dummy protrusion and the second dummy protrusion are adjacent to each other in the second direction, and the source test line passes through the area between the first dummy protrusion and the second dummy protrusion.

12. The display panel according to claim 11, wherein, the first dummy protrusion is located at the end of the dummy area close to the input area.

13. The display panel according to any one of claims 7-10, wherein, the plurality of output protrusions are arranged in a matrix of M rows and N columns along the first direction and the second direction, the matrix includes M rows of output protrusions and N columns of output protrusions, the output protrusions in the i-th row are farther from the dummy area than the output protrusions in the (i + 1)-th row, both N and M are positive integers, and i is less than or equal to M - 1, one end of the source test line is connected to one of the plurality of output protrusions, and the other end of the source test line is connected to one of the plurality of connection protrusions in the display panel.

14. The display panel according to claim 13, wherein, the source test line does not pass through the dummy area, and the source test line avoids the first spacer area.

15. The display panel according to claim 14, wherein, the one end of the source test line is connected to one of the plurality of output protrusions in the first row of output protrusions at the end far from the dummy area and extends to a position far from the wiring area for wiring.

16. The display panel according to claim 14, wherein, the one end of the source test line is connected to one of the plurality of output protrusions in the M-th row of output protrusions at the end close to the dummy area, there is a second spacer area between the plurality of output protrusions and the plurality of dummy protrusions, and the source test line passes through the second spacer area.

17. The display panel according to any one of claims 6-16, wherein, the plurality of signal lines further include a plurality of first signal lines, at least a part of the first signal lines extends along the first direction, and the first signal lines are located between the input area and the output area, and the first signal lines include a first stacked structure in a direction perpendicular to the substrate.

18. The display panel according to claim 17, wherein, the display panel includes a substrate, and a first conductive pattern, a second conductive pattern, a third conductive pattern, a fourth conductive pattern, and a fifth conductive pattern sequentially disposed on the substrate, and the first conductive pattern is closer to the substrate than the second conductive pattern, the plurality of signal lines further includes a plurality of second signal lines, at least a part of the second signal lines extends along the second direction, the plurality of second signal lines are located on one side of the wiring area in the first direction, and one end of the second signal line is connected to the connection protrusion in the display panel, the first signal line is located in the third conductive pattern or in the fifth conductive pattern, and the second signal line is located in the fourth conductive pattern.

19. The display panel according to claim 18, wherein, the second signal line includes a second stacked structure in a direction perpendicular to the substrate.

20. The display panel according to claim 19, wherein, the first stacked structure and / or the second stacked structure includes a Ti / Al / Ti structure.

21. The display panel according to any one of claims 17-20 further includes an organic pattern, and the organic pattern includes an opening, wherein, the display panel further includes a support structure located in the opening, and the support structure includes an organic material.

22. The display panel according to claim 21, the organic pattern includes a first organic pattern, a second organic pattern, and a third organic pattern, the first organic pattern, the second organic pattern, and the third organic pattern are sequentially stacked in a direction perpendicular to the substrate, and the first organic pattern is closer to the substrate than the second organic pattern, the first organic pattern includes a first opening, the second organic pattern includes a second opening, the third organic pattern includes a third opening, and the display panel includes an opening area exposed by the first opening, the second opening, and the third opening, wherein, the display panel further includes a plurality of the support structures located in the opening area.

23. The display panel according to claim 22, the support structure is located between the first signal line and the input protrusion, the support structure includes a first organic structure, a second organic structure, and a third organic structure sequentially stacked in a direction perpendicular to the substrate, the first organic structure is located in the first organic pattern, the second organic structure is located in the second organic pattern, and the third organic structure is located in the third organic pattern.

24. The display panel according to claim 23, a positive projection of the first organic structure on the substrate falls within a positive projection of the second organic structure on the substrate, and a positive projection of the second organic structure on the substrate falls within a positive projection of the third organic structure on the substrate.

25. The display panel according to claim 23 or 24, wherein the second organic structure covers the first organic structure, and the third organic structure covers the second organic structure.

26. A display panel, comprising: a display area and a peripheral area surrounding the display area, the peripheral area including a wiring area located on one side of the display area; the display panel further includes a substrate and a plurality of signal lines located on the substrate, the plurality of signal lines including a crack detection line and a source test line, the crack detection line being located in the peripheral area and surrounding the display area, the crack detection line being configured to detect cracks in the display panel, and the source test line being configured to perform a source test, wherein the wiring area has an input area and a dummy area, the dummy area and the input area are arranged in sequence in a direction away from the display area, the input area has a plurality of input protrusions, and the dummy area has a plurality of dummy protrusions, a first spacer area is provided between the plurality of input protrusions and the plurality of dummy protrusions, and at most one of the crack detection line and the source test line passes through the first spacer area.

27. The display panel according to claim 26, wherein, the wiring area further includes an output area located on a side of the dummy area away from the input area, the output area having a plurality of output protrusions, the plurality of input protrusions and the plurality of output protrusions on the display panel are both configured to be connected to an integrated circuit, the display panel further includes a plurality of connection protrusions located on a side of the wiring area away from the display area, and the plurality of connection protrusions are configured to be connected to a flexible circuit board, at least a part of the plurality of input protrusions is arranged in a row in a first direction, at least a part of the plurality of dummy protrusions is arranged in a column in a second direction, both the first direction and the second direction are parallel to the substrate, and the first direction intersects the second direction.

28. The display panel according to claim 27, wherein, the plurality of connection protrusions include a first connection protrusion and a second connection protrusion, and two end portions of the crack detection line are respectively connected to the first connection protrusion and the second connection protrusion, the wiring area is located within an area surrounded by the crack detection line, and the wiring area is spaced apart from the crack detection line.

29. The display panel according to claim 26 or 28, wherein, the source test line does not pass through the dummy area, and the source test line avoids the first spacer area.

30. A display device, including the display panel according to any one of claims 1-29.

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