Large-scale array radar radio frequency system design method

Abstract

The invention discloses a large-scale array radar radio frequency system design method, and the method comprises the steps: carrying out the system demand analysis; then, a microstrip unit antenna structure suitable for a large-scale array distribution configuration and based on feed port transition optimization, a power distribution network suitable for large-scale array radar multi-radio-frequency subsystem cascading and a clock routing structure suitable for large-scale array radar multi-radio-frequency subsystem cascading are constructed; then, a parallel subsystem cascade coherent synchronization scheme and a series subsystem cascade coherent synchronization scheme are provided; and finally, the schemes are selected according to actual conditions to construct the large-scale array radar radio frequency system based on cascade of the multiple radio frequency subsystems. Compared with an existing scene monitoring array radar system, under the condition that the number of radar receiving and transmitting channels is limited, a large-scale virtual array can be formed in the azimuth direction, the radar gain and the azimuth angle resolution are remarkably improved, and a low-cost scheme is provided for a scene monitoring radar with high-resolution imaging capacity.

Description

Technical Field

[0001] The present invention belongs to the technical field of radar radio frequency systems, and particularly relates to a design method for a large-scale array radar radio frequency system. Background Art

[0002] Scene surveillance radars are widely used in applications such as geological disaster monitoring and airport ground traffic management. Existing scene surveillance array radars are difficult to achieve high angular resolution due to limited numbers of transceiver channels, and cannot meet the high-resolution imaging requirements in practical applications. Directly increasing the number of transceiver channels will result in high hardware costs.

[0003] The literature "W.Zhang, N.Li, C.Li, D.Dong, C.Wang and E.Kasper, 'A Two-Chip-Cascaded 4D Millimeter-Wave Imaging Radar Aiming for Automotive SLAM,' 2024 15th Global Symposium on Millimeter-Waves & Terahertz (GSMM), Hong Kong, 2024, pp.252-254." proposed a two-chip cascaded radar solution, which combines sparse array technology and MIMO principle to form 48 virtual channels. However, the cascading scale of this radar is small and the angular resolution is low. The literature "W.Peng, W.Jin and W.Zou, 'Design of MIMO Radar Using Cascaded Millimeter-Wave Sensors,' 2022 International Conference on Microwave and Millimeter Wave Technology (ICMMT), Harbin, China, 2022, pp.1-3." proposed a MIMO radar design based on cascaded millimeter-wave sensors, which can form a 6×32 virtual array. However, the number of virtual array elements formed by this radar in the azimuth direction is small and the angular resolution is low. The literature "Q.Guo, L.Yang, T.Xu, T.Hu, Q.Deng and Z.Xu, 'Millimeter-wave MIMO imaging radar with an ultra-high angular resolution of 0.6 degree,' 2021 13th Global Symposium on Millimeter-Waves & Terahertz (GSMM), Nanjing, China, 2021, pp.1-3." proposed a millimeter-wave MIMO radar solution based on the cascading of six chips, which can form 192 virtual array elements and achieve a high angular resolution of 0.6°. However, the physical antenna aperture size of this radar is large and the cost is high.

[0004] In summary, the existing technical solutions have the problem of difficulty in balancing high angular resolution and physical size. Increasing the number of physical channels to improve the resolution will lead to an increase in the size of the RF board and the hardware cost, and it is difficult to balance performance and cost. Summary of the Invention

[0005] To solve the above technical problems, the present invention proposes a design method for a large-scale array radar RF system, which forms a large-scale virtual array in the azimuth direction under the condition of limited number of radar transceiver channels, significantly improves the radar gain and azimuth angle resolution, and provides a low-cost solution for a scene surveillance radar with high-resolution imaging ability.

[0006] The technical solution adopted by the present invention is as follows: a design method for a large-scale array radar RF system, and the specific steps are as follows:

[0007] S1. Conduct system requirement analysis to determine the scale and array index of a large-scale array radar RF system based on cascading multiple RF subsystems;

[0008] Among them, it is set that the system includes a total of M transmit channels and N receive channels, and the system includes 1 master RF subsystem master and P - 1 slave RF subsystems slave.

[0009] S2. Construct an array distribution configuration suitable for a large-scale array radar;

[0010] S3. Construct a microstrip unit antenna structure based on optimized feed port transition;

[0011] S4. Construct a power distribution network suitable for cascading multiple RF subsystems of a large-scale array radar;

[0012] S5. Construct a clock routing structure suitable for cascading multiple RF subsystems of a large-scale array radar;

[0013] S6. Based on steps S1 - S5, construct a parallel subsystem cascading coherent synchronization scheme;

[0014] S7. Based on steps S1 - S5, construct a series subsystem cascading coherent synchronization scheme;

[0015] S8. Based on steps S1 - S7, construct a large-scale array radar RF system based on cascading multiple RF subsystems;

[0016] Among them, the system selects a parallel subsystem cascading coherent synchronization scheme or a series subsystem cascading coherent synchronization scheme according to the actual situation.

[0017] Further, the specific content of step S2 is as follows:

[0018] Construct an array distribution configuration suitable for large-scale array radars. Set all transmitting antenna elements to be horizontally equally spaced, and the spacing between the phase centers of adjacent transmitting antennas is Nλ / 4. All receiving antenna elements are on the same horizontal line, and the receiving antennas are divided into two groups, each group containing N / 2 receiving antenna elements. The spacing between the phase centers of the receiving antennas within each group is λ / 2, and the spacing between the phase centers of the receiving antennas between the two groups is (M - 1)Nλ / 4.

[0019] Among them, λ represents the vacuum wavelength of the electromagnetic wave. And through orthogonal waveform design, the array distribution configuration forms a total of MN virtual channels.

[0020] Furthermore, the specific steps of step S3 are as follows:

[0021] Set the microstrip unit antenna structure to include a K-element resonant microstrip series-fed antenna. The resonant length of each element The initial width of each element The spacing d between each element is λ g / 2, and the final width of each element is readjusted according to the Chebyshev distribution.

[0022] Among them, c represents the speed of light in vacuum, f c represents the operating frequency, Δl represents the extension length of the microstrip antenna element caused by the edge effect, ε e represents the effective dielectric constant; ε r represents the relative dielectric constant; λ g represents the wavelength of the electromagnetic wave in the dielectric substrate.

[0023] The microstrip unit antenna structure includes a transition optimization structure suitable for the feeding port of the resonant microstrip series-fed antenna. A microstrip line transition section is introduced between the pin of the RF output end and the antenna feeding port. Set the spacing g1 between the pin of the RF output end and the ground plane to be greater than the width w of the coplanar waveguide feeder f , the width w of the microstrip line transition section m is wider than the width w of the coplanar waveguide feeder f , the spacing g2 between the feeder and the ground plane is less than the width w of the coplanar waveguide feeder f , suppressing the impedance discontinuity caused by the sudden change in the ground plane spacing near the pin of the RF output end, and meeting the 50Ω characteristic impedance requirement. Periodic vias are arranged around the feeder to reduce the insertion loss and surface wave loss. At the same time, the feeders of the transmitting and receiving antennas are made of equal length to ensure equal-amplitude and in-phase feeding of the transmitting and receiving antennas.

[0024] Furthermore, the specific steps of step S4 are as follows:

[0025] The power distribution network structure includes a power divider for equal power distribution, which is respectively connected to the local oscillator signal output port of the main radio frequency subsystem and the local oscillator signal input ports of P - 1 slave radio frequency subsystems, and performs equal - length processing on the local oscillator signal link to ensure the synchronization of the local oscillator signal link.

[0026] In the power distribution network, the radio frequency board adopts a multi - layer hybrid - press PCB design. The transceiver antenna array is located on the top layer, and the local oscillator signal transmission line is located on the third layer. Back - drilling is performed on the vias at the input and output ports of the power divider to remove the via stubs from the bottom layer to the third layer.

[0027] Among them, the number of layers of the radio frequency board is set according to the actual situation.

[0028] Further, the specific steps of step S5 are as follows:

[0029] The clock routing structure includes 3 clock input sources: 1 internal clock input source a, and 2 external clock input sources b and c with broadband amplifiers. And the clock routing structure includes 2 internal selectors s1 and s2. The clock source a is connected to a tunable oscillator that can operate independently, and together with the clock source b, they are used as the two inputs of s1. The output port f of s1 and the clock source c are used as the two inputs of s2, and the output port of s2 is g.

[0030] The clock routing structure includes 3 clock output sources d, e, and h with buffers, which are used to connect other radio frequency subsystems and achieve local oscillator synchronization. The clock output sources d and e are connected to the output port f, and the clock output source h is connected to the output port g.

[0031] The clock routing structure adopts 1 clock routing logic control circuit, which can generate 3 clock routing modes: master mode, slave mode, and feedback mode.

[0032] Among them, in the master mode, s1 selects the clock source a, and s2 selects the port f; in the slave mode, s1 selects the clock source b, and s2 selects the port f; in the feedback mode, s1 selects the clock source b, and s2 selects the clock source c, and the feedback mode is only used for calibrating the local oscillator signal synchronization.

[0033] Further, the specific steps of step S6 are as follows:

[0034] The parallel - type subsystem - level cascade coherent synchronization scheme includes P radio frequency subsystems cascaded through the power distribution network described in step S4. Each radio frequency subsystem includes M / P transmitting channels and N / P receiving channels, and a hybrid clock system that meets the clock routing structure described in step S5. The transmitting and receiving channels of each radio frequency subsystem are all connected to the microstrip unit antenna based on the optimization of the feeding - port transition described in step S3, and the antenna layout in the parallel - type subsystem - level cascade coherent synchronization scheme meets the array distribution configuration described in step S2.

[0035] In the parallel sub-system cascaded coherent synchronization scheme, the clock routing mode of the master RF sub-system master is the master mode, and the clock routing mode of the slave RF sub-system slave is the slave mode. The clock output source e of the master is connected to the clock input sources b of slave1, slave2... slave P-2 respectively after passing through a power divider, and the clock output sources d of slave1, slave2... slave P-2 are connected to their own clock input sources c after passing through a power divider, and the other path is connected to the clock input source b of slave P-1 . The clock output sources d and e of the slave RF sub-systems slave1, slave2... slave P-1 can be connected to the clock input sources b of other slave RF sub-systems respectively after passing through a power divider. The lengths of the clock output links eb, db, and dc of each RF sub-system are kept consistent, and the link insertion loss needs to attenuate the signal power output by the clock output sources d and e to within the specified input power range of the clock input sources b and c.

[0036] Further, the specific steps of step S7 are as follows:

[0037] The series sub-system cascaded coherent synchronization scheme includes P RF sub-systems cascaded through the power distribution network described in step S4. Each RF sub-system includes M / P transmit channels and N / P receive channels, and is a hybrid clock system that satisfies the clock routing structure described in step S5. The transmit and receive channels of each RF sub-system are connected to the microstrip unit antenna based on the optimization of the feeding port transition described in step S3, and the antenna layout in the series sub-system cascaded coherent synchronization scheme satisfies the array distribution configuration described in step S2.

[0038] In the series sub-system cascaded coherent synchronization scheme, the clock routing mode of the master RF sub-system master is the master mode, and the clock routing mode of the slave RF sub-system slave is the slave mode. The clock output source e or d of the master is connected to the clock input source b of slave1, and the clock output source e or d of slave1 is connected to the clock input source b of slave2, that is, the clock output source e or d of each slave RF sub-system is connected to the clock input source b of the next slave RF sub-system until it is connected to the last slave RF sub-system slave P-1 . The lengths of the clock output links eb or db of each RF sub-system are kept consistent, and the link insertion loss needs to attenuate the signal power output by the clock output source e or d to within the specified input power range of the clock input source b.

[0039] Advantages of the present invention: The method of the present invention first conducts system requirement analysis, and then constructs a microstrip unit antenna structure suitable for large-scale array distribution configuration and based on optimized feed port transition, a power distribution network suitable for cascading of multiple radio frequency subsystems of large-scale array radar, and a clock routing structure suitable for cascading of multiple radio frequency subsystems of large-scale array radar. Then, a parallel subsystem cascaded coherent synchronization scheme and a series subsystem cascaded coherent synchronization scheme are proposed. Finally, a large-scale array radar radio frequency system based on cascading of multiple radio frequency subsystems is constructed according to the actual situation. The method of the present invention solves the problem that it is difficult to achieve high azimuth angle resolution due to limited number of transceiver channels in existing surface surveillance array radars. Compared with the existing surface surveillance array radar systems, when the number of radar transceiver channels is limited, a large-scale virtual array can be formed in the azimuth direction, significantly improving the radar gain and azimuth angle resolution, and providing a low-cost solution for surface surveillance radars with high-resolution imaging capabilities. Description of the Drawings

[0040] Figure 1 It is a flowchart of a design method for a large-scale array radar radio frequency system of the present invention.

[0041] Figure 2 It is a schematic diagram of an array distribution configuration suitable for large-scale array radar in an embodiment of the present invention.

[0042] Figure 3 It is a PCB layout of an array distribution configuration suitable for large-scale array radar in an embodiment of the present invention.

[0043] Figure 4 It is a schematic diagram of a microstrip unit antenna structure based on optimized feed port transition in an embodiment of the present invention.

[0044] Figure 5 It is a PCB layout of a microstrip unit antenna based on optimized feed port transition in an embodiment of the present invention.

[0045] Figure 6 It is a PCB layout of the antenna feed port in an embodiment of the present invention.

[0046] Figure 7 It is a schematic diagram of the echo loss simulation result of the microstrip unit antenna in an embodiment of the present invention.

[0047] Figure 8 It is a schematic diagram of a power distribution network structure suitable for cascading of multiple radio frequency subsystems in an embodiment of the present invention.

[0048] Figure 9 It is an example diagram of a power distribution network suitable for cascading of multiple radio frequency subsystems in an embodiment of the present invention.

[0049] Figure 10Schematic diagram of the simulation model of the through-hole of the input and output ports of the Wilkins power divider in the embodiment of the present invention.

[0050] Figure 11 Schematic diagram of the insertion loss simulation result of the local oscillator link in the embodiment of the present invention.

[0051] Figure 12 Schematic diagram of the clock routing structure applicable to the cascade of multiple radio frequency subsystems in the embodiment of the present invention.

[0052] Figure 13 Schematic diagram of the parallel subsystem cascade coherent synchronization scheme in the embodiment of the present invention.

[0053] Figure 14 Schematic diagram of the series subsystem cascade coherent synchronization scheme in the embodiment of the present invention.

[0054] Figure 15 Top-layer PCB layout of the radio frequency system adopting the parallel subsystem cascade coherent synchronization scheme in the embodiment of the present invention.

[0055] Figure 16 Schematic diagram of the measured result of the large-scale array radio frequency system in the embodiment of the present invention. Detailed implementation manners

[0056] The method of the present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0057] As Figure 1 shown, the flowchart of a design method for a large-scale array radar radio frequency system of the present invention is as follows:

[0058] S1. Conduct system requirement analysis to determine the scale and array index of the large-scale array radar radio frequency system based on the cascade of multiple radio frequency subsystems;

[0059] Among them, it is set that the system includes M transmitting channels and N receiving channels in total, and the system includes 1 main radio frequency subsystem master and P - 1 slave radio frequency subsystems, and in this embodiment, P = 4. The large-scale array radar radio frequency system constructed in this embodiment has an operating frequency set to f c = 77 GHz.

[0060] S2. Construct an array distribution configuration suitable for a large-scale array radar to form a large-scale virtual array in the azimuth direction, effectively increasing the virtual aperture of the radar while significantly reducing the size of the radio frequency board and saving hardware costs;

[0061] S3. Construct a microstrip unit antenna structure based on the optimization of the feed port transition to achieve a low sidelobe level while expanding the antenna impedance bandwidth and increasing the antenna gain;

[0062] S4. Construct a power distribution network suitable for the cascading of multiple RF subsystems in a large-scale array radar to achieve the local oscillator link synchronization and cascading among multiple RF subsystems;

[0063] S5. Construct a clock routing structure suitable for the cascading of multiple RF subsystems in a large-scale array radar, which can achieve the cascading in parallel and series forms of RF subsystems, and has the advantages of high flexibility and strong expansion ability;

[0064] S6. Based on steps S1 - S5, construct a parallel subsystem cascading coherent synchronization scheme to achieve controllable attenuation while improving the coherent accuracy;

[0065] S7. Based on steps S1 - S5, construct a series subsystem cascading coherent synchronization scheme to avoid adding additional local oscillator amplification circuits while increasing the cascading expansion scale, and reduce the system cost;

[0066] S8. Based on steps S1 - S7, construct a large-scale array radar RF system based on the cascading of multiple RF subsystems;

[0067] Among them, the system selects a parallel subsystem cascading coherent synchronization scheme or a series subsystem cascading coherent synchronization scheme according to the actual situation.

[0068] In this embodiment, the specific content of step S2 is as follows:

[0069] Construct an array distribution configuration suitable for a large-scale array radar, and the structure is as Figure 2 shown. The PCB layout of the array distribution configuration in this embodiment is as Figure 3 shown. In this embodiment, the number of transmitting channels M = 12, the number of receiving channels N = 16. All transmitting antenna units are horizontally equidistant, and the distance between the phase centers of each transmitting antenna is Nλ / 4; all receiving antenna units are on the same horizontal line, and the receiving antennas are divided into two groups, each group contains N / 2 receiving antenna units, the distance between the phase centers of the receiving antennas within the group is λ / 2, and the distance between the phase centers of the receiving antennas between groups is (M - 1)Nλ / 4.

[0070] Among them, λ≈0.0039m represents the vacuum wavelength of electromagnetic waves.

[0071] Then, through orthogonal waveform design, the array distribution configuration in this embodiment forms a total of MN = 192 virtual channels. Compared with a large-scale array directly formed by MN physical channels, the number of array elements is reduced by MN - (M + N), and the horizontal antenna aperture is reduced by (MN - 1)λ / 2 - (MN - N)λ / 4.

[0072] In this embodiment, the specific content of step S3 is as follows:

[0073] The microstrip unit antenna structure is asFigure 4 As shown, the PCB layout of the microstrip element antenna in this embodiment is as follows Figure 5 As shown, it can be seen that the microstrip element antenna in this embodiment includes a K = 8 element resonant microstrip series-fed antenna, and the resonant length of each element The initial width of each element The spacing d between each element is λ g / 2. The resonant point of the microstrip element antenna in this embodiment is f c = 77 GHz. RO3003 with a thickness of h = 0.127 mm and a relative dielectric constant of ε r = 3 is used as the dielectric substrate, and the final width of each element is readjusted according to the Chebyshev distribution, that is, the -25 dB Chebyshev distribution is used to adjust the amplitude of the excitation current of each element, achieving the effects of low sidelobe level and narrow beam width while improving the antenna gain.

[0074] Among them, c represents the speed of light in vacuum, Δl represents the extended length of the microstrip antenna element caused by the edge effect, and ε e represents the effective dielectric constant; λ g represents the wavelength of the electromagnetic wave in the dielectric substrate. The amplitude of the excitation current of each element is as follows:

[0075] I1:I2:I3:I4:I5:I6:I7:I8 = 0.378:0.584:0.842:1:1:0.842:0.584:0.378

[0076] According to the corresponding relationship between the element width and the excitation current amplitude, it can be obtained that:

[0077] w1:w2:w3:w4:w5:w6:w7:w8 = 0.378:0.584:0.842:1:1:0.842:0.584:0.378

[0078] In this embodiment, the optimal structural parameters (element antenna size) of the element antenna are obtained through three-dimensional electromagnetic simulation software optimization. The final structural parameters are shown in Table 1 (the element antenna is a symmetric structure, and only the dimensions of half of the structure are given).

[0079] Table 1

[0080]

[0081] Among them, w0 represents the width of the feeder between elements, w match represents the width of the antenna impedance matching section, L match represents the length of the antenna impedance matching section, w 50 represents the width of the 50 Ω feeder, and L 50 represents the length of the 50 Ω feeder.

[0082] The microstrip unit antenna structure includes a transition optimization structure applicable to the feed port of a resonant microstrip series-fed antenna. A microstrip line transition section is introduced between the RF output terminal pin and the antenna feed port to enhance the impedance continuity of the transmission line. It is set that the distance g1 between the RF output terminal pin and the ground plane is greater than the width w of the coplanar waveguide feeder. f The width w of the microstrip line transition section m is wider than the width w of the coplanar waveguide feeder f The distance g2 between the feeder and the ground plane is less than the width w of the coplanar waveguide feeder f to suppress the impedance discontinuity caused by the sudden change in the ground plane distance near the RF output terminal pin and meet the 50Ω characteristic impedance requirement. Periodic vias are arranged around the feeder to reduce the insertion loss and surface wave loss. At the same time, the feeders of the transmitting and receiving antennas are made of equal length to ensure that the transmitting and receiving antennas are fed with equal amplitude and in-phase.

[0083] In this embodiment, the transmitting antenna of the main RF subsystem is calculated by SI9000 software, and the line width of the coplanar waveguide transmission line is w f = 0.213mm, the distance between it and the ground plane is g2 = 0.106mm, the width of the microstrip line transition section is w m = 0.269mm, the distance between the RF output terminal pin and the ground plane is g1 = 0.254mm, and periodic ground vias are arranged around the transmission line. The corresponding relationship between the microstrip line width and the characteristic impedance is shown in Table 2.

[0084] Table 2

[0085]

[0086] In this embodiment, the PCB layout of the antenna feed port is as Figure 6 shown, and the simulation result of the return loss S of the microstrip unit antenna is as 11 shown. Figure 7 shown. Figure 6 (a) is the PCB layout of the antenna feed port without transition optimization, Figure 6 (b) is the PCB layout of the antenna feed port with transition optimization, Figure 7 (a) is the S 11 simulation result of the microstrip unit antenna without feed port transition optimization, Figure 7 (b) is the S 11 simulation result of the microstrip unit antenna with feed port transition optimization. It can be seen from the simulation results that before the feed port transition optimization, the impedance bandwidth of the antenna has a large in-band fluctuation and the matching effect is poor. After the feed port transition optimization, the impedance bandwidth of the antenna is flat in-band and the matching effect is significantly improved.

[0087] In this embodiment, the specific steps of step S4 are as follows:

[0088] The power distribution network structure is as follows Figure 8 shown, including two power dividers with equal power distribution. In this embodiment, the Wilkinson power divider with equal power distribution is used. The power dividers are respectively connected to the local oscillator signal output port 1 and output port 2 of the main RF subsystem, and the local oscillator signal input ports 1, 2, and 3 of the slave RF subsystem 1, slave RF subsystem 2, and slave RF subsystem 3. One of the power divider outputs is connected to the input port 4 of the main RF subsystem, and the local oscillator signal link is made of equal length to ensure the synchronization of the local oscillator signal link.

[0089] Figure 9 This is the power distribution network of this embodiment. In the power distribution network, the RF board adopts a multi-layer hybrid PCB design. In this embodiment, 8 layers are used. The transceiver antenna array is located on the top layer, and the coplanar waveguide structure is used for the feeding form. Periodic vias are arranged around the feeder to reduce the insertion loss and surface wave loss. At the same time, the feeders of the transceiver antennas are respectively made of equal length to ensure that the transceiver antennas are fed with equal amplitude and in-phase; the local oscillator signal transmission line is located on the third layer, and the lower layer medium is RO4835 and the upper layer medium is RO4450F.

[0090] The simulation model of the vias at the input and output ports of the Wilkins power divider in this embodiment is as follows Figure 10 shown Figure 10 (a) is the simulation model without the backdrill structure. Below the layer where the transmission line is located is the via stub. Figure 10 (b) is the simulation model with the backdrill structure. There is no via stub below the layer where the transmission line is located. To ensure that the local oscillator signal power transmitted from the main RF subsystem to the slave RF subsystem is higher than the minimum power requirement for the synchronization of the chip cascade subsystem, the vias at the input and output ports of the Wilkinson power divider are backdrilled, as shown in Figure 10 (b). The backdrill removes the via stubs from the bottom layer to the third layer, reducing the overall link loss of the system. To prove the effect of the backdrill structure in reducing the insertion loss in this embodiment, further simulation verification is carried out in the 3D electromagnetic simulation software, and the simulation results are as follows Figure 11 shown.

[0091] Among them, Figure 11 (a) is the simulation result of the insertion loss of the local oscillator link without the backdrill structure. The line insertion loss S 21 is about -21.63 dB; Figure 11 (b) is the simulation result of the insertion loss of the local oscillator link with the backdrill structure. The line insertion loss S 21 is about -7.7 dB. The simulation results show that the via stub will cause higher loss, severely attenuating the transmitted signal power. The via after the backdrill treatment can significantly reduce the loss.

[0092] In summary, the power distribution network described above can be applied to a monolithic microwave integrated circuit with a local oscillator output signal, and can also be applied to a radio frequency subsystem with the hybrid clock designed in step S5.

[0093] In this embodiment, step S5 is specifically as follows:

[0094] The clock routing structure is as Figure 12 shown, including 3 clock input sources: 1 internal clock input source a, and 2 external clock input sources b and c with broadband amplifiers. And the clock routing structure includes 2 internal selectors s1 and s2. The clock source a is connected to a tunable oscillator that can operate independently, and together with the clock source b, they serve as the two inputs of s1. The output port f of s1 and the clock source c serve as the two inputs of s2, and the output port of s2 is g.

[0095] The clock routing structure includes 3 clock output sources d, e, and h with buffers, which are used to connect other radio frequency subsystems and achieve local oscillator synchronization. The clock output sources d and e are connected to the output port f, and the clock output source h is connected to the output port g.

[0096] The clock routing structure adopts 1 clock routing logic control circuit, which can generate 3 clock routing modes: master mode, slave mode, and feedback mode.

[0097] Among them, in the master mode, s1 selects the clock source a, and s2 selects the port f; in the slave mode, s1 selects the clock source b, and s2 selects the port f; in the feedback mode, s1 selects the clock source b, and s2 selects the clock source c, and the feedback mode is only used to calibrate the local oscillator signal synchronization.

[0098] In this embodiment, step S6 is specifically as follows:

[0099] As Figure 13 shown, in the parallel sub-system cascaded coherent synchronization scheme, it includes P radio frequency subsystems cascaded through the power distribution network described in step S4. Each radio frequency subsystem includes M / P transmitting channels and N / P receiving channels, and satisfies the hybrid clock system of the clock routing structure described in step S5. The transmitting and receiving channels of each radio frequency subsystem are all connected to the microstrip unit antenna based on the optimization of the feed port transition described in step S3, and the antenna layout in the parallel sub-system cascaded coherent synchronization scheme satisfies the array distribution configuration described in step S2.

[0100] In the parallel sub-system cascaded coherent synchronization scheme, the clock routing mode of the master RF sub-system master is the master mode, and the clock routing mode of the slave RF sub-system slave is the slave mode. The clock output source e of master is connected to the clock input sources b of slave1 and slave2 respectively after passing through a power divider. The clock output source d is connected to its own clock input source c after passing through a power divider, and the other path is connected to the clock input source b of slave3. For the slave RF sub-system slave 1-3 After the clock output sources d and e pass through a power divider, they can be respectively connected to the clock input sources b of other slave RF sub-systems. The lengths of the clock output links eb, db, and dc of each RF sub-system are kept consistent, and the link insertion loss needs to attenuate the signal power output from the clock output sources d and e to within the specified input power range of the clock input sources b and c.

[0101] In this embodiment, the specific steps of step S7 are as follows:

[0102] As Figure 14 shown, the series sub-system cascaded coherent synchronization scheme includes P RF sub-systems cascaded through the power distribution network described in step S4. Each RF sub-system includes M / P transmit channels and N / P receive channels, and is a hybrid clock system that satisfies the clock routing structure described in step S5. The transmit and receive channels of each RF sub-system are connected to the microstrip unit antenna optimized based on the feed port transition described in step S3, and the antenna layout in the series sub-system cascaded coherent synchronization scheme satisfies the array distribution configuration described in step S2.

[0103] In the series sub-system cascaded coherent synchronization scheme, the clock routing mode of the master RF sub-system master is the master mode, and the clock routing mode of the slave RF sub-system slave is the slave mode. The clock output source e or d of master is connected to the clock input source b of slave1, and the clock output source e or d of slave1 is connected to the clock input source b of slave2, that is, the clock output source e or d of each slave RF sub-system is connected to the clock input source b of the next slave RF sub-system until it is connected to the last slave RF sub-system slave P-1 . The lengths of the clock output links eb or db of each RF sub-system are kept consistent, and the link insertion loss needs to attenuate the signal power output from the clock output source e or d to within the specified input power range of the clock input source b.

[0104] In this embodiment, the specific steps of step S8 are as follows:

[0105] Select the parallel sub-system cascaded coherent synchronization scheme to construct the RF system. The top-level PCB layout of the system is as Figure 15As shown in the figure, based on the array configuration, antenna elements, and power distribution network in steps S2 - S5, a monolithic microwave integrated circuit AWR2243 chip with cascaded synchronous clocks is adopted in the RF system of this embodiment. There is a total of 1 master RF subsystem and 3 slave RF subsystems in the system. 1-3 , and a hybrid clock system that meets the clock routing scheme described in step S5. Each RF subsystem includes 3 transmit channels and 4 receive channels. The master is excited by an internal clock source a. The clock output source d of the master is connected to the input port of a Wilkinson power divider. One output port of this power divider is connected to the clock input source c of the master, and the other output port is connected to the clock input source b of slave1. The clock output source e of the master is connected to the input port of another Wilkinson power divider. The two output ports of this power divider are respectively connected to the clock input sources b of slave2 and slave3. The clock input sources b and c, clock output sources d and e of each RF subsystem, and the input and output ports of the Wilkinson power divider are all back - drilled. The LO link is kept of equal length and is located on the third layer. Using the large - scale array RF system designed above, the measured results are as Figure 16 shown. It can be seen from the results that the radar system implemented in this embodiment can achieve an angular resolution better than 0.8°.

[0106] In summary, the method of the present invention constructs a large - scale array distribution configuration, which can equivalently virtualize a large number of array elements with fewer channels, significantly reduce the size of the RF board, and save hardware costs; constructs a microstrip unit antenna structure based on the optimization of the feed - port transition, which not only expands the antenna impedance bandwidth, but also realizes a low sidelobe level while improving the antenna gain; constructs a power distribution network suitable for the cascading of multiple RF subsystems in a large - scale array radar, realizing the LO synchronization in the case of long links of multiple RF subsystems; constructs a clock routing scheme suitable for the cascading of multiple RF subsystems in a large - scale array radar, which can achieve the cascading of RF subsystems in series and parallel forms, with the advantage of strong expansion ability; the parallel - type subsystem cascading coherent synchronization scheme proposed by the method of the present invention realizes controllable attenuation while improving the coherent accuracy, and the series - type subsystem cascading coherent synchronization scheme avoids adding an additional LO amplifier circuit while increasing the cascading expansion scale, reducing the system cost. The method of the present invention solves the problem that it is difficult to achieve a high azimuth angle resolution in the existing surface surveillance array radar due to the limited number of transceiver channels. Compared with the existing surface surveillance array radar system, in the case of limited radar transceiver channels, it can form a large - scale virtual array in the azimuth direction, significantly improve the radar gain and azimuth angle resolution, and provide a low - cost solution for a surface surveillance radar with high - resolution imaging capabilities.

[0107] Those of ordinary skill in the art will realize that the embodiments described herein are provided to assist the reader in understanding the principles of the present invention, and it should be understood that the scope of protection of the present invention is not limited to such specific statements and embodiments. Those of ordinary skill in the art can make various other specific deformations and combinations that do not depart from the essence of the present invention based on these technical revelations disclosed in the present invention, and these deformations and combinations are still within the scope of protection of the present invention.

Claims

1. A design method for a large-scale array radar RF system, the specific steps are as follows: S1. Conduct system requirement analysis to determine the scale and array indicators of the large-scale array radar RF system based on cascading multiple RF subsystems; Among them, It is set that the system includes M transmitting channels and N receiving channels in total, and the system includes 1 master RF subsystem master and P - 1 slave RF subsystems slave; S2. Construct an array distribution configuration suitable for large-scale array radar; S3. Construct a microstrip unit antenna structure based on optimized feed port transition; S4. Construct a power distribution network suitable for cascading multiple RF subsystems of large-scale array radar; S5. Construct a clock routing structure suitable for cascading multiple RF subsystems of large-scale array radar; S6. Based on steps S1 - S5, construct a parallel subsystem cascaded coherent synchronization scheme; S7. Based on steps S1 - S5, construct a series subsystem cascaded coherent synchronization scheme; S8. Based on steps S1 - S7, construct a large-scale array radar RF system based on cascading multiple RF subsystems; Among them, the system selects a parallel subsystem cascaded coherent synchronization scheme or a series subsystem cascaded coherent synchronization scheme according to the actual situation.

2. A design method for a large-scale array radar RF system according to claim 1, characterized in that, The specific content of step S2 is as follows: Construct an array distribution configuration suitable for large-scale array radar. It is set that all transmitting antenna elements are horizontally equally spaced, and the spacing between the phase centers of adjacent transmitting antennas is Nλ / 4; all receiving antenna elements are on the same horizontal line, and the receiving antennas are divided into two groups, each group contains N / 2 receiving antenna elements, the spacing between the phase centers of the receiving antennas within the group is λ / 2, and the spacing between the phase centers of the receiving antennas between the groups is (M - 1)Nλ / 4; Among them, λ represents the vacuum wavelength of electromagnetic waves; and through orthogonal waveform design, the array distribution configuration forms MN virtual channels in total.

3. A design method for a large-scale array radar RF system according to claim 1, characterized in that The specific content of step S3 is as follows: It is set that the microstrip unit antenna structure includes a K-element resonant microstrip series-fed antenna, and the resonant length of each element The initial width of each element The spacing d between each element is λ g / 2, and the final width of each element is readjusted according to the Chebyshev distribution; Among them, c represents the speed of light in vacuum, f c represents the operating frequency, Δl represents the extended length of the microstrip antenna element caused by the edge effect, ε e represents the effective dielectric constant; ε r represents the relative dielectric constant; λ g represents the wavelength of the electromagnetic wave in the dielectric substrate; The microstrip unit antenna structure includes a transition optimization structure applicable to the feeding port of a resonant microstrip series-fed antenna. A microstrip line transition section is introduced between the radio frequency output terminal pin and the antenna feeding port. It is set that the distance g1 between the radio frequency output terminal pin and the ground plane is greater than the width w of the coplanar waveguide feeder. f , the width w of the microstrip line transition section m is wider than the width w of the coplanar waveguide feeder f , the distance g2 between the feeder and the ground plane is less than the width w of the coplanar waveguide feeder f , to suppress the impedance discontinuity caused by the sudden change in the ground plane distance near the radio frequency output terminal pin and meet the 50Ω characteristic impedance requirement; and periodically arranged vias are arranged around the feeder to reduce the insertion loss and surface wave loss. At the same time, the feeders of the transmitting and receiving antennas are respectively made of equal length to ensure that the transmitting and receiving antennas are fed in equal amplitude and in phase.

4. A design method for a large-scale array radar RF system according to claim 1, characterized in that The specific content of step S4 is as follows: The power distribution network structure includes power dividers with equal power distribution, which are respectively connected to the local oscillator signal output port of the master RF subsystem and the local oscillator signal input ports of P - 1 slave RF subsystems, and equal-length processing is performed on the local oscillator signal link to ensure the synchronization of the local oscillator signal link; In the power distribution network, the RF board adopts a multi-layer mixed-pressure PCB design. The transceiver antenna array is located on the top layer, and the local oscillator signal transmission line is located on the third layer. Backdrilling is performed on the vias at the input and output ports of the power divider to remove the via stubs from the bottom layer to the third layer; Among them, the number of layers of the RF board is set according to the actual situation.

5. A design method for a large-scale array radar radio frequency system according to claim 1, characterized in that The specific content of step S5 is as follows: The clock routing structure includes 3 clock input sources: 1 internal clock input source a, 2 external clock input sources b and c with broadband amplifiers; and the clock routing structure includes 2 internal selectors s1 and s2. The clock source a is connected to a tunable oscillator that can operate independently, and together with the clock source b, they are used as the two inputs of s1. The output port f of s1 and the clock source c are used as the two inputs of s2, and the output port of s2 is g; The clock routing structure includes three clock output sources d, e, and h with buffers, which are used to connect to other RF subsystems and achieve local oscillator synchronization. The clock output sources d and e are connected to the output port f, and the clock output source h is connected to the output port g; The clock routing structure adopts one clock routing logic control circuit, which can generate three clock routing modes: master mode, slave mode, and feedback mode; Among them, in the master mode, s1 selects the clock source a and s2 selects the port f; in the slave mode, s1 selects the clock source b and s2 selects the port f; in the feedback mode, s1 selects the clock source b and s2 selects the clock source c, and the feedback mode is only used for calibrating the local oscillator signal synchronization.

6. A design method for a large-scale array radar radio frequency system according to claim 1, characterized in that The specific steps of step S6 are as follows: In the parallel sub-system cascaded coherent synchronization scheme, there are P RF subsystems cascaded through the power distribution network described in step S4. Each RF subsystem includes M / P transmit channels and N / P receive channels, and satisfies the hybrid clock system of the clock routing structure described in step S5; The transmit and receive channels of each RF subsystem are connected to the microstrip unit antenna based on the optimization of the feed port transition described in step S3, and the antenna layout in the parallel sub-system cascaded coherent synchronization scheme satisfies the array distribution configuration described in step S2; In the parallel sub-system cascaded coherent synchronization scheme, the clock routing mode of the master radio frequency sub-system master is the master mode, and the clock routing mode of the slave radio frequency sub-system slave is the slave mode; the clock output source e of master is connected to the clock input sources b of slave1, slave2... slave P-2 respectively after passing through a power divider, and the clock output sources d of slave1, slave2... slave P-2 are connected to their own clock input sources c through one path after passing through a power divider, and to the clock input source b of slave P-1 through the other path; the clock output sources d and e of the slave radio frequency sub-systems slave1, slave2... slave P-1 can be respectively connected to the clock input sources b of other slave radio frequency sub-systems after passing through a power divider; the lengths of the clock output links eb, db, and dc of each radio frequency sub-system are kept the same, and the link insertion loss needs to attenuate the signal power output by the clock output sources d and e to within the specified input power range of the clock input sources b and c.

7. A design method for a large-scale array radar RF system according to claim 1, characterized in that The specific steps of step S7 are as follows: In the series sub-system cascaded coherent synchronization scheme, there are P RF subsystems cascaded through the power distribution network described in step S4. Each RF subsystem includes M / P transmit channels and N / P receive channels, and satisfies the hybrid clock system of the clock routing structure described in step S5; the transmit and receive channels of each RF subsystem are connected to the microstrip unit antenna based on the optimization of the feed port transition described in step S3, and the antenna layout in the series sub-system cascaded coherent synchronization scheme satisfies the array distribution configuration described in step S2; In the described cascaded coherent synchronization scheme of the series sub-system, the clock routing mode of the master radio frequency sub-system master is the master mode, and the clock routing mode of the slave radio frequency sub-system slave is the slave mode; the clock output source e or d of master is connected to the clock input source b of slave1, and the clock output source e or d of slave1 is connected to the clock input source b of slave2, that is, the clock output source e or d of each slave radio frequency sub-system is connected to the clock input source b of the next slave radio frequency sub-system until it is connected to the last slave radio frequency sub-system slave P-1 ; the lengths of the clock output links eb or db of each radio frequency sub-system are kept consistent, and the link insertion loss needs to attenuate the signal power output from the clock output source e or d to within the specified input power range of the clock input source b.

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