Display panel and display device

Abstract

The invention discloses a display panel and a display device. A control end of a shift module in the display panel is connected to a first node, the shift module outputs shift input signals, a first control end of an output module is connected to a second node, a first end of a first switch unit is connected to the first node, and a second end of the first switch unit is connected to the second node. The control end of the first switch unit receives a first refresh control signal or a second refresh control signal. The shift register units comprise a first type of shift register units and a second type of shift register units, the first type of shift register units receive first refresh control signals, the second type of shift register units receive second refresh control signals, and the second refresh control signals are different from the first refresh control signals. According to the technical scheme, the control freedom degree of the first type of shift register units and the second type of shift register units in time can be increased, so that cascade transmission failure of the first type of shift register units when low frequency is switched to high frequency is avoided.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] With the development of display technologies, the application scenarios of display panels are increasing, and the display requirements of users for display panels are also becoming more diverse. For example, short videos in short video applications often only appear in the middle area of the display panel. Therefore, a higher refresh rate is required for the middle area, while for other areas such as the static comment area, menu area, or black border, a lower refresh rate is required.

[0003] Currently, when a display panel switches from a low refresh rate to a high refresh rate, there is a technical problem of the failure of the cascaded signal transmission of the shift register units. Summary of the Invention

[0004] The present invention provides a display panel and a display device, which avoid the failure of the cascaded transmission of the first type of shift register units when switching from a low frequency to a high frequency by increasing the control freedom of the first type of shift register units and the second type of shift register units in terms of time.

[0005] In a first aspect, the present invention provides a display panel, which includes:

[0006] A driving circuit, the driving circuit includes a plurality of cascaded shift register units;

[0007] The shift register unit includes a first switching unit, a shifting module, and at least one output module;

[0008] The control end of the shifting module is connected to a first node, the shifting module outputs a shifted input signal, and the first control end of the output module is connected to a second node; the first end of the first switching unit is connected to the first node, the second end of the first switching unit is connected to the second node, and the control end of the first switching unit receives a first refresh control signal or a second refresh control signal;

[0009] The plurality of shift register units include a first type of shift register units and a second type of shift register units. The first type of shift register units receive the first refresh control signal, the second type of shift register units receive the second refresh control signal, and the second refresh control signal is different from the first refresh control signal.

[0010] In a second aspect, the present invention further provides a display device, which includes the display panel according to any one of the first aspect.

[0011] In the technical solution of the present invention, the first end of the first switching unit is connected to the first node, and the second end is connected to the second node. Under the action of the first refresh control signal or the second refresh control signal, the conduction between the first node and the second node can be controlled through the first switching unit. On this basis, the first type of shift register unit receives the first refresh control signal and controls the conduction and cutoff between the first node and the second node in the first type of shift register unit according to the first refresh control signal. The second type of shift register unit receives the second refresh control signal and controls the conduction and cutoff between the first node and the second node in the second type of shift register unit according to the second refresh control signal, and the first refresh control signal is different from the second refresh control signal. In this way, by increasing the signal lines in space, the control freedom in time is exchanged, so that the refresh control signals of the first type of shift register unit and the second type of shift register unit do not affect each other. Furthermore, when the second refresh control signal controls the second type of shift register unit to switch from low frequency to high frequency (the first node and the second node in the second type of shift register unit are conducted), the first type of shift register unit arranged in the previous stage of the second type of shift register unit can maintain the cutoff state between the first node and the second node, avoiding the situation where when the first node is at a high level (valid level) and the second node is at a low level (invalid level) in the first type of shift register unit, the capacitor near the second node pulls down the potential of the first node to the invalid level when the first node and the second node are conducted, thereby avoiding the problems of output and cascade transmission failure of the first type of shift register unit. Description of the Drawings

[0012] Figure 1 is a schematic circuit structure diagram of a display panel provided by an embodiment of the present invention;

[0013] Figure 2 is a schematic circuit structure diagram of a shift register unit provided by an embodiment of the present invention;

[0014] Figure 3 is a schematic circuit structure diagram of another shift register unit provided by an embodiment of the present invention;

[0015] Figure 4 is a schematic circuit structure diagram of another display panel provided by an embodiment of the present invention;

[0016] Figure 5 is a schematic circuit structure diagram of another shift register circuit provided by an embodiment of the present invention;

[0017] Figure 6 is a schematic timing diagram of a display panel provided by an embodiment of the present invention;

[0018] Figure 7 is a schematic timing diagram of another display panel provided by an embodiment of the present invention;

[0019] Figure 8 It is another timing diagram of a display panel provided by an embodiment of the present invention;

[0020] Figure 9 It is another timing diagram of a display panel provided by an embodiment of the present invention;

[0021] Figure 10 It is another timing diagram of a display panel provided by an embodiment of the present invention;

[0022] Figure 11 It is another timing diagram of a display panel provided by an embodiment of the present invention;

[0023] Figure 12 It is a circuit structure diagram of another shift register circuit provided by an embodiment of the present invention;

[0024] Figure 13 It is a structure diagram of a display device provided by an embodiment of the present invention. Detailed implementation manners

[0025] To make the objectives, technical solutions and advantages of the present invention clearer, the following will describe the technical solutions of the present invention completely through specific implementation manners in combination with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present invention. Without departing from the spirit or scope of the present invention, various modifications and changes can be made to the present invention, which are obvious to those skilled in the art. Therefore, the present invention is intended to cover the modifications and changes of the present invention that fall within the scope of the corresponding claims (the claimed technical solutions) and their equivalents.

[0026] Moreover, the "first", "second", and similar terms used in the embodiments of the present disclosure do not denote any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as "a", "an", or "the" do not denote a quantity limitation, but rather indicate the presence of at least one. Terms such as "comprising" or "including" mean that the elements or items appearing before this term encompass the elements or items listed after this term and their equivalents, without excluding other elements or items. Terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper", "lower", "left", and "right" are only used to represent relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly. Additionally, in the embodiments of the present disclosure, descriptions such as "identical", "equal", etc. do not mean that the two objects have exactly the same size and exactly the same shape, and allow them to be approximately the same and approximately equal within a certain error range. It should be noted that the embodiments provided in the embodiments of the present invention can be combined with each other without conflict.

[0027] Figure 1 is a schematic circuit structure diagram of a display panel provided by an embodiment of the present invention. Figure 2 is a schematic circuit structure diagram of a shift register unit provided by an embodiment of the present invention. Refer to Figure 1 and Figure 2 , the display panel includes a driving circuit, and the driving circuit includes a plurality of cascaded shift register units 10. The shift register unit 10 includes a first switching unit 110, at least one shift module 120, and at least one output module 130. In Figure 2 , the shift register unit 10 including one shift module 120 and one output module 130 is taken as an example for explanation. In other embodiments, the shift register unit 10 may include at least two shift modules 120 and / or at least two output modules 130. The control end of the shift module 120 is connected to the first node N1, and the shift module 120 outputs a shift input signal NEXT. The first control end of the output module 130 is connected to the second node N2. The first end of the first switching unit 110 is connected to the first node N1, the second end of the first switching unit 110 is connected to the second node N2, and the control end of the first switching unit 110 receives a first refresh control signal Goff1 or a second refresh control signal Goff2. The plurality of shift register units 10 includes a first type of shift register unit 101 and a second type of shift register unit 102. The first type of shift register unit 101 receives the first refresh control signal Goff1, and the second type of shift register unit 102 receives the second refresh control signal Goff2. The second refresh control signal Goff2 is different from the first refresh control signal Goff1.

[0028] Specifically, as in Figure 1 and Figure 2 In the embodiment shown, the driving circuit further includes an input module 140. The output terminal of the input module 140 is connected to the first node N1 to control the potential of the first node N1 through the input module 140. The driving circuit includes N cascaded shift register units 10, where N is a positive integer. The first-stage shift register unit (not shown in the figure) receives the start signal as the input signal. Starting from the second stage, the shift module 120 of each stage of the shift register unit 10 outputs the shift input signal NEXT to the first control terminal INF of the input module 140 of the next-stage shift register unit 10. It can be understood that the input terminal of the shift module 120 can be connected to the first input terminal of the output module 130, and the first input terminal of the output module 130 is electrically connected to the output clock signal terminal OUT, that is, the input terminal of the shift module 120 can be electrically connected to the output clock signal terminal OUT. The gate driving signals Gout output by the N shift register units 10 are shifted in sequence. The shift register unit 10 is electrically connected to at least one scan line (not shown in the figure) to provide the gate driving signal for the scan line. When the gate driving signal transmitted on the scan line is at an effective level, the switching device in the pixel electrically connected to the scan line can be controlled to turn on, so that the pixel electrically connected to the scan line can receive the data signal transmitted on the data line and display it as a corresponding gray scale according to the data signal, so as to realize the refresh of the pixel electrically connected to the scan line.

[0029] Continue to refer to Figure 2, in the same shift register unit 10, the input module 140 is configured to receive at least the control signal of the first control terminal INF and the first scan control signal U2D to control the potential of the first node N1. Other embodiments of the input module 140 may further include that the control terminal and the first terminal of the input module 140 are electrically connected and receive the control signal of the first control terminal INF. For the input module 140, the circuit structure for receiving the control signal of the first control terminal INF and for controlling the potential of the first node N1 can be included in this application. The output module 130 is configured to receive the signal of the first node N1, the first level signal VGL, and the clock signal of the output clock signal terminal OUT during at least part of the time when the display panel is operating, and output the gate driving signal Gout. The first end of the first switch unit 110 is connected to the first node N1, the second end of the first switch unit 110 is connected to the second node N2, and the first control terminal of the output module 130 is connected to the second node N2. When both the control signal of the first control terminal INF received by the input module 140 and the first scan control signal U2D are valid levels, the level of the first node N1 becomes a valid level. If the control terminal of the first switch unit 110 is a valid level, the first switch unit 110 conducts, so that conduction occurs between the first node N1 and the second node N2, that is, the signal of the second node N2 is a valid level, and the first control terminal of the output module 130 can be controlled to conduct the output module 130, so that the clock signal of the output clock signal terminal OUT serves as the gate driving signal Gout of the output module 130. At this time, the shift register unit 10 outputs a valid pulse gate driving signal Gout to control the pixels of the corresponding row to be normally refreshed, that is, this part of the pixels operates at a high refresh rate (high frequency). If the control terminal of the first switch unit 110 is an invalid level and the level of the second node N2 is also an invalid level, the output module 130 outputs an invalid level gate driving signal Gout. At this time, the shift register unit 10 outputs an invalid level gate driving signal Gout to control the pixels of the corresponding row not to be refreshed, that is, this part of the pixels operates at a low refresh rate (low frequency).

[0030] In the related art, since the first switch units of all shift register units are controlled by the same refresh control signal, that is, the control terminals of the first switch units of all shift register units are connected to the same refresh control signal line. When switching from low frequency to high frequency, since the current-stage shift register unit is at low frequency (the output module 130 outputs an invalid level), that is, the potential of the first node in the current-stage shift register unit is a valid level (high level) and the potential of the second node is an invalid level (low level). At this time, if the first switch unit is controlled to conduct, affected by the capacitance near the second node, the potential of the first node will be pulled down to an invalid level, resulting in the failure of the cascade transmission of the current-stage shift register unit.

[0031] To this end, in the embodiment of the present invention, the refresh control signal is set to include a first refresh control signal Goff1 and a second refresh control signal Goff2. The plurality of shift register units 10 include a first type of shift register unit 101 and a second type of shift register unit 102. The first type of shift register unit 101 and the second type of shift register unit 102 are cascaded. The first type of shift register unit 101 receives the first refresh control signal G0ff1, and the second type of shift register unit 102 receives the second refresh control signal G0ff2. That is, the conduction and cutoff between the first node N1 and the second node N2 in the first type of shift register unit 101 are controlled by the first refresh control signal G0ff1, so as to control the interval time during which the second node N2 in the first type of shift register unit 101 is at an effective level according to the first refresh control signal G0ff1 (for example, when the first node N1 and the second node N2 are conducting and the first node N1 is at an effective level, the second node N2 is at an effective level, and when the first node N1 and the second node N2 are cutoff, the second node N2 is at an invalid level). Similarly, the conduction and cutoff between the first node N1 and the second node N2 in the second type of shift register unit 102 are controlled by the second refresh control signal Goff2, so as to control the interval time during which the second node N2 in the second type of shift register unit 102 is at an effective level according to the second refresh control signal Goff2. The first refresh control signal Goff1 is different from the second refresh control signal Goff2. In this way, by adding a control logic spatially or structurally, the control freedom in time is exchanged, so that the refresh control of the first type of shift register unit 101 and the refresh control of the second type of shift register unit 102 do not affect each other.

[0032] When switching from low frequency to high frequency, the first type of shift register unit 101 serves as the low-frequency stage, and the next-stage second type of shift register unit 102 cascaded with it serves as the high-frequency stage. Then, when the second refresh control signal Goff2 controls the low-frequency to high-frequency switching of the second type of shift register unit 102 (the first node N1 and the second node N2 in the second type of shift register unit 102 are turned on), the first type of shift register unit 101 (low-frequency stage) arranged in the previous stage of the second type of shift register unit 102 can maintain the cut-off state between the first node N1 and the second node N2. That is, the first refresh control signal Goff1 controls the cut-off of the first switch unit 110 in the first type of shift register unit 101 of the low-frequency stage. It can be understood that since the potential of the first node N1 in the second type of shift register unit 102 is affected by the shift input signal NEXT output by the shift module 120 in the previous-stage first type of shift register unit 101 (low-frequency stage), and the potentials of both the first node N1 and the second node N2 in the second type of shift register unit 102 are low levels (invalid levels). Furthermore, when the shift module 120 in the previous-stage first type of shift register unit 101 (low-frequency stage) outputs an active shift input signal NEXT (valid level), and the second refresh control signal Goff2 controls the conduction of the first node N1 and the second node N2 in the second type of shift register unit 102, the shift input signal NEXT can raise the potentials of both the first node N1 and the second node N2 in the second type of shift register unit 102 to the valid level, thereby ensuring that the second type of shift register unit 102 can output a valid level, that is, switch from low frequency to high frequency. At this time, the first type of shift register unit 101 (low-frequency stage) in the previous stage of the second type of shift register unit 102 maintains the cut-off state between the first node N1 and the second node N2, avoiding the problem that when the first node N1 in the first type of shift register unit 101 is at a high level (valid level) and the second node N2 is at a low level (invalid level), the capacitor near the second node N2 pulls down the potential of the first node N1 to the invalid level when the first node N1 and the second node N2 are turned on, thus avoiding the problem of cascaded transmission failure in the first type of shift register unit 101 output stage.

[0033] In summary, in the embodiment of the present invention, the first type of shift register unit receives the first refresh control signal to control the conduction and cutoff of the first node and the second node in the first type of shift register unit through the first refresh control signal, and the second type of shift register unit receives the second refresh control signal to control the conduction and cutoff of the first node and the second node in the second type of shift register unit through the second refresh control signal. The first refresh control signal and the second refresh control signal are different. In this way, by adding a new control signal line in space, the control freedom in time is exchanged, so that the refresh control signals of the first type of shift register unit and the second type of shift register unit do not affect each other. Furthermore, when the second refresh control signal controls the second type of shift register unit to switch from low frequency to high frequency (the first node and the second node in the second type of shift register unit are conducting), the first type of shift register unit arranged in the previous stage of the second type of shift register unit can maintain the cutoff state between the first node and the second node, avoiding the situation where when the first node in the first type of shift register unit is at a high level (valid level) and the second node is at a low level (invalid level), the capacitor near the second node pulls down the potential of the first node to the invalid level when the first node and the second node are conducting, thus avoiding the problems of output and cascaded transmission failure of the first type of shift register unit.

[0034] Optionally, on the basis of the above embodiment, Figure 3 is a schematic circuit structure diagram of another shift register unit provided by the embodiment of the present invention. Refer to Figure 1 and Figure 3 , the shift register unit 10 further includes a second switch unit 150. The first end of the second switch unit 150 is connected to the second node N2. The second end of the second switch unit 150 receives the first level signal VGL, and the control end of the second switch unit 150 receives the third refresh control signal Goff3.

[0035] Exemplarily, as Figure 3In the illustrated embodiment, the shift register unit 10 further includes a reset module 160. The output terminal of the reset module 160 and the second control terminal of the output module 130 are connected to the third node N3. The reset module 160 is configured to receive at least the signal provided by the first reset clock terminal RSTF and the first scan control signal U2D, and control the potential of the third node N3. Then, the reset module 160 can control the signal of the third node N3 to be an effective level when both the signal provided by the first reset clock terminal RSTF and the first scan control signal U2D are at effective levels. When the output module 130 can receive the signal of the first node N1 and the signal of the first node N1 is at an effective level, the output module 130 can output the clock signal provided by the output clock signal terminal OUT as the gate driving signal Gout. If the clock signal provided by the output clock signal terminal OUT is at an effective level at this stage, the gate driving signal Gout output by the output module 130 is also at an effective level. When the output module 130 receives the signal of the third node N3 and the signal of the third node N3 is at an effective level, the output module 130 can output the first level signal VGL as the gate driving signal Gout. At this time, the gate driving signal Gout is at an invalid level.

[0036] In addition, the shift register unit further includes a second switch unit 150. The first end of the second switch unit 150 is connected to the second node N2. The second end of the second switch unit 150 receives the first level signal VGL. The control terminal of the second switch unit 150 receives the third refresh control signal Goff3. Specifically, taking the first type of shift register unit 101 as an example, when the first refresh control signal Goff1 is at an effective level and the third refresh control signal Goff3 is at an invalid level, the first switch unit 110 is turned on and the second switch unit 150 is turned off. At this stage, if both the signal of the first node N1 and the clock signal provided by the output clock signal terminal OUT are at effective levels, the shift register unit 10 can provide an effective pulse of the gate driving signal Gout to the scan line. When the third refresh control signal Goff3 is at an effective level and the first refresh control signal Goff1 is at an invalid level, the first switch unit 110 is turned off and the second switch unit 150 is turned on. At this stage, the shift register unit 10 cannot provide an effective pulse of the gate driving signal Gout to the scan line, and the gate driving signal Gout provided by the shift register unit 10 to the scan line is at an invalid level.

[0037] It should be noted that the first refresh control signal Goff1 and the third refresh control signal Goff3 cannot be at the effective level simultaneously, so as to avoid incomplete opening or closing of the first switching unit 110 and the second switching unit 150, making the operating states of the first switching unit 110 and the second switching unit 150 uncontrollable, unable to control the potential of the gate driving signal Gout output by the shift register unit 10, and affecting the display quality of the display panel. Similarly, the second refresh control signal Goff2 and the third refresh control signal Goff3 cannot be at the effective level simultaneously.

[0038] It should also be noted that, on the basis of the above embodiments, the shift register unit 10 further includes a node mutual control module 170. The node mutual control module 170 is configured to receive at least the signal of the first node N1 and the signal of the third node N3, and control the signal of the third node N3 according to the signal of the first node N1, and control the signal of the first node N1 according to the signal of the third node N3. When the signal of the first node N1 is at the effective level, the node mutual control module 170 can control the signal of the third node N3 to be at the ineffective level according to the signal of the first node N1; when the signal of the third node N3 is at the effective level, the node mutual control module 170 can control the signal of the first node N1 to be at the ineffective level according to the signal of the third node N3. In this way, the signals of the first node N1 and the third node N3 can be mutually clamped, and the signals of the first node N1 and the third node N3 will not be at the effective level simultaneously, which is beneficial to ensuring the orderly operation of the shift register unit 10, improving the accuracy and stability of the gate driving signal Gout output by the shift register unit 10, and avoiding the signals of the first node N1 and the third node N3 being at the effective level simultaneously, so that the output module 130 outputs the first level signal VGL and the clock signal provided by the output clock signal terminal OUT as the gate driving signal Gout at the same time, resulting in a large deviation in the gate driving signal Gout output by the shift register unit 10, affecting the conduction of the switching device in the pixel, causing the data signal written into the pixel to be inaccurate, and the display quality to be poor.

[0039] Optionally, on the basis of the above embodiments, continue to refer to Figure 1, the display panel includes a first control signal line S1, a second control signal line S2, and a third control signal line S3. The control end of the first switch unit 110 in the first type of shift register unit 101 is connected to the first control signal line S1, the control end of the first switch unit 110 in the second type of shift register unit 102 is connected to the second control signal line S2, and the control end of the second switch unit 150 in the first type of shift register unit 101 and the second type of shift register unit 102 is connected to the third control signal line S3. The first control signal line S1 transmits a first refresh control signal Goff1 to the control end of the first switch unit 110 in the first type of shift register unit 101, and the second control signal line S2 transmits a second refresh control signal Goff2 to the control end of the first switch unit 110 in the second type of shift register unit 102. The third control signal line S3 transmits a third refresh control signal Goff3 to the control end of the second switch unit 150 in the first type of shift register unit 101 and the second type of shift register unit 102. Thus, by adding a second control signal line S2 structurally, the signals transmitted by the first control signal line S1 and the second control signal line S2 are different, and the first control signal line S1 and the second control signal line S2 control the control ends of the first switch units 110 in different shift register units 10, so that the refresh control of the first type of shift register unit 101 and the refresh control of the second type of shift register unit 102 do not affect each other. Furthermore, when the second control signal line S2 controls the second type of shift register unit 102 to switch from low frequency to high frequency, the first type of shift register unit 101 arranged in the previous stage of the second type of shift register unit 102 can maintain the cut-off state between the first node N1 and the second node N2, avoiding the situation where when the first node N1 is at an effective level and the second node N2 is at an ineffective level in the first type of shift register unit 101, the capacitor near the second node N2 pulls down the potential of the first node N1 to an ineffective level when the first node N1 and the second node N2 are turned on, thus avoiding the problem of cascaded transmission failure of the first type of shift register unit 101.

[0040] Optionally, based on the above embodiment, continue to refer to Figure 3 , the first type of shift register unit 101 and the second type of shift register unit 102 connected to the same third control signal line S3 are alternately arranged.

[0041] Specifically, the first type of shift register unit 101 is connected to the first control signal line S1, and the second type of shift register unit 102 is connected to the second control signal line S2, as Figure 3In the embodiment shown, the cascaded multiple shift register units 10 include a first-stage shift register unit, a second-stage shift register unit, a third-stage shift register unit, a fourth-stage shift register unit, and so on. The first type of shift register units 101 and the second type of shift register units 102 are arranged alternately. Then, the first-stage shift register unit is the first type of shift register unit 101, the second-stage shift register unit is the second type of shift register unit 102, the third-stage shift register unit is the first type of shift register unit 101, the fourth-stage shift register unit is the second type of shift register unit 102, and so on. In this way, by arranging the first type of shift register units 101 and the second type of shift register units 102 alternately, it can be ensured that any two adjacent shift register units both include the first type of shift register unit 101 and the second type of shift register unit 102, so that when switching from low frequency to high frequency at any position, the refresh controls of the two connected shift register units will not affect each other.

[0042] Optionally, based on the above embodiment, Figure 4 FIG. [ID] is a schematic circuit diagram of another circuit structure of a display panel provided by an embodiment of the present invention. Figure 5 FIG. [ID] is a schematic circuit diagram of yet another shift register circuit provided by an embodiment of the present invention. Figure 6 FIG. [ID] is a timing diagram of a display panel provided by an embodiment of the present invention. Refer to Figures 4 - 6 , the shift register unit 10 further includes an input module 140, and the output end of the input module 140 is connected to the first node N1. The first type of shift register unit 101 includes the i-th stage shift register unit VSR(i), the second type of shift register unit 102 includes the j-th stage shift register unit VSR(j), and the output end of the shift module 120 in the i-th stage shift register unit VSR(i) is electrically connected to the input end of the input module 140 in the j-th stage shift register unit; i and j are positive integers and i is not equal to j. The display panel includes a first working process. In the first working process, the start time of the effective pulse of the second refresh control signal Goff2 is before the end time of the effective pulse of the shift input signal generated by the i-th stage shift register unit VSR(i).

[0043] Exemplarily, such as Figure 4In the illustrated embodiment, taking the case where the shift register module includes two output modules 130 as an example for illustration, the two output modules 130 include a first output module 131 and a second output module 132. The first output module 131 outputs a first gate driving signal Gout1, and the second output module 132 outputs a second gate driving signal Gout2. The first control ends of the first output module 131 and the second output module 132 are both connected to the second node N2, and the second control ends of the first output module 131 and the second output module 132 are both connected to the third node N3. The first input end of the first output module 131 is connected to the first output clock signal terminal OUT1, the first input end of the second output module 132 is connected to the second output clock signal terminal OUT2, and the second input ends of the first output module 131 and the second output module 132 are both connected to the first level signal VGL. Further, when the first refresh control signal Goff1 or the second refresh control signal Goff2 outputs an effective level, a conduction is established between the first node N1 and the second node N2. The first output module 131 can output the clock signal provided by the first output clock signal terminal OUT1 as the first gate driving signal Gout1, and the second output module 132 can output the clock signal provided by the second output clock signal terminal OUT2 as the second gate driving signal Gout2.

[0044] Exemplarily, as Figure 5 In the illustrated embodiment, let i and j be adjacent positive integers. Then, the i-th stage shift register unit VSR(i) is a first type of shift register unit 101, and the j-th stage shift register unit VSR(j) is a second type of shift register unit 102. The first output module 131 of the i-th stage shift register unit VSR(i) outputs a gate driving signal Gout(2N - 1), the second output module 132 outputs a gate driving signal Gout(2N), and the shift module 120 outputs a shift input signal NEXT(2N) to the first control end INF of the input module 140 of the j-th stage shift register unit VSR(j); the first output module 131 of the j-th stage shift register unit VSR(j) outputs a gate driving signal Gout(2N + 1), the second output module 132 outputs a gate driving signal Gout(2N + 2), and the shift module 120 outputs a shift input signal NEXT(2N + 2) to the next stage shift register unit.

[0045] Based on the above embodiments, refer to Figure 5 and Figure 6, the display panel includes a first working process. The first working process can be a process of switching from low frequency to high frequency. Let the i-th stage shift register unit VSR(i) be the current low-frequency stage, and the j-th stage shift register unit VSR(j) be the switched high-frequency stage. Then, when the second refresh control signal Goff2 with an effective level is output to the j-th stage shift register unit VSR(j) through the second control signal line S2, when the first node N1 and the second node N2 of the j-th stage shift register unit VSR(j) are turned on, on the one hand, it is necessary to output the first refresh control signal Goff1 with an ineffective level to the i-th stage shift register unit VSR(i) through the first control signal line S1, so as to avoid the cascaded output failure of the i-th stage shift register unit VSR(i) (at this time, the first node N1 in the i-th stage shift register unit VSR(i) is at an effective level, and the second node N2 is at an ineffective level. If turned on, the potential of the first node N1 will be pulled down to ineffective). On the other hand, it is also necessary to ensure that the shift input signal NEXT(2N) generated by the i-th stage shift register unit VSR(i) is an effective pulse, so as to ensure that the shift input signal NEXT(2N) generated by the i-th stage shift register unit VSR(i) can raise the potentials of the first node N1 and the second node N2 of the j-th stage shift register unit VSR(j) from ineffective levels to effective levels. Therefore, by setting the start time of the effective pulse of the second refresh control signal Goff2 before the end time of the effective pulse of the shift input signal generated by the i-th stage shift register unit VSR(i), that is, before the effective pulse of the shift input signal generated by the i-th stage shift register unit VSR(i) fails, the first switch unit 110 in the j-th stage shift register unit VSR(j) is turned on, so as to avoid turning on the transmission path between the first node N1 and the second node N2 after the shift input signal NEXT(2N) jumps to a low level and the signal of the first node N1 becomes a floating signal. At this time, although the potential of the first node N1 can still be maintained at a high level, the signal of the first node N1 is a passive signal and does not have enough charge to raise the potential of the second node N2, which may cause the signal of the second node N2 to not reach the expected high level, affecting the output gate drive signal Gout, and ultimately resulting in inaccurate gate drive signals Gout on the scan line, incomplete opening of the switching device in the pixel, and inability of the pixel to write accurate data signals, affecting the display quality.

[0046] Exemplarily, continue to refer to Figure 6, taking the invalid level as the low level and the valid level as the high level as an example for illustration. In the time period t21, the first refresh control signal Goff1 is at the low level and the third refresh control signal Goff3 is at the high level, then the cut-off between the first node N1 and the second node N2 in the i-th stage shift register unit VSR(i), and the second node N2 is at the low level. In the time period t22, the first refresh control signal Goff1 is at the low level and the third refresh control signal Goff3 is at the low level, the cut-off between the first node N1 and the second node N2 in the i-th stage shift register unit VSR(i), the second node N2 is at the low level, and the i-th stage shift register unit VSR(i) outputs the invalid level, that is, the i-th stage shift register unit VSR(i) is the low-frequency current stage. The second refresh control signal Goff2 is at the low level, and the cut-off between the first node N1 and the second node N2 in the j-th stage shift register unit VSR(j). In the t23 stage, the high level of the second refresh control signal Goff2 is before the high level of the first refresh control signal Goff1, that is, when the conduction between the first node N1 and the second node N2 in the j-th stage shift register unit VSR(j), the cut-off state can be maintained between the first node N1 and the second node N2 in the i-th stage shift register unit VSR(i). In addition, in the time period t23, the shift input signal NEXT(2N) output by the i-th stage shift register unit VSR(i) is at the high level, and the rising edge of the second refresh control signal Goff2 is before the falling edge of the shift input signal generated by the i-th stage shift register unit VSR(i), so as to ensure that the shift input signal NEXT(2N) is active, that is, it can raise the potentials of the first node N1 and the second node N2 in the j-th stage shift register unit VSR(j) from the low level to the high level. At this time, the first output module 131 of the j-th stage shift register unit VSR(j) outputs the scan signal provided by the fourth clock signal line CK4 to the first output clock signal terminal OUT1, and the second output module 132 of the j-th stage shift register unit VSR(j) outputs the scan signal provided by the first clock signal line CK1 to the second output clock signal OUT2.

[0047] Optionally, on the basis of the above embodiments, Figure 7 is another timing schematic diagram of the display panel provided by the embodiment of the present invention. Refer to Figure 4 、 Figure 5 and Figure 7 , the start time of the effective pulse of the second refresh control signal Goff2 is before the start time of the effective pulse of the shift input signal NEXT(2N) generated by the i-th stage shift register unit VSR(i).

[0048] Specifically, the earliest conduction time of the first switch unit 110 in the j-th stage shift register unit VSR(j) needs to be before the start time of the effective pulse of the shift input signal generated by the i-th stage shift register unit VSR(i). That is, first, the conduction between the first node N1 and the second node N2 in the j-th stage shift register unit VSR(j) is turned on. Then, the potentials of the first node N1 and the second node N2 in the j-th stage shift register unit VSR(j) are pulled up from a low level to a high level by the active shift input signal NEXT(2N) generated by the i-th stage shift register unit VSR(i). The potential of the second node N2 is pulled up in an active manner, thereby improving the accuracy of the potential of the second node N2.

[0049] Exemplarily, continue to refer to Figure 7 , taking the invalid level as the low level and the effective level as the high level as an example for illustration. In the time period t21, the first refresh control signal Goff1 is at a low level, and the third refresh control signal Goff3 is at a high level. Then, the conduction between the first node N1 and the second node N2 in the i-th stage shift register unit VSR(i) is cut off, and the second node N2 is at a low level. In the time period t22, the first refresh control signal Goff1 is at a low level, and the third refresh control signal Goff3 is at a low level. The conduction between the first node N1 and the second node N2 in the i-th stage shift register unit VSR(i) is cut off, the second node N2 is at a low level, and the i-th stage shift register unit VSR(i) outputs an invalid level, that is, the i-th stage shift register unit VSR(i) is the low-frequency current stage. The second refresh control signal Goff2 is at a low level, and the conduction between the first node N1 and the second node N2 in the j-th stage shift register unit VSR(j) is cut off. In the time period t23, the rising edge of the second refresh control signal Goff2 is before the rising edge of the shift input signal NEXT(2N), that is, the start time of the effective pulse of the second refresh control signal Goff2 is before the start time of the effective pulse of the shift input signal NEXT(2N) generated by the i-th stage shift register unit VSR(i), so as to ensure that the shift input signal NEXT(2N) can pull up the potentials of the first node N1 and the second node N2 in the j-th stage shift register unit VSR(j) from a low level to a high level in an active manner. At this time, the first output module 131 of the j-th stage shift register unit VSR(j) outputs a scan signal provided by the fourth clock signal line CK4 to the first output clock signal terminal OUT1, and the second output module 132 of the j-th stage shift register unit VSR(j) outputs a scan signal provided by the first clock signal line CK1 to the second output clock signal terminal OUT2.

[0050] Optionally, on the basis of the above embodiments, Figure 8 is another timing diagram of a display panel provided by an embodiment of the present invention. Refer to Figure 4 、 Figure 5and Figure 8 , the input terminal of the input module 140 receives the start signal STV or the shift input signal NEXT as the input signal. The start time of the valid pulse of the second refresh control signal Goff2 is after the end time of the valid pulse of the input signal received by the i-th stage shift register unit VSR(i).

[0051] Specifically, when the input signal received by the i-th stage shift register unit VSR(i) is the shift input signal NEXT generated by the previous stage shift register unit 10 (such as the (j - 2)-th stage shift register unit, which is the second type of shift register unit 102), since the (j - 2)-th stage shift register unit is also controlled by the second refresh control signal Goff2, therefore, it is necessary to set the start time of the valid pulse of the second refresh control signal Goff2 to be after the end time of the valid pulse of the input signal received by the i-th stage shift register unit VSR(i), that is, the rising edge of the second refresh control signal Goff2 needs to be at the earliest after the falling edge of the shift input signal NEXT output by the (j - 2)-th stage shift register unit, so as to avoid the situation where the first switching unit 110 of the (j - 2)-th stage shift register unit is turned on when controlling the first switching unit 110 of the j-th stage shift register unit VSR(j) to be turned on and output a valid pulse.

[0052] Exemplarily, continue to refer to Figure 8, taking the invalid level as the low level and the valid level as the high level as an example for illustration. In the time period t21, the first refresh control signal Goff1 is at the low level, and the third refresh control signal Goff3 is at the high level, then the connection between the first node N1 and the second node N2 in the i-th stage shift register unit VSR(i) is cut off, and the second node N2 is at the low level. In the time period t22, the first refresh control signal Goff1 is at the low level, and the third refresh control signal Goff3 is at the low level. The connection between the first node N1 and the second node N2 in the i-th stage shift register unit VSR(i) is cut off, the second node N2 is at the low level, and the i-th stage shift register unit VSR(i) outputs the invalid level, that is, the i-th stage shift register unit VSR(i) is the low-frequency current stage. The second refresh control signal Goff2 is at the high level, and the connection between the first node N1 and the second node N2 of the j-th stage shift register unit VSR(j) is conducted. In the time period t23, the rising edge of the second refresh control signal Goff2 is after the falling edge of the input signal received by the i-th stage shift register unit VSR(i), that is, the rising edge of the second refresh control signal Goff2 is after the falling edge of the shift input signal generated by the previous stage shift register unit of the i-th stage shift register unit VSR(i), so as to avoid the situation that the first switching unit 110 in the previous stage shift register unit of the i-th stage shift register unit VSR(i) is conducted when controlling the first switching unit 110 of the j-th stage shift register unit VSR(j) to be conducted and output the valid pulse.

[0053] Optionally, on the basis of the above embodiments, Figure 9 is another timing diagram of a display panel provided by an embodiment of the present invention. Refer to Figure 4 、 Figure 5 and Figure 9 , the first type of shift register unit 101 further includes a k-th stage shift register unit VSR(k), and the output end of the shift module 120 in the j-th stage shift register unit VSR(j) is electrically connected to the input end of the input module 140 in the k-th stage shift register unit VSR(k); k is a positive integer, k is not equal to i, and k is not equal to j. The start time of the valid pulse of the first refresh control signal Goff1 is before the end time of the valid pulse of the shift input signal NEXT(2N + 2) generated by the j-th stage shift register unit VSR(j).

[0054] Specifically, as Figure 4 、 Figure 5 and Figure 9As shown, let i, j, and k be consecutive natural numbers. The first output module 131 of the k-th stage shift register unit VSR(k) outputs the gate drive signal Gout(2N + 3), the second output module 132 outputs the gate drive signal Gout(2N + 4), and the shift module 120 outputs the shift input signal NEXT(2N + 4) to the subsequent stage shift register unit 10. If the k-th stage shift register unit VSR(k) is the first type of shift register unit 101, the first switch unit 110 of the k-th stage shift register unit VSR(k) is controlled by the first refresh control signal Goff1. On this basis, the rising edge of the first refresh control signal Goff1 is set before the falling edge of the shift input signal NEXT(2N + 2) generated by the j-th stage shift register unit VSR(j). Exemplarily, if it is desired to achieve an effective pulse output from the k-th stage shift register unit VSR(k), that is, the k-th stage shift register unit VSR(k) switches from low frequency to high frequency, on the basis of setting the first switch unit 110 in the k-th stage shift register unit VSR(k) to be turned on, it is also necessary to set the shift input signal NEXT(2N + 2) generated by the j-th stage shift register unit VSR(j) to be an effective pulse, so as to ensure that the shift input signal NEXT(2N + 2) generated by the j-th stage shift register unit VSR(j) can raise the potentials of the first node N1 and the second node N2 of the k-th stage shift register unit VSR(k) from invalid levels to effective levels. That is, before the effective pulse of the shift input signal generated by the j-th stage shift register unit VSR(j) expires, the first switch unit 110 in the k-th stage shift register unit VSR(k) is turned on, to avoid turning on the transmission path for the signal of the first node N1 to be transmitted to the second node N2 when the signal of the first node N1 becomes a floating signal after the shift input signal NEXT(2N + 2) jumps to a low level.

[0055] Exemplarily, such as Figure 9As shown, taking the invalid level as the low level and the valid level as the high level as an example for illustration. In the time period t24, the second refresh control signal Goff2 is at the high level, the first node N1 and the second node N2 in the j-th stage shift register unit VSR(j) are at the high level, the first output clock signal terminal OUT1 is electrically connected to the fourth clock signal line CK4, and the fourth clock signal line CK4 provides a high level, so the gate driving signal Gout(2N + 1) output by the j-th stage shift register unit VSR(j) is at the high level. In addition, the first reset clock terminal RSTF of the reset module 160 in the k-th stage shift register unit VSR(k) is electrically connected to the fourth clock signal line CK4. Further, the reset module 160 in the k-th stage shift register unit VSR(k) controls the potential of the third node N3 to be at the high level. Under the action of the node mutual control module 170, the high-level third node N3 controls the potential of the first node N1 to be at the low level, thereby resetting the first node N1 in the k-th stage shift register unit VSR(k), so that both the first node N1 and the second node N2 in the k-th stage shift register unit VSR(k) are at the low level (to avoid the problem of output failure when the first node N1 is at the high level during subsequent conduction). In the time period t25, the first node N1 and the second node N2 in the j-th stage shift register unit VSR(j) are at the high level, the second output clock signal terminal OUT2 is electrically connected to the first clock signal line CK1. At this time, the scan signal provided by the first clock signal line CK1 is at the high level, so the gate driving signal Gout(2N + 2) output by the j-th stage shift register unit VSR(j) is at the high level. And the shift input signal NEXT(2N + 2) generated by the j-th stage shift register unit VSR(j) is at the high level. Since the first refresh control signal Goff1 is at the high level, the shift input signal NEXT(2N + 2) can pull up the potentials of the first node N1 and the second node N2 in the k-th stage shift register unit VSR(k). In the time period t26, the output module 130 in the k-th stage shift register unit VSR(k) outputs an effective pulse to achieve a full switch to high frequency.

[0056] Optionally, on the basis of the above embodiments, Figure 10 is another timing diagram of a display panel provided by an embodiment of the present invention. Refer to Figure 4 、 Figure 5 and Figure 10 , the start time of the effective pulse of the first refresh control signal Goff1 is before the start time of the effective pulse of the shift input signal NEXT(2N + 2) generated by the j-th stage shift register unit VSR(j).

[0057] Specifically, the earliest conduction time of the first switching unit 110 in the k-th stage shift register unit VSR(k) is before the start time of the valid pulse of the shift input signal NEXT(2N + 2) generated by the j-th stage shift register unit VSR(j). That is, first, the conduction between the first node N1 and the second node N2 in the k-th stage shift register unit VSR(k) is turned on, and then the potentials of the first node N1 and the second node N2 in the k-th stage shift register unit VSR(k) are pulled from the low level to the high level by the active shift input signal NEXT(2N + 2) generated by the j-th stage shift register unit VSR(j). That is, the potential of the second node N2 is pulled up in an active manner, thereby improving the potential accuracy of the second node N2.

[0058] Exemplarily, as Figure 10 shown, taking the invalid level as the low level and the valid level as the high level as an example for illustration. In the time period t24, the second refresh control signal Goff2 is at the high level, the first node N1 and the second node N2 in the j-th stage shift register unit VSR(j) are at the high level, the first output clock signal terminal OUT1 is electrically connected to the fourth clock signal line CK4, and the fourth clock signal line CK4 provides a high level, then the gate driving signal Gout(2N + 1) output by the j-th stage shift register unit VSR(j) is at the high level. In addition, the first reset clock terminal RSTF of the reset module 160 in the k-th stage shift register unit VSR(k) is electrically connected to the fourth clock signal line CK4, and further, the reset module 160 in the k-th stage shift register unit VSR(k) controls the potential of the third node N3 to be at the high level. Under the action of the node mutual control module 170, the high-level third node N3 controls the potential of the first node N1 to be at the low level, thereby resetting the first node N1 in the k-th stage shift register unit VSR(k), so that both the first node N1 and the second node N2 in the k-th stage shift register unit VSR(k) are at the low level (to avoid the problem of output failure when the first node N1 is at the high level during subsequent conduction). In the time period t25, the first node N1 and the second node N2 in the j-th stage shift register unit VSR(j) are at the high level, the second output clock signal terminal OUT2 is electrically connected to the first clock signal line CK1. At this time, the scan signal provided by the first clock signal line CK1 is at the high level, then the gate driving signal Gout(2N + 2) output by the j-th stage shift register unit VSR(j) is at the high level. And the shift input signal NEXT(2N + 2) generated by the j-th stage shift register unit VSR(j) is at the high level. Since the first refresh control signal Goff1 is at the high level, the shift input signal NEXT(2N + 2) can pull up the potentials of the first node N1 and the second node N2 in the k-th stage shift register unit VSR(k). In the time period t26, both the third clock signal line CK3 and the second clock signal line CK2 provide a high level, as Figure 5As shown, the second clock signal line CK2 is electrically connected to the first output clock signal terminal OUT1 in the k-th stage shift register unit VSR(k), and the third clock signal line CK3 is electrically connected to the second output clock signal terminal OUT2 in the k-th stage shift register unit VSR(k). Therefore, the first output module 131 in the k-th stage shift register unit VSR(k) outputs the effective level provided by the first output clock signal terminal OUT1, and the second output module 132 outputs the effective level provided by the second output clock signal terminal OUT2, that is, the output module 130 in the k-th stage shift register unit VSR(k) outputs an effective pulse, realizing a full switching to high frequency.

[0059] Optionally, based on the above embodiments, Figure 11 is a timing diagram of another display panel provided by an embodiment of the present invention. Refer to Figure 4 、 Figure 5 and Figure 11 , the start time of the effective pulse of the first refresh control signal Goff1 is located after the end time of the effective pulse of the input signal received by the j-th stage shift register unit VSR(j).

[0060] Specifically, the input signal received by the j-th stage shift register unit VSR(j) is the shift input signal NEXT(2N) generated by the i-th stage shift register unit VSR(i). Since the control terminals of the first switching unit 110 in the k-th stage shift register unit VSR(k) and the control terminals of the first switching unit 110 in the i-th stage shift register unit VSR(i) are both controlled by the first refresh control signal Goff1, therefore, it is necessary to set the start time of the effective pulse of the first refresh control signal Goff1 to be located after the end time of the effective pulse of the input signal received by the j-th stage shift register unit VSR(j), that is, the start time of the effective pulse of the first refresh control signal Goff1 needs to be located after the end time of the effective pulse of the shift input signal NEXT(2N) generated by the i-th stage shift register unit VSR(i), so as to avoid misleading conduction of the first switching unit 110 in the i-th stage shift register unit VSR(i) when controlling the first switching unit 110 in the k-th stage shift register unit VSR(k) to conduct and output an effective pulse, resulting in the output failure of the i-th stage shift register unit VSR(i).

[0061] Exemplarily, such as Figure 11As shown, taking the invalid level as the low level and the valid level as the high level as an example for illustration. During the time period t24, the second refresh control signal Goff2 is at the high level, the first node N1 and the second node N2 in the j-th stage shift register unit VSR(j) are at the high level, the first output clock signal terminal OUT1 is electrically connected to the fourth clock signal line CK4, and the fourth clock signal line CK4 provides a high level, so the gate driving signal Gout(2N + 1) output by the j-th stage shift register unit VSR(j) is at the high level. In addition, the first reset clock terminal RSTF of the reset module 160 in the k-th stage shift register unit VSR(k) is electrically connected to the fourth clock signal line CK4. Furthermore, the reset module 160 in the k-th stage shift register unit VSR(k) controls the potential of the third node N3 to be at the high level. Under the action of the node mutual control module 170, the high-level third node N3 controls the potential of the first node N1 to be at the low level, thereby resetting the first node N1 in the k-th stage shift register unit VSR(k), making both the first node N1 and the second node N2 in the k-th stage shift register unit VSR(k) at the low level (to avoid the problem of output failure when the first node N1 is at the high level during subsequent conduction). The first refresh control signal Goff1 is at the high level, so conduction occurs between the first node N1 and the second node N2 in the k-th stage shift register unit VSR(k). At this time, the high level of the input signal received by the j-th stage shift register unit VSR(j) has ended, that is, the output of the i-th stage shift register unit VSR(i) has ended. During the time period t25, the first node N1 and the second node N2 in the j-th stage shift register unit VSR(j) are at the high level, the second output clock signal terminal OUT2 is electrically connected to the first clock signal line CK1. At this time, the scan signal provided by the first clock signal line CK1 is at the high level, so the gate driving signal Gout(2N + 2) output by the j-th stage shift register unit VSR(j) is at the high level. And the shift input signal NEXT(2N + 2) generated by the j-th stage shift register unit VSR(j) is at the high level, and further the shift input signal NEXT(2N + 2) can raise the potentials of the first node N1 and the second node N2 in the k-th stage shift register unit VSR(k). During the time period t26, the output module 130 in the k-th stage shift register unit VSR(k) outputs an effective pulse to achieve a full switch to high frequency.

[0062] Optionally, on the basis of the above example, continue to refer to Figure 4 、 Figure 5 and Figure 9, the period of the valid level of the first node N1 in the i-th stage shift register unit VSR(i), the period of the invalid level of the second node N2 in the i-th stage shift register unit VSR(i), and the period of the invalid level of the first refresh control signal Goff1 overlap. Exemplarily, taking the high level as the valid level and the low level as the invalid level as an example, the period when the first node N1 in the i-th stage shift register unit VSR(i) is at the high level, the period when the second node N2 in the i-th stage shift register unit VSR(i) is at the low level, and the period when the first refresh control signal Goff1 is at the low level overlap. That is, when the first node N1 in the i-th stage shift register unit VSR(i) is at the high level and the second node N2 is at the low level, the first refresh control signal Goff1 is at the low level. At this time, the connection between the first node N1 and the second node N2 in the i-th stage shift register unit VSR(i) is cut off, thereby preventing the capacitor near the second node N2 from pulling down the potential of the first node N1 and avoiding the problem of the output failure of the i-th stage shift register unit VSR(i). The period of the valid level of the first node N1 in the k-th stage shift register unit VSR(k), the period when the second node N2 in the k-th stage shift register unit VSR(k) is at the valid level, and the period of the valid level of the first refresh control signal Goff1 overlap. Specifically, when both the first node N1 and the second node N2 are at the high level, there will be no problem that the capacitor near the second node N2 pulls down the potential of the first node N1. Furthermore, when the first node N1 in the k-th stage shift register unit VSR(k) is at the high level and the second node N2 is at the high level, the first refresh control signal Goff1 is at the high level, thereby ensuring that the output module 130 of the k-th stage shift register unit VSR(k) can output an effective pulse and realizing the low-frequency to high-frequency switching.

[0063] Optionally, on the basis of the above embodiment, continue to refer to Figure 9 , the period of the valid level of the first node N1 in the j-th stage shift register unit VSR(j), the period of the valid level of the second node N2 in the j-th stage shift register unit VSR(j), and the period of the valid level of the second refresh control signal Goff2 overlap. Similarly, when the first node N1 in the j-th stage shift register unit VSR(j) is at the high level and the second node N2 is at the high level, the second refresh control signal Goff2 is at the high level, thereby ensuring that the output module 130 of the j-th stage shift register unit VSR(j) can output an effective pulse and realizing the low-frequency to high-frequency switching.

[0064] Optionally, on the basis of the above embodiment, continue to refer to Figure 4 and Figure 9 , the display panel includes a first working process. In the first working process, the start time of the effective pulse of the second refresh control signal Goff2 is before the start time of the effective pulse of the first refresh control signal Goff1.

[0065] Specifically, the first working process may be a process of switching from low frequency to high frequency. The effective pulse of the second refresh control signal Goff2 can control the conduction between the first node N1 and the second node N2 in the second type of shift register unit 102, and the effective pulse of the first refresh control signal Goff1 can control the conduction between the first node N1 and the second node N2 in the first type of shift register unit 101. Furthermore, by setting the start time of the effective pulse of the second refresh control signal Goff2 to be before the start time of the effective pulse of the first refresh control signal Goff1, when the second refresh control signal Goff2 controls the second type of shift register unit 102 to switch from low frequency to high frequency (the first node N1 and the second node N2 in the second type of shift register unit 102 are conducted), the first type of shift register unit 101 arranged in the previous stage of the second type of shift register unit 102 can maintain the cut-off state between the first node N1 and the second node N2, avoiding the situation where when the first node N1 is at a high level (effective level) and the second node N2 is at a low level (ineffective level) in the first type of shift register unit 101, the capacitor near the second node N2 pulls down the potential of the first node N1 to the ineffective level when the first node N1 and the second node N2 are conducted, thus avoiding the problems of output and cascaded transmission failure of the first type of shift register unit 101.

[0066] Optionally, on the basis of the above embodiments, continue to refer to Figure 5 and Figure 9 , the display panel includes a first working process. In the first working process, the end time of the effective pulse of the third refresh control signal Goff3 is before the start time of the effective pulse of the second refresh control signal Goff2.

[0067] Specifically, the active pulse of the second refresh control signal Goff2 can control the conduction between the first node N1 and the second node N2 in the j-th stage shift register unit VSR(j). The active pulse of the third refresh control signal Goff3 is used to write the first level signal VGL to the second node N2. Then, when the third refresh control signal Goff3 is an active pulse, even if the active pulse of the second refresh control signal Goff2 controls the conduction between the first node N1 and the second node N2 in the j-th stage shift register unit VSR(j), since the first level signal VGL (invalid level) is continuously written to the second node N2, the potential of the second node N2 cannot be raised. As a result, the output module 130 of the j-th stage shift register unit VSR(j) cannot output an active pulse. Furthermore, by setting the end time of the active pulse of the third refresh control signal Goff3 to be before the start time of the active pulse of the second refresh control signal Goff2, that is, after setting the end of the active pulse of the third refresh control signal Goff3, setting the second refresh control signal Goff2 to be an active pulse, it is ensured that when the conduction between the first node N1 and the second node N2 in the j-th stage shift register unit VSR(j) is established, the potential of the second node N2 can be raised, and it is ensured that the output module 130 of the j-th stage shift register unit VSR(j) can output an active pulse.

[0068] Optionally, based on the above embodiments, continue to refer to Figure 4 and Figure 5 The shift register unit 10 includes a first output module 131 and a second output module 132. The shift module 120 includes a first shift module 121 and a second shift module 122. The input end of the first shift module 121 is electrically connected to the first input end of the second output module 132. The input end of the second shift module 122 is electrically connected to the first input end of the first output module 131. The input module 140 includes a first control end INF and a second control end INB. The output end of the first shift module 121 in the i-th stage shift register unit VSR(i) is electrically connected to the first control end INF of the input module 140 in the j-th stage shift register unit VSR(j). The output end of the second shift module 122 in the j-th stage shift register unit VSR(j) is electrically connected to the second control end INB of the input module 140 in the i-th stage shift register unit VSR(i).

[0069] Specifically, the first control end INF of the input module 140 receives the input signal from the previous-stage shift register unit 10, and the second control end INB of the input module 140 receives the input signal from the subsequent-stage shift register unit 10. Exemplarily, as Figure 4 and Figure 5As shown, let the subsequent shift register unit 10 of the j-th stage shift register unit VSR(j) be the k-th stage shift register unit VSR(k), where i, j, and k are adjacent positive integers. Then, the output terminal of the first shift module 121 of the j-th stage shift register unit VSR(j) is electrically connected to the first control terminal INF of the input module 140 in the k-th stage shift register unit VSR(k), and the output terminal of the second shift module 122 of the j-th stage shift register unit VSR(j) is electrically connected to the second control terminal INB of the input module 140 in the i-th stage shift register unit VSR(i). As Figure 4 As shown, the input terminal of the first shift module 121 is electrically connected to the first input terminal of the second output module 132, that is, the input terminal of the first shift module 121 is electrically connected to the second output clock signal terminal OUT2. The input terminal of the second shift module 122 is electrically connected to the first input terminal of the first output module 131, that is, the input terminal of the second shift module 122 is electrically connected to the first output clock signal terminal OUT1. The control terminals of the first shift module 121 and the second shift module 122 are both connected to the first node N1. The input module 140 includes a first transistor M1 and a second transistor M2. Among them, the first end of the first transistor M1 inputs a first scan control signal U2D, the second end of the first transistor M1 is connected to the first node N1, the control terminal of the first transistor M1 is electrically connected to the first control terminal INF, the first end of the second transistor M2 inputs a second scan control signal D2U, the second end of the second transistor M2 is connected to the first node N1, and the control terminal of the second transistor M2 is electrically connected to the second control terminal INB. The first scan control signal U2D can be an enable control signal for forward scanning from top to bottom. When the first scan control signal U2D is at an effective level, each stage of the shift register unit 10 can sequentially shift the control signal of the first control terminal INF from top to bottom, and the effective pulses of the gate driving signal are sequentially output; the second scan control signal D2U can be an enable control signal for reverse scanning from bottom to top. When the second scan control signal D2U is at an effective level, each stage of the shift register unit 10 can sequentially shift the control signal of the reverse second control terminal INB from bottom to top, and the effective pulses of the gate driving signal are sequentially output.

[0070] It should be noted that, based on the above embodiments, the reset module 160 includes a third transistor M3, a fourth transistor M4, and a fifth transistor M5. Among them, the first end of the third transistor M3 is connected to the first reset clock terminal RSTF, and the control end is connected to the first scan control signal U2D. The first end of the fourth transistor M4 is connected to the second reset clock terminal RSTB, and the control end is connected to the second scan control signal D2U. The second ends of the third transistor M3 and the fourth transistor M2 are both electrically connected to the control end of the fifth transistor M5. The first end of the fifth transistor M5 is connected to the second level signal VGH, and the second end is connected to the third node N3. Further, when the second scan control signal D2U is at an effective level, the fourth transistor M4 is turned on, so that the gate potential of the fifth transistor M5 is the same as the signal of the second reset clock terminal RSTB. When the signal of the second reset clock terminal RSTB is at an effective level, the fifth transistor M5 is turned on, and the signal of the third node N1 is the effective level of the second level signal VGH.

[0071] It should also be noted that, based on the above embodiments, continue to refer to Figure 4, the first switching unit 110 may include a sixth transistor M6, and the second switching unit 150 may include a seventh transistor M7. The control terminal of the sixth transistor M6 may receive a first refresh control signal Goff1 or a second refresh control signal Goff2. The first terminal of the sixth transistor M6 is connected to the first node N1, and the second terminal is connected to the second node N2. The control terminal of the seventh transistor M7 may receive a third refresh control signal Goff3, the first terminal may receive a first level signal VGL, and the second terminal is connected to the second node N2. The first output module 131 includes an eighth transistor M8 and a ninth transistor M9. Among them, the control terminal of the eighth transistor M8 (the first control terminal of the first output module 131) is electrically connected to the second node N2, the first terminal is electrically connected to the first output clock signal terminal OUT1, and the second terminal is connected to the second terminal of the ninth transistor M9 at the output terminal of the first output module 131. The first terminal of the ninth transistor M9 receives the first level signal VGL, and the control terminal (the second control terminal of the first output module 131) is electrically connected to the third node N3. The second output module 132 includes a tenth transistor M10 and an eleventh transistor M11. Among them, the control terminal of the tenth transistor M10 (the first control terminal of the second output module 132) is electrically connected to the second node N2, the first terminal is electrically connected to the second output clock signal terminal OUT2, and the second terminal is connected to the second terminal of the eleventh transistor M11 at the output terminal of the second output module 132. The first terminal of the eleventh transistor M11 receives the first level signal VGL, and the control terminal (the second control terminal of the second output module 132) is electrically connected to the third node N3. The first shift module 121 includes a twelfth transistor M12, and the second shift module 122 includes a thirteenth transistor M13. The control terminals of the twelfth transistor M12 and the thirteenth transistor M13 are both electrically connected to the first node N1. The first terminal of the twelfth transistor M12 is electrically connected to the second output clock signal terminal OUT2, and the second terminal outputs a shift input signal. The first terminal of the thirteenth transistor M13 is electrically connected to the first output clock signal terminal OUT1, and the second terminal outputs a shift input signal.

[0072] Optionally, on the basis of the above embodiments, continue to refer to Figure 1 and Figure 2 , the display panel includes a second working process. In the second working process, the valid pulses of the first refresh control signal Goff1 and the second refresh control signal Goff2 end at the same moment.

[0073] Specifically, the second working process may be a process of switching from high frequency to low frequency, that is, a process in which the shift register unit 10 switches from outputting an effective pulse to outputting an invalid level. Exemplarily, the shift register unit 10 includes a first switching unit 110. The control end of the first switching unit 110 receives the first refresh control signal Goff1 or the second refresh control signal Goff2. Then, by setting the first refresh control signal Goff1 and the second refresh control signal Goff2 to output invalid levels simultaneously during the second working process, the connection between the first node N1 and the second node N2 of the shift register unit 10 is cut off, that is, the shift register unit 10 outputs an invalid level, realizing the switching from high frequency to low frequency.

[0074] Optionally, on the basis of the above embodiment, Figure 12 is a schematic circuit structure diagram of another shift register circuit provided by an embodiment of the present invention. Refer to Figure 12 , the shift register unit 10 further includes a bootstrap capacitor C. The first electrode plate of the bootstrap capacitor C is electrically connected to the control end of the shift module 20, and the second electrode plate of the bootstrap capacitor C is electrically connected to the output end of the shift module 120.

[0075] Specifically, in the embodiment shown in Figure 12 , the shift module 120 includes a first shift module 121 and a second shift module 122. The control ends of the first shift module 121 and the second shift module 122 are both electrically connected to the first node N1. The input end of the first shift module 121 is electrically connected to the second output clock signal terminal OUT2, and the input end of the second shift module 122 is electrically connected to the first output clock signal terminal OUT1. In the related art, when the signal of the second output clock signal terminal OUT2 is transmitted to the next-level shift register unit 10 through the first shift module 121, due to the influence of the control transistor in the first shift module 121, there will be a problem of threshold voltage drop, resulting in voltage attenuation of the finally transmitted to the next-level shift register unit, and finally leading to the failure of the shift register unit to transmit. Similarly, the second shift module 122 also has the same problem. For this reason, in the present invention, bootstrap capacitors C are respectively arranged between the control ends and the output ends of the first shift module 121 and the second shift module 122. By using the coupling effect of the bootstrap capacitors, the gate potential of the control end of the shift module 120 is changed, so that the shift module 120 is fully turned on, thereby ensuring that there is no voltage loss during transmission.

[0076] Based on the same inventive concept, an embodiment of the present invention further provides a display device. Figure 13 is a schematic structure diagram of a display device provided by an embodiment of the present invention. As shown in Figure 13As shown, the display device includes the display panel 01 in the above embodiment. The display device includes the display panel 01 of any embodiment of the present invention. Therefore, the display device provided by the embodiment of the present invention has the corresponding beneficial effects of the display panel 01 provided by the embodiment of the present invention, which will not be elaborated here. Exemplarily, the display device may be an electronic device such as a mobile phone, a computer, a smart wearable device (for example, a smart watch), and a vehicle-mounted display device, etc., and the embodiment of the present invention does not limit this.

[0077] Note that the above is only the preferred embodiment of the present invention and the technical principles applied. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described here, and various obvious changes, re-adjustments, and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, it may also include more other equivalent embodiments, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, It includes a driving circuit, and the driving circuit includes a plurality of cascaded shift register units; The shift register unit includes a first switching unit, at least one shift module, and at least one output module; The control end of the shift module is connected to a first node, the shift module outputs a shift input signal, and the first control end of the output module is connected to a second node; the first end of the first switching unit is connected to the first node, the second end of the first switching unit is connected to the second node, and the control end of the first switching unit receives a first refresh control signal or a second refresh control signal; The plurality of shift register units include a first type of shift register unit and a second type of shift register unit. The first type of shift register unit receives the first refresh control signal, and the second type of shift register unit receives the second refresh control signal. The second refresh control signal is different from the first refresh control signal.

2. The display panel according to claim 1, wherein The shift register unit further includes a second switching unit. The first end of the second switching unit is connected to the second node, the second end of the second switching unit receives a first level signal, and the control end of the second switching unit receives a third refresh control signal.

3. The display panel according to claim 2, wherein It includes a first control signal line, a second control signal line, and a third control signal line; the control end of the first switching unit in the first type of shift register unit is connected to the first control signal line, the control end of the first switching unit in the second type of shift register unit is connected to the second control signal line, and the control ends of the second switching units in the first type of shift register unit and the second type of shift register unit are connected to the third control signal line.

4. The display panel according to claim 3, wherein The first type of shift register unit and the second type of shift register unit connected to the same third control signal line are arranged alternately.

5. The display panel according to claim 1, characterized in that The shift register unit further includes an input module, and the output end of the input module is connected to the first node; The first type of shift register unit includes an i-th stage shift register unit, and the second type of shift register unit includes a j-th stage shift register unit. The output end of the shift module in the i-th stage shift register unit is electrically connected to the control end of the input module in the j-th stage shift register unit; i and j are positive integers, and i is not equal to j; The display panel includes a first working process. In the first working process, the start time of the valid pulse of the second refresh control signal is before the end time of the valid pulse of the shift input signal generated by the i-th stage shift register unit.

6. The display panel according to claim 5, wherein The start time of the valid pulse of the second refresh control signal is before the start time of the valid pulse of the shift input signal generated by the i-th stage shift register unit.

7. The display panel according to claim 5, wherein The control end of the input module receives a start signal or the shift input signal as an input signal; The start time of the valid pulse of the second refresh control signal is after the end time of the valid pulse of the input signal received by the i-th stage shift register unit.

8. The display panel according to claim 5, characterized in that, The first type of shift register unit further includes a k-th stage shift register unit, and an output end of the shift module in the j-th stage shift register unit is electrically connected to a control end of the input module in the k-th stage shift register unit; k is a positive integer, k is not equal to i, and k is not equal to j; A start time of an effective pulse of the first refresh control signal is before an end time of an effective pulse of a shift input signal generated by the j-th stage shift register unit.

9. The display panel according to claim 8, wherein A start time of an effective pulse of the first refresh control signal is before a start time of an effective pulse of a shift input signal generated by the j-th stage shift register unit.

10. The display panel according to claim 8, characterized in that, A start time of an effective pulse of the first refresh control signal is after an end time of an effective pulse of an input signal received by the j-th stage shift register unit.

11. The display panel according to claim 8, wherein, A time period of an effective level of the first node in the i-th stage shift register unit, a time period of an invalid level of the second node in the i-th stage shift register unit, and a time period of an invalid level of the first refresh control signal overlap. A time period of an effective level of the first node in the k-th stage shift register unit, a time period of an effective level of the second node in the k-th stage shift register unit, and a time period of an effective level of the second refresh control signal overlap.

12. The display panel according to claim 5, characterized in that, A time period of an effective level of the first node in the j-th stage shift register unit, a time period of an effective level of the second node in the j-th stage shift register unit, and a time period of an effective level of the second refresh control signal overlap.

13. The display panel according to claim 5, wherein The at least one output module includes a first output module and a second output module; The at least one shift module includes a first shift module and a second shift module. An input end of the first shift module is electrically connected to a first input end of the second output module, and an input end of the second shift module is electrically connected to a first input end of the first output module; The input module includes a first control end and a second control end; An output end of the first shift module in the i-th stage shift register unit is electrically connected to the first control end of the input module in the j-th stage shift register unit; An output end of the second shift module in the j-th stage shift register unit is electrically connected to the second control end of the input module in the i-th stage shift register unit.

14. The display panel according to claim 1, characterized in that, The display panel includes a first working process. In the first working process, a start time of an effective pulse of the second refresh control signal is before a start time of an effective pulse of the first refresh control signal.

15. The display panel according to claim 2, wherein The display panel includes a first working process. In the first working process, an end time of an effective pulse of the third refresh control signal is before a start time of an effective pulse of the second refresh control signal.

16. The display panel according to claim 1, wherein The display panel includes a second working process. In the second working process, effective pulses of the first refresh control signal and the second refresh control signal end at the same moment.

17. The display panel according to claim 1, wherein, The shift register unit further includes a bootstrap capacitor. A first electrode plate of the bootstrap capacitor is electrically connected to a control end of the shift module, and a second electrode plate of the bootstrap capacitor is electrically connected to an output end of the shift module.

18. A display device, characterized in that, including the display panel according to any one of claims 1-17.

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