Display device and method for manufacturing display device

Abstract

The invention relates to a display device and a method for manufacturing the same. The display device includes: a substrate including an emission area and a non-emission area; a first bank layer positioned on the emission region of the substrate; a first bank insulating layer positioned on a side surface of the first bank layer; a second bank layer positioned on the first bank layer and including a tip protruding more than the side surface of the first bank layer toward the non-emission region; a pixel electrode positioned on the second bank layer; a light emitting layer positioned on the pixel electrode; a residual pattern positioned on the non-emission region of the substrate and spaced apart from the pixel electrode, where the residual pattern and the pixel electrode include the same material; and a pixel defining layer positioned on the residual pattern and covering the first bank layer, the second bank layer, and the pixel electrode.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority and all benefits arising therefrom to Korean Patent Application No. 10-2024-0009915, filed on January 23, 2024, the entire content of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device and a method of manufacturing the display device. Background Art

[0004] As the information society has developed, the demand for display devices for displaying images has increased and diversified. For example, display devices have been applied to various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart televisions. The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, or an organic light emitting display device. Among these flat panel display devices, since each of the plurality of pixels of the display panel includes a light emitting element that can emit light by itself, the light emitting display device can display an image without a backlight unit that supplies light to the display panel.

[0005] Recently, display devices have been applied to glasses-type devices for providing virtual reality and augmented reality. To be applied to glasses-type devices, the display device may be implemented in a very small size of 2 inches or less, but to achieve high resolution, the display device should have a high pixel integration. For example, the display device may have a high pixel integration of 1000 pixels per inch (PPI) or higher.

[0006] When the display device is implemented in a very small size but has a high pixel integration as described herein, the area of the emission region of the light emitting element is reduced, and thus, it is difficult to implement light emitting elements separated from each other for each emission region through a mask process. Summary of the Invention

[0007] Aspects of the present disclosure provide a display device and a method of manufacturing the display device. In terms of the display device, the method may be capable of forming pixel electrodes spaced apart from each other without a separate etching process and simultaneously solving a short circuit defect caused by contact between the pixel electrode and the bank structure.

[0008] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given hereinafter.

[0009] Details of other embodiments are described in the detailed description and illustrated in the drawings.

[0010] In an embodiment of the present disclosure, a display device includes: a substrate including an emission region and a non-emission region; a first bank layer positioned on the emission region of the substrate; a first bank insulating layer positioned on a side surface of the first bank layer; a second bank layer positioned on the first bank layer and including a tip protruding toward the non-emission region more than the side surface of the first bank layer; a pixel electrode positioned on the second bank layer; a light-emitting layer positioned on the pixel electrode; a residual pattern positioned on the non-emission region of the substrate and spaced apart from the pixel electrode, wherein the residual pattern and the pixel electrode include the same material; and a pixel defining layer positioned on the residual pattern and covering the first bank layer, the second bank layer, and the pixel electrode.

[0011] In an embodiment, the light-emitting layer may overlap with the first bank layer and the second bank layer in a direction perpendicular to the substrate.

[0012] In an embodiment, an undercut may be formed between the side surface of the first bank layer and the tip of the second bank layer, and the undercut overlaps with the light-emitting layer in the direction perpendicular to the substrate.

[0013] In an embodiment, the height of the first bank layer may be greater than the height of the second bank layer.

[0014] In an embodiment, the first bank layer and the second bank layer may include different respective metals or alloys.

[0015] In an embodiment, the first bank insulating layer may completely cover the side surface of the first bank layer.

[0016] In an embodiment, the first bank insulating layer may overlap with the light-emitting layer in a direction perpendicular to the substrate.

[0017] In an embodiment, the first bank insulating layer may include fluoride ions.

[0018] In an embodiment, the first bank insulating layer may include aluminum fluoride or fluorinated alumina.

[0019] In an embodiment, the second bank layer may include a first surface facing the pixel electrode and a side surface facing the non-emission region, and the pixel electrode covers the side surface of the second bank layer.

[0020] In an embodiment, the pixel electrode may be in contact with the side surface of the second bank layer.

[0021] In an embodiment, the second bank layer may further include a second surface opposite to the first surface, and the second bank insulating layer may be positioned on the second surface in a portion overlapping with the tip of the second bank layer.

[0022] In an embodiment, the second bank insulating layer may overlap with the light-emitting layer in a direction perpendicular to the substrate, and the second bank insulating layer may include titanium oxide.

[0023] In an embodiment, the pixel defining layer may completely cover the first bank insulating layer and the tip of the second bank layer.

[0024] In an embodiment, the pixel electrode may include: a first layer disposed on the second bank layer and including a metal; and a second layer disposed on the first layer and including a transparent conductive oxide (TCO).

[0025] In an embodiment, the residual pattern may include a first residual pattern and a second residual pattern, wherein the first residual pattern and the first layer include the same first material, and the second residual pattern and the second layer include the same second material.

[0026] In an embodiment of the present disclosure, a method of manufacturing a display device includes: forming a first bank layer on a substrate and forming a second bank layer on the first bank layer; removing portions of the second bank layer and the first bank layer; etching a part of the first bank layer such that the second bank layer includes a tip protruding from a side surface of the first bank layer; forming a bank insulating layer on the side surface of the first bank layer; and forming a pixel electrode on the second bank layer and forming a residual pattern on the substrate.

[0027] In an embodiment, the forming of the bank insulating layer may include injecting a fluorine ion gas or injecting a fluorine ion gas and oxygen.

[0028] In an embodiment, in the forming of the bank insulating layer, the bank insulating layer may completely cover the side surface of the first bank layer.

[0029] In an embodiment, the forming of the pixel electrode on the second bank layer and the forming of the residual pattern on the substrate may include disconnecting a material for forming the pixel electrode through the tip of the second bank layer, wherein the disconnecting of the material includes separating the material into the pixel electrode and the residual pattern.

[0030] A display device and a method for manufacturing the display device according to an embodiment include a bank structure having an undercut structure under a pixel electrode, so that a gap between pixel electrodes can be reduced, and thus, a high-resolution display device can be realized. In some aspects, the display device according to an embodiment includes a bank insulating layer on a side surface of the bank structure, so that a short-circuit defect caused by contact between the pixel electrode and the bank structure can be solved.

[0031] The effects of the present disclosure are not limited to the foregoing effects, and various other effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects and features of the present disclosure will become more apparent by referring to the embodiments of the present disclosure described in detail with reference to the accompanying drawings, in which:

[0033] Figure 1 is a perspective view showing a head-mounted electronic device according to an embodiment;

[0034] Figure 2 is Figure 1 an exploded perspective view of the head-mounted electronic device;

[0035] Figure 3 is a perspective view showing a head-mounted electronic device according to another embodiment;

[0036] Figure 4 is an exploded perspective view showing a display device according to an embodiment;

[0037] Figure 5 is a schematic cross-sectional view taken along line X1-X1' in Figure 4 of a display panel according to an embodiment;

[0038] Figure 6 is Figure 5 an enlarged cross-sectional view of region A1 of

[0039] Figure 7 is according to another embodiment Figure 5 an enlarged cross-sectional view of region A1 of

[0040] Figure 8 is a schematic cross-sectional view taken along line X1-X1' in Figure 4 of a display panel according to another embodiment; and

[0041] Figures 9 to 17 is a cross-sectional view sequentially showing a manufacturing process of a bank structure, a manufacturing process of a pixel electrode, and a manufacturing process of a pixel defining layer of a display panel according to an embodiment. DETAILED DESCRIPTION

[0042] The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. However, aspects supported by the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example aspects of the present disclosure to those skilled in the art. Like reference numerals refer to like elements throughout.

[0043] It will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or there can be intervening elements between the element and the other element. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements.

[0044] It will be understood that although the terms “first,” “second,” and “third,” etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, first component, first region, first layer, or first section discussed hereinafter could be termed a second element, second component, second region, second layer, or second section without departing from the teachings herein.

[0045] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. Unless the context clearly dictates otherwise, as used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms (including “at least one”). Thus, a reference to “an” element in the claims after a reference to “the” element includes one element and a plurality of the elements. For example, unless the context clearly dictates otherwise, “an element” and “at least one element” have the same meaning. “At least one” should not be construed as limiting “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that when used in this specification, the terms “comprises” and / or “comprising,” or “includes” and / or “including” specify the presence of the stated feature, region, whole, step, operation, element, and / or component, but do not preclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components, and / or groups thereof.

[0046] In addition, relative terms, such as by way of example "lower" or "bottom" and "upper" or "top", may be used herein to describe the relationship of one element to another element as shown in the figures. It will be understood that relative terms are intended to cover different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is flipped, an element described as on the "lower" side of other elements will then be oriented on the "upper" side of the other elements. Thus, depending on the particular orientation of the figures, the term "lower" can encompass both the "lower" and "upper" orientations. Similarly, if the device in one of the figures is flipped, an element described as "beneath" or "under" other elements will then be oriented "above" the other elements. Thus, the terms "beneath" or "under" can encompass both the upper and lower orientations.

[0047] Taking into account the measurements under discussion and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), as used herein "about" or "approximately" includes the stated value and means within an acceptable deviation of the particular value as determined by a person of ordinary skill in the art. For example, the term "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0048] As used herein, the term "substantially" means approximate or actual. The term "substantially equal" means approximately equal or actually equal. The term "substantially the same" means approximately the same or actually the same.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in a general dictionary, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0050] Embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments. Accordingly, variations in the shape of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, the embodiments described herein should not be construed as limited to the particular shapes of regions shown herein, but should include deviations in shape, for example, due to manufacturing. For example, regions shown or described as flat will generally have rough and / or non-linear features. In addition, sharp corners shown may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the exact shape of the regions and are not intended to limit the scope of the claims.

[0051] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0052] Figure 1 is a perspective view showing a head-mounted electronic device 1 according to an embodiment. Figure 2 is Figure 1 an exploded perspective view of the head-mounted electronic device 1.

[0053] Referring Figure 1 and Figure 2 According to an embodiment, the head-mounted electronic device 1 may include a display device 10, a display device housing part 110, a housing part cover 120, a first eyepiece 131, a second eyepiece 132, a head-mounted band 140, an intermediate frame 160, a first optical member 151, a second optical member 152, and a control circuit board 170.

[0054] The display device 10 may include a first display device 10_1 and a second display device 10_2. The first display device 10_1 provides an image to the user's left eye, and the second display device 10_2 provides an image to the user's right eye. The display device 10 will be described in detail later with reference to Figure 4 and Figure 5 and

[0055] The first optical member 151 may be disposed between the first display device 10_1 and the first eyepiece 131, and the second optical member 152 may be disposed between the second display device 10_2 and the second eyepiece 132. Each of the first optical member 151 and the second optical member 152 may include at least one convex lens.

[0056] The intermediate frame 160 may be disposed between the first display device 10_1 and the control circuit board 170 and between the second display device 10_2 and the control circuit board 170. The intermediate frame 160 is for supporting and fixing the first display device 10_1, the second display device 10_2, and the control circuit board 170.

[0057] The control circuit board 170 may be disposed between the intermediate frame 160 and the display device housing part 110. The control circuit board 170 may be connected to the first display device 10_1 and the second display device 10_2 through a connector. The control circuit board 170 may convert an image source input from the outside into digital video data, and transmit the digital video data to the first display device 10_1 and the second display device 10_2 through the connector.

[0058] The control circuit board 170 may transmit digital video data corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and transmit digital video data corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. Alternatively, the control circuit board 170 may transmit the same digital video data to the first display device 10_1 and the second display device 10_2.

[0059] The display device housing part 110 is for accommodating the display device 10, the intermediate frame 160, the first optical member 151, the second optical member 152, and the control circuit board 170. The housing part cover 120 is provided to cover an open surface of the display device housing part 110. The housing part cover 120 may include a first eyepiece 131 on which the user's left eye is disposed and a second eyepiece 132 on which the user's right eye is disposed. Figure 1 and Figure 2 Although the first eyepiece 131 and the second eyepiece 132 have been shown to be provided separately, embodiments of the present disclosure are not limited thereto. The first eyepiece 131 and the second eyepiece 132 may be combined into one eyepiece.

[0060] The first eyepiece 131 may be aligned with the first display device 10_1 and the first optical member 151, and the second eyepiece 132 may be aligned with the second display device 10_2 and the second optical member 152. Accordingly, the user may observe an image of the first display device 10_1 magnified into a virtual image by the first optical member 151 through the first eyepiece 131, and may observe an image of the second display device 10_2 magnified into a virtual image by the second optical member 152 through the second eyepiece 132.

[0061] The head-mounted band 140 is for fixing the display device housing part 110 to the user's head such that the first eyepiece 131 and the second eyepiece 132 of the housing part cover 120 may be maintained in a state where the first eyepiece 131 and the second eyepiece 132 are respectively disposed on the user's left eye and right eye. In an example where the display device housing part 110 is implemented to have a light weight and a small size, the head-mounted electronic device 1 may include, instead of the head-mounted band 140, Figure 3 the spectacle frame as shown.

[0062] In some aspects, the head-mounted electronic device 1 may further include a battery for supplying power, an external memory slot for accommodating an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a wireless fidelity (WiFi) module, or a Bluetooth module.

[0063] Figure 3 is a perspective view showing a head-mounted electronic device 1 according to another embodiment.

[0064] Reference Figure 3 , the head-mounted electronic device 1_1 according to another embodiment may be a glasses-type electronic device in which the display device housing part 120_1 is implemented to have a light weight and a small size. The head-mounted electronic device 1_1 according to another embodiment may include a display device 10, a left-eye lens 311, a right-eye lens 312, a support frame 350, glasses frame legs 341 and 342, an optical member 320, an optical path conversion member 330, and a display device housing part 120_1.

[0065] Figure 3 The display device 10 shown in Figure 2 may include a third display device 10_3. The third display device 10_3 may be substantially the same as the first display device 10_1 and the second display device 10_2 shown in Figure 4 and Figure 5 . The display device 10 will be described later with reference to

[0066] The display device housing part 120_1 may include the display device 10, the optical member 320, and the optical path conversion member 330. The image displayed in the display device 10 may be magnified by the optical member 320, converted in the optical path by the optical path conversion member 330, and provided to the user's right eye through the right-eye lens 312. Accordingly, the user may observe an augmented reality image in which the virtual image displayed in the display device 10 seen through his / her right eye and the real image seen through the right-eye lens 312 are combined with each other.

[0067] Figure 3 It has been shown in

[0068] Figure 4 that the display device housing part 120_1 is provided at the right end of the support frame 350, but the embodiments of the present disclosure are not limited thereto. For example, the display device housing part 120_1 may be provided at the left end of the support frame 350, and in this case, the image of the display device 10 may be provided to the user's left eye. Alternatively, the display device housing part 120_1 may be provided at both the left end and the right end of the support frame 350, and in this case, the user may observe the image displayed in the display device 10 through both his / her left eye and right eye.

[0069] Reference Figure 4, the display device 10 according to an embodiment is a device that displays dynamic images or static images. The display device 10 according to an embodiment can be applied to portable electronic devices, such as mobile phones, smartphones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs) as examples. For example, the display device 10 can be used as a display device for a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) device. Alternatively, the display device 10 can be applied to a smartwatch, a watch phone, or a head-mounted display (HMD) for implementing virtual reality and augmented reality.

[0070] The display device 10 according to an embodiment includes a display panel 410, a heat dissipation layer 420, a circuit board 430, a driving circuit 440, and a power supply circuit 450.

[0071] In a plan view, the display panel 410 may have a shape similar to a rectangular shape. For example, in a plan view, the display panel 410 may have a shape similar to a rectangular shape having a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction) that intersects the first direction (X-axis direction). In the display panel 410, the corners where the short side in the first direction (X-axis direction) and the long side in the second direction (Y-axis direction) intersect may be rounded with a predetermined curvature or be right angles. The shape of the display panel 410 in a plan view is not limited to a rectangular shape and may be a shape similar to other polygonal shapes, circular shapes, or elliptical shapes. The shape of the display device 10 in a plan view may follow the shape of the display panel 410 in a plan view, but embodiments of the present disclosure are not limited thereto.

[0072] The display area DA may be positioned at the center of the display panel 410 and may occupy most of the area of the display panel 410. The display area DA may include a pixel group PXG, and the pixel group PXG may be the smallest unit that emits white light. The pixel group PXG may include a plurality of pixels, for example, a first pixel SP1, a second pixel SP2, and a third pixel SP3. The first pixel SP1, the second pixel SP2, and the third pixel SP3 may emit light of the same color or emit light of different colors. The non-display area NDA may surround the edge of the display area DA.

[0073] The heat dissipation layer 420 may overlap with the display panel 410 in a third direction (Z-axis direction), which is the thickness direction of the display panel 410. The heat dissipation layer 420 may be disposed on one surface (e.g., the rear surface) of the display panel 410. The heat dissipation layer 420 is used to dissipate heat generated from the display panel 410. The heat dissipation layer 420 may include a layer formed of graphite or a metal having a high thermal conductivity, such as silver (Ag), copper (Cu), or aluminum (Al) as an example.

[0074] The circuit board 430 may be positioned on the non-display area NDA of the display panel 410 using a conductive adhesive member, such as an anisotropic conductive film as an example. The circuit board 430 may be a flexible printed circuit board or a flexible film having a flexible material. Figure 4 It has been shown in the figure that the circuit board 430 is not bent, but the circuit board 430 may be bent. In this case, one end of the circuit board 430 may be disposed on the rear surface of the display panel 410. One end of the circuit board 430 may be the end opposite to the other ends of the plurality of pads that are connected to the pad area of the display panel 410 using the conductive adhesive member of the circuit board 430.

[0075] The driving circuit 440 may receive digital video data and timing signals from the outside. The driving circuit 440 may generate a scan timing control signal, a emission timing control signal, and a data timing control signal for controlling the display panel 410 according to the timing signals.

[0076] The power supply circuit 450 may generate a plurality of panel driving voltages according to an external source voltage. For example, the power supply circuit 450 may generate a first driving voltage, a second driving voltage, and a third driving voltage, and supply the first driving voltage, the second driving voltage, and the third driving voltage to the display panel 410.

[0077] Each of the driving circuit 440 and the power supply circuit 450 may be formed as an integrated circuit (IC) and attached to one surface of the circuit board 430.

[0078] Figure 5 is a schematic cross-sectional view taken along the line X1-X1' in the Figure 4 of the display panel according to an embodiment.

[0079] Refer to Figure 5 , the display panel 410 includes a semiconductor backplane SBP, a light-emitting element backplane EBP, a light-emitting element layer EML, a encapsulation layer TFE, an optical layer OPL, and a cover layer CVL.

[0080] The semiconductor backplane SBP may include a semiconductor substrate SSUB including a plurality of transistors PTR, a plurality of semiconductor insulating films covering the plurality of transistors PTR, and a plurality of contact terminals CTE respectively electrically connected to the plurality of transistors PTR.

[0081] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first-type impurity. A plurality of well regions can be provided in the upper surface of the semiconductor substrate SSUB. The plurality of well regions can be regions doped with a second-type impurity. The second-type impurity can be different from the first-type impurity described herein. In an example where the first-type impurity is a p-type impurity, the second-type impurity can be an n-type impurity. Alternatively, when the first-type impurity is an n-type impurity, the second-type impurity can be a p-type impurity.

[0082] Each of the plurality of well regions includes a source region S corresponding to the source electrode of the transistor PTR, a drain region D corresponding to the drain electrode of the transistor PTR, and a channel region CH provided between the source region S and the drain region D.

[0083] Each of the source region S and the drain region D can be a region doped with a first-type impurity. The gate electrode GE of the transistor PTR can overlap the well region in the third direction (Z-axis direction). The channel region CH can overlap the gate electrode GE in the third direction (Z-axis direction). The source region S can be provided on one side of the gate electrode GE, and the drain region D can be provided on the other side of the gate electrode GE.

[0084] The first insulating layer SINS1 can be provided on the semiconductor substrate SSUB. The first insulating layer SINS1 can be formed as an inorganic film such as silicon carbonitride (SiCN) or silicon oxide (SiO x ) but the embodiments of the present disclosure are not limited thereto.

[0085] The second insulating layer SINS2 can be provided on the first insulating layer SINS1. The second insulating layer SINS2 can be formed as an inorganic film such as silicon oxide (SiO x ) but the embodiments of the present disclosure are not limited thereto.

[0086] A plurality of contact terminals CTE can be provided on the second insulating layer SINS2. Each of the plurality of contact terminals CTE can be connected to any one of the gate electrode GE, the source region S, and the drain region D of each of the plurality of transistors PTR through a hole penetrating the first insulating layer SINS1 and the second insulating layer SINS2.

[0087] Each of the plurality of contact terminals CTE can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or an alloy thereof.

[0088] The third insulating layer SINS3 may be disposed on a side surface of the contact terminal CTE. An upper surface of each of the plurality of contact terminals CTE may be exposed without being covered by the third insulating layer SINS3. The third insulating layer SINS3 may be formed as an inorganic film such as silicon oxide (SiO x 2), but embodiments of the present disclosure are not limited thereto.

[0089] The semiconductor substrate SSUB may be replaced with a glass substrate or a polymer resin substrate (such as a polyimide substrate as an example). In this case, thin film transistors may be disposed on the glass substrate or the polymer resin substrate. The glass substrate may be a rigid substrate that does not bend, and the polymer resin substrate may be a flexible substrate that can be bent or curved.

[0090] The light-emitting element backplane EBP includes a first metal layer ML1 to an eighth metal layer ML8, a plurality of vias VA1 to VA9, and a plurality of interlayer insulating layers INS1 to INS10.

[0091] The first metal layer ML1 to the eighth metal layer ML8 are used to implement circuits of pixels SP1 to SP3 by connecting a plurality of contact terminals CTE exposed from the semiconductor backplane SBP to each other.

[0092] The first interlayer insulating layer INS1 may be disposed on the semiconductor backplane SBP. Each of the plurality of first vias VA1 may penetrate the first interlayer insulating layer INS1 and be connected to a contact terminal CTE exposed from the semiconductor backplane SBP. Each of the plurality of first metal layers ML1 may be disposed on the first interlayer insulating layer INS1 and be connected to the first via VA1.

[0093] The second interlayer insulating layer INS2 may be disposed on the first interlayer insulating layer INS1 and the first metal layer ML1. Each of the plurality of second vias VA2 may penetrate the second interlayer insulating layer INS2 and be connected to the exposed first metal layer ML1. Each of the plurality of second metal layers ML2 may be disposed on the second interlayer insulating layer INS2 and be connected to the second via VA2.

[0094] The third interlayer insulating layer INS3 may be disposed on the second interlayer insulating layer INS2 and the second metal layer ML2. Each of the plurality of third vias VA3 may penetrate the third interlayer insulating layer INS3 and be connected to the exposed second metal layer ML2. Each of the plurality of third metal layers ML3 may be disposed on the third interlayer insulating layer INS3 and be connected to the third via VA3.

[0095] The fourth interlayer insulating layer INS4 can be disposed on the third interlayer insulating layer INS3 and the third metal layer ML3. Each of the plurality of fourth vias VA4 can penetrate the fourth interlayer insulating layer INS4 and be connected to the exposed third metal layer ML3. Each of the plurality of fourth metal layers ML4 can be disposed on the fourth interlayer insulating layer INS4 and be connected to the fourth via VA4.

[0096] The fifth interlayer insulating layer INS5 can be disposed on the fourth interlayer insulating layer INS4 and the fourth metal layer ML4. Each of the plurality of fifth vias VA5 can penetrate the fifth interlayer insulating layer INS5 and be connected to the exposed fourth metal layer ML4. Each of the plurality of fifth metal layers ML5 can be disposed on the fifth interlayer insulating layer INS5 and be connected to the fifth via VA5.

[0097] The sixth interlayer insulating layer INS6 can be disposed on the fifth interlayer insulating layer INS5 and the fifth metal layer ML5. Each of the plurality of sixth vias VA6 can penetrate the sixth interlayer insulating layer INS6 and be connected to the exposed fifth metal layer ML5. Each of the plurality of sixth metal layers ML6 can be disposed on the sixth interlayer insulating layer INS6 and be connected to the sixth via VA6.

[0098] The seventh interlayer insulating layer INS7 can be disposed on the sixth interlayer insulating layer INS6 and the sixth metal layer ML6. Each of the plurality of seventh vias VA7 can penetrate the seventh interlayer insulating layer INS7 and be connected to the exposed sixth metal layer ML6. Each of the plurality of seventh metal layers ML7 can be disposed on the seventh interlayer insulating layer INS7 and be connected to the seventh via VA7.

[0099] The eighth interlayer insulating layer INS8 can be disposed on the seventh interlayer insulating layer INS7 and the seventh metal layer ML7. Each of the plurality of eighth vias VA8 can penetrate the eighth interlayer insulating layer INS8 and be connected to the exposed seventh metal layer ML7. Each of the plurality of eighth metal layers ML8 can be disposed on the eighth interlayer insulating layer INS8 and be connected to the eighth via VA8.

[0100] The contact terminal CTE of the semiconductor backplane SBP and the first to sixth metal layers ML1 to ML6 of the light-emitting element backplane EBP can be connected to the drain region D, the source region S, and the gate electrode GE of the transistor PTR. In the example, the seventh metal layer ML7 and the eighth metal layer ML8 are connected to the drain region D, but can be connected to the source region S.

[0101] The first metal layer ML1 to the eighth metal layer ML8 and the first vias VA1 to the eighth vias VA8 may be formed of substantially the same material. Each of the first metal layer ML1 to the eighth metal layer ML8 and the first vias to the eighth vias VA1 to VA8 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or an alloy thereof. The first vias VA1 to the eighth vias VA8 may be formed of substantially the same material. The first interlayer insulating layer INS1 to the eighth interlayer insulating layer INS8 may be formed as an inorganic film such as silicon oxide (SiO x ) but embodiments of the present disclosure are not limited thereto.

[0102] The ninth interlayer insulating layer INS9 may be disposed on the eighth interlayer insulating layer INS8 and the eighth metal layer ML8. The ninth interlayer insulating layer INS9 may be formed as an inorganic film such as silicon oxide (SiO x ) but embodiments of the present disclosure are not limited thereto.

[0103] Each of the plurality of ninth vias VA9 may penetrate the ninth interlayer insulating layer INS9 and be connected to the exposed eighth metal layer ML8. Each of the plurality of ninth vias VA9 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or an alloy thereof.

[0104] The tenth interlayer insulating layer INS10 may be disposed on the ninth interlayer insulating layer INS9. The tenth interlayer insulating layer INS10 may overlap with the pixel electrode AND of the emission region EA to be described later, and the respective tenth interlayer insulating layers INS10 may be spaced apart from each other. The tenth interlayer insulating layer INS10 may be formed as an inorganic film such as silicon nitride (SiN x ) but embodiments of the present disclosure are not limited thereto. The ninth vias VA9 may penetrate the tenth interlayer insulating layer INS10.

[0105] The light-emitting element layer EML may be disposed on the light-emitting element backplane EBP. The light-emitting element layer EML may include a bank structure BNS, a bank insulating layer BINS, a light-emitting element ED, a first residual pattern RSD1 and a second residual pattern RSD2, and a pixel defining layer PDL.

[0106] The display panel 410 according to an embodiment may include an emission region EA and a non-emission region NLA. The emission region EA and the non-emission region NLA may be located in Figure 4 the display area DA.

[0107] The emission area EA may include a first emission area EA1, a second emission area EA2, and a third emission area EA3 that emit light of different colors. The first emission area EA1, the second emission area EA2, and the third emission area EA3 may emit red light, green light, and blue light, respectively, and the colors of the light emitted from the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be different from each other depending on the type of the light-emitting element ED to be described later. In an embodiment, the first emission area EA1 may emit red light (which is light of the first color), the second emission area EA2 may emit green light (which is light of the second color), and the third emission area EA3 may emit blue light (which is light of the third color), but the embodiments of the present disclosure are not limited thereto.

[0108] The first pixel SP1 may be positioned in a portion overlapping with the first emission area EA1, the second pixel SP2 may be positioned in a portion overlapping with the second emission area EA2, and the third pixel SP3 may be positioned in a portion overlapping with the third emission area EA3.

[0109] The non-emission area NLA may help prevent each light emitted from the first emission area EA1, the second emission area EA2, and the third emission area EA3 from mixing with each other. The pixel definition layer PDL may be positioned in the non-emission area NLA.

[0110] Figure 6 is Figure 5 an enlarged view of the area A1, and more particularly shows the bank structure BNS, the bank insulating layer BINS, the light-emitting element ED, and the pixel definition layer PDL of the light-emitting element layer EML.

[0111] Reference Figure 5 and Figure 6 , the bank structure BNS may be disposed on the tenth interlayer insulating layer INS10. The bank structure BNS may be positioned in a portion overlapping with the emission area EA. The bank structure BNS may include a first bank layer BN1 and a second bank layer BN2 stacked in sequence.

[0112] According to an embodiment, the first bank layer BN1 may be disposed on the tenth interlayer insulating layer INS10. The first bank layer BN1 may be connected to the ninth via VA9. The first bank layer BN1 and the ninth via VA9 may include the same material.

[0113] The first bank layer BN1 may include a plurality of patterns, and each pattern may be separated or spaced apart from each other in a first direction (X-axis direction) in a portion overlapping with the first emission region EA1, the second emission region EA2, and the third emission region EA3. That is, the first bank layer BN1 may have an island pattern. Each island pattern of the first bank layer BN1 may have a circular shape or a polygonal shape (such as a triangular shape or a rectangular shape as an example) in a plan view.

[0114] In some embodiments, the first bank layer BN1 may include a side surface 1c. The side surface 1c of the first bank layer BN1 may face the bank insulating layer BINS. The side surface 1c of the first bank layer BN1 may be recessed (concave) toward the center of the emission region EA compared to the side surface 2c of the second bank layer BN2.

[0115] The second bank layer BN2 according to an embodiment may be disposed on the first bank layer BN1. The second bank layer BN2 may include a plurality of patterns, and each pattern may be separated or spaced apart from each other in a first direction (X-axis direction) in a portion overlapping with the first emission region EA1, the second emission region EA2, and the third emission region EA3. In an embodiment, the second bank layer BN2 may have an island pattern. Each island pattern of the second bank layer BN2 may have a circular shape or a polygonal shape (such as a triangular shape or a rectangular shape as an example) in a plan view.

[0116] The first bank layer BN1 and the second bank layer BN2 according to an embodiment may include different materials. In other words, the first bank layer BN1 and the second bank layer BN2 may respectively include materials having different etching rates, and the second bank layer BN2 may include a material having an etching rate lower than that of the first bank layer BN1. As an example, the first bank layer BN1 may include aluminum (Al) or an aluminum alloy, and the second bank layer BN2 may include titanium (Ti) or a titanium alloy.

[0117] In some embodiments, the second bank layer BN2 may include a side surface 2c. The side surface 2c of the second bank layer BN2 may protrude more in a first direction (X-axis direction) than the side surface 1c of the first bank layer BN1. As described herein, in the manufacturing process of the bank structure BNS, the first bank layer BN1 may include a material having an etching rate higher than that of the second bank layer BN2. Therefore, the second bank layer BN2 may have a tip TIP that protrudes more in a first direction (X-axis direction) than the side surface 1c of the first bank layer BN1, and an undercut may be formed between the side surface 1c of the first bank layer BN1 and the tip TIP of the second bank layer BN2.

[0118] In some embodiments, the height H2 of the second bank layer BN2 may be less than the height H1 of the first bank layer BN1.

[0119] According to an embodiment, the bank insulating layer BINS may be disposed on the side surface 1c of the first bank layer BN1. The bank insulating layer BINS may be in complete contact with the side surface 1c of the first bank layer BN1 and may completely cover the side surface 1c of the first bank layer BN1.

[0120] The bank insulating layer BINS may be formed by injecting a fluorine-based gas (i.e., a fluorine ion gas) and oxygen after forming the bank structure BNS in a manufacturing process. Accordingly, the bank insulating layer BINS may include aluminum fluoride (AlF x ) and aluminum oxyfluoride (AlO x F y ). The manufacturing process will be described later.

[0121] The bank insulating layer BINS may solve or prevent a short circuit defect that occurs due to contact between the material for forming the pixel electrode AND according to an embodiment and the material for forming the first bank layer BN1 in the manufacturing process of the display panel 410. For ease of explanation, the bank insulating layer BINS has been shown covering the side surface 1c of the first bank layer BN1 with a uniform thickness, but embodiments of the present disclosure are not limited thereto. The bank insulating layer BINS may completely cover the side surface 1c of the first bank layer BN1 and may have various thicknesses. For example, the bank insulating layer BINS may have various thicknesses at respective portions where the bank insulating layer BINS is in contact with the side surface 1c of the first bank layer BN1.

[0122] According to an embodiment, the light-emitting element ED may be disposed on the second bank layer BN2. The light-emitting element ED may include a first light-emitting element ED1 disposed in the first emission region EA1, a second light-emitting element ED2 disposed in the second emission region EA2, and a third light-emitting element ED3 disposed in the third emission region EA3. The first light-emitting element ED1 may include a pixel electrode AND, a first light-emitting layer IL1, and a common electrode CAT, the second light-emitting element ED2 may include a pixel electrode AND, a second light-emitting layer IL2, and a common electrode CAT, and the third light-emitting element ED3 may include a pixel electrode AND, a third light-emitting layer IL3, and a common electrode CAT.

[0123] The first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 that overlap with the first emission region EA1, the second emission region EA2, and the third emission region EA3, respectively, can emit light of different colors according to the material of the light-emitting layer IL. For example, the first light-emitting element ED1 can emit red light (which is light of the first color), the second light-emitting element ED2 can emit green light (which is light of the second color), and the third light-emitting element ED3 can emit blue light (which is light of the third color). However, the embodiments of the present disclosure are not limited thereto, and the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 that overlap with the first emission region EA1, the second emission region EA2, and the third emission region EA3, respectively, can also emit light of the same color.

[0124] The pixel electrode AND according to an embodiment can be disposed on the second bank layer BN2. The pixel electrode AND can be electrically connected to the ninth via hole VA9 through the conductive bank structure BNS, and then connected to the drain region D or the source region S of the transistor PTR through the first via hole VA1 to the eighth via hole VA8, the first metal layer ML1 to the eighth metal layer ML8, and the contact terminal CTE.

[0125] The pixel electrode AND can include a first layer AND1 containing a metal and a second layer AND2 disposed on the first layer AND1 and containing a transparent conductive oxide (TCO).

[0126] As an example, the first layer AND1 can include any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), and the second layer AND2 can include one or more of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc indium tin oxide (ZITO), indium gallium zinc oxide (IGZO), and zinc tin oxide (ZTO). Figure 5 and Figure 6 Although the pixel electrode AND has been shown to have a multilayer structure, according to an embodiment, the pixel electrode AND can also be formed to have a single-layer structure.

[0127] The display panel 410 according to an embodiment includes a bank structure BNS having an undercut formed under a pixel electrode AND, and thus, the pixel electrode AND positioned to overlap with the first emission region EA1, the second emission region EA2, and the third emission region EA3 can be formed without a separate etching process. In other words, in the display panel 410 according to an embodiment, the second bank layer BN2 includes a tip TIP protruding more than the first bank layer BN1, and thus, a plurality of pixel electrodes AND positioned to be spaced apart from each other can be formed without a separate etching process. Therefore, in the display panel 410 according to an embodiment, a plurality of pixel electrodes AND adjacent to each other can be formed to have a very small gap therebetween, and the display panel 410 according to an embodiment can be applied to a display device capable of providing high resolution.

[0128] In some embodiments, the pixel electrode AND according to an embodiment can be disposed not only on the upper surface 2a of the second bank layer BN2, but also on the side surface 2c of the second bank layer BN2. The pixel electrode AND can cover the side surface 2c of the second bank layer BN2 and be in contact with the side surface 2c of the second bank layer BN2. The manufacturing process will be described later.

[0129] The residual pattern RSD according to an embodiment can be disposed on the ninth interlayer insulating layer INS9 in a portion overlapping with the non-emission region NLA. The residual pattern RSD can be a result formed when the material for forming the pixel electrode AND is disconnected from the pixel electrode AND rather than connected to the pixel electrode AND through the tip TIP of the second bank layer BN2 during the manufacturing process of the pixel electrode AND. For example, in the manufacturing process of the pixel electrode AND, the material for forming the pixel electrode AND can be divided into different parts due to the tip TIP of the second bank layer BN2.

[0130] The residual pattern RSD can include the same material as the pixel electrode AND. Therefore, when the pixel electrode AND has a multi-layer structure, the residual pattern RSD can also have a multi-layer structure, and the stacking structure of the residual pattern RSD can be the same as the stacking structure of the pixel electrode AND. As an example, the residual pattern RSD can include a first residual pattern RSD1 and a second residual pattern RSD2, wherein the first residual pattern RSD1 and the first layer AND1 of the pixel electrode AND can include the same first material, and the second residual pattern RSD2 and the second layer AND2 of the pixel electrode AND can include the same second material. For example, the residual pattern RSD can include a first residual pattern RSD1 including the same first material as the first layer AND1 of the pixel electrode AND and a second residual pattern RSD2 including the same second material as the second layer AND2 of the pixel electrode AND.

[0131] The residual pattern RSD can be disposed between a plurality of tenth interlayer insulating layers INS10 in a first direction (X-axis direction). The residual pattern RSD can be disposed at a lower position or level than the second bank layer BN2.

[0132] The pixel defining layer PDL according to an embodiment can be positioned on the tenth interlayer insulating layer INS10 and the residual pattern RSD. The pixel defining layer PDL can be positioned in a portion overlapping with the non-emitting region NLA. The bank structure BNS and the pixel electrode AND according to an embodiment can be insulated from each other and spaced apart in the first direction (X-axis direction), and the pixel defining layer PDL is interposed between the bank structure BNS and the pixel electrode AND.

[0133] In some embodiments, the pixel defining layer PDL can contact the residual pattern RSD, the bank insulating layer BINS, the tip TIP of the second bank layer BN2, and the pixel electrode AND. In some aspects, the pixel defining layer PDL can cover the undercut formed on the side surface 1c of the first bank layer BN1 and under the tip TIP of the second bank layer BN2.

[0134] The pixel defining layer PDL can include an inorganic insulating material such as at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, tantalum oxide, hafnium oxide, zinc oxide, and amorphous silicon, but is not limited thereto.

[0135] The light emitting layer IL according to an embodiment can be positioned on the pixel electrode AND and the pixel defining layer PDL. The light emitting layer IL can be positioned in a portion overlapping with the emitting region EA and the non-emitting region NLA. The light emitting layer IL can be above the bank structure BNS and the first bank insulating layer BINS1 in a third direction (Z-axis direction). In other words, the light emitting layer IL can be above the first bank layer BN1 and the second bank layer BN2 in a third direction (Z-axis direction). In another way of expression, according to the plan view, the light emitting layer IL can overlap with the bank structure BNS and the first bank insulating layer BINS1 in the first direction (X-axis direction) (i.e., parallel to the semiconductor substrate SSUB). According to the plan view, the light emitting layer IL can overlap with the first bank layer BN1 and the second bank layer BN2 in the first direction (X-axis direction) (i.e., parallel to the semiconductor substrate SSUB).

[0136] The light-emitting layer IL according to an embodiment may include a first light-emitting layer IL1, a second light-emitting layer IL2, and a third light-emitting layer IL3 positioned to overlap with a first emission region EA1, a second emission region EA2, and a third emission region EA3, respectively. The first light-emitting layer IL1, the second light-emitting layer IL2, and the third light-emitting layer IL3 may emit lights of different colors. For example, the first light-emitting layer IL1 disposed in the first emission region EA1 may emit red light having a peak wavelength in the range of 610 nm to 650 nm, the second light-emitting layer IL2 disposed in the second emission region EA2 may emit green light having a peak wavelength in the range of 510 nm to 550 nm, and the third light-emitting layer IL3 disposed in the third emission region EA3 may emit blue light having a peak wavelength in the range of 440 nm to 480 nm. The first emission region EA1 to the third emission region EA3 constituting one pixel may include light-emitting elements that emit lights of different colors to represent white grayscale. Alternatively, the light-emitting layer IL includes a plurality of materials that emit lights of different colors such that a single light-emitting layer may emit mixed light.

[0137] According to an embodiment, the common electrode CAT may be disposed on the light-emitting layer IL and the pixel defining layer PDL. The common electrode CAT may be positioned in a portion overlapping with the emission region EA and the non-emission region NLA. In other words, the common electrode CAT may be formed integrally.

[0138] The common electrode CAT may include a transparent conductive material to emit the light generated from the light-emitting layer IL. The common electrode CAT may receive a common voltage or a low-potential voltage. In an example where the pixel electrode AND receives a voltage corresponding to a data voltage and the common electrode CAT receives a low-potential voltage, a potential difference is formed between the pixel electrode AND and the common electrode CAT such that the light-emitting layer IL may emit light. As an example, the common electrode CAT may be formed of a transparent conductive material (TCO) such as ITO or IZO capable of transmitting light through it, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). In an example where the common electrode CAT is formed of a semi-transmissive conductive material, the light emission efficiency of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 may be improved by a microcavity.

[0139] The encapsulation layer TFE can be disposed on the light-emitting element layer EML. The encapsulation layer TFE can include at least one inorganic film to prevent oxygen or moisture from penetrating into the light-emitting element layer EML. In some aspects, the encapsulation layer TFE can include at least one organic film to protect the light-emitting element layer EML from foreign substances (such as dust for example). The encapsulation layer TFE can include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3 stacked in sequence. The first encapsulation layer TFE1 can be disposed on the common electrode CAT, the second encapsulation layer TFE2 can be disposed on the first encapsulation layer TFE1, and the third encapsulation layer TFE3 can be disposed on the second encapsulation layer TFE2.

[0140] The first encapsulation layer TFE1 and the third encapsulation layer TFE3 can be formed of an inorganic insulating material. As an example, the first encapsulation layer TFE1 and the third encapsulation layer TFE3 can include silicon nitride (SiN x ), silicon oxynitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), and aluminum oxide (AlO x ).

[0141] The second encapsulation layer TFE2 can be formed of an organic material. As an example, the second encapsulation layer TFE2 can include an acrylic resin, an epoxy resin, a silicone resin, a silicone acrylic resin, a phenolic resin, a polyamide resin, or a polyimide resin, etc.

[0142] The adhesive layer ADL can be a layer for adhesively bonding the encapsulation layer TFE and the optical layer OPL to each other. The adhesive layer ADL can be a double-sided adhesive member. In some aspects, the adhesive layer ADL can be a transparent adhesive member (such as a transparent adhesive or a transparent adhesive resin for example).

[0143] The optical layer OPL can include a plurality of first color filters CF1, second color filters CF2, and third color filters CF3, a plurality of lenses LNS, and a filling layer FIL.

[0144] The first color filters CF1, the second color filters CF2, and the third color filters CF3 can be disposed on the adhesive layer ADL. The first color filters CF1, the second color filters CF2, and the third color filters CF3 can include colorants (such as dyes or pigments that absorb light in wavelength bands other than a specific wavelength band), and can be disposed to correspond to the color of the light emitted from the emission region EA.

[0145] The first color filter CF1 may be a red color filter that is disposed to overlap with the first emission region EA1 and transmits only red light therethrough. The second color filter CF2 may be a green color filter that is disposed to overlap with the second emission region EA2 and transmits only green light therethrough, and the third color filter CF3 may be a blue color filter that is disposed to overlap with the third emission region EA3 and transmits only blue light therethrough.

[0146] Multiple lenses LNS may be respectively disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3. The multiple lenses LNS may be a structure for increasing the ratio of light directed to the front surface of the display panel 410 (or the front surface of the display device). The multiple lenses LNS may have a cross-sectional shape that bulges in the upward direction.

[0147] The filling layer FIL may be disposed on the multiple lenses LNS. The filling layer FIL may have a predetermined refractive index such that light propagates in the third direction (Z-axis direction) at the interface between the multiple lenses LNS and the filling layer FIL. In some aspects, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic film formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin, etc.

[0148] The cover layer CVL may be disposed on the optical layer OPL. The cover layer CVL may be a glass substrate or include a polymer resin. In an example where the cover layer CVL is a glass substrate, the cover layer CVL may be attached to the filling layer FIL. In this case, the filling layer FIL may be used to adhere the cover layer CVL. In an example where the cover layer CVL is a glass substrate, the cover layer CVL may be used as a packaging substrate. In an example where the cover layer CVL includes a polymer resin, the cover layer CVL may be directly applied to the filling layer FIL.

[0149] Figure 7 is according to another embodiment Figure 5 is an enlarged cross-sectional view of the region A1.

[0150] Reference Figure 7 , the display panel 410b according to another embodiment is different from the display panel 410 described herein (see Figure 6 ) in that the bank insulation layer BINS includes a first bank insulation layer BINS1 and a second bank insulation layer BINS2. Hereinafter, the differences between the display panel 410 and the display panel 410b will be described in detail.

[0151] In some embodiments, the first bank insulating layer BINS1 may be positioned on the side surface 1c of the first bank layer BN1. The first bank insulating layer BINS1 may have the same structure and characteristics as the bank insulating layer BINS of the display panel 410. That is, the first bank insulating layer BINS1 may completely cover the side surface 1c of the first bank layer BN1 and may be in complete contact with the side surface 1c of the first bank layer BN1.

[0152] In the manufacturing process of the display panel 410b, in a subsequent process after forming the bank structure BNS, the first bank insulating layer BINS1 may be formed on the side surface 1c of the first bank layer BN1 by injecting a fluorine-based gas or oxygen or injecting a fluorine-based gas and oxygen simultaneously. As an example, the first bank insulating layer BINS1 may include aluminum fluoride (AlF x ) and aluminum oxyfluoride (AlO x F y ).

[0153] In some embodiments, the second bank layer BN2 may include an upper surface 2a, a lower surface 2b, and a side surface 2c. The upper surface 2a may be the surface facing the pixel electrode AND, the lower surface 2b may be the surface opposite to the upper surface 2a, and the side surface 2c may be the surface connecting the upper surface 2a and the lower surface 2b to each other.

[0154] According to another embodiment, the second bank insulating layer BINS2 may be positioned on the lower surface 2b of the second bank layer BN2. The second bank insulating layer BINS2 may completely cover the lower surface 2b of the second bank layer BN2 and may be in complete contact with the lower surface 2b of the second bank layer BN2.

[0155] In the manufacturing process of the display panel 410b, in a subsequent process after forming the bank structure BNS, the second bank insulating layer BINS2 may be formed on the lower surface 2b of the second bank layer BN2 by injecting oxygen or injecting oxygen and a fluorine-based oxygen simultaneously. That is, the first bank insulating layer BINS1 and the second bank insulating layer BINS2 may be formed simultaneously in the same process. As an example, the second bank insulating layer BINS2 may include titanium dioxide (TiO2). Other repetitive descriptions will be omitted.

[0156] The second bank insulating layer BINS2 may be positioned to overlap with the tip TIP of the second bank layer BN2. For ease of explanation, Figure 7The second bank insulating layer BINS2 has been shown to be formed with the same thickness in [the reference], but embodiments of the present disclosure are not limited thereto. The second bank insulating layer BINS2 may cover the lower surface 2b of the second bank layer BN2 in a portion positioned to overlap with the tip TIP of the second bank layer BN2 and may have various thicknesses. For example, the second bank insulating layer BINS2 may have various thicknesses at respective portions of the second bank insulating layer BINS2 in contact with the lower surface 2b of the second bank layer BN2. In some aspects, the second bank insulating layer BINS2 may overlap with the light-emitting layer IL in the third direction (Z-axis direction).

[0157] Figure 8 is a schematic cross-sectional view taken along the Figure 4 line X1-X1' of a display panel according to another embodiment.

[0158] Refer to Figure 8 , the light-emitting layer ILs of the display panel 410s according to another embodiment are different from the light-emitting layer IL (refer to Figure 5 ) of the display panel 410 described herein (refer to Figure 5 ) in that the light-emitting layer ILs of the display panel 410s are integrally formed in a portion overlapping with the emission region EA and the non-emission region NLA. Hereinafter, the differences between the display panel 410 and the display panel 410s will be described in detail.

[0159] The light-emitting layer ILs according to another embodiment may have a tandem structure including a plurality of first light-emitting layers IL1s, second light-emitting layers IL2s, and third light-emitting layers IL3s that emit different lights. For example, the first light-emitting layers IL1s may emit light of a first color, the second light-emitting layers IL2s may emit light of a second color, and the third light-emitting layers IL3s may emit light of a third color. The first light-emitting layers IL1s, the second light-emitting layers IL2s, and the third light-emitting layers IL3s may be stacked in sequence.

[0160] The first light-emitting layers IL1s may have a structure in which a first hole transport layer, a first organic light-emitting layer that emits light of a first color, and a first electron transport layer are stacked in sequence. The second light-emitting layer IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer that emits light of a second color, and a second electron transport layer are stacked in sequence. The third light-emitting layers IL3s may have a structure in which a third hole transport layer, a third organic light-emitting layer that emits light of a third color, and a third electron transport layer are stacked in sequence.

[0161] The light-emitting layer ILs according to another embodiment may be positioned to overlap with the bank structure BNS and the bank insulating layer BINS in the third direction (Z-axis direction), and may also be positioned to overlap with the first residual pattern RSD1 and the second residual pattern RSD2. Other repetitive descriptions will be omitted.

[0162] Figures 9 to 17 are cross-sectional views sequentially showing a manufacturing process of a bank structure BNS of a display panel 410, a manufacturing process of a pixel electrode AND, and a manufacturing process of a pixel defining layer PDL according to an embodiment.

[0163] Reference Figures 9 to 17 describes example aspects of methods and processes supported by aspects of the present disclosure. In the description of the methods and processes herein, operations may be performed in an order different from the order shown and / or described, or operations may be performed in a different order or at different times. Specific operations may also be excluded from the methods and the processes, one or more operations may be repeated, or additional operations may be added. Descriptions such as an element "may be provided" and "may be formed" include methods, processes, and techniques for providing, forming, positioning, and modifying elements, etc. according to the example aspects described herein.

[0164] Reference Figures 9 to 11 , the process may include completely forming a tenth interlayer material layer INS10L on a ninth interlayer insulating layer INS9, and completely forming a first bank material layer BNL1L and a second bank material layer BNL2L on the tenth interlayer material layer INS10L. Although not shown in Figures 9 to 11 , the process may include providing the ninth interlayer insulating layer INS9 on a semiconductor backplane SBP, and first to eighth interlayer insulating layers INS1 to INS8 and first to eighth metal layers ML1 to ML8 of a light-emitting element backplane EBP, and its detailed structure is the same as the structure described with reference to Figure 5 herein. A detailed description thereof will be omitted.

[0165] Subsequently, the process may include forming a photoresist PR on the second bank material layer BNL2L. In an example, a plurality of photoresists PR may be formed, and the plurality of photoresists PR may be spaced apart from each other.

[0166] Next, the process may include performing a first etching process (first etch) using the plurality of photoresists PR as a mask. As an example, the first etching process (first etch) may be a dry etching process.

[0167] In this process, the process may include isotropically removing the tenth interlayer material layer INS10L, the first bank material layer BNL1L, and the second bank material layer BNL2L in portions where the photoresist PR is not formed. In some aspects, holes HOL may be formed in the portions where the tenth interlayer material layer INS10L, the first bank material layer BNL1L, and the second bank material layer BNL2L are removed, and the ninth interlayer insulating layer INS9 may be exposed in portions overlapping the holes HOL.

[0168] Subsequently, referring to Figure 12 and Figure 13 , the process may include forming a photoresist PR in the same portion as the first etching process (first etch), and the process may include performing a second etching process (second etch) using a plurality of photoresists PR as masks. As an example, the second etching process (second etch) may be a wet etching process.

[0169] In this process, the tenth interlayer material layer INS10L, the first bank material layer BNL1L, and the second bank material layer BNL2L overlapping the inside of the hole HOL can be anisotropically removed. Specifically, the first bank material layer BNL1L according to an embodiment may include a material having an etching rate higher than the etching rates of the second bank material layer BNL2L and the tenth interlayer material layer INS10L. Therefore, through the second etching process (second etch), the first bank material layer BNL1L may have a side surface recessed (concave) in the first direction (X-axis direction) compared to the second bank material layer BNL2L and the tenth interlayer material layer INS10L. In other words, the side surface of the second bank material layer BNL2L may protrude in the first direction (X-axis direction) compared to the side surface of the first bank material layer BNL1L.

[0170] In this process, the tenth interlayer material layer INS10L, the first bank material layer BNL1L, and the second bank material layer BNL2L may be formed in the shape of the tenth interlayer insulating layer INS10 and the bank structure BNS including the first bank layer BN1 and the second bank layer BN2 shown in Figure 5 . That is, the second bank layer BN2 may have a tip TIP protruding from the side surface of the first bank layer BN1, and an undercut may be formed between the side surface of the first bank layer BN1 and the tip TIP of the second bank layer BN2.

[0171] Next, referring to Figure 14 and Figure 15 , the process may include moving the display panel 410 to a dry etching chamber and injecting a fluorine-based gas, oxygen, or a fluorine-based gas and oxygen into the display panel 410.

[0172] The process may include forming a bank insulating layer BINS on the side surface of the first bank layer BN1. As described herein with reference to Figure 5 , the first bank layer BN1 according to an embodiment may include aluminum. Generally, aluminum ions can easily form stable ionic bonds with fluorine-based ions. Therefore, the process can easily form the bank insulating layer BINS on the side surface of the first bank layer BN1 without another separate process. The bank insulating layer BINS may cover the entire side surface of the first bank layer BN1.

[0173] Subsequently, referring toFigure 16 , the process may include forming a pixel electrode AND on the second bank layer BN2. The pixel electrode AND may be formed using a sputtering process or a thermal deposition method. Since the second bank layer BN2 includes tips TIP (see Figure 7 ), the material for forming the pixel electrode AND according to the embodiment may be formed such that the material is spaced apart from each other on the plurality of bank structures BNS without a separate etching process. Therefore, in the display panel 410 according to the embodiment, the gap between the pixel electrodes can be reduced, and thus, a high-resolution display device can be realized.

[0174] However, in some embodiments, the material for forming the pixel electrode AND may also be positioned on the ninth interlayer insulating layer INS9 in a portion that does not overlap with the bank structure BNS. The material for forming the pixel electrode AND formed on the ninth interlayer insulating layer INS9 in a portion that does not overlap with the bank structure BNS may be formed into Figure 5 the shape of the residual pattern RSD shown in

[0175] According to the embodiment, the pixel electrode AND may include a first layer AND1 and a second layer AND2, and thus, the residual pattern RSD may include a first residual pattern RSD1 and a second residual pattern RSD2.

[0176] Next, referring to Figure 17 , the process may include forming a pixel defining layer PDL that fills the undercut of the bank structure BNS and covers the residual pattern RSD. The pixel defining layer PDL may cover the edge of the pixel electrode AND.

[0177] Subsequently, although not shown in Figure 17 , the process may include manufacturing the display panel 410 by sequentially stacking Figure 5 's light-emitting layer IL, common electrode CAT, encapsulation layer TFE, adhesive layer ADL, and optical layer OPL. The light-emitting layer IL, common electrode CAT, encapsulation layer TFE, adhesive layer ADL, and optical layer OPL are the same as the light-emitting layer IL, common electrode CAT, encapsulation layer TFE, adhesive layer ADL, and optical layer OPL described herein with reference to Figure 5 , and thus, a detailed description thereof will be omitted.

[0178] The present invention should not be construed as limited to the embodiments set forth herein. On the contrary, the example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

[0179] While the invention has been particularly shown and described with reference to embodiments thereof, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. A display device, wherein, The display device includes: a substrate including an emission region and a non-emission region; a first bank layer positioned on the emission region of the substrate; a first bank insulating layer positioned on a side surface of the first bank layer; a second bank layer positioned on the first bank layer and including a tip protruding toward the non-emission region from the side surface of the first bank layer; a pixel electrode positioned on the second bank layer; a light-emitting layer positioned on the pixel electrode; a residual pattern positioned on the non-emission region of the substrate and spaced apart from the pixel electrode, wherein the residual pattern and the pixel electrode include the same material; and a pixel defining layer positioned on the residual pattern and covering the first bank layer, the second bank layer, and the pixel electrode.

2. The display device according to claim 1, wherein, The light-emitting layer overlaps with the first bank layer and the second bank layer in a direction perpendicular to the substrate.

3. The display device according to claim 2, wherein: an undercut is formed between the side surface of the first bank layer and the tip of the second bank layer, and the undercut overlaps with the light-emitting layer in the direction perpendicular to the substrate.

4. The display device according to claim 3, wherein, The height of the first bank layer is greater than the height of the second bank layer.

5. The display device according to claim 4, wherein, The first bank layer and the second bank layer include different respective metals or alloys.

6. The display device according to claim 1, wherein, The first bank insulating layer completely covers the side surface of the first bank layer.

7. The display device according to claim 6, wherein, The first bank insulating layer overlaps with the light-emitting layer in a direction perpendicular to the substrate.

8. The display device according to claim 7, wherein, The first bank insulating layer includes fluoride ions.

9. The display device according to claim 8, wherein, The first bank insulating layer includes aluminum fluoride or fluorinated alumina.

10. The display device according to claim 1, wherein: the second bank layer includes a first surface facing the pixel electrode and a side surface facing the non-emission region, and the pixel electrode covers the side surface of the second bank layer.

11. The display device according to claim 10, wherein, The pixel electrode is in contact with the side surface of the second bank layer.

12. The display device according to claim 11, wherein: the second bank layer further includes a second surface opposite to the first surface, and a second bank insulating layer is positioned on the second surface in a portion overlapping with the tip of the second bank layer.

13. The display device according to claim 12, wherein: the second bank insulating layer overlaps with the light-emitting layer in a direction perpendicular to the substrate, and the second bank insulating layer includes titanium oxide.

14. The display device according to claim 1, wherein, The pixel defining layer completely covers the first bank insulating layer and the tip of the second bank layer.

15. The display device according to claim 1, wherein, The pixel electrode includes: a first layer disposed on the second bank layer and including a metal; and a second layer disposed on the first layer and including a transparent conductive oxide.

16. The display device according to claim 15, wherein: the residual pattern includes a first residual pattern and a second residual pattern, wherein the first residual pattern and the first layer include the same first material, and the second residual pattern and the second layer include the same second material, and the second residual pattern covers the first residual pattern.

17. A method for manufacturing a display device, wherein, The method for manufacturing a display device includes: Form a first bank layer on a substrate and form a second bank layer on the first bank layer; Remove a portion of the second bank layer and the first bank layer; Etch a portion of the first bank layer such that the second bank layer includes a tip protruding from a side surface of the first bank layer; Form a bank insulating layer on the side surface of the first bank layer; and Form a pixel electrode on the second bank layer and form a residual pattern on the substrate.

18. The method for manufacturing a display device according to claim 17, wherein, The forming of the bank insulating layer includes injecting a fluoride ion gas or injecting a fluoride ion gas and oxygen.

19. The method for manufacturing a display device according to claim 18, wherein, In the forming of the bank insulating layer, the bank insulating layer completely covers the side surface of the first bank layer.

20. The method for manufacturing a display device according to claim 19, wherein, The forming of the pixel electrode on the second bank layer and the forming of the residual pattern on the substrate include disconnecting a material for forming the pixel electrode through the tip of the second bank layer, wherein the disconnecting of the material includes separating the material into the pixel electrode and the residual pattern.

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