Display device and method for manufacturing same

Abstract

The invention discloses a display device and a method for manufacturing the same. The display device includes: a substrate; a circuit layer; an element layer; and a packaging layer. The substrate comprises a display area; a non-display area; an aperture region; and a hole peripheral area disposed between the hole area and the display area; the circuit layer includes: an interlayer insulating layer disposed on the substrate; two or more package auxiliary portions disposed in the hole peripheral region on the interlayer insulating layer, where the two or more package auxiliary portions surround the hole region; and one or more recessed portions disposed between the two or more package auxiliary portions, where the one or more recessed portions are located on the interlayer insulating layer, each of the two or more package auxiliary portions has a cross-sectional shape whose width gradually widens as it extends away from the interlayer insulating layer in a direction from the substrate to the interlayer insulating layer.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2024 - 0009912, filed with the Korean Intellectual Property Office on January 23, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure relates to a display device and a method for manufacturing the same. Background art

[0004] As society becomes increasingly information - oriented, the demand for multifunctional display devices continues to grow. These devices are essential for many electronic products such as smart phones, digital cameras, laptop computers, navigation systems, and smart TVs.

[0005] The display device may be a flat - panel type such as a liquid - crystal display device, a field - emission display device, or a light - emitting display device. The light - emitting display device may include an organic light - emitting display device including organic light - emitting elements, an inorganic light - emitting display device including inorganic light - emitting elements such as inorganic semiconductors, and a micro - light - emitting display device including micro - light - emitting elements.

[0006] The organic light - emitting display device displays an image using light - emitting elements each including a light - emitting layer made of an organic material. The organic light - emitting display device uses self - emitting elements and can provide excellent performance in terms of power consumption, response speed, luminous efficiency, brightness, and viewing angle compared to other types of display devices.

[0007] One side surface of the display device serves as a display surface including a display area for presenting an image. The display area includes emission areas that emit light of various brightnesses and colors. Summary of the invention

[0008] The display device may include a light - transmissive hole disposed in a hole area surrounded by the display area.

[0009] The element layer may include light - emitting elements disposed in the emission areas, each light - emitting element including a first common layer between the anode electrode and the light - emitting layer and a second common layer between the light - emitting layer and the cathode electrode.

[0010] The cathode electrode and the second common layer are entirely disposed within the display area and may also be disposed in the hole area surrounded by the display area and in a hole peripheral area between the hole area and the display area.

[0011] Accordingly, the second common layer disposed adjacent to the light - transmissive hole contributes to the penetration of oxygen or moisture, which can significantly shorten the lifespan of the display device.

[0012] In view of the above, embodiments of the present disclosure provide a display device designed to extend its lifespan by delaying the penetration of oxygen or moisture through a second common layer in a peripheral region of a hole, and a method for manufacturing the display device.

[0013] According to an embodiment of the present disclosure, there is provided a display device including: a substrate; a circuit layer disposed on the substrate; an element layer disposed on the circuit layer; and a packaging layer disposed on the element layer, wherein the substrate includes: a display region in which an emission region is arranged; a non-display region adjacent to the display region; a hole region surrounded by the display region; and a hole peripheral region disposed between the hole region and the display region, and the circuit layer includes: an interlayer insulating layer disposed on the substrate; two or more packaging auxiliary portions disposed in the hole peripheral region on the interlayer insulating layer, wherein the two or more packaging auxiliary portions surround the hole region; and one or more recessed portions disposed between the two or more packaging auxiliary portions, wherein the one or more recessed portions are located on the interlayer insulating layer, and each of the two or more packaging auxiliary portions has a cross-sectional shape whose width gradually widens as it extends away from the interlayer insulating layer in a direction from the substrate to the interlayer insulating layer.

[0014] The display device further includes a light-transmitting hole in the hole region, wherein the light-transmitting hole penetrates the substrate, the circuit layer, the element layer, and the packaging layer.

[0015] The display device further includes one or more hole peripheral dams disposed between the two or more packaging auxiliary portions and the hole region, wherein the one or more hole peripheral dams surround the hole region, and the packaging layer includes: a first packaging layer disposed on the element layer; a second packaging layer disposed on the first packaging layer and overlapping with the display region; and a third packaging layer disposed on the first packaging layer and the second packaging layer, wherein the second packaging layer includes an organic insulating material extending to the one or more hole peripheral dams and spaced apart from the hole region, the first packaging layer and the third packaging layer include inorganic insulating materials and are in contact with each other in a region between the hole region and the one or more hole peripheral dams, and the two or more packaging auxiliary portions overlap with the second packaging layer.

[0016] The circuit layer further includes: a first source-drain conductive layer disposed on the interlayer insulating layer; a first planarization layer disposed in the display area on the interlayer insulating layer, wherein the first planarization layer is spaced apart from two or more package assisting portions and covers the first source-drain conductive layer; a second source-drain conductive layer disposed on the first planarization layer; and a second planarization layer disposed on the first planarization layer, wherein the second planarization layer covers the second source-drain conductive layer, and each of the two or more package assisting portions includes: a first assisting layer disposed on the interlayer insulating layer and spaced apart from the first planarization layer; and a second assisting layer disposed on the first assisting layer and formed in the same layer as the second source-drain conductive layer, wherein the second assisting layer covers the top surface of the first assisting layer, extends to a part of the side surface of the first assisting layer, and is spaced apart from the interlayer insulating layer.

[0017] The first assisting layer includes a negative photoresist material cured by exposure and has a cross-sectional shape whose width gradually widens as it extends away from the interlayer insulating layer in the direction from the substrate to the interlayer insulating layer.

[0018] Each of the two or more package assisting portions further includes one or more grooves disposed on the side facing an adjacent package assisting portion and formed on the side surface of the first assisting layer.

[0019] The first encapsulation layer overlapping the two or more package assisting portions is continuous, and the first encapsulation layer overlapping the one or more recessed portions is spaced apart from the second encapsulation layer.

[0020] The element layer includes: an anode electrode disposed in the emission area; a pixel defining layer disposed in the non-emission area between the emission areas, wherein the pixel defining layer covers the edge of each of the anode electrodes; a spacer layer disposed on the pixel defining layer; a first common layer disposed on the anode electrodes; a light emitting layer disposed on the first common layer; a second common layer disposed in the display area, wherein the second common layer covers the pixel defining layer, the spacer layer, and the light emitting layer; and a cathode electrode disposed on the second common layer.

[0021] The second common layer includes: two or more first divided portions disposed on the second assisting layer of each of the two or more package assisting portions; and one or more second divided portions disposed in the one or more recessed portions, wherein the one or more second divided portions are spaced apart from the two or more first divided portions.

[0022] Between the two or more package assisting portions, the cathode electrode is in contact with the interlayer insulating layer.

[0023] Each of the one or more hole peripheral dams includes two or more dam layers, and each of the two or more dam layers is disposed in the same layer as a corresponding one of the second planarization layer, the pixel definition layer, and the spacer layer.

[0024] The display device further includes: two or more dummy auxiliary portions disposed between the one or more hole peripheral dams and the hole region, wherein the two or more dummy auxiliary portions surround the hole region; and one or more dummy recessed portions disposed between the two or more dummy auxiliary portions, wherein the second common layer includes: two or more third divided portions disposed on the two or more dummy auxiliary portions; and one or more fourth divided portions disposed in the one or more dummy recessed portions, wherein the one or more fourth divided portions are spaced apart from the two or more third divided portions.

[0025] The circuit layer further includes: a buffer layer disposed on the substrate; a first gate insulating layer disposed on the buffer layer; and a second gate insulating layer disposed on the first gate insulating layer, wherein an interlayer insulating layer is disposed on the second gate insulating layer, and a light-transmitting hole penetrates through the third encapsulation layer, the first encapsulation layer, the cathode electrode, the second common layer, the interlayer insulating layer, the second gate insulating layer, the first gate insulating layer, the buffer layer, and the substrate.

[0026] According to an embodiment of the present disclosure, there is provided a method for manufacturing a display device, the method including: providing a substrate including: a display region in which an emission region is disposed; a non-display region disposed around the display region; a hole region surrounded by the display region; and a hole peripheral region disposed between the hole region and the display region; disposing a circuit layer on the substrate; disposing an element layer on the circuit layer; disposing an encapsulation layer on the element layer; and forming a light-transmitting hole penetrating through the substrate, the circuit layer, the element layer, and the encapsulation layer in the hole region, wherein the disposing of the circuit layer includes: disposing an interlayer insulating layer on the substrate; disposing a first source-drain conductive layer on the interlayer insulating layer; disposing a first planarization layer covering the first source-drain conductive layer on the interlayer insulating layer in the display region; disposing two or more first auxiliary layers surrounding the hole region on the interlayer insulating layer in the hole peripheral region by partially etching a negative photoresist material laminated on the interlayer insulating layer, wherein the two or more first auxiliary layers are spaced apart from the first planarization layer; disposing a second source-drain conductive layer on the first planarization layer and disposing two or more second auxiliary layers on the two or more first auxiliary layers; and disposing a second planarization layer covering the second source-drain conductive layer on the first planarization layer.

[0027] Each of the two or more first auxiliary layers has a cross-section whose width gradually decreases as it approaches the interlayer insulating layer, and the arrangement of the second source-drain conductive layer and the two or more second auxiliary layers includes: laminating a conductive material layer; and partially removing the conductive material layer to provide the second source-drain conductive layer on the first planarization layer and the two or more second auxiliary layers on the two or more first auxiliary layers, wherein the two or more second auxiliary layers cover the top surface of the two or more first auxiliary layers, extend to a part of the side surface of the two or more first auxiliary layers and are spaced apart from the interlayer insulating layer, and in the arrangement of the second source-drain conductive layer and the two or more second auxiliary layers, two or more encapsulation auxiliary parts each having a laminated structure of a first auxiliary layer and a second auxiliary layer are formed.

[0028] In the partial removal of the conductive material layer, between the two or more first auxiliary layers, a part of the interlayer insulating layer is removed together with the conductive material layer to form one or more recessed portions on the interlayer insulating layer.

[0029] The arrangement of the element layer includes: providing an anode electrode of the emission region on the second planarization layer; providing a pixel defining layer on the second planarization layer in the non-emission region between the emission regions and providing a spacer layer on a part of the pixel defining layer; providing a first common layer on the anode electrode; providing a light emitting layer on the first common layer; providing a second common layer covering the pixel defining layer, the spacer layer and the light emitting layer in the display region; and providing a cathode electrode on the second common layer, wherein the second common layer includes: two or more first dividing portions provided on the two or more second auxiliary layers; and one or more second dividing portions provided in the one or more recessed portions and spaced apart from the two or more first dividing portions.

[0030] The arrangement of the circuit layer further includes: after providing the second source-drain conductive layer and the two or more second auxiliary layers, performing an ashing process on the side surfaces of the two or more first auxiliary layers to form one or more grooves in each of the two or more first auxiliary layers, and the one or more grooves in each of the two or more first auxiliary layers are provided on the side facing the adjacent first auxiliary layer and are formed on the side surface of the first auxiliary layer.

[0031] In the setting of the pixel defining layer and the spacer layer, one or more hole peripheral dams are formed between two or more encapsulation assisting portions and the hole region and surround the hole region. The one or more hole peripheral dams include two or more dam layers, and each of the two or more dam layers is formed in the same layer as a corresponding one of the second planarization layer, the pixel defining layer, and the spacer layer. The setting of the encapsulation layer includes: a first encapsulation layer covering the cathode electrode and containing an inorganic insulating material; a second encapsulation layer provided on the first encapsulation layer and overlapping with the display region; and an inorganic insulating material laminated on the first encapsulation layer, and a third encapsulation layer provided to cover the second encapsulation layer. Wherein, the second encapsulation layer includes an organic insulating material extending to one or more hole peripheral dams, overlapping with two or more encapsulation assisting portions, and spaced apart from the hole region.

[0032] Some portions of the first encapsulation layer that overlap with two or more second assisting layers are connected to each other.

[0033] The display device according to an embodiment includes a substrate, a circuit layer provided on the substrate, an element layer provided on the circuit layer, and an encapsulation layer provided on the element layer.

[0034] The substrate includes a display region where emission regions are arranged, a non-display region provided around the display region, a hole region surrounded by the display region, and a hole peripheral region provided between the hole region and the display region.

[0035] The circuit layer includes: an interlayer insulating layer provided on the substrate; two or more encapsulation assisting portions provided in the hole peripheral region, on the interlayer insulating layer, and sequentially surrounding the hole region; and one or more recessed portions provided between the two or more encapsulation assisting portions and engraved on the interlayer insulating layer.

[0036] According to an embodiment, each of the two or more encapsulation assisting portions may include a first assisting layer provided on the interlayer insulating layer and a second assisting layer provided on the first assisting layer.

[0037] The first assisting layer includes a negative photoresist material cured by exposure, and thus may have a cross-sectional shape whose width gradually increases as it moves away from the interlayer insulating layer in the direction from the substrate to the interlayer insulating layer.

[0038] The second assisting layer may cover the top surface of the first assisting layer, extend to a part of the side surface of the first assisting layer, and be spaced apart from the interlayer insulating layer.

[0039] Accordingly, each of the two or more encapsulation assisting portions may have a cross-sectional shape in which its width gradually increases as it moves away from the interlayer insulating layer in the direction from the substrate to the interlayer insulating layer. In other words, the cross-section of each side surface of the two or more encapsulation assisting portions may have an inverted conical shape.

[0040] Thus, the second common layer may include a first divided portion disposed on the two or more encapsulation assisting portions and a second divided portion disposed on the interlayer insulating layer between the two or more encapsulation assisting portions and spaced apart from the first divided portion. In other words, the second common layer may be separated by the two or more encapsulation assisting portions. Accordingly, the generation of an oxygen or moisture permeation path through the second common layer can be delayed.

[0041] Furthermore, according to an embodiment, due to one or more recessed portions disposed between the two or more encapsulation assisting portions and engraved on the interlayer insulating layer, the separation distance between the side surface of the two or more encapsulation assisting portions and the interlayer insulating layer can be increased. Accordingly, the separation distance between the first divided portion and the second divided portion is increased, which further delays the formation of an oxygen or moisture permeation path through the second common layer.

[0042] Therefore, according to an embodiment, the lifespan of the display device can be increased.

[0043] In addition, according to an embodiment, the first assisting layer of the two or more encapsulation assisting portions includes a negative photoresist material. Due to the difference in exposure amount for each thickness, this allows it to relatively easily form an inverted conical cross-section.

[0044] Thus, even though the encapsulation assisting portions are included to separate the second common layer, the method for manufacturing the display device can remain uncomplicated. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The above and other features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0046] Figure 1 is a perspective view of a display device according to an embodiment;

[0047] Figure 2 is a plan view of the Figure 1 display device;

[0048] Figure 3 is a cross-sectional view taken along line A-A' of the Figure 2 ;

[0049] Figure 4 is a layout view of part B of the Figure 2 display device;

[0050] Figure 5 shows Figure 4 the equivalent circuit diagram of a pixel;

[0051] Figure 6 shows Figure 5 a cross-sectional view of a light-emitting element, a first transistor, and a sixth transistor;

[0052] Figure 7 illustrates Figure 2 the layout diagram of part C;

[0053] Figure 8 , Figure 9 and Figure 10 is a cross-sectional view taken along line D-D' according to an embodiment; Figure 7 ;

[0054] Figure 11 , Figure 12 and Figure 13 is a flowchart illustrating a method for manufacturing a display device according to an embodiment; and

[0055] Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 shows Figure 11 , Figure 12 and Figure 13 a process view of some of the steps; DETAILED DESCRIPTION

[0056] The features and methods of the present disclosure can be better understood by referring to the following detailed description of the embodiments and the accompanying drawings. However, the present disclosure can be implemented in many different forms and should not be limited to the embodiments set forth herein.

[0057] It will be understood that when an element or layer is referred to as being "on" another element or layer, the element or layer can be directly on the other element or layer, or intervening elements or layers are between them. Throughout the specification, like reference numerals refer to like elements. The shapes, sizes, ratios, angles, quantities, etc. depicted in the drawings are merely examples, and the present disclosure is not limited to the details illustrated.

[0058] Terms such as first, second, third, etc. may be used herein to distinguish various elements and should not impose any limitation. These terms are used to distinguish one element from another. Thus, the first element discussed below can be referred to as the second element.

[0059] The features of the various embodiments of the present disclosure can be partially or fully combined, combined, and interoperated in different technical ways. These embodiments can be implemented independently or together in a mutually dependent relationship.

[0060] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0061] Figure 1 is a perspective view illustrating a display device according to an embodiment. Figure 2 is illustrated Figure 1 a plan view of the display device of. Figure 3 is along Figure 2 a cross-sectional view taken along line A-A' of. Figure 4 is illustrated Figure 2 a layout view of part B of.

[0062] Referring to Figure 1 and Figure 2 , the display device 100 is a device for displaying moving images or still images. The display device 100 can be used as a display screen for various devices such as televisions, laptop computers, monitors, billboards, and Internet of Things (IoT) devices, as well as portable electronic devices such as mobile phones, smartphones, tablet personal computers (PCs), smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs).

[0063] The display device 100 can be a light-emitting display device such as an organic light-emitting display device using organic light-emitting diodes, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a micro light-emitting display device using micro or nano light-emitting diodes (LEDs). In the following description, it is assumed that the display device 100 is an organic light-emitting display device. However, the present disclosure is not limited thereto and can also be applied to display devices including organic insulating materials, organic light-emitting materials, and metal materials.

[0064] The display device 100 can be designed to be flat, but is not limited to this form. For example, the display device 100 can include curved portions formed at the left and right ends with a constant or varying curvature. Additionally, the display device 100 can be manufactured to be flexible, allowing it to be bent, folded, or curled.

[0065] As Figure 1 , Figure 2 and Figure 3 shown in, the display device 100 includes a substrate 110.

[0066] The substrate 110 may include a main area MA corresponding to the display surface of the display device 100 and a sub-area SBA protruding from one side of the main area MA.

[0067] As Figure 2 shown, the main area MA may include a display area DA mainly located in the center and a non-display area NDA provided around the display area DA.

[0068] The display area DA may be formed in a rectangular shape in a plan view having a short side extending in a first direction DR1 and a long side extending in a second direction DR2 intersecting the first direction DR1. The corners where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be rounded with a predetermined curvature or may form right angles. The planar shape of the display area DA is not limited to a rectangular shape and may alternatively be formed into another polygonal shape, circular shape, or elliptical shape.

[0069] The non-display area NDA may be provided at the edge of the main area MA to surround the display area DA.

[0070] The sub-area SBA may be an area protruding from the non-display area NDA of the main area MA to one side in the second direction DR2.

[0071] Figure 2 and Figure 3 FIG. shows a display device 100 in which a part of the sub-area SBA is in a bent state.

[0072] As Figure 2 and Figure 3 shown, a part of the sub-area SBA is bent, which allows another part of the sub-area SBA to be provided on the rear surface of the substrate 110 opposite to the display surface.

[0073] The display driving circuit 200 may be mounted on the sub-area SBA of the substrate 110, and the circuit board 300 may be attached to the sub-area SBA.

[0074] The display driving circuit 200 may be electrically connected to the data line DL (see Figure 3 ) of the circuit layer 120 (see Figure 5 ). The display driving circuit 200 may output a data signal Vdata (see Figure 5 ) based on the control signal and power supply voltage supplied from the circuit board 300.

[0075] The display driving circuit 200 may be provided as an integrated circuit (IC) and mounted on the sub-area SBA of the substrate 110 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic method. However, this is only an example, and one embodiment is not limited thereto. For example, the display driving circuit 200 may be mounted on the circuit board 300.

[0076] One end of the circuit board 300 can be attached to a pad disposed on an edge of the sub-region SBA of the substrate 110 by using an anisotropic conductive film.

[0077] The circuit board 300 can be a bendable flexible printed circuit board (FPCB), a rigid printed circuit board (PCB) maintaining a flat shape, or a composite printed circuit board having both a rigid printed circuit board and a flexible printed circuit board.

[0078] The substrate 110 according to an embodiment can include a hole region HLA surrounded by a display region DA and a hole peripheral region PHA disposed between the hole region HLA and the display region DA.

[0079] Reference Figure 3 , the display device 100 according to an embodiment includes a substrate 110, a circuit layer 120 disposed on the substrate 110, an element layer 130 disposed on the circuit layer 120, and a package layer 140 disposed on the element layer 130.

[0080] The display device 100 according to an embodiment can further include a cover window 150 disposed on the package layer 140. The cover window 150 can be joined to face the substrate 110. Alternatively, the cover window 150 can be coupled to a bracket below the rear surface of the substrate 110. The bracket can accommodate the substrate 110, the display driving circuit 200, and the circuit board 300.

[0081] The display device 100 according to an embodiment can further include a touch sensor layer 160 disposed on the package layer 140 (see Figure 6 ).

[0082] The display device 100 according to an embodiment can further include a polarization layer disposed on the package layer 140 to reduce reflection of external light.

[0083] The substrate 110 can be formed of an insulating material such as a polymer resin. For example, the substrate 110 can be formed of polyimide. The substrate 110 can be a flexible substrate capable of being bent, folded, or curled.

[0084] Alternatively, the substrate 110 can be formed of an insulating material such as glass.

[0085] The substrate 110 can include a main region MA and a sub-region SBA. The main region MA can include a display region DA and a non-display region NDA.

[0086] The circuit layer 120 may include a conductive layer, one or more semiconductor layers, and insulating layers therebetween. The circuit layer 120 may include transistors formed of one or more semiconductor layers and one or more conductive layers, and signal lines each formed of at least one of the conductive layers.

[0087] The element layer 130 may include light-emitting elements that emit light in response to a driving current applied by the circuit layer 120.

[0088] The encapsulation layer 140 may cover both the circuit layer 120 and the element layer 130, preventing oxygen or moisture from penetrating into the element layer 130.

[0089] The cover window 150 may include a light-transmitting material. The cover window 150 may be made of an inorganic material such as glass or an organic material such as a plastic or polymer material.

[0090] The display device 100 according to an embodiment may further include a light-transmitting hole TRH that overlaps with the hole region HLA and penetrates the substrate 110, the circuit layer 120, the element layer 130, and the encapsulation layer 140, and an optical device 400 disposed below the substrate 110 and overlapping with the light-transmitting hole TRH. The optical device 400 may process light incident through the light-transmitting hole TRH.

[0091] Reference Figure 4 , the display area DA of the substrate 110 of the display device 100 according to an embodiment may include an emission area EA. In addition, the display area DA may further include a non-emission area disposed in a gap between the emission areas EA.

[0092] The element layer 130 (see Figure 3 ) may include light-emitting elements LE (see Figure 5 ) respectively disposed in the emission areas EA.

[0093] The circuit layer 120 (see Figure 3 ) may include light-emitting pixel drivers EPD arranged side by side in a main area MA in a first direction DR1 and a second direction DR2. The light-emitting pixel drivers EPD may be electrically connected to the light-emitting elements LE of the element layer 130 (see Figure 5 ).

[0094] In a plan view, the emission area EA may have a rhombus shape or a rectangular shape. However, this is merely an example, and the planar shape of the emission area EA according to an embodiment is not limited to Figure 4 the shape illustrated therein. For example, in a plan view, the emission area EA may have a polygonal shape such as a square, pentagon, hexagon, etc., or may have a circular shape or an oval shape including curved edges.

[0095] The emission region EA may include a first emission region EA1 that emits light of a first color in a predetermined wavelength band, a second emission region EA2 that emits light of a second color in a wavelength band lower than that of the first color, and a third emission region EA3 that emits light of a third color in a wavelength band lower than that of the second color.

[0096] For example, the first color may be red having a wavelength band of approximately 600 nm to 750 nm. The second color may be green having a wavelength band of approximately 480 nm to 560 nm. The third color may be blue having a wavelength band of approximately 370 nm to 460 nm.

[0097] The first emission region EA1 and the third emission region EA3 may be alternately arranged in at least one of a first direction DR1 and a second direction DR2.

[0098] The second emission region EA2 may be arranged side by side in at least one of the first direction DR1 and the second direction DR2.

[0099] In addition, the second emission region EA2 may be adjacent to the first emission region EA1 and the third emission region EA3 in diagonal directions DR4 and DR5 that intersect the first direction DR1 and the second direction DR2.

[0100] Within the emission region EA, pixels PX that display their respective brightness and colors may be formed by the first emission region EA1, the second emission region EA2, and the third emission region EA3 that are adjacent to each other.

[0101] In other words, the pixels PX may serve as basic units that display various colors including white at a predetermined brightness.

[0102] Each of the pixels PX may include at least one first emission region EA1, at least one second emission region EA2, and at least one third emission region EA3 that are adjacent to each other. Accordingly, each of the pixels PX may display various colors by mixing the light emitted from the adjacent first emission region EA1, second emission region EA2, and third emission region EA3.

[0103] Figure 5 is a schematic circuit diagram of Figure 4 the pixels shown.

[0104] Referring to Figure 5 , the pixel PX may include a light-emitting pixel driver EPD and a light-emitting element LE. One of the light-emitting elements LE in the element layer 130 may be electrically connected between one of the light-emitting pixel drivers EPD in the circuit layer 120 and a second power line that transmits a second power supply ELVSS.

[0105] For example, the anode electrode of the light-emitting element LE is electrically connected to the light-emitting pixel driver EPD, and the cathode electrode of the light-emitting element LE may be applied with a second power supply ELVSS lower than the first power supply ELVDD.

[0106] The capacitor Cel connected in parallel with the light-emitting element LE refers to the parasitic capacitance between the anode electrode and the cathode electrode of the light-emitting element LE.

[0107] The circuit layer 120 may further include a first power supply line VDL for transmitting the first power supply ELVDD, a first initialization voltage line VGIL for transmitting the first initialization voltage VGINT, and a second initialization voltage line VAIL for transmitting the second initialization voltage VAINT.

[0108] The circuit layer 120 may further include a scan write line GWL for transmitting the scan write signal GW, a scan initialization line GIL for transmitting the scan initialization signal GI, a transmission control line ECL for transmitting the emission control signal EC, a gate control line GCL for transmitting the gate control signal GC, and a data line DL for transmitting the data signal Vdata.

[0109] One light-emitting pixel driver EPD of the circuit layer 120 may include a first transistor T1 configured to generate a driving current for driving the light-emitting element LE, and at least one capacitor PC1 and two or more transistors T2 to T7 electrically connected to the first transistor T1 or the light-emitting element LE.

[0110] The first transistor T1 may be electrically connected between the first node N1 and the second node N2.

[0111] The first electrode (e.g., source electrode) of the first transistor T1 may be electrically connected to the first node N1 and electrically connected to the first power supply line VDL through the fifth transistor T5.

[0112] The second electrode (e.g., drain electrode) of the first transistor T1 may be electrically connected to the second node N2 and electrically connected to the anode electrode of the light-emitting element LE through the sixth transistor T6.

[0113] The second transistor T2 may be electrically connected between the data line DL and the first node N1.

[0114] In other words, the first electrode of the first transistor T1 may be electrically connected to the data line DL through the second transistor T2.

[0115] The second transistor T2 may be turned on by the scan write signal GW of the scan write line GWL.

[0116] The gate electrode of the first transistor T1 may be electrically connected to the third node N3.

[0117] The capacitor PC1 can be electrically connected between the third node N3 and the first power supply line VDL.

[0118] Accordingly, the potential of the gate electrode of the first transistor T1 can be maintained at the voltage charged in the first power supply line VDL.

[0119] In addition, when the data signal Vdata of the data line DL is transmitted to the first electrode of the first transistor T1 through the turned-on second transistor T2, the voltage difference between the gate electrode and the first electrode of the first transistor T1 can be the difference between the first power supply ELVDD and the data signal Vdata.

[0120] In this case, when the voltage difference (e.g., gate-source voltage difference) between the gate electrode and the first electrode of the first transistor T1 becomes equal to or greater than the threshold voltage, the first transistor T1 can be turned on, thereby generating a drain-source current corresponding to the data signal Vdata.

[0121] Then, when the fifth transistor T5 and the sixth transistor T6 are turned on, the first transistor T1 can be connected in series with the light-emitting element LE between the first power supply line VDL and the second power supply line. Accordingly, the drain-source current corresponding to the data signal Vdata of the first transistor T1 can be supplied as a driving current for the light-emitting element LE.

[0122] Accordingly, the light-emitting element LE can emit light with a brightness corresponding to the data signal Vdata.

[0123] The third transistor T3 can be electrically connected between the second node N2 and the third node N3. In other words, the third transistor T3 can be electrically connected between the gate electrode and the second electrode of the first transistor T1.

[0124] The third transistor T3 can include a plurality of sub-transistors connected in series. For example, the third transistor T3 can include a first sub-transistor T31 and a second sub-transistor T32.

[0125] The first electrode of the first sub-transistor T31 can be connected to the gate electrode of the first transistor T1, the second electrode of the first sub-transistor T31 can be connected to the first electrode of the second sub-transistor T32, and the second electrode of the second sub-transistor T32 can be connected to the second electrode of the first transistor T1.

[0126] In this way, it is possible to prevent the potential of the gate electrode of the first transistor T1 from changing due to the leakage current caused by the third transistor T3 when the third transistor T3 is not turned on.

[0127] The first sub-transistor T31 and the second sub-transistor T32 can be turned on by a write scan signal GW of a write scan line GWL.

[0128] When the first sub-transistor T31 and the second sub-transistor T32 are turned on, the voltage difference between the second node N2 and the third node N3 can be initialized.

[0129] The fourth transistor T4 can be electrically connected between the third node N3 and the first initialization voltage line VGIL. In other words, the fourth transistor T4 can be connected between the gate electrode of the first transistor T1 and the first initialization voltage line VGIL.

[0130] The fourth transistor T4 can include a plurality of sub-transistors connected in series. For example, the fourth transistor T4 can include a third sub-transistor T41 and a fourth sub-transistor T42.

[0131] The first electrode of the third sub-transistor T41 can be connected to the gate electrode of the first transistor T1, the second electrode of the third sub-transistor T41 can be connected to the first electrode of the fourth sub-transistor T42, and the second electrode of the fourth sub-transistor T42 can be connected to the first initialization voltage line VGIL.

[0132] In this way, it is possible to prevent the potential of the gate electrode of the first transistor T1 from changing due to the leakage current caused by the fourth transistor T4 when the fourth transistor T4 is not turned on.

[0133] The third sub-transistor T41 and the fourth sub-transistor T42 can be turned on by a scan initialization signal GI of a scan initialization line GIL.

[0134] When the third sub-transistor T41 and the fourth sub-transistor T42 are turned on, the potential of the third node N3 can be initialized to a first initialization voltage VGINT.

[0135] The fifth transistor T5 can be electrically connected between the first node N1 and the first power supply line VDL.

[0136] The sixth transistor T6 can be electrically connected between the second node N2 and the fourth node N4.

[0137] The fourth node N4 can be electrically connected to the anode electrode of the light-emitting element LE.

[0138] The fifth transistor T5 and the sixth transistor T6 can be turned on by an emission control signal EC of an emission control line ECL.

[0139] The seventh transistor T7 can be electrically connected between the fourth node N4 and the second initialization voltage line VAIL.

[0140] The seventh transistor T7 can be turned on by the gate control signal GC of the gate control line GCL.

[0141] Through the turned-on seventh transistor T7, the potential of the fourth node N4 can be initialized to the second initialization voltage VAINT.

[0142] According to an embodiment, the first transistor T1 to the seventh transistor T7 can be P-type MOSFETs. Alternatively, among the first transistor T1 to the seventh transistor T7, the third transistor T3 and the fourth transistor T4 can be N-type MOSFETs instead of P-type MOSFETs.

[0143] Figure 6 is a cross-sectional view of Figure 5 the light-emitting element and the first and sixth transistors.

[0144] Referring to Figure 6 , the display device 100 according to an embodiment can include a substrate 110, a circuit layer 120 on the substrate 110, an element layer 130 on the circuit layer 120, and a packaging layer 140 on the element layer 130.

[0145] The display device 100 according to an embodiment can further include a touch sensor layer 160 on the packaging layer 140 and a cover window 150 on the touch sensor layer 160. The display device 100 can further include a polarization layer disposed between the touch sensor layer 160 and the cover window 150.

[0146] According to an embodiment, the circuit layer 120 can include an interlayer insulating layer 124 disposed on the substrate 110, a first source-drain conductive layer SDCDL1 (e.g., a first anode connection electrode ANCE1) disposed on the interlayer insulating layer 124, a first planarization layer 125 covering the first source-drain conductive layer SDCDL1, a second source-drain conductive layer SDCDL2 (e.g., a second anode connection electrode ANCE2) disposed on the first planarization layer 125, and a second planarization layer 126 covering the second source-drain conductive layer SDCDL2.

[0147] In addition, the circuit layer 120 can further include semiconductor layers CH1, E11, E21, CH6, E16, and E26 disposed on the substrate 110, a first gate insulating layer 122 covering the semiconductor layers, a first gate conductive layer (e.g., the gate electrode G1 of the first transistor T1 and the gate electrode G6 of the sixth transistor T6) disposed on the first gate insulating layer 122, a second gate insulating layer 123 covering the first gate conductive layer, and a second gate conductive layer (e.g., a capacitor electrode CAE) disposed on the second gate insulating layer 123.

[0148] The interlayer insulating layer 124 can be disposed on the second gate insulating layer 123 and cover the second gate conductive layer.

[0149] The circuit layer 120 may further include a buffer layer 121 covering the substrate 110.

[0150] In this case, the semiconductor layers CH1, E11, E21, CH6, E16, and E26 may be disposed on the buffer layer 121.

[0151] According to an embodiment, each of the light-emitting pixel drivers EPD may include a first transistor T1 and at least one capacitor PC1 (see Figure 5 ) electrically connected to the first transistor T1 or the light-emitting element LE (see Figure 5 ) and second transistors T2 to seventh transistors T7 (see Figure 5 ).

[0152] Figure 6 Shown Figure 5 is the light-emitting element LE and the first transistor T1 and the sixth transistor T6 of the light-emitting pixel driver EPD.

[0153] The semiconductor layers on the buffer layer 121 may include channel portions CH1 and CH6, first electrode portions E11 and E16, and second electrode portions E21 and E26 of each of the first transistor T1 and the sixth transistor T6.

[0154] In each of the first transistor T1 and the sixth transistor T6, the first electrode portions E11 and E16 may be respectively connected to one end of the channel portions CH1 and CH6, while the second electrode portions E21 and E26 may be respectively connected to the other end of the channel portions CH1 and CH6.

[0155] The second electrode portion E21 of the first transistor T1 may be connected to the first electrode portion E16 of the sixth transistor T6.

[0156] The first gate conductive layer on the first gate insulating layer 122 may include gate electrodes G1 and G6 of each of the first transistor T1 and the sixth transistor T6.

[0157] In the first transistor T1 and the sixth transistor T6, the gate electrodes G1 and G6 may respectively overlap the channel portions CH1 and CH6.

[0158] In the light-emitting pixel driver EPD, the second transistor T2 (see Figure 5 ), the first sub-transistor T31 (see Figure 5 ), the second sub-transistor T32 (see Figure 5 ), the third sub-transistor T41 (see Figure 5 ), the fourth sub-transistor T42 (see Figure 5 ), the fifth transistor T5 (see Figure 5) and the seventh transistor T7 (see Figure 5 ) and the first transistor T1 and the sixth transistor T6 are provided as the same P-type MOSFET. Therefore, redundant descriptions will be omitted below.

[0159] The second gate conductive layer on the second gate insulating layer 123 may include a capacitor electrode CAE.

[0160] The capacitor electrode CAE may overlap with the gate electrode G1 of the first transistor T1.

[0161] Accordingly, the first capacitor PC1 (see Figure 5 ) may be formed by an overlapping region between the capacitor electrode CAE and the gate electrode G1 of the first transistor T1.

[0162] The first source / drain conductive layer SDCDL1 on the interlayer insulating layer 124 may include a first anode connection electrode ANCE1.

[0163] The first anode connection electrode ANCE1 may be electrically connected to the second electrode portion E26 of the sixth transistor T6 through a first anode connection hole ANCH1.

[0164] The second source / drain conductive layer SDCDL2 on the first planarization layer 125 may include a second anode connection electrode ANCE2.

[0165] The second anode connection electrode ANCE2 may be electrically connected to the first anode connection electrode ANCE1 through a second anode connection hole ANCH2.

[0166] The anode electrode 131 of the element layer 130 may be disposed on the second planarization layer 126 and may be electrically connected to the second anode connection electrode ANCE2 through a third anode connection hole ANCH3.

[0167] Accordingly, the anode electrode 131 may be electrically connected to the second electrode portion E26 of the sixth transistor T6 through the first anode connection electrode ANCE1 and the second anode connection electrode ANCE2.

[0168] The element layer 130 on the circuit layer 120 may include light-emitting elements LE respectively disposed in the emission regions EA1, EA2, and EA3.

[0169] Each of the light-emitting elements LE may include a structure in which a light-emitting layer 133 is disposed between an anode electrode 131 and a cathode electrode 134 facing each other.

[0170] According to an embodiment, the element layer 130 may include an anode electrode 131 disposed in the emission region EA, a pixel defining layer 132 disposed in the non-emission region NEA and covering the edge of the anode electrode 131, a spacer layer 132' disposed on a part of the pixel defining layer 132, a light emitting layer 133 disposed on the anode electrode 131 respectively, and a cathode electrode 134 disposed on the light emitting layer 133, the pixel defining layer 132 and the spacer layer 132'.

[0171] In addition, each of the light emitting elements LE may further include a first common layer 135 disposed between the anode electrode 131 and the light emitting layer 133, and a second common layer 136 disposed between the light emitting layer 133 and the cathode electrode 134.

[0172] The encapsulation layer 140 may be disposed on the circuit layer 120 and cover the element layer 130.

[0173] The encapsulation layer 140 is designed to prevent oxygen or moisture from penetrating into the element layer 130, and reduce the electrical or physical influence on both the circuit layer 120 and the element layer 130.

[0174] The encapsulation layer 140 may include: a first encapsulation layer 141 disposed on the circuit layer 120, covering the element layer 130 and including an inorganic insulating material; a second encapsulation layer 142 disposed on the first encapsulation layer 141, overlapping with the element layer 130 in the display region DA and including an organic insulating material; and a third encapsulation layer 143 disposed on the first encapsulation layer 141, covering the second encapsulation layer 142 and including an inorganic insulating material.

[0175] The touch sensor layer 160 may be disposed on the encapsulation layer 140. The touch sensor layer 160 may include touch electrodes that detect signals varying with the touch of a person or an object, and sense the points where a touch has occurred in the main area MA.

[0176] The cover window 150 may be disposed on the touch sensor layer 160.

[0177] Figure 7 Is the layout diagram of Figure 2 part C of

[0178] Reference Figure 7 , the substrate 110 of the display device 100 according to an embodiment (see Figure 3 ) may include a hole region HLA surrounded by the display region DA and a hole peripheral region PHA disposed between the hole region HLA and the display region DA.

[0179] Penetrating through the substrate 110 (see Figure 3 ), the circuit layer 120 (see Figure 3 ), the element layer 130 (see Figure 3) and the light-transmitting hole TRH of the encapsulation layer 140 (see Figure 3 ) can be disposed in the hole region HLA. Figure 3 )

[0180] According to an embodiment, the circuit layer 120 (see Figure 3 ) may further include two or more encapsulation auxiliary parts ENAS disposed in the peripheral hole region PHA and sequentially surrounding the hole region HLA.

[0181] The two or more encapsulation auxiliary parts ENAS are used to separate the second common layer 136 (see Figure 6 ) of the element layer 130 (see Figure 6 ) disposed in the peripheral hole region PHA. Accordingly, permeation of oxygen or moisture through the second common layer 136 (see Figure 3 ) adjacent to the light-transmitting hole TRH of the hole region HLA can be delayed. Figure 6 )

[0182] The display device 100 according to an embodiment may further include one or more hole peripheral dams HPDM disposed between the hole region HLA and the two or more encapsulation auxiliary parts ENAS in the peripheral hole region PHA. The one or more hole peripheral dams HPDM may surround the hole region HLA.

[0183] The circuit layer 120 of the display device 100 according to an embodiment may further include two or more dummy auxiliary parts DMAS disposed between the hole region HLA and the one or more hole peripheral dams HPDM in the peripheral hole region PHA. The two or more dummy auxiliary parts DMAS may surround the hole region HLA.

[0184] According to an embodiment, the circuit layer 120 (see Figure 3 ) may include a light-emitting pixel driver EPD disposed in the display area DA in a first direction DR1 and a second direction DR2, and a data line DL extending in the second direction DR2 and transmitting a data signal Vdata (see Figure 5 ) to the light-emitting pixel driver EPD.

[0185] Since the light-emitting pixel driver EPD is disposed on both sides of the peripheral hole region PHA in the second direction DR2, the data line DL may include a hole-intersecting data line HIDL intersecting with the hole region HLA or the peripheral hole region PHA.

[0186] In other words, the data line DL may include a hole-intersecting data line HIDL intersecting with the hole region HLA or the peripheral hole region PHA and a normal data line NDL that is the remaining data line other than the hole-intersecting data line HIDL.

[0187] Each of the hole-intersecting data lines HIDL may include a first hole isolation line HINL1 on one side in the second direction DR2 facing the hole peripheral area PHA, a second hole isolation line HINL2 on the other side in the second direction DR2 facing the hole peripheral area PHA, and a hole bypass line HDE disposed in the hole peripheral area PHA and electrically connecting the first hole isolation line HINL1 and the second hole isolation line HINL2.

[0188] The hole bypass line HDE may be an arc-shaped curve disposed between two or more package assisting portions ENAS and the display area DA and extending around the two or more package assisting portions ENAS.

[0189] Each of the normal data lines NDL may not intersect the hole area HLA and the hole peripheral area PHA, and may not include the hole bypass line HDE.

[0190] According to an embodiment, the circuit layer 120 may further include dummy light-emitting pixel drivers DEPD disposed closest to the hole peripheral area PHA.

[0191] The dummy light-emitting pixel drivers DEPD may have the same structure as the light-emitting pixel drivers EPD, except that they are not electrically connected to the light-emitting elements LE (see Figure 3 ) of the element layer 130 (see Figure 5 ).

[0192] In the process of forming the light-transmitting holes TRH (see Figure 3 ) in the hole area HLA, physical or chemical shocks may be buffered by the dummy light-emitting pixel drivers DEPD. This reduces the possibility of damaging the light-emitting pixel drivers EPD during the forming process.

[0193] Figure 8 、 Figure 9 and Figure 10 are cross-sectional views taken along the line D-D’ according to an embodiment. Figure 7

[0194] Referring to Figure 8 , the circuit layer 120 of the display device 100 according to an embodiment may include: an interlayer insulating layer 124 disposed on the substrate 110; two or more package assisting portions ENAS disposed in the hole peripheral area PHA and on the interlayer insulating layer 124; and one or more recessed portions CCV disposed between the two or more package assisting portions ENAS and engraved on the interlayer insulating layer 124.

[0195] According to an embodiment, the circuit layer 120 may include: a first source-drain conductive layer SDCDL1 disposed on the interlayer insulating layer 124 (see Figure 6);Provided in the display area DA, on the interlayer insulating layer 124, spaced apart from two or more package assisting portions ENAS and covering the first source-drain conductive layer SDCDL1 (see Figure 6 ) is the first planarization layer 125; the second source-drain conductive layer SDCDL2 provided on the first planarization layer 125; and the second planarization layer 126 provided on the first planarization layer 125 and covering the second source-drain conductive layer SDCDL2.

[0196] The second source-drain conductive layer SDCDL2 may include a data line DL (see Figure 7 ).

[0197] The data line DL (see Figure 7 ) may include a via-intersecting data line HIDL (see Figure 7 ) and a normal data line NDL. The via-intersecting data line HIDL (see Figure 7 ) may include a first via isolation line HINL1 (see Figure 7 ), a second via isolation line HINL2 (see Figure 7 ) and a via bypass line HDE.

[0198] In other words, the second source-drain conductive layer SDCDL2 may include a normal data line NDL and a via bypass line HDE.

[0199] As Figure 6 shown, according to an embodiment, the element layer 130 may include an anode electrode 131 provided in the emission area EA (see Figure 4 ), a pixel defining layer 132 provided in the non-emission area NEA between the emission areas EA (see Figure 4 ) and covering the edge of the anode electrode 131, a spacer layer 132' provided on a part of the pixel defining layer 132, a first common layer 135 provided on the anode electrode 131, a light emitting layer 133 provided on the first common layer 135, a second common layer 136 covering the pixel defining layer 132, the spacer layer 132' and the light emitting layer 133, and a cathode electrode 134 provided on the second common layer 136.

[0200] The anode electrode 131 and the pixel defining layer 132 may be provided on the second planarization layer 126 of the circuit layer 120.

[0201] The spacer layer 132' may protrude in the third direction DR3 from some parts of the pixel defining layer 132.

[0202] As Figure 7As shown, according to an embodiment, the display device 100 may include one or more hole peripheral dams HPDM disposed between two or more encapsulation assist portions ENAS and the hole region HLA. One or more hole peripheral dams HPDM may surround the hole region HLA. In other words, one or more hole peripheral dams HPDM may be sequentially arranged between two or more encapsulation assist portions ENAS and the hole region HLA.

[0203] As Figure 8 shown, each of the one or more hole peripheral dams HPDM may include two or more dam layers DML1, DML2, and DML3.

[0204] Each of the two or more dam layers DML1, DML2, and DML3 may be disposed in the same layer as a corresponding one of the second planarization layer 126, the pixel definition layer 132, and the spacer layer 132'.

[0205] For example, each of the one or more hole peripheral dams HPDM may include a first dam layer DML1 formed in the same layer as the second planarization layer 126, a second dam layer DML2 formed in the same layer as the pixel definition layer 132, and a third dam layer DML3 formed in the same layer as the spacer layer 132'.

[0206] The encapsulation layer 140 of the display device 100 according to an embodiment may include a first encapsulation layer 141 disposed on the element layer 130, a second encapsulation layer 142 disposed on the first encapsulation layer 141 and overlapping the display area DA, and a third encapsulation layer 143 disposed on the first encapsulation layer 141 and covering the second encapsulation layer 142.

[0207] The second encapsulation layer 142 may include an organic insulating material extending to one or more hole peripheral dams HPDM and spaced apart from the hole region HLA.

[0208] Each of the first encapsulation layer 141 and the third encapsulation layer 143 may include an inorganic insulating material.

[0209] Since the second encapsulation layer 142 extends to one or more hole peripheral dams HPDM, the first encapsulation layer 141 and the third encapsulation layer 143 may be in contact with each other in a region between the hole region HLA and one or more hole peripheral dams HPDM in the hole peripheral region PHA.

[0210] In addition, the second encapsulation layer 142 may extend to one or more hole peripheral dams HPDM, and two or more encapsulation assist portions ENAS may be arranged between the display area DA and one or more hole peripheral dams HPDM in the hole peripheral region PHA. Accordingly, two or more encapsulation assist portions ENAS may overlap with the second encapsulation layer 142.

[0211] In this way, the second encapsulation layer 142 can protect two or more encapsulation assist parts ENAS from physical shock.

[0212] As described above, according to an embodiment, the second common layer 136 and the cathode electrode 134 of the element layer 130 can be entirely disposed within the display area DA.

[0213] Accordingly, as Figure 8 shown, the second common layer 136 and the cathode electrode 134 can also be disposed within the hole peripheral area PHA surrounded by the display area DA.

[0214] Since the second common layer 136 includes an organic material that is relatively permeable to oxygen or moisture, oxygen or moisture can easily enter the circuit layer 120 and the element layer 130 of the display area DA through the second common layer 136 and the light-transmitting holes TRH of the hole area HLA.

[0215] To prevent or delay this situation, as Figure 7 shown, the circuit layer 120 of the display device 100 according to an embodiment can include two or more encapsulation assist parts ENAS.

[0216] Two or more encapsulation assist parts ENAS can sequentially surround the hole area HLA. In other words, two or more encapsulation assist parts ENAS can be sequentially arranged around the hole area HLA.

[0217] As Figure 8 shown, the cross-section of each of the two or more encapsulation assist parts ENAS can have a shape in which its width gradually widens as it extends away from the interlayer insulating layer 124 in the third direction DR3 from the substrate 110 to the interlayer insulating layer 124. In other words, the side surface of each of the two or more encapsulation assist parts ENAS can have an inverted conical cross-section.

[0218] Accordingly, the second common layer 136 disposed within the hole peripheral area PHA can be separated by the inverted conical side surfaces of each of the two or more encapsulation assist parts ENAS. In other words, the second common layer 136 disposed within the hole peripheral area PHA can be divided into several parts without the need for an additional etching process or masking process for the second common layer 136. This separation of the second common layer 136 within the hole peripheral area PHA helps to delay the penetration of oxygen or moisture through the second common layer 136.

[0219] Therefore, even if the display device 100 according to an embodiment includes the light-transmitting holes TRH surrounded by the display area DA, a sharp drop in lifespan can be prevented by two or more encapsulation assist parts ENAS.

[0220] According to an embodiment, each of two or more encapsulation assist parts ENAS may include a first assist layer ASL1 disposed on the interlayer insulating layer 124 and spaced apart from the first planarization layer 125 of the display area DA, and a second assist layer ASL2 disposed on the first assist layer ASL1 and formed in the same layer as the second source-drain conductive layer SDCDL2. The first assist layer ASL1 disposed on the interlayer insulating layer 124 may be in direct contact with the interlayer insulating layer 124.

[0221] According to an embodiment, the first assist layer ASL1 may include a negative photoresist material cured by exposure.

[0222] Accordingly, when an exposure process is performed on the soft negative photoresist material laminated on the interlayer insulating layer 124 in a direction from the interlayer insulating layer 124 toward the substrate 110, a portion of the negative photoresist material closer to the interlayer insulating layer 124 may be exposed to a relatively small amount of light.

[0223] In other words, among the negative photoresist materials exposed during the exposure process, the upper materials spaced farther from the interlayer insulating layer 124 are exposed to a larger amount of light and thus may have a relatively larger width. In contrast, the lower materials adjacent to the interlayer insulating layer 124 are exposed to a smaller amount of light, causing them to aggregate together and thus have a relatively smaller width.

[0224] For example, the first assist layer ASL1 may have a thickness of about 1.5 μm to about 2.0 μm, enabling it to have an inverted conical cross-section due to exposure differences.

[0225] In this way, since the first assist layer ASL1 is made of a negative photoresist material, it may have an inverted conical cross-section shape with a gradually increasing width as it moves away from the interlayer insulating layer 124 in the third direction DR3.

[0226] Since the first assist layer ASL1 has an inverted conical cross-section shape, the second assist layer ASL2 may cover the top surface of the first assist layer ASL1 and extend to a part of the side surface of the first assist layer ASL1. That is, the second assist layer ASL2 may be disposed only on the part of the side surface of the first assist layer ASL1 connected to the top surface. In other words, the second assist layer ASL2 does not extend along the side surface of the first assist layer ASL1 to the interlayer insulating layer 124.

[0227] As described above, according to an embodiment, each of two or more encapsulation assist parts ENAS includes a first assist layer ASL1 made of a negative photoresist material, and thus may relatively easily have a cross-section shape with a gradually decreasing width as it approaches the interlayer insulating layer 124.

[0228] In addition, since setting two or more encapsulation assist parts ENAS does not require a separate mask process, the display device 100 can be manufactured more simply.

[0229] Since each side surface of two or more encapsulation assist parts ENAS has an inverted conical cross-section, it is difficult for the second common layer 136 provided in the hole peripheral area PHA to extend along each side surface of two or more encapsulation assist parts ENAS and reach the interlayer insulating layer 124. In other words, the second common layer 136 provided in the hole peripheral area PHA can be separated by two or more encapsulation assist parts ENAS.

[0230] Accordingly, the second common layer 136 provided in the hole peripheral area PHA may include two or more first divided parts 1361 provided on the second assist layer ASL2 of each of two or more encapsulation assist parts ENAS, and one or more second divided parts 1362 provided on the interlayer insulating layer 124 between two or more encapsulation assist parts ENAS and spaced apart from the two or more first divided parts 1361. Between two or more encapsulation assist parts ENAS, the cathode electrode 134 may be in contact with the interlayer insulating layer 124.

[0231] Since two or more encapsulation assist parts ENAS are spaced apart from the first planarization layer 125 of the display area DA, the two or more first divided parts 1361 may be separated from the second common layer 136 of the display area DA.

[0232] In addition, according to an embodiment, the circuit layer 120 may include one or more recessed parts CCV provided between two or more encapsulation assist parts ENAS and engraved on the interlayer insulating layer 124.

[0233] Accordingly, one or more second divided parts 1362 of the second common layer 136 provided in the hole peripheral area PHA may be provided in the one or more recessed parts CCV.

[0234] In this way, the separation distance between the two or more first divided parts 1361 and the one or more second divided parts 1362 can be further increased by the one or more recessed parts CCV engraved on the interlayer insulating layer 124, thereby further delaying the penetration of oxygen or moisture through the second common layer 136.

[0235] In addition, according to the embodiment, the circuit layer 120 may further include two or more dummy auxiliary portions DMAS disposed between the one or more hole peripheral dams HPDM and the hole region HLA and sequentially surrounding the hole region HLA. In addition, one or more dummy concave portions DMCCV may be disposed between the two or more dummy auxiliary portions DMAS.

[0236] The two or more dummy auxiliary portions DMAS and the one or more dummy concave portions DMCCV are the same as the two or more encapsulation auxiliary portions ENAS and the one or more concave portions CCV, except that they are disposed between the one or more hole peripheral dams HPDM and the hole region HLA and do not overlap with the second encapsulation layer 142. Therefore, redundant descriptions will be omitted below.

[0237] In other words, each of the two or more dummy auxiliary portions DMAS may include a first dummy auxiliary layer DASL1 disposed on the interlayer insulating layer 124. The two or more dummy auxiliary portions DMAS include a negative photoresist material and each has a side surface with an inverted conical cross-section. In addition, a second dummy auxiliary layer DASL2 is disposed on a part of the side surface and the top surface of the first dummy auxiliary layer DASL1. The second dummy auxiliary layer DASL2 is formed in the same layer as the second source-drain conductive layer SDCDL2.

[0238] The second source-drain conductive layer SDCDL2 may include a common data line NDL disposed in the display area DA, a hole bypass line HDE disposed in the hole peripheral area PHA, a second auxiliary layer ASL2, and a second dummy auxiliary layer DASL2.

[0239] One or more dummy concave portions DMCCV may be engraved on the interlayer insulating layer 124.

[0240] Accordingly, the second common layer 136 disposed in the hole peripheral area PHA may further include two or more third divided portions 1363 disposed on the two or more dummy auxiliary portions DMAS and one or more fourth divided portions 1364 disposed in the one or more dummy concave portions DMCCV and spaced apart from the two or more third divided portions 1363.

[0241] The circuit layer 120 may further include a buffer layer 121 disposed on the substrate 110, a first gate insulating layer 122 disposed on the buffer layer 121, and a second gate insulating layer 123 disposed on the first gate insulating layer 122. The interlayer insulating layer 124 may be disposed on the second gate insulating layer 123.

[0242] Each of the buffer layer 121, the first gate insulating layer 122, the second gate insulating layer 123, and the interlayer insulating layer 124 may include an inorganic insulating material.

[0243] Each of the second common layer 136 and the cathode electrode 134 may be entirely disposed within the display area DA.

[0244] Each of the first encapsulation layer 141 and the third encapsulation layer 143 may include an inorganic insulating material and may be entirely disposed within the display area DA.

[0245] Accordingly, the light transmissive hole TRH of the hole area HLA may penetrate through the third encapsulation layer 143, the first encapsulation layer 141, the cathode electrode 134, the second common layer 136, the interlayer insulating layer 124, the second gate insulating layer 123, the first gate insulating layer 122, the buffer layer 121, and the substrate 110.

[0246] Reference Figure 9 , the display device 100 according to an embodiment is substantially the same as the Figure 8 embodiment, except that each of the two or more encapsulation assisting portions ENAS further includes one or more grooves GRV. Accordingly, redundant descriptions will be omitted hereinafter.

[0247] In each of the two or more encapsulation assisting portions ENAS, one or more grooves GRV may be disposed on the side facing an adjacent encapsulation assisting portion ENAS and may be engraved on the side surface of the first assisting layer ASL1. One or more grooves GRV may be engraved on the portion of the side surface of the first assisting layer ASL1 where the second assisting layer ASL2 is not disposed. In other words, the second assisting layer ASL2 may not be located within the grooves GRV.

[0248] In this manner, due to the one or more grooves GRV, the side surface of each of the two or more encapsulation assisting portions ENAS may have a steeper inclination. Accordingly, the two or more first dividing portions 1361 disposed on the two or more encapsulation assisting portions ENAS are relatively unlikely to extend into the grooves GRV and may only extend to the periphery of the grooves GRV. Therefore, the separation distance between the two or more first dividing portions 1361 and the one or more second dividing portions 1362 can be ensured to be greater than or equal to the width of the grooves GRV.

[0249] In addition, according to the Figure 9 embodiment, the two or more dummy assisting portions DMAS may also further include one or more grooves GRV.

[0250] Accordingly, the penetration of oxygen or moisture through the second common layer 136 of the hole peripheral area PHA can be further delayed.

[0251] Reference Figure 10, except that some parts of the first encapsulation layer 141 that overlap with two or more encapsulation assist parts ENAS are connected to each other, the display device 100 according to another embodiment is the same as Figure 8 the embodiment of. Therefore, redundant descriptions will be omitted below.

[0252] In accordance with Figure 10 another embodiment shown in, when the gap between two or more encapsulation assist parts ENAS is less than Figure 8 the gap in the embodiment of, some parts of the first encapsulation layer 141 that overlap with two or more encapsulation assist parts ENAS may contact each other.

[0253] For example, in the embodiment shown in Figure 10 , the gap between two or more encapsulation assist parts ENAS may be greater than the sum of the thickness of the first divided part 1361 of the second common layer 136 and the thickness of the cathode electrode 134, but less than the sum of the thickness of the first divided part 1361 of the second common layer 136, the thickness of the cathode electrode 134, and the thickness of the first encapsulation layer 141.

[0254] In this way, an empty space surrounded by the first encapsulation layer 141 can be created in the area between two or more encapsulation assist parts ENAS. The second encapsulation layer 142 may not enter the empty space surrounded by the first encapsulation layer 141.

[0255] Accordingly, another part of the first encapsulation layer 141 that overlaps with one or more recessed parts CCV may be spaced apart from the second encapsulation layer 142.

[0256] Therefore, the penetration of oxygen or moisture through the second common layer 136 and the second encapsulation layer 142 can be delayed.

[0257] Figure 11 , Figure 12 and Figure 13 are flowcharts illustrating a method for manufacturing a display device according to an embodiment. Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 are process views showing some of the steps of Figure 11 , Figure 12 and Figure 13 .

[0258] Referring to Figure 11, A method for manufacturing a display device 100 according to an embodiment may include providing a substrate 110 (step S10), disposing a circuit layer 120 on the substrate 110 (step S20), disposing an element layer 130 on the circuit layer 120 (step S30), disposing a packaging layer 140 on the element layer 130 (step S40), and forming a light-transmitting hole TRH that penetrates the substrate 110, the circuit layer 120, the element layer 130, and the packaging layer 140 in a hole region HLA (see Figure 2 ).

[0259] In step S10 of providing the substrate 110, the substrate 110 may include a display region DA (see Figure 4 ) where an emission region EA is arranged, a non-display region NDA (see Figure 2 ) disposed around the display region DA, a hole region HLA (see Figure 2 ) surrounded by the display region DA, and a hole peripheral region PHA (see Figure 2 ) disposed between the display region DA and the hole region HLA. Figure 2 )

[0260] Refer to Figure 12 , step S20 of disposing the circuit layer 120 according to an embodiment may include: disposing an interlayer insulating layer 124 (see Figure 8 ) on the substrate 110 (step S210); disposing a first source-drain conductive layer SDCDL1 (see Figure 6 ) on the interlayer insulating layer 124 in the display region DA (step S220); disposing a first planarization layer 125 covering the first source-drain conductive layer SDCDL1 on the interlayer insulating layer 124 in the display region DA (step S230); disposing two or more first auxiliary layers ASL1 (see Figure 8 ) on the interlayer insulating layer 124 in the hole peripheral region PHA (step S240); disposing a second source-drain conductive layer SDCDL2 (see Figure 6 ) on the first planarization layer 125 and disposing two or more second auxiliary layers ASL2 on two or more first auxiliary layers ASL1 (step S250); and disposing a second planarization layer 126 covering the second source-drain conductive layer SDCDL2 on the first planarization layer 125 (step S260).

[0261] Step S20 of disposing the circuit layer 120 according to an embodiment may include, before step S210 of disposing the interlayer insulating layer 124, disposing semiconductor layers CH1, E11, E21, CH6, E16, and E26 (see Figure 6 ) on the substrate 110 (step S201), disposing a first gate insulating layer 122 covering the semiconductor layers CH1, E11, E21, CH6, E16, and E26 (see Figure 6and Figure 8 )(Step S202), a first gate conductive layer G1 and G6 are provided on the first gate insulating layer 122 (see Figure 6 )(Step S203), a second gate insulating layer 123 covering the first gate conductive layer G1 and G6 is provided (see Figure 6 and Figure 8 )(Step S204), and a second gate conductive layer CAE is provided on the second gate insulating layer 123 (see Figure 6 )(Step S205).

[0262] Reference Figure 13 , according to the embodiment, step S30 of setting the element layer 130 may include: setting an anode electrode 131 of the emission region EA on the second planarization layer 126 (see Figure 6 )(Step S310); setting a pixel defining layer 132 on the second planarization layer 126 in the non-emission region NEA disposed between the emission regions EA (see Figure 6 and Figure 8 ) and setting a spacer layer 132' on a part of the pixel defining layer 132 (see Figure 6 and Figure 8 )(Step S320); setting a first common layer 135 on the anode electrode 131 (see Figure 6 )(Step S330); setting a light emitting layer 133 on the first common layer 135 (see Figure 6 )(Step S340); setting a second common layer 136 in the display region DA (see Figure 6 and Figure 8 ) to cover the pixel defining layer 132, the spacer layer 132' and the light emitting layer 133 (Step S350); and setting a cathode electrode 134 on the second common layer 136 (see Figure 6 and Figure 8 )(Step S360).

[0263] Step S40 of setting the encapsulation layer 140 may include setting a first encapsulation layer 141 (see Figure 8 )(Step S410), setting a second encapsulation layer 142 (see Figure 8 )(Step S420), and setting a third encapsulation layer 143 (see Figure 8 )(Step S430).

[0264] Reference Figure 14 , in step S240, two or more first auxiliary layers ASL1 may be provided on the interlayer insulating layer 124 in the hole peripheral area PHA by partially etching the negative photoresist material laminated on the interlayer insulating layer 124.

[0265] Two or more first auxiliary layers ASL1 can be formed through portions of the negative photoresist material on the interlayer insulating layer 124 that are exposed during the exposure process.

[0266] Two or more first auxiliary layers ASL1 can sequentially surround the hole region HLA and can be spaced apart from the first planarization layer 125.

[0267] The cross-section of each of the two or more first auxiliary layers ASL1 can have a shape in which its width gradually widens as it extends away from the interlayer insulating layer 124 in the third direction DR3.

[0268] In step S240, two or more first dummy auxiliary layers DASL1 that are adjacent to the hole region HLA can be further provided than the two or more first auxiliary layers ASL1.

[0269] Reference Figure 15 and Figure 16 , step S250 can include providing a conductive material layer CDML that covers the first planarization layer 125, the two or more first auxiliary layers ASL1, and the two or more first dummy auxiliary layers DASL1, and partially removing the conductive material layer CDML using a mask layer MSK on the conductive material layer CDML.

[0270] As Figure 15 shown, some portions of the conductive material layer CDML laminated in the gaps between the two or more first auxiliary layers ASL1 and in the gaps between the two or more first dummy auxiliary layers DASL1 can be provided to have a relatively small thickness.

[0271] As Figure 16 shown, in the step of partially removing the conductive material layer CDML, the second source-drain conductive layer SDCDL2 can be formed from the portions of the conductive material layer CDML that remain after being masked by the mask layer MSK on the first planarization layer 125.

[0272] In the step of partially removing the conductive material layer CDML, two or more second auxiliary layers ASL2 can be provided by the conductive material layer CDML on the two or more first auxiliary layers ASL1. Accordingly, two or more encapsulation auxiliary portions ENAS each including a laminated structure of a first auxiliary layer ASL1 and a second auxiliary layer ASL2 can be provided.

[0273] In addition, in the step of partially removing the conductive material layer CDML, two or more second dummy auxiliary layers DASL2 can be provided by the conductive material layer CDML on two or more first dummy auxiliary layers DASL1. Accordingly, two or more dummy auxiliary portions DMAS of a laminated structure each including a first dummy auxiliary layer DASL1 and a second dummy auxiliary layer DASL2 can be provided.

[0274] In addition, since the conductive material layer CDML is disposed with a relatively small thickness between two or more first auxiliary layers ASL1 and between two or more first dummy auxiliary layers DASL1, in the step of partially removing the conductive material layer CDML, the interlayer insulating layer 124 can be exposed to an etching process after the conductive material layer CDML is removed.

[0275] In other words, between two or more first auxiliary layers ASL1, a portion of the interlayer insulating layer 124 can be removed together with the conductive material layer CDML. Accordingly, one or more recessed portions CCV can be formed on the interlayer insulating layer 124 between two or more first auxiliary layers ASL1.

[0276] In addition, one or more dummy recessed portions DMCCV can be formed between two or more first dummy auxiliary layers DASL1.

[0277] As Figure 17 shown, the method for manufacturing the display device 100 according to the Figure 9 embodiment may further include: after step S250, performing an ashing process on side surfaces of two or more first auxiliary layers ASL1.

[0278] Accordingly, one or more grooves GRV can be formed on side surfaces of each of two or more first auxiliary layers ASL1.

[0279] In addition, one or more grooves GRV can also be formed on side surfaces of each of two or more first dummy auxiliary layers DASL1.

[0280] In Figure 16 or Figure 17 the process of Figure 18 as shown, in step S260, the second planarization layer 126 can be disposed in the display area DA by partially removing the organic insulating material covering the second source / drain conductive layer SDCDL2 and two or more second auxiliary layers ASL2.

[0281] In addition, a first dam layer DML1 of one or more hole peripheral dams HPDM can be disposed between two or more encapsulation auxiliary portions ENAS and two or more dummy auxiliary portions DMAS.

[0282] As shown in Figure 19 In step S320, by partially removing the organic insulating material covering the anode electrode 131, two or more encapsulation auxiliary parts ENAS, two or more dummy auxiliary parts DMAS, and the first dam layer DML1, a pixel defining layer 132 of a non-emission area NEA can be provided by a part of the organic insulating material having a first thickness, and a spacer layer 132' can be provided by another part of the organic insulating material maintained at a second thickness greater than the first thickness.

[0283] In addition, the second dam layer DML2 and the third dam layer DML3 can be formed by another part of the organic insulating material on the first dam layer DML1. Accordingly, one or more hole peripheral dams HPDM can be provided in the hole peripheral area PHA.

[0284] Referring to Figure 20 , in step S350, the second common layer 136 can be provided by completely laminating an organic material in the display area DA, the hole peripheral area PHA surrounded by the display area DA, and the hole area HLA.

[0285] The second common layer 136 provided in the hole peripheral area PHA can include two or more first divided parts 1361 provided on two or more encapsulation auxiliary parts ENAS, and one or more second divided parts 1362 provided in one or more recessed parts CCV and spaced apart from the two or more first divided parts 1361.

[0286] The two or more first divided parts 1361 can be spaced apart from each other, and can also be spaced apart from the part of the second common layer 136 provided in the display area DA.

[0287] The second common layer 136 provided in the hole peripheral area PHA can further include two or more third divided parts 1363 provided on two or more dummy auxiliary parts DMAS, and one or more fourth divided parts 1364 provided in one or more dummy recessed parts DMCCV and spaced apart from the two or more third divided parts 1363.

[0288] Referring to Figure 21 , in step S360, the cathode electrode 134 can be provided by laminating a light-transmissive conductive material covering the second common layer 136 in the display area DA, the hole peripheral area PHA surrounded by the display area DA, and the hole area HLA.

[0289] Referring to Figure 22, in step S410, the first encapsulation layer 141 can be provided by laminating an inorganic insulating material covering the cathode electrode 134 in the display area DA, the hole peripheral area PHA and the hole area HLA surrounded by the display area DA.

[0290] According to Figure 10 the embodiment shown in, in step S410, some portions of the first encapsulation layer 141 that overlap with two or more second auxiliary layers ASL2 can be connected to each other. In other words, the portions of the first encapsulation layer 141 that overlap with two or more second auxiliary layers ASL2 can be in direct physical contact or electrical contact with each other.

[0291] After Figure 22 the process of, as Figure 23 shown in, in step S420, the second encapsulation layer 142 can be provided by spreading the liquid organic insulating material dropped on the display area DA onto one or more hole peripheral dams HPDM and then curing it.

[0292] Then, in step S430, the third encapsulation layer 143 can be provided by laminating an inorganic insulating layer covering the second encapsulation layer 142 in the display area DA, the hole peripheral area PHA and the hole area HLA surrounded by the display area DA.

[0293] Then, as Figure 24 shown in, in step S50, a light-transmitting hole TRH that penetrates the third encapsulation layer 143, the first encapsulation layer 141, the cathode electrode 134, the second common layer 136, the interlayer insulating layer 124, the second gate insulating layer 123, the first gate insulating layer 122, the buffer layer 121, and the substrate 110 can be formed by performing chemical or mechanical etching in the hole area HLA.

[0294] However, the effects of the present disclosure are not limited to the effects described herein. By referring to the claims, additional effects will become more apparent to those skilled in the art.

Claims

1. A display device, comprising: a substrate; a circuit layer disposed on the substrate; an element layer disposed on the circuit layer; and a packaging layer disposed on the element layer, wherein the substrate includes: a display area in which an emission area is arranged; a non-display area adjacent to the display area; a hole area surrounded by the display area; and a hole peripheral area disposed between the hole area and the display area, and the circuit layer includes: an interlayer insulating layer disposed on the substrate; two or more packaging auxiliary portions disposed on the interlayer insulating layer in the hole peripheral area, wherein the two or more packaging auxiliary portions surround the hole area; and one or more recessed portions disposed between the two or more packaging auxiliary portions, wherein the one or more recessed portions are located on the interlayer insulating layer, wherein each of the two or more packaging auxiliary portions has a cross-sectional shape whose width gradually widens as it extends away from the interlayer insulating layer in a direction from the substrate to the interlayer insulating layer.

2. The display device according to claim 1, further comprising a light-transmitting hole in the hole region, wherein, The light-transmitting hole penetrates the substrate, the circuit layer, the element layer, and the packaging layer.

3. The display device according to claim 2, further comprising one or more hole peripheral dams disposed between the two or more encapsulation assisting portions and the hole region, wherein, The one or more hole peripheral dams surround the hole area, wherein the packaging layer includes: a first packaging layer disposed on the element layer; a second packaging layer disposed on the first packaging layer and overlapping with the display area; and a third packaging layer disposed on the first packaging layer and the second packaging layer, wherein the second packaging layer includes an organic insulating material extending to the one or more hole peripheral dams and spaced apart from the hole area, the first packaging layer and the third packaging layer include an inorganic insulating material and are in contact with each other in a region between the hole area and the one or more hole peripheral dams, and the two or more packaging auxiliary portions overlap with the second packaging layer.

4. The display device according to claim 3, wherein, The circuit layer further includes: a first source-drain conductive layer disposed on the interlayer insulating layer; a first planarization layer disposed on the interlayer insulating layer in the display area, wherein the first planarization layer is spaced apart from the two or more packaging auxiliary portions and covers the first source-drain conductive layer; a second source-drain conductive layer disposed on the first planarization layer; and a second planarization layer disposed on the first planarization layer, wherein the second planarization layer covers the second source-drain conductive layer, and each of the two or more packaging auxiliary portions includes: a first auxiliary layer disposed on the interlayer insulating layer and spaced apart from the first planarization layer; and a second auxiliary layer disposed on the first auxiliary layer and formed in the same layer as the second source-drain conductive layer, wherein the second auxiliary layer covers a top surface of the first auxiliary layer, extends to a part of a side surface of the first auxiliary layer, and is spaced apart from the interlayer insulating layer.

5. The display device according to claim 4, wherein, The first auxiliary layer includes a negative photoresist material cured by exposure and has a cross-sectional shape whose width gradually widens as it extends away from the interlayer insulating layer in the direction from the substrate to the interlayer insulating layer.

6. The display device according to claim 4, wherein, Each of the two or more encapsulation auxiliary portions further includes one or more grooves provided on a side facing an adjacent encapsulation auxiliary portion and formed on the side surface of the first auxiliary layer.

7. The display device according to claim 4, wherein, The first encapsulation layer overlapping the two or more encapsulation auxiliary portions is continuous, and the first encapsulation layer overlapping the one or more recessed portions is spaced apart from the second encapsulation layer.

8. The display device according to claim 4, wherein, The element layer includes: anode electrodes provided in the emission regions; a pixel defining layer provided in non-emission regions between the emission regions, wherein the pixel defining layer covers edges of each of the anode electrodes; a spacer layer provided on the pixel defining layer; a first common layer provided on the anode electrodes; a light-emitting layer provided on the first common layer; a second common layer provided in the display region, wherein the second common layer covers the pixel defining layer, the spacer layer, and the light-emitting layer; and a cathode electrode provided on the second common layer.

9. The display device according to claim 8, wherein, The second common layer includes: two or more first divided portions provided on the second auxiliary layer of each of the two or more encapsulation auxiliary portions; and one or more second divided portions provided in the one or more recessed portions, wherein the one or more second divided portions are spaced apart from the two or more first divided portions.

10. The display device according to claim 9, wherein, Between the two or more encapsulation auxiliary portions, the cathode electrode is in contact with the interlayer insulating layer.

11. The display device according to claim 8, wherein, Each of the one or more hole peripheral dams includes two or more dam layers, and each of the two or more dam layers is provided in the same layer as a corresponding one of the second planarization layer, the pixel defining layer, and the spacer layer.

12. The display device according to claim 8, further comprising: two or more dummy auxiliary portions provided between the one or more hole peripheral dams and the hole region, wherein the two or more dummy auxiliary portions surround the hole region; and one or more dummy recessed portions provided between the two or more dummy auxiliary portions, wherein the second common layer includes: two or more third divided portions provided on the two or more dummy auxiliary portions; and one or more fourth divided portions provided in the one or more dummy recessed portions, wherein the one or more fourth divided portions are spaced apart from the two or more third divided portions.

13. The display device according to claim 12, wherein, The circuit layer further includes: a buffer layer provided on the substrate; a first gate insulating layer provided on the buffer layer; and a second gate insulating layer provided on the first gate insulating layer, wherein the interlayer insulating layer is provided on the second gate insulating layer, and The light-transmitting hole penetrates through the third encapsulation layer, the first encapsulation layer, the cathode electrode, the second common layer, the interlayer insulating layer, the second gate insulating layer, the first gate insulating layer, the buffer layer, and the substrate.

14. A method for manufacturing a display device, comprising: providing a substrate, the substrate including: a display area in which an emission area is disposed; a non-display area disposed around the display area; a hole area surrounded by the display area; and a hole peripheral area disposed between the hole area and the display area; disposing a circuit layer on the substrate; disposing an element layer on the circuit layer; disposing an encapsulation layer on the element layer; and forming a light-transmitting hole in the hole area that penetrates through the substrate, the circuit layer, the element layer, and the encapsulation layer, wherein the setting of the circuit layer includes: disposing an interlayer insulating layer on the substrate; disposing a first source / drain conductive layer on the interlayer insulating layer; disposing a first planarization layer covering the first source / drain conductive layer on the interlayer insulating layer in the display area; setting two or more first auxiliary layers surrounding the hole area on the interlayer insulating layer in the hole peripheral area by partially etching a negative photoresist material laminated on the interlayer insulating layer, wherein the two or more first auxiliary layers are spaced apart from the first planarization layer; disposing a second source / drain conductive layer on the first planarization layer and disposing two or more second auxiliary layers on the two or more first auxiliary layers; and disposing a second planarization layer covering the second source / drain conductive layer on the first planarization layer.

15. The method according to claim 14, wherein, Each of the two or more first auxiliary layers has a cross-section with a shape whose width gradually decreases as it approaches the interlayer insulating layer, and the setting of the second source / drain conductive layer and the two or more second auxiliary layers includes: laminating a conductive material layer; and partially removing the conductive material layer to provide the second source / drain conductive layer on the first planarization layer and the two or more second auxiliary layers on the two or more first auxiliary layers, wherein the two or more second auxiliary layers cover the top surfaces of the two or more first auxiliary layers, extend to a part of the side surfaces of the two or more first auxiliary layers and are spaced apart from the interlayer insulating layer, and forming two or more encapsulation auxiliary parts each having a laminated structure of the first auxiliary layer and the second auxiliary layer in the setting of the second source / drain conductive layer and the two or more second auxiliary layers.

16. The method according to claim 15, wherein In the partial removal of the conductive material layer, between the two or more first auxiliary layers, a part of the interlayer insulating layer is removed together with the conductive material layer to form one or more recessed parts on the interlayer insulating layer.

17. The method according to claim 16, wherein The setting of the element layer includes: disposing an anode electrode of the emission area on the second planarization layer; A pixel defining layer is disposed on the second planarization layer in a non-emitting region provided between the emitting regions, and a spacer layer is disposed on a part of the pixel defining layer; A first common layer is disposed on the anode electrode; An emitting layer is disposed on the first common layer; A second common layer covering the pixel defining layer, the spacer layer, and the emitting layer is disposed in the display region; and A cathode electrode is disposed on the second common layer, wherein the second common layer includes: Two or more first divided portions disposed on the two or more second auxiliary layers; and One or more second divided portions disposed in the one or more recessed portions and spaced apart from the two or more first divided portions.

18. The method according to claim 17, wherein, The setting of the circuit layer further includes: After setting the second source-drain conductive layer and the two or more second auxiliary layers, an ashing process is performed on side surfaces of the two or more first auxiliary layers to form one or more grooves in each of the two or more first auxiliary layers, and The one or more grooves in each of the two or more first auxiliary layers are disposed on a side facing an adjacent first auxiliary layer and are formed on the side surface of the first auxiliary layer.

19. The method according to claim 17, wherein, In the setting of the pixel defining layer and the spacer layer, one or more hole peripheral dams are formed between the two or more encapsulation auxiliary portions and the hole region and surrounding the hole region, The one or more hole peripheral dams include two or more dam layers, Each of the two or more dam layers is formed in the same layer as a corresponding one of the second planarization layer, the pixel defining layer, and the spacer layer, and The setting of the encapsulation layer includes: Setting a first encapsulation layer covering the cathode electrode and containing an inorganic insulating material; Setting a second encapsulation layer overlapping the display region on the first encapsulation layer; and Laminating an inorganic insulating material on the first encapsulation layer and setting a third encapsulation layer covering the second encapsulation layer, wherein the second encapsulation layer includes an organic insulating material extending to the one or more hole peripheral dams, overlapping the two or more encapsulation auxiliary portions, and spaced apart from the hole region.

20. The method according to claim 19, wherein Some portions of the first encapsulation layer overlapping the two or more second auxiliary layers are connected to each other.

Images