Display substrate and display device

Abstract

The invention provides a display substrate and a display device. The display substrate comprises a substrate, a circuit layer and a shading layer. The circuit layer comprises a detection circuit, a scanning signal line, a first output signal line, a second output signal line and a data signal line. The detection circuit comprises a first sub-detection circuit and a second sub-detection circuit, the first sub-detection circuit comprises at least one first transistor, and the second sub-detection circuit comprises at least one second transistor. Grid electrodes of the first transistor and the second transistor are respectively connected with a scanning signal line, first poles of the first transistor and the second transistor are respectively connected with a data signal line, a second pole of the first transistor is connected with a first output signal line, and a second pole of the second transistor is connected with a second output signal line. The orthographic projection of the channel region of the first transistor on the substrate is covered by the orthographic projection of the shading layer on the substrate, and the orthographic projection of the channel region of the second transistor on the substrate is not overlapped with the orthographic projection of the shading layer on the substrate.

Description

Display substrate and display device Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the continuous development of display technology, display devices such as mobile phones, laptops, and televisions have become necessities in people's work and life. Liquid crystal display devices have become the mainstream display device due to their advantages such as high brightness, vivid colors, and wide viewing angle.

[0003] Summary of the Invention

[0004] The present application provides a display substrate and a display device.

[0005] According to a first aspect of an embodiment of the present application, a display substrate is provided. The display substrate includes:

[0006] substrate;

[0007] a circuit layer located on the substrate, the circuit layer comprising at least one group of detection circuits, scan signal lines, first output signal lines, second output signal lines, and data signal lines, the detection circuit comprising a first sub-detection circuit and a second sub-detection circuit, the first sub-detection circuit comprising at least one first transistor, the second sub-detection circuit comprising at least one second transistor; the first transistor and the second transistor respectively comprising a gate, a first electrode, and a second electrode; the gate of the first transistor and the gate of the second transistor are respectively connected to the scan signal lines, the first electrode of the first transistor and the first electrode of the second transistor are respectively connected to the data signal lines, the second electrode of the first transistor is connected to the first output signal line, and the second electrode of the second transistor is connected to the second output signal line;

[0008] A light-shielding layer is located on a side of the circuit layer away from the substrate, the orthographic projection of the channel region of the first transistor on the substrate is covered by the orthographic projection of the light-shielding layer on the substrate, and the orthographic projection of the channel region of the second transistor on the substrate does not overlap with the orthographic projection of the light-shielding layer on the substrate.

[0009] In one embodiment, the display substrate includes a display area and a peripheral area located on at least one side of the display area; the detection circuit and each signal line connected to the detection circuit are located in the peripheral area.

[0010] In one embodiment, the peripheral area includes a plurality of sub-peripheral areas, each of the sub-peripheral areas is located on one side of the display area; and each transistor of the detection circuit is located in the same sub-peripheral area.

[0011] In one embodiment, the display substrate further includes a liquid crystal layer located between the circuit layer and the light-shielding layer, the detection circuit is located in the peripheral area, and the liquid crystal layer includes a plurality of liquid crystal molecules; the display substrate further includes at least one row of first sub-pixels located between the second sub-detection circuit and the display area, the first sub-pixels include liquid crystal molecules, and the long axis direction of the liquid crystal molecules of the first sub-pixels is perpendicular to the surface of the substrate.

[0012] In one embodiment, in the same detection circuit, the number of the first transistors and the number of the second transistors are both plural. In the same detection circuit, the first transistors are connected in parallel, and the second transistors are connected in parallel.

[0013] In one embodiment, in the same detection circuit, the first transistor and the second transistor are arranged along a row direction or a column direction.

[0014] In one embodiment, the channel region of the first transistor and the channel region of the second transistor respectively include a source region and a drain region. When the first transistor and the second transistor are arranged along the row direction, the source region and the drain region extend along the column direction; when the first transistor and the second transistor are arranged along the column direction, the source region and the drain region extend along the row direction.

[0015] In one embodiment, in the same detection circuit, the first transistor and the second transistor are located in the same row, and the first transistor and the second transistor are arranged alternately; or, the first transistor and the second transistor are located in the same column, and the first transistor and the second transistor are arranged alternately;

[0016] The first transistor and the second transistor are connected to the same scanning signal line and the same data signal line.

[0017] In one embodiment, the circuit layer includes a first conductive layer and a second conductive layer; in the same detection circuit, the extension direction of the first output signal line and the extension direction of the second output signal line are respectively the same as the arrangement direction of the first transistor and the second transistor; the second electrode of the first transistor and the second electrode of the second transistor are located in the second conductive layer, and at least one of the first output signal line and the second output signal line is located in the first conductive layer.

[0018] In one embodiment, the first output signal line and the second output signal line are both located in the first conductive layer.

[0019] In one embodiment, in the same detection circuit, each first transistor and each second transistor are located in the same row, and all the first transistors are adjacent to each other, and all the second transistors are arranged adjacent to each other; or, each first transistor and each second transistor are located in the same column, and all the first transistors are adjacent to each other, and all the second transistors are arranged adjacent to each other.

[0020] In one embodiment, in the same detection circuit, the first transistors are located in the same row, the second transistors are located in the same row, and the first transistor and the second transistor are located in different rows; or, the first transistors are located in the same column, the second transistors are located in the same column, and the first transistor and the second transistor are located in different columns.

[0021] In one embodiment, the display substrate includes a peripheral area, and the circuit layer also includes a plurality of pins and a first connecting line located in the peripheral area; the scanning signal line includes a first scanning signal line and a second scanning signal line; in the same detection circuit, the first electrode of each first transistor is connected to the first scanning signal line, and the first electrode of each second transistor is connected to the second scanning signal line, and the two ends of the first connecting line are respectively connected to the ends of the first scanning signal line and the second scanning signal line on the same side; the first connecting line is connected to the pin.

[0022] In one embodiment, the display substrate includes a peripheral area, and the display substrate also includes a plurality of pins and a second connecting line located in the peripheral area; the data signal line includes a first data signal line and a second data signal line; in the same detection circuit, the first electrode of each first transistor is connected to the first data signal line, the first electrode of each second transistor is connected to the second data signal line, and the two ends of the second connecting line are respectively connected to the ends of the first data signal line and the second data signal line on the same side; the second connecting line is connected to the pin.

[0023] In one embodiment, in the same detection circuit, the number of the first transistors is the same as the number of the second transistors.

[0024] In one embodiment, the light-shielding layer is provided with a plurality of hollow portions, the first transistor and the second transistor include an active layer, the orthographic projection of one of the hollow portions on the substrate covers the orthographic projection of the active layer of one transistor on the substrate, and the spacing between adjacent hollow portions is greater than or equal to 100 μm.

[0025] In one embodiment, the display substrate includes a common electrode layer, the common electrode layer is provided with an opening, the orthographic projection of the first transistor on the substrate falls within the orthographic projection of the opening on the substrate, and the orthographic projection of the second transistor on the substrate falls within the orthographic projection of the opening on the substrate.

[0026] In one embodiment, in the same detection circuit, the orthographic projection of each of the first transistors on the substrate and the orthographic projection of each of the second transistors on the substrate both fall within the orthographic projection of one of the openings on the substrate.

[0027] In one embodiment, the display substrate includes a display area; the display substrate also includes a common voltage signal line surrounding the display area and a common electrode layer at least partially located in the display area, the common voltage signal line is electrically connected to the common electrode layer, and the detection circuit is located between the common electrode layer and the common voltage signal line.

[0028] According to a second aspect of an embodiment of the present application, a display device is provided, comprising the above-mentioned display substrate.

[0029] In the display substrate and display device provided by the embodiments of the present application, the orthographic projection of the first transistor of the first sub-detection circuit on the substrate is covered by the orthographic projection of the light-shielding layer on the substrate, so that the ambient light incident on the display substrate cannot be incident on the channel of the first transistor, and the current output by the first output signal line is not affected by the ambient light; the orthographic projection of the channel of the second transistor of the second sub-detection circuit on the substrate is not covered by the orthographic projection of the light-shielding layer on the substrate, so that the ambient light incident on the display substrate can be incident on the channel region of the second transistor and affect the output current of the second transistor, and thus affect the current output by the second output signal line; the intensity of the external ambient light can be determined according to the difference between the current output by the first output signal line and the current output by the second output signal line, so that the brightness of the backlight source can be adjusted according to the intensity of the ambient light, which helps to reduce the power consumption of the backlight source. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG1 is a partial cross-sectional view of a display substrate provided by an exemplary embodiment of the present application;

[0031] FIG2 is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present application;

[0032] FIG3 is a circuit diagram of a display device in which a display substrate is provided according to an exemplary embodiment of the present application;

[0033] FIG4 is a schematic diagram of a partial structure of a display substrate provided by an exemplary embodiment of the present application;

[0034] FIG5 is a schematic structural diagram of a display substrate provided by another exemplary embodiment of the present application;

[0035] FIG6 is a schematic structural diagram of a display substrate provided by yet another exemplary embodiment of the present application;

[0036] FIG7 is a schematic structural diagram of a detection circuit of a display substrate provided by an exemplary embodiment of the present application;

[0037] FIG8 is a schematic structural diagram of a detection circuit of a display substrate provided by another exemplary embodiment of the present application;

[0038] FIG9 is a schematic structural diagram of a detection circuit of a display substrate provided by yet another exemplary embodiment of the present application;

[0039] FIG10 is a schematic diagram of a partial structure of a display substrate provided by an exemplary embodiment of the present application;

[0040] FIG. 11 is a schematic diagram of a partial structure of a display substrate provided by another exemplary embodiment of the present application. DETAILED DESCRIPTION

[0041] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0042] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. As used in this application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0043] It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0044] The embodiments of the present application provide a display substrate and a display device. The display substrate and the display device in the embodiments of the present application are described in detail below with reference to the accompanying drawings. The features of the following embodiments may complement or be combined with each other unless they conflict.

[0045] The present invention provides a display substrate. As shown in FIG1 , the display substrate includes a substrate 10, a circuit layer 20, and a light shielding layer 30. The circuit layer 20 is located on the substrate 10. The light shielding layer 30 is located on a side of the circuit layer 20 away from the substrate 10.

[0046] As shown in Figures 2 to 4, the circuit layer 20 includes at least one detection circuit 50, a scan signal line 61, a first output signal line 62, a second output signal line 63, and a data signal line 64. The detection circuit includes a first sub-detection circuit 51 and a second sub-detection circuit 52. The first sub-detection circuit 51 includes at least one first transistor 70, and the second sub-detection circuit 52 includes at least one second transistor 80. The first transistor 70 includes a gate 73, a first electrode 71, and a second electrode 72; the second transistor 80 includes a gate 83, a first electrode 81, and a second electrode 82. The gate 73 of the first transistor 70 and the gate 83 of the second transistor 80 are respectively connected to the scan signal line 61, the first electrode 71 of the first transistor 70 and the first electrode 81 of the second transistor 80 are respectively connected to the data signal line 64, the second electrode 72 of the first transistor 70 is connected to the first output signal line 62, and the second electrode 82 of the second transistor 80 is connected to the second output signal line 63.

[0047] 4 , the orthographic projection of the channel region of the first transistor 70 on the substrate 10 is covered by the orthographic projection of the light-shielding layer 30 on the substrate 10 , and the orthographic projection of the channel region of the second transistor 80 on the substrate 10 does not overlap with the orthographic projection of the light-shielding layer 30 on the substrate.

[0048] In the display substrate provided by the embodiment of the present application, the orthographic projection of the first transistor of the first sub-detection circuit on the substrate is covered by the orthographic projection of the light-shielding layer on the substrate, so that the ambient light incident on the display substrate cannot be incident on the channel of the first transistor, and the current output by the first output signal line is not affected by the ambient light; the orthographic projection of the channel of the second transistor of the second sub-detection circuit on the substrate is not covered by the orthographic projection of the light-shielding layer on the substrate, so that the ambient light incident on the display substrate can be incident on the channel region of the second transistor and affect the output current of the second transistor, and thus affect the current output by the second output signal line; the intensity of the external ambient light can be determined according to the difference between the current output by the first output signal line and the current output by the second output signal line, so that the brightness of the backlight source can be adjusted according to the intensity of the ambient light, which helps to reduce the power consumption of the backlight source.

[0049] In one embodiment, as shown in FIG3 , the display device on which the display substrate is located includes a first current detection circuit 65, a second current detection circuit 66, and a control circuit 67. The first current detection circuit 65 is connected to the output end of the first output signal line 62, the second current detection circuit 66 is connected to the output end of the second output signal line 63, and the control circuit 67 is connected to the first current detection circuit 65 and the second current detection circuit 66, respectively. The first current detection circuit 65 detects the magnitude of the current output by the first output signal line 62 and outputs it to the control circuit 66; the second current detection circuit 66 detects the magnitude of the current output by the second output signal line 63 and outputs it to the control circuit 67. The control circuit 67 can determine the ambient light intensity based on the difference between the magnitude of the current output by the first current output signal line 62 and the magnitude of the current output by the second current output signal line 63, and adjust the brightness of the backlight source based on the ambient light intensity.

[0050] In one embodiment, as shown in FIG2 , the display substrate includes a display area 101 and a peripheral area 102 located on at least one side of the display area 101. In the embodiment shown in FIG2 , the peripheral area 102 is disposed around the display area 101. The peripheral area 102 includes a plurality of sub-peripheral areas, each of which is located on a side of the display area 101. In the embodiment shown in FIG2 , the peripheral area 102 includes four sub-peripheral areas: a first sub-peripheral area 1021, a second sub-peripheral area 1022, a third sub-peripheral area 1023, and a fourth sub-peripheral area 1024. The first sub-peripheral area 1021 is disposed opposite the second sub-peripheral area 1022, and the third sub-peripheral area 1023 is disposed opposite the fourth sub-peripheral area 1024.

[0051] In one embodiment, as shown in FIG1 , the display substrate includes a first substrate 110 and a second substrate 120 disposed opposite each other, and a liquid crystal layer 42 and a sealant 43 located between the first substrate 110 and the second substrate 120. The first substrate 110 includes the substrate 10 and the circuit layer 20, with the circuit layer 20 located on the side of the substrate 10 facing the second substrate 120. The second substrate 120 includes a substrate 41 and a light shielding layer 30 located on the side of the substrate 41 facing the first substrate 110. The sealant 43 is disposed around the liquid crystal layer 42, adhering the first substrate 110 and the second substrate 120 together via the sealant 43. The liquid crystal layer 42 includes a plurality of liquid crystal molecules 421.

[0052] In one embodiment, the substrate 10 and the substrate 41 may both be flexible substrates or rigid substrates. The substrates 10 and 41 have high light transmittance to reduce light loss when light emitted by the backlight passes through them. The flexible substrate material may include one or more of polyimide, polyethylene terephthalate, polycarbonate, and organic resin materials. The organic resin material may include epoxy resin, triazine, silicone resin, or polyimide. Rigid substrates include any of glass substrates, quartz substrates, and sapphire substrates.

[0053] In one embodiment, the display substrate further includes a first electrode layer and a second electrode layer, one of the first electrode layer and the second electrode layer is a pixel electrode layer, and the other is a common electrode layer. The display substrate may be an ADS (Advanced Super Dimension Switch) display substrate. The ADS display substrate has a fast response speed, and the display screen has bright colors and high saturation. In the ADS display substrate, the pixel electrode layer and the common electrode layer are located on the same side of the liquid crystal layer. For example, the common electrode layer and the pixel electrode layer are both located on the first substrate 110, and are located on the side of the substrate 10 facing the second substrate 120, and the pixel electrode layer and the common electrode layer are arranged opposite to each other. The first electrode layer and the second electrode layer are both at least partially located in the display area.

[0054] In one embodiment, the pixel electrode layer includes a plurality of strip-shaped pixel electrodes, the common electrode layer may be a plate-shaped electrode, and each pixel electrode, the portion of the common electrode layer facing the pixel electrode, and the liquid crystal molecules facing the pixel electrode form a sub-pixel.

[0055] In another embodiment, the pixel electrode layer includes a plurality of strip-shaped pixel electrodes, and the common electrode layer includes a plurality of strip-shaped common electrodes. The pixel electrodes and the common electrodes may extend in the same direction. The pixel electrodes and the strip-shaped common electrodes may correspond one to one, and each pixel electrode, the common electrode corresponding to the pixel electrode, and the liquid crystal molecules located between the pixel electrode and the common electrode form a sub-pixel.

[0056] In one embodiment, the circuit layer 20 may include a plurality of pixel circuits, each corresponding to a sub-pixel, and each pixel circuit drives a corresponding sub-pixel. The pixel circuit may include a plurality of thin film transistors. The pixel circuit may also include a capacitor.

[0057] In one embodiment, the circuit layer 20 includes a first conductive layer, an active film layer located on a side of the first conductive layer away from the substrate, and a second conductive layer located on a side of the active film layer away from the substrate 10. The gate of the first transistor 70 and the gate of the second transistor 80 may be located in the first conductive layer. The first transistor 70 includes an active layer 74 located in the active film layer (see FIG. 4 ), and the second transistor 80 includes an active layer 84 located in the active film layer (see FIG. 4 ). The active layer of each transistor includes a channel region. The first electrode 71 of the first transistor 70, the second electrode 72 of the first transistor 70, the first electrode 81 of the second transistor 80, and the second electrode 82 of the second transistor 80 are respectively located in the second conductive layer. The materials of the first conductive layer and the second conductive layer may both be metal.

[0058] In one embodiment, one of the first electrode and the second electrode is a source electrode, and the other is a drain electrode. The first transistor 70 and the second transistor 80 can be N-type transistors or P-type transistors. The embodiment shown in FIG3 is illustrated by taking the first transistor 70 and the second transistor 80 as an example in which both the first transistor 70 and the second transistor 80 are N-type transistors.

[0059] In one embodiment, the active layers of the first transistor 70 and the second transistor 80 are made of amorphous silicon. As such, the electron mobility of the active layer is different when no light is incident and when light is incident. By configuring the detection circuit to include a first sub-detection circuit 51 and a second sub-detection circuit 52, the channel region of the first transistor of the first sub-detection circuit is covered by a light-shielding layer, while the channel region of the second transistor of the second sub-detection circuit 52 is not. This allows the ambient light intensity to be determined more accurately based on the difference in current output by the first and second sub-detection circuits, compared to a solution in which the detection circuit includes only the second sub-detection circuit.

[0060] In one embodiment, the orthographic projection of the light shielding layer 30 on the substrate 10 covers the orthographic projection of the active layer of the first transistor 70 on the substrate 10. Furthermore, the orthographic projection of the light shielding layer 30 on the substrate 10 covers the entire area of ​​the orthographic projection of the first transistor 70 on the substrate 10. This configuration prevents light reflection from the metal structure of the first transistor 70 and affects the display effect of the display substrate.

[0061] In one embodiment, as shown in FIG4 , the orthographic projections of the active layers 84 of the second transistors 80 on the substrate 10 may all be located within the orthographic projection of the hollow portion 31 of one light shielding layer 30 on the substrate 10. The active layers 84 of the second transistors may correspond to the hollow portions 31 one by one, and the orthographic projection of the active layer 84 of each second transistor on the substrate 10 may be located within the orthographic projection of the corresponding hollow portion 31 on the substrate 10.

[0062] In one embodiment, the spacing between adjacent hollow portions 31 is greater than or equal to 100 μm. The hollow portions 31 expose part of the metal structure. By setting the spacing between adjacent hollow portions 31 to be greater than or equal to 100 μm, the visual effect of the display substrate can be reduced.

[0063] In one embodiment, as shown in Figures 2, 5, and 6, the display substrate includes a plurality of detection circuits 50. With this arrangement, the control circuit determines an ambient light intensity based on the current signal output by each detection circuit 50, then determines an average of the ambient light intensities based on all the ambient light intensities, and uses the determined average of the ambient light intensities as the ambient light intensity to adjust the brightness of the backlight source, thereby improving the accuracy of the determined ambient light intensity.

[0064] In one embodiment, as shown in FIG3 , the first sub-detection circuit 51 includes a plurality of first transistors 70 connected in parallel, and the second sub-detection circuit 52 includes a plurality of second transistors 80 connected in parallel. This allows the current signals output by the first output signal line 62 and the second output signal line 63 to be larger, thereby reducing the impact of current loss during current signal transmission on current signal accuracy.

[0065] In one embodiment, within the same detection circuit, the number of first transistors 70 in the first sub-detection circuit 51 is the same as the number of second transistors 80 in the second sub-detection circuit 52. This allows the ambient light intensity to be determined directly based on the difference between the current signal output by the second output signal line and the current signal output by the second output signal line. In other embodiments, within the same detection circuit, the number of first transistors 70 in the first sub-detection circuit 51 may be different from the number of second transistors 80 in the second sub-detection circuit 52. For example, the number of first transistors 70 in the first sub-detection circuit 51 is X, and the number of second transistors 80 in the second sub-detection circuit 52 is Y, where X≠Y. In this embodiment, the average value of the current signal output by each second transistor 80 can be calculated by dividing the current signal output by the second output signal line by Y. The average value of the current signal output by the second transistor 80 is then multiplied by X to obtain a current correction value. The ambient light intensity can be determined based on the difference between the current correction value and the current signal output by the first output signal line.

[0066] In one embodiment, the subpixels of the display substrate include first subpixels located in the peripheral area and second subpixels located in the display area. The second subpixels in the display area are used to display images. At least one row of first subpixels is located between the detection circuit 50 and the display area 101. The long axis of the liquid crystal molecules in the first subpixels is perpendicular to the surface of the substrate 10. Because the long axis of the liquid crystal molecules in the first subpixels is perpendicular to the surface of the first substrate 10, the first subpixels are not used to display images. As a result, the boundary of the area of ​​the display substrate where light emitted by the backlight source is incident can be located on the side of the first subpixel closest to the display area, thereby preventing light emitted by the backlight source from entering the channel region of the second transistor 80. In some embodiments, the long axis of the liquid crystal molecules in the first subpixels can be perpendicular to the surface of the first substrate 10 by controlling the electrical signal output by the pixel circuit to the pixel electrode of the first subpixel. In some embodiments, the first subpixels and the detection circuit 50 are respectively located in the first sub-peripheral area 1021. Each row of first subpixels includes a plurality of first subpixels arranged along the extension direction of the first sub-peripheral area 1021. The display substrate may include, for example, multiple rows of first sub-pixels, or may include only one row of first sub-pixels.

[0067] In one embodiment, the detection circuit 50 and the signal lines connected to the detection circuit 50 are all located in the peripheral area 102. The signal lines connected to the detection circuit 50 include the detection circuit 50, the scan signal line 61, the first output signal line 62, the second output signal line 63, and the data signal line 64. With this arrangement, the detection circuit 50 and the signal lines connected to the detection circuit 50 do not occupy space in the display area 101 and do not affect the arrangement of pixel circuits and signal lines in the display area 101.

[0068] Furthermore, the transistors of the detection circuit 50 are located in the same sub-peripheral area. This arrangement reduces the distance between the first transistor 70 and the second transistor 80 in the same detection circuit 50, thereby minimizing the difference between the film layers of the first transistor 70 and the corresponding film layers of the second transistor 80 in the same detection circuit, thereby improving the accuracy of the determined ambient light intensity.

[0069] Furthermore, the first sub-detection circuit 51 and the second sub-detection circuit 52 are arranged adjacent to each other in the same detection circuit 50. In this way, each first transistor 70 and each second transistor 80 in the same detection circuit 50 can be connected to the same scan signal line and / or the same data signal line, which helps to simplify the wiring of the display substrate.

[0070] In the embodiment shown in FIG2 , each detection circuit 50 is located in the first sub-peripheral area 1021. In the embodiment shown in FIG5 , the detection circuits 50 are distributed in the third sub-peripheral area 1023 and the fourth sub-peripheral area 1024. In the embodiment shown in FIG6 , each detection circuit 50 is located in the fourth sub-peripheral area 1024.

[0071] In other embodiments, in the same detection circuit, the first sub-detection circuit and the second sub-detection circuit may be located in different sub-peripheral areas, for example, the first sub-detection circuit is located in the third sub-peripheral area 1023 or the fourth sub-peripheral area 1024, and the second sub-detection circuit is located in the first sub-peripheral area.

[0072] In one embodiment, as shown in Figures 2, 5, and 6, the display substrate further includes at least one pin region 90 located in the peripheral region. The pin region 90 is provided with a plurality of pins 901. Some of the pins 901 are connected to signal lines connected to the detection circuit, and some of the pins 901 can be connected to drive signal lines that provide drive signals to the pixel circuit. The pin region 90 can be located in the first sub-peripheral region 1021.

[0073] In one embodiment, as shown in FIG2 , each of the detection circuits 50 and each of the pin areas 90 are located in the same sub-peripheral area, and the pin area 90 is located on the side of the detection circuit 50 away from the display area 101. Placing the detection circuit 50 and the pin area 90 in the same sub-peripheral area can make the distance between each detection circuit 50 and the pin 901 closer, so that the length between the signal line connecting the detection circuit 50 and the pin 901 is shorter, which helps to simplify the wiring complexity of the display substrate. Placing the pin area 90 on the side of the detection circuit 50 away from the display area 101 facilitates the connection of the pin 901 of the pin area 90 to the circuit board. In the embodiments shown in FIG2 and FIG5 , each of the detection circuits 50 and each of the pin areas 90 are located in the first sub-peripheral area 1021.

[0074] In another embodiment, as shown in Figures 5 and 6, the detection circuit 50 and the pin area 90 are located in different sub-peripheral areas. In this way, the space of each sub-peripheral area can be fully utilized, avoiding the problem that the detection circuit 50 and the pin area 90 are located in the same sub-peripheral area, resulting in a larger width of the sub-peripheral area. In the embodiment shown in Figure 5, the detection circuit 50 is located in the third sub-peripheral area 1023 and the fourth sub-peripheral area 1024, and the pin area 90 is located in the first sub-peripheral area 1021. In the embodiment shown in Figure 6, the detection circuit 50 is located in the second sub-peripheral area 1022, and the pin area 90 is located in the first sub-peripheral area 1021, that is, the detection circuit 50 and the pin area 90 are located on opposite sides of the display area 101.

[0075] In one embodiment, each signal line connected to the same detection circuit 50 is connected to the pin 901 of the same pin area 90. For example, each signal line connected to the detection circuit 50 can be connected to the pin area 90 adjacent to the detection circuit 50. Alternatively, each signal line connected to the same detection circuit 50 can be connected to the pin 901 of different pin areas 90. For example, each signal line connected to the detection circuit 50 can be connected to two pin areas 90 adjacent to the detection circuit 50.

[0076] In one embodiment, in the same detection circuit 50, the first transistor 70 and the second transistor 80 are arranged in a row direction or a column direction. With this arrangement, the signal line connected to the detection circuit 50 can be arranged in the same direction as the transistors in the detection circuit 50, and can be substantially straight. The signal line does not need to bend or has fewer bends, which helps to reduce the space occupied by the signal line.

[0077] Furthermore, the arrangement direction of the transistors in the detection circuit 50 is the same as the extension direction of the sub-peripheral area in which they are located. This helps to reduce the width of the sub-peripheral area. For example, the detection circuit 50 is located in the first sub-peripheral area 1021, the first sub-peripheral area 1021 extends along the row direction, and the first transistors 70 and the second transistors 80 in the detection circuit 50 are arranged along the row direction; the first transistors 70 and the second transistors 80 can be located in the same row or in different rows. For example, the detection circuit 50 is located in the third sub-peripheral area 1023, the third sub-peripheral area 1023 extends along the column direction, and the first transistors 70 and the second transistors 80 in the detection circuit 50 are arranged along the column direction; the first transistors 70 and the second transistors 80 can be located in the same column or in different columns.

[0078] In one embodiment, the channel region of the first transistor 70 and the channel region of the second transistor 80 include a source region and a drain region, respectively. When the first transistor 70 and the second transistor 80 are arranged in a row direction, the source region and the drain region extend in a column direction; when the first transistor and the second transistor are arranged in a column direction, the source region and the drain region extend in a row direction. The source region refers to the region of the channel region that contacts the source, and the drain region refers to the region of the channel region that contacts the drain. By arranging the first transistor 70 and the second transistor 80 along the row direction, the source region and the drain region extend along the column direction, and the source and drain of each transistor extend along the column direction, so that the signal line connected to the source can extend along the row direction, and the signal line connected to the drain can extend along the row direction. The signal line does not need to bend or has fewer bends, which can reduce the space occupied by the signal line; by arranging the first transistor 70 and the second transistor 80 along the column direction, the source region and the drain region extend along the row direction, and the source and drain of each transistor extend along the row direction, so that the signal line connected to the source can extend along the column direction, and the signal line connected to the drain can extend along the column direction. The signal line does not need to bend or has fewer bends, which can reduce the space occupied by the signal line. One of the source region and the drain region is in the shape of an elongated strip, and the other is roughly U-shaped. For example, the source region is in the shape of an elongated strip, and the drain region is roughly U-shaped. The drain region extends along the column direction, which means that the direction in which the opening end of the drain region points away from the end of the opening is the column direction. The drain region extends along the row direction, which means that the direction in which the opening end of the drain region points away from the end of the opening is the row direction.

[0079] In one embodiment, as shown in FIG7 , in the same detection circuit 50 , the first transistor 70 and the second transistor 80 are located in the same row, and the first transistor 70 and the second transistor 80 are arranged alternately; or, in the same detection circuit 50 , the first transistor 70 and the second transistor 80 are located in the same column, and the first transistor 70 and the second transistor 80 are arranged alternately therein. The gate 73 of each first transistor 70 and the gate 83 of each second transistor 80 are connected to the same scan signal line 61, the first electrode 71 of each first transistor 70 and the first electrode 81 of each second transistor 80 are connected to the same data signal line 64, the second electrode 72 of each first transistor 70 is connected to the same first output signal line 62, and the second electrode 82 of each second transistor 80 is connected to the same second output signal line 63. This can reduce the number of signal lines connected to the detection circuit, helping to simplify the wiring of the display substrate.

[0080] In the embodiment shown in FIG7 , in the same detection circuit, one second transistor 80 is provided between two adjacent first transistors 70, and one first transistor 70 is provided between two adjacent second transistors 80. In other embodiments, two or more second transistors 80 may be provided between two adjacent first transistors 70, and two or more first transistors 70 may be provided between two adjacent second transistors 80.

[0081] Furthermore, in the same detection circuit 50, the extension direction of the first output signal line 62 and the extension direction of the second output signal line 63 are respectively the same as the arrangement direction of the first transistor 70 and the second transistor 80; the second electrode of the first transistor 70 and the second electrode of the second transistor 80 are located in the second conductive layer, and at least one of the first output signal line 62 and the second output signal line 63 is located in the first conductive layer. This arrangement can avoid the problem of the first output signal line 62 and the second electrode of the second transistor 80 intersecting and causing a short circuit, and avoid the problem of the second output signal line 63 and the second electrode of the first transistor 70 intersecting and causing a short circuit.

[0082] Furthermore, the first output signal line 62 and the second output signal line 63 are both located in the first conductive layer. With this arrangement, the second electrode of the first transistor 70 is connected to the first output signal line 62 via a through-hole penetrating the insulating layer between the first and second conductive layers, and the second electrode of the second transistor 80 is connected to the second output signal line 63 via a through-hole penetrating the insulating layer. Because the through-hole penetrating the insulating layer increases the resistance of the first output signal line 62 and the second output signal line 63 by substantially the same amount, the loss of current output by the first sub-detection circuit and the loss of current output by the second output signal line 63 are substantially the same. The calculated difference between the current output by the first sub-detection circuit and the current output by the second sub-detection circuit is substantially unaffected, thereby helping to improve the accuracy of the determined ambient light intensity.

[0083] In other embodiments, one of the first output signal line 62 and the second output signal line 63 is located in the first conductive layer, and the other is located in the second conductive layer. For example, the first output signal line 62 is located in the first conductive layer, and the second output signal line 63 is located in the second conductive layer, or the first output signal line 62 is located in the second conductive layer, and the second output signal line 63 is located in the first conductive layer.

[0084] In one embodiment, as shown in FIG8 , in the same detection circuit 50, each first transistor 70 and each second transistor 80 are located in the same row, and all first transistors 70 are adjacent to each other, and all second transistors 80 are adjacent to each other; alternatively, each first transistor 70 and each second transistor 80 are located in the same column, and all first transistors 70 are adjacent to each other, and all second transistors 80 are adjacent to each other. With this arrangement, the second output signal line 62, the third output signal line 63, the second electrode of the first transistor 70, and the second electrode of the second transistor 80 can all be arranged in the same conductive layer, with the second electrode of the first transistor 70 directly connected to the second output signal line 62, and the second electrode of the second transistor 80 directly connected to the third output signal line 63. This helps to simplify the manufacturing process of the display substrate and helps to reduce current loss during the transmission of the current signal output by the first sub-detection circuit and the current signal output by the second sub-detection circuit.

[0085] In one embodiment, as shown in FIG9 , in the same detection circuit 50, each first transistor 70 is located in the same row, each second transistor 80 is located in the same row, and the first transistor 70 and the second transistor 80 are located in different rows; or each first transistor 70 is located in the same column, each second transistor 80 is located in the same column, and the first transistor 70 and the second transistor 80 are located in different columns. With such an arrangement, the second output signal line 62, the third output signal line 63, the second electrode of the first transistor 70, and the second electrode of the second transistor 80 can all be arranged in the same conductive layer, the second electrode of the first transistor 70 is directly connected to the second output signal line 62, and the second electrode of the second transistor 80 is directly connected to the third output signal line 63, which helps to simplify the manufacturing process of the display substrate and helps to reduce the current loss of the current signal output by the first sub-detection circuit and the current signal output by the second sub-detection circuit during the transmission process.

[0086] Furthermore, in the same detection circuit, the first transistor 70 and the second transistor 80 are arranged adjacent to each other. With this arrangement, the distance between the first transistor 70 and the second transistor 80 in the same detection circuit is small, and the difference between each film layer of the first transistor 70 and the corresponding film layer of the second transistor 80 is small, which helps to improve the accuracy of the determined ambient light intensity.

[0087] Furthermore, as shown in Figure 9, the circuit layer also includes a first connecting line 691 located in the peripheral area 102; the scanning signal line 61 includes a first scanning signal line 611 and a second scanning signal line 612; in the same detection circuit 50, the first electrode of each first transistor 70 is connected to the first scanning signal line 611, and the first electrode of each second transistor 80 is connected to the second scanning signal line 612, and the two ends of the first connecting line 691 are respectively connected to the ends of the first scanning signal line 611 and the second scanning signal line 612 on the same side; the first connecting line 691 is connected to the pin 901. In this arrangement, the first scanning signal line 611 and the second scanning signal line 612 are both connected to the pin 901 through the first connecting line 691. Compared with the scheme in which the first scanning signal line 611 and the second scanning signal line 612 are connected to the pin 901 through different connecting lines, the wiring of the circuit layer can be simplified; compared with the scheme in which the first scanning signal line 611 or the second scanning signal line 612 is connected to the pin 901, the signal sizes provided by the pin 901 to the first scanning signal line 611 and the second scanning signal line 612 are basically the same or the difference is very small, which helps to improve the accuracy of the determined ambient light intensity.

[0088] Furthermore, as shown in Figure 9, the circuit layer also includes a second connecting line 692; the data signal line 64 includes a first data signal line 641 and a second data signal line 642; in the same detection circuit 50, the first electrode of each first transistor 70 is connected to the first data signal line 641, and the first electrode of each second transistor 80 is connected to the second data signal line 642, and the two ends of the second connecting line 692 are respectively connected to the ends of the first data signal line 641 and the second data signal line 642 on the same side; the second connecting line 692 is connected to the pin 901. In this arrangement, the first data signal line 641 and the second data signal line 642 are both connected to the pin 901 through the second connecting line 692. Compared with the scheme in which the first data signal line 641 and the second data signal line 642 are connected to the pin 901 through different connecting lines, the wiring of the circuit layer can be simplified; compared with the scheme in which the first data signal line 641 or the second data signal line 642 is connected to the pin 901, the signal size provided by the pin 901 to the first data signal line 641 or the second data signal line 642 is basically the same or the difference is very small, which helps to improve the accuracy of the determined ambient light intensity.

[0089] Furthermore, the first transistor 70 may be located between the second transistor 80 and the display area. In other embodiments, the first transistor 70 may be located on a side of the second transistor 80 away from the display area.

[0090] It should be noted that, in the embodiments shown in Figures 7 to 9, only a few first transistors 70 and second transistors 80 are illustrated in the same detection circuit. In practice, the number of first transistors 70 and second transistors 80 included in the detection circuit is much larger than the number shown in the figures. For example, the number of first transistors 70 and second transistors 80 in the same detection circuit may be 100, 200, etc.

[0091] In one embodiment, as shown in FIG10 , the common electrode layer 93 has an opening 931. The orthographic projection of the first transistor 70 on the substrate falls within the orthographic projection of the opening 931 on the substrate, and the orthographic projection of the second transistor 80 on the substrate falls within the orthographic projection of the opening on the substrate. Because the voltage signal of the common electrode layer 93 is a constant voltage signal, placing the common electrode layer 93 around the first transistor 70 and the second transistor 80 helps shield the signals of the first transistor 70 and the second transistor 80 from interference by external electric fields, thereby improving the accuracy of the determined ambient light intensity.

[0092] Furthermore, as shown in FIG10 , in the same detection circuit 50, the orthographic projections of each of the first transistors 70 and each of the second transistors 80 on the substrate fall within the orthographic projection of one of the openings 931 on the substrate. This arrangement reduces the number of openings 931 provided on the common electrode layer 93, thereby simplifying the fabrication process of the common electrode layer 93.

[0093] In another embodiment, as shown in FIG11 , the display substrate further includes a common voltage signal line 94 surrounding the display area, the common voltage signal line 94 being electrically connected to the common electrode layer 93, and the detection circuit 50 being located between the common electrode layer 93 and the common voltage signal line 94. Because the signals of the common voltage signal line 94 and the common electrode layer 93 are identical and constant electrical signals, placing the detection circuit between the common voltage signal line 94 and the common electrode layer 93 can shield the detection circuit from interference from external electric fields, thereby improving the accuracy of the determined ambient light intensity.

[0094] The present application also provides a method for preparing a display substrate. The method comprises the following steps:

[0095] First, a first substrate and a second substrate are formed; the first substrate includes a substrate and a circuit layer located on one side of the substrate; the second substrate includes a base substrate and a light shielding layer located on one side of the base substrate.

[0096] Subsequently, a sealing glue is provided on one of the first substrate and the second substrate, and a liquid crystal layer is provided on the other substrate. The first substrate and the second substrate are assembled so that the first substrate and the second substrate are bonded together by the sealing glue, and the sealing glue surrounds the liquid crystal layer.

[0097] In one embodiment, the preparation process of the first substrate may include the following steps:

[0098] First, a first electrode layer is formed on a substrate;

[0099] Subsequently, an insulating film layer is formed on a side of the first electrode layer away from the substrate;

[0100] Subsequently, a first conductive layer is formed on a side of the insulating film layer away from the substrate, wherein the first conductive layer includes a gate of the first transistor and a gate of the second transistor;

[0101] Subsequently, a gate insulating layer is formed on a side of the first conductive layer away from the substrate;

[0102] Subsequently, an active film layer is formed on a side of the gate insulating layer away from the substrate, wherein the active film layer includes an active layer of the first transistor and an active layer of the second transistor;

[0103] Subsequently, an interlayer dielectric layer is formed on a side of the active film layer away from the substrate, and a plurality of through holes are formed penetrating the interlayer dielectric layer;

[0104] Subsequently, a second conductive layer is formed on a side of the interlayer dielectric layer away from the substrate, the second conductive layer including a first electrode and a second electrode of the first transistor, and a first electrode and a second electrode of the second transistor, the first electrode and the second electrode of the first transistor being electrically connected to the active layer of the first transistor via a through hole penetrating the interlayer dielectric layer, and the first electrode and the second electrode of the second transistor being electrically connected to the active layer of the second transistor via a through hole penetrating the interlayer dielectric layer;

[0105] Subsequently, a passivation layer is formed on a side of the second conductive layer away from the substrate;

[0106] Subsequently, a second electrode layer is formed on a side of the passivation layer away from the substrate.

[0107] The embodiment of the method for preparing a display substrate provided in this application and the embodiment of the display substrate belong to the same inventive concept, and the description of relevant details and beneficial effects can be referred to each other, and will not be repeated here.

[0108] The present application also provides a display device, which includes the display substrate described in any one of the above embodiments.

[0109] In one embodiment, the display substrate further includes a backlight source, and the backlight source is located on a side of the first substrate away from the second substrate.

[0110] In one embodiment, the display device further includes a flexible circuit board and a driving chip. The flexible circuit board is electrically connected to the pins of the pin area, and the driving chip is electrically connected to the flexible circuit board.

[0111] In one embodiment, the display device further includes a first current detection circuit, a second current detection circuit, and a control circuit, wherein the first current detection circuit and the second current detection circuit may be disposed on a flexible printed circuit board. The control circuit may be a control chip.

[0112] In some embodiments, the display device further includes a housing, and the display substrate is embedded in the housing.

[0113] The display device provided in the embodiments of the present application may be any appropriate display device, including but not limited to mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, navigators, e-books, and any other products or components with display functions.

[0114] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it may be the only layer between the two layers or elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0115] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the contents disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0116] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A display substrate, characterized in that, the display substrate comprises: a substrate; a circuit layer located on the substrate, the circuit layer comprising at least one set of detection circuits, scan signal lines, a first output signal line, a second output signal line, and data signal lines, the detection circuit comprising a first sub-detection circuit and a second sub-detection circuit, the first sub-detection circuit comprising at least one first transistor, and the second sub-detection circuit comprising at least one second transistor; the first transistor and the second transistor each comprise a gate, a first pole, and a second pole; the gates of the first transistor and the second transistor are respectively connected to the scan signal line, the first poles of the first transistor and the second transistor are respectively connected to the data signal line, the second pole of the first transistor is connected to the first output signal line, and the second pole of the second transistor is connected to the second output signal line; a light-shielding layer located on a side of the circuit layer away from the substrate, a positive projection of the channel region of the first transistor on the substrate being covered by a positive projection of the light-shielding layer on the substrate, and a positive projection of the channel region of the second transistor on the substrate having no overlap with the positive projection of the light-shielding layer on the substrate.

2. The display substrate according to claim 1, characterized in that, the display substrate comprises a display area and a peripheral area located on at least one side of the display area; the detection circuit and each signal line connected to the detection circuit are both located in the peripheral area.

3. The display substrate according to claim 2, characterized in that, the peripheral area comprises a plurality of sub-peripheral areas, each of the sub-peripheral areas being located on one side of the display area; each transistor of the detection circuit is located in the same sub-peripheral area.

4. The display substrate according to claim 2, characterized in that, the display substrate further comprises a liquid crystal layer located between the circuit layer and the light-shielding layer, the detection circuit being located in the peripheral area, the liquid crystal layer comprising a plurality of liquid crystal molecules; the display substrate further comprises at least one row of first sub-pixels located between the second sub-detection circuit and the display area, the first sub-pixels comprising liquid crystal molecules, and a long axis direction of the liquid crystal molecules of the first sub-pixels being perpendicular to a surface of the substrate.

5. The display substrate according to claim 1, characterized in that, in the same detection circuit, the number of the first transistors and the number of the second transistors are both a plurality, and in the same detection circuit, the first transistors are connected in parallel, and the second transistors are connected in parallel.

6. The display substrate according to claim 5, characterized in that, in the same detection circuit, the first transistors and the second transistors are arranged along a row direction or a column direction.

7. The display substrate according to claim 6, characterized in that, The channel regions of the first transistor and the second transistor respectively include a source region and a drain region. When the first transistor and the second transistor are arranged in a row direction, the source region and the drain region extend in a column direction; when the first transistor and the second transistor are arranged in a column direction, the source region and the drain region extend in a row direction.

8. The display substrate according to claim 6, wherein, in the same detection circuit, the first transistor and the second transistor are in the same row, and the first transistor and the second transistor are arranged alternately; or, the first transistor and the second transistor are in the same column, and the first transistor and the second transistor are arranged alternately; the first transistor and the second transistor are connected to the same scan signal line and the same data signal line.

9. The display substrate according to claim 8, wherein, the circuit layer includes a first conductive layer and a second conductive layer; in the same detection circuit, the extending directions of the first output signal line and the second output signal line are respectively the same as the arrangement directions of the first transistor and the second transistor; the second poles of the first transistor and the second transistor are located in the second conductive layer, and at least one of the first output signal line and the second output signal line is located in the first conductive layer.

10. The display substrate according to claim 9, wherein, both the first output signal line and the second output signal line are located in the first conductive layer.

11. The display substrate according to claim 6, wherein, in the same detection circuit, each of the first transistors and each of the second transistors are in the same row, and all the first transistors are adjacent, and all the second transistors are arranged adjacent to each other; or, each of the first transistors and each of the second transistors are in the same column, and all the first transistors are adjacent, and all the second transistors are arranged adjacent to each other.

12. The display substrate according to claim 6, wherein, in the same detection circuit, each of the first transistors is in the same row, each of the second transistors is in the same row, and the first transistor and the second transistor are in different rows; or, each of the first transistors is in the same column, each of the second transistors is in the same column, and the first transistor and the second transistor are in different columns.

13. The display substrate according to claim 12, wherein, the display substrate includes a peripheral region, the circuit layer further includes a plurality of pins and a first connection line located in the peripheral region; the scan signal line includes a first scan signal line and a second scan signal line; in the same detection circuit, the first poles of each of the first transistors are connected to the first scan signal line, the first poles of each of the second transistors are connected to the second scan signal line, and both ends of the first connection line are connected to the ends on the same side of the first scan signal line and the second scan signal line; the first connection line is connected to the pins.

14. The display substrate according to claim 12, It is characterized in that the display substrate includes a peripheral area, and the display substrate further includes a plurality of pins and second connection lines located in the peripheral area; the data signal lines include first data signal lines and second data signal lines; in the same detection circuit, the first poles of the first transistors are connected to the first data signal lines, the first poles of the second transistors are connected to the second data signal lines, two ends of the second connection lines are respectively connected to ends on the same side of the first data signal lines and the second data signal lines; the second connection lines are connected to the pins.

15. The display substrate according to claim 6, It is characterized in that in the same detection circuit, the number of the first transistors is the same as the number of the second transistors.

16. The display substrate according to claim 1, It is characterized in that the light-shielding layer is provided with a plurality of hollow portions, the first transistors and the second transistors include active layers, a positive projection of one hollow portion on the substrate covers a positive projection of an active layer of a transistor on the substrate, and a distance between adjacent hollow portions is greater than or equal to 100 μm.

17. The display substrate according to claim 1, It is characterized in that the display substrate includes a common electrode layer, the common electrode layer is provided with an opening, a positive projection of the first transistor on the substrate falls within a positive projection of the opening on the substrate, and a positive projection of the second transistor on the substrate falls within a positive projection of the opening on the substrate.

18. The display substrate according to claim 17, It is characterized in that in the same detection circuit, positive projections of the first transistors on the substrate and positive projections of the second transistors on the substrate all fall within a positive projection of an opening on the substrate.

19. The display substrate according to claim 1, It is characterized in that the display substrate includes a display area; the display substrate further includes a common voltage signal line surrounding the display area and at least part of the common electrode layer located in the display area, the common voltage signal line is electrically connected to the common electrode layer, and the detection circuit is located between the common electrode layer and the common voltage signal line.

20. A display device, It is characterized in that the display device includes the display substrate according to any one of claims 1 to 19.

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