A design method, device, equipment and storage medium for many-core processor architecture

Abstract

The present invention discloses a design method, device, equipment and storage medium for a many-core processor architecture, relating to the field of distributed computing technology. The design method comprises the following steps: 1: dividing all cores into groups; 2: integrating a CPU pipeline, an intra-core private memory, a hardware FIFO queue and a DMA engine within each core; 3: labeling the cores within each group according to their coordinates, storing shared data of the processors within the group using the intra-group shared memory, and controlling the inter-group communication interface through the intra-group master core to transmit and receive NoC data packets for intra-group communication; and 4: planning an optimal inter-group transmission path based on the coordinates of the cores of the source processor group and the target processor group for transmission, for inter-group communication. The present invention dynamically optimizes NoC transmission by automatically calculating the shortest path between groups. The hardware FIFO and DMA engine are used to achieve low-latency data transmission, and the master core exchanges data efficiently between groups through the NoC to achieve response.

Description

Technical Field

[0001] The present invention discloses a design method, device, equipment and storage medium for a many-core processor architecture, and relates to the field of distributed computing technology. Background Art

[0002] Many-core processors (MCPs) are processor architectures that integrate a large number of simple computing cores. They improve overall performance through parallel computing and are widely used in fields such as high-performance computing, artificial intelligence, and big data processing. As the scale of MCPs increases, existing architectures face challenges with inter-core communication, including poor scalability, high latency, and congestion. In particular, designs with shared memory within a group and a fixed master core present significant communication bottlenecks and load imbalance, limiting overall performance improvements. Summary of the Invention

[0003] In response to the problems of the prior art, the present invention provides a design method, apparatus, device and storage medium for a many-core processor architecture. The method dynamically optimizes NoC transmission by automatically calculating the shortest path between groups. Hardware FIFO and DMA engines are used within the group to achieve low-latency data transmission. The main core exchanges data efficiently between groups through the NoC to achieve interrupt / polling response.

[0004] The specific scheme proposed by the present invention is:

[0005] The present invention provides a design method for a many-core processor architecture, based on a many-core processor, comprising:

[0006] Step 1: Divide all cores into groups. Each group has a fixed number of cores. Specify the master core and common cores of each group. The master cores between groups are connected through NoC and are responsible for inter-group communication.

[0007] Step 2: Integrate the CPU pipeline, in-core private memory, hardware FIFO queue, and DMA engine within each core. Use the CPU pipeline to perform calculations and logical task processing; use the in-core private memory to store data required for calculations; use the hardware FIFO queue to store requests from ordinary cores or responses from the main core; and use the DMA engine to transfer calculation or status data between the main core and ordinary cores.

[0008] Step 3: Label the cores in each group according to their coordinates. Each group integrates an intra-group shared memory and an inter-group communication interface. The intra-group shared memory is used to store the shared data of the processors in the group. The inter-group communication interface is controlled by the main core in the group to send and receive NoC data packets for intra-group communication.

[0009] Step 4: Based on the coordinates of the cores of the source processor group and the target processor group, plan the optimal transmission path between the groups for inter-group communication.

[0010] Furthermore, in step 3 of the method for designing a many-core processor architecture, the process of data transmission between cores in a group is as follows:

[0011] Step 31: Submit a request to the main core through the normal core:

[0012] The normal core writes the request to the local hardware FIFO and marks the target as the main core.

[0013] After the main core detects the request through interruption or polling, it reads the message from the hardware FIFO.

[0014] The main core executes the request;

[0015] Step 32: The main core returns the operation result to the common core:

[0016] After the main core completes the operation, it determines whether the operation result is a response or data.

[0017] If the operation result is a response, the result is written into the local hardware FIFO of the master core, and the target is marked as the normal core that issued the request;

[0018] If the operation result is data, the result data is directly transferred to the private memory of the target core through the DMA engine.

[0019] Ordinary cores obtain results through interrupts or polling.

[0020] Furthermore, in step 4 of the design method for a many-core processor architecture, the master core communicates between the groups via the NoC, and the process is as follows:

[0021] Step 41: The main core of the source processor group encapsulates the inter-group communication information into a message, sends it to the main core of the target processor group through the NoC network, and determines the NoC transmission path according to the optimal path planning;

[0022] Step 42: After the main core of the target processor group processes the request, it returns a response.

[0023] The present invention also provides a design device for a many-core processor architecture, based on a many-core processor including a main core and a common core.

[0024] All cores are divided into groups, each with a fixed number of cores, and each group is assigned a master core and a common core. The master cores between groups are connected via NoC, which is responsible for inter-group communication.

[0025] Each core integrates the CPU pipeline, in-core private memory, hardware FIFO queue, and DMA engine. The CPU pipeline is used for calculation and logical task processing; the in-core private memory is used to store the data required for calculation; the hardware FIFO queue is used to store the requests of the common core or the responses of the main core; and the DMA engine is used to transfer operation or status data between the main core and the common core.

[0026] Each core in the group is numbered according to its coordinates. Each group integrates an intra-group shared memory and an inter-group communication interface. The intra-group shared memory is used to store the shared data of the processors in the group. The inter-group communication interface is controlled by the main core in the group to send and receive NoC data packets for intra-group communication.

[0027] According to the coordinates of the cores of the source processor group and the target processor group, the optimal transmission path between the groups is planned for inter-group communication.

[0028] Furthermore, the data transmission process between cores in a group of the design device for a many-core processor architecture is as follows:

[0029] Step 31: Submit a request to the main core through the normal core:

[0030] The normal core writes the request to the local hardware FIFO and marks the target as the main core.

[0031] After the main core detects the request through interruption or polling, it reads the message from the hardware FIFO.

[0032] The main core executes the request;

[0033] Step 32: The main core returns the operation result to the common core:

[0034] After the main core completes the operation, it determines whether the operation result is a response or data.

[0035] If the operation result is a response, the result is written into the local hardware FIFO of the master core, and the target is marked as the normal core that issued the request;

[0036] If the operation result is data, the result data is directly transferred to the private memory of the target core through the DMA engine.

[0037] Ordinary cores obtain results through interrupts or polling.

[0038] Furthermore, the main core of the design device for a many-core processor architecture communicates between the groups through the NoC, and the process is as follows:

[0039] The main core of the source processor group encapsulates the inter-group communication information into a message and sends it to the main core of the target processor group through the NoC network. The NoC transmission path is determined based on the optimal path planning;

[0040] The master core of the target processor group processes the request and returns a response.

[0041] The present invention also provides a design device for a many-core processor architecture, comprising: at least one memory and at least one processor;

[0042] The at least one memory is configured to store a machine-readable program;

[0043] The at least one processor is configured to call the machine-readable program to execute the method for designing a many-core processor architecture.

[0044] The present invention also provides a storage medium on which computer instructions are stored. When the computer instructions are executed by a processor, the processor executes the design method of a many-core processor architecture.

[0045] The benefits of the present invention are:

[0046] Implement hardware-level optimal path planning: automatically calculate the shortest path between groups and dynamically optimize NoC transmission;

[0047] Implementing an efficient communication mechanism: Hardware FIFO and DMA engines are used within the group to achieve low-latency data transmission. The main core exchanges data efficiently between groups through the NoC, supporting interrupt / polling responses.

[0048] The architecture of the present invention is suitable for scenarios such as high-performance computing and AI training, and significantly improves the communication efficiency and parallel computing capabilities of many-core processors. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 This is a schematic diagram of the hardware interconnection between groups in the layered many-core processor architecture.

[0050] Figure 2 It is a schematic diagram of the structure within the layered many-core processor architecture group.

[0051] Figure 3 It is a schematic diagram of the internal structure of the layered many-core processor architecture. DETAILED DESCRIPTION

[0052] NoC (Network on Chip), on-chip network, NoC transmission is a network-based communication interconnection method within the system on chip (SoC).

[0053] The present invention will be further described below with reference to the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it. However, the embodiments are not intended to limit the present invention.

[0054] Embodiment 1: The present invention provides a design method for a many-core processor architecture, based on a many-core processor, comprising:

[0055] Step 1: Divide all cores into groups. Each group has a fixed number of cores. Specify the master core and ordinary cores for each group. The master cores between groups are connected through NoC and are responsible for inter-group communication.

[0056] Step 2: Integrate the CPU pipeline, in-core private memory, hardware FIFO queue, and DMA engine within each core. Use the CPU pipeline for calculations and logical task processing; use the in-core private memory to store the data required for calculations; use the hardware FIFO queue to store requests from ordinary cores or responses from the main core; and use the DMA engine to transfer calculation or status data between the main core and the ordinary core.

[0057] Step 3: Label each core within the group according to its coordinates. Each group integrates intra-group shared memory and inter-group communication interfaces. The intra-group shared memory is used to store the shared data of the processors within the group. The inter-group communication interface is controlled by the main core within the group to send and receive NoC data packets for intra-group communication.

[0058] The data transmission process between cores in a group is as follows:

[0059] Step 31: Submit a request to the main core through the normal core:

[0060] The normal core writes the request to the local hardware FIFO and marks the target as the main core.

[0061] After the main core detects the request through interruption or polling, it reads the message from the hardware FIFO.

[0062] The main core executes the request;

[0063] Step 32: The main core returns the operation result to the common core:

[0064] After the main core completes the operation, it determines whether the operation result is a response or data.

[0065] If the operation result is a response, the result is written into the local hardware FIFO of the master core, and the target is marked as the normal core that issued the request;

[0066] If the operation result is data, the result data is directly transferred to the private memory of the target core through the DMA engine.

[0067] Ordinary cores obtain results through interrupts or polling.

[0068] Step 4: Based on the coordinates of the cores of the source processor group and the target processor group, plan the optimal transmission path between the groups for inter-group communication.

[0069] The main core communicates between groups through the NoC. The process is as follows:

[0070] Step 41: The main core of the source processor group encapsulates the inter-group communication information into a message, sends it to the main core of the target processor group through the NoC network, and determines the NoC transmission path according to the optimal path planning;

[0071] Step 42: After the main core of the target processor group processes the request, it returns a response.

[0072] The main core can be dynamically adjusted according to the direction of inter-group communication. For example, the right core is selected for horizontal communication, and the lower core is selected for vertical communication, to reduce the number of hops and balance the load.

[0073] For example, Figure 1 As shown in the figure, the primary core changes depending on the position of two adjacent core groups. For example, when transferring from Group 0_0 to Group 1_1, the primary cores are Core 2_2 of Group 0_0 and Core 0_0 of Group 1_1; when transferring from Group 0_1 to Group 0_2, the primary cores are Core 1_2 of Group 0_1 and Core 1_0 of Group 0_2, and so on.

[0074] When planning the optimal transmission path based on the coordinates of the source processor group and the target processor group, for example, when transmitting from Group 0_0 to Group 1_2, the optimal transmission path is Group 0_0 to Group 1_1 to Group 1_2.

[0075] When transferring data, let's take the scenario where Core 1_1 of Group 0_0 needs to access the shared memory data of Group 1_2 as an example. The execution steps are as follows:

[0076] S1: Optimal path planning:

[0077] Query the optimal path planning and obtain the path: Group (0,0)→Group (1,1)→Group (1,2).

[0078] S2: Perform the first hop transmission Group (0,0) → Group (1,1):

[0079] S21: Initiate a request within the group:

[0080] Core (1,1) of Group (0,0) writes the request packet into the local FIFO.

[0081] Mark the target: Master_Core(2,2),

[0082] Specify the operation type: Remote_Read (Group 1_2, 0x1234),

[0083] S22: Main core processing:

[0084] Master_Core(2,2) of Group(0,0) detects that FIFO is not empty.

[0085] Parse the request and find that cross-group communication is required;

[0086] Encapsulate NoC packet header: src=(0,0), dst=(1,1);

[0087] Select interface: Based on the relative position (1,1), use the southeast interface;

[0088] Send to Master_Core(0,0) of Group(1,1).

[0089] S3: Perform the second hop transmission Group 1_1 → Group 1_2:

[0090] Core 0_0 parses the request and finds that cross-group communication is required;

[0091] The request is transmitted to Core 1_2 through Group 1_1's hardware FIFO;

[0092] Encapsulate NoC packet header: src=(1,1), dst=(1,2),

[0093] Select the eastbound interface to send to Core 1_0 of Group 1_2.

[0094] S4: Target group processing:

[0095] Core 1_0 of Group 1_2 accesses local shared memory 0x1234 and transmits the data and ACK response back to Core 2_2 of Group 0_0 through the original path.

[0096] S5: Result returned:

[0097] After receiving the ACK, Core 2_2 of Group 0_0 updates the status and triggers DMA to transfer the return data to the private memory of Core 1_1.

[0098] Embodiment 2: The present invention also provides a design device for a multi-core processor architecture, based on a multi-core processor including a main core and a common core.

[0099] All cores are divided into groups, each with a fixed number of cores, and each group is assigned a master core and a common core. The master cores between groups are connected via NoC, which is responsible for inter-group communication.

[0100] Each core integrates the CPU pipeline, in-core private memory, hardware FIFO queue, and DMA engine. The CPU pipeline is used for calculation and logical task processing; the in-core private memory is used to store the data required for calculation; the hardware FIFO queue is used to store the requests of the common core or the responses of the main core; and the DMA engine is used to transfer operation or status data between the main core and the common core.

[0101] Each core in the group is numbered according to its coordinates. Each group integrates an intra-group shared memory and an inter-group communication interface. The intra-group shared memory is used to store the shared data of the processors in the group. The inter-group communication interface is controlled by the main core in the group to send and receive NoC data packets for intra-group communication.

[0102] According to the coordinates of the cores of the source processor group and the target processor group, the optimal transmission path between the groups is planned for inter-group communication.

[0103] Since the information interaction, execution process and other contents between the modules in the above-mentioned device are based on the same concept as the embodiment of the method of the present invention, the specific contents can be found in the description of the embodiment of the method of the present invention and will not be repeated here.

[0104] Similarly, the device of the present invention can achieve hardware-level optimal path planning: automatically calculate the shortest path between groups and dynamically optimize NoC transmission; realize efficient communication mechanism: use hardware FIFO and DMA engine to achieve low-latency data transmission within the group, and the main core exchanges data efficiently between groups through NoC, supporting interrupt / polling response;

[0105] The architecture of the present invention is suitable for scenarios such as high-performance computing and AI training, and significantly improves the communication efficiency and parallel computing capabilities of many-core processors.

[0106] It should be noted that not all steps and modules in the above-mentioned processes and device structures are required, and certain steps or modules can be omitted according to actual needs. The execution order of each step is not fixed and can be adjusted as needed. The system structure described in the above-mentioned embodiments can be a physical structure or a logical structure, that is, some modules may be implemented by the same physical entity, or some modules may be implemented by multiple physical entities, or may be implemented by certain components in multiple independent devices.

[0107] Embodiment 3: The present invention further provides a design device for a many-core processor architecture, comprising: at least one memory and at least one processor;

[0108] The at least one memory is configured to store a machine-readable program;

[0109] The at least one processor is configured to call the machine-readable program to execute the method for designing a many-core processor architecture.

[0110] The information interaction, execution of readable program process, etc. of the processor in the above-mentioned device are based on the same concept as the embodiment of the method of the present invention. The specific contents can be found in the description of the embodiment of the method of the present invention and will not be repeated here.

[0111] Similarly, the device of the present invention can implement hardware-level optimal path planning: automatically calculate the shortest path between groups and dynamically optimize NoC transmission; realize efficient communication mechanism: guide the use of hardware FIFO and DMA engine within the group to achieve low-latency data transmission, and the main core between groups efficiently exchanges data through NoC, supporting interrupt / polling response.

[0112] Embodiment 4: The present invention further provides a storage medium storing computer instructions. When executed by a processor, the computer instructions cause the processor to execute the method for designing a many-core processor architecture. Specifically, a system or device equipped with a storage medium can be provided. The storage medium stores software program code that implements the functions of any of the above embodiments, and the computer (or CPU or MPU) of the system or device reads and executes the program code stored in the storage medium.

[0113] In this case, the program code itself read from the storage medium can realize the function of any one of the above-mentioned embodiments, and thus the program code and the storage medium storing the program code constitute part of the present invention.

[0114] Examples of storage media for providing program code include floppy disks, hard disks, magneto-optical disks, optical disks (e.g., CD-ROMs, CD-Rs, CD-RWs, DVD-ROMs, DVD-RAMs, DVD-RWs, and DVD+RWs), magnetic tapes, non-volatile memory cards, and ROMs. Alternatively, the program code may be downloaded from a server computer via a communications network.

[0115] In addition, it should be clear that the functions of any of the above embodiments can be achieved not only by executing the program code read by the computer, but also by enabling the operating system operating on the computer to complete part or all of the actual operations based on the instructions of the program code.

[0116] In addition, it can be understood that the program code read from the storage medium is written into the memory provided in the expansion board inserted into the computer or into the memory provided in the expansion unit connected to the computer, and then based on the instructions of the program code, the CPU installed on the expansion board or expansion unit is enabled to perform part or all of the actual operations, thereby realizing the functions of any of the above embodiments.

[0117] The above embodiments are merely preferred embodiments for the purpose of fully illustrating the present invention, and the scope of protection of the present invention is not limited thereto. Equivalent substitutions or modifications made by those skilled in the art based on the present invention are within the scope of protection of the present invention. The scope of protection of the present invention shall be subject to the claims.

Claims

1. A design method for a many-core processor architecture, characterized by Based on a many-core processor, including: Step 1: Divide all cores into groups. Each group has a fixed number of cores. Specify the master core and common cores of each group. The master cores between groups are connected through NoC and are responsible for inter-group communication. Step 2: Integrate the CPU pipeline, in-core private memory, hardware FIFO queue, and DMA engine within each core. Use the CPU pipeline to perform calculations and logical task processing; use the in-core private memory to store data required for calculations; use the hardware FIFO queue to store requests from ordinary cores or responses from the main core; and use the DMA engine to transfer calculation or status data between the main core and ordinary cores. Step 3: Label the cores in each group according to their coordinates. Each group integrates an intra-group shared memory and an inter-group communication interface. The intra-group shared memory is used to store the shared data of the processors in the group. The inter-group communication interface is controlled by the main core in the group to send and receive NoC data packets for intra-group communication. The data transmission process between cores in a group is as follows: Step 31: Submit a request to the main core through the normal core: The normal core writes the request to the local hardware FIFO and marks the target as the main core. After the main core detects the request through interruption or polling, it reads the message from the hardware FIFO. The main core executes the request; Step 32: The main core returns the operation result to the common core: After the main core completes the operation, it determines whether the operation result is a response or data. If the operation result is a response, the result is written into the local hardware FIFO of the master core, and the target is marked as the normal core that issued the request; If the operation result is data, the result data is directly transferred to the private memory of the target core through the DMA engine. Ordinary cores obtain results through interrupts or polling; Step 4: Based on the coordinates of the cores of the source processor group and the target processor group, plan the optimal transmission path between the groups for inter-group communication.

2. The design method of a many-core processor architecture according to claim 1, Its characteristic is that in step 4, the main core communicates between the groups through the NoC, and the process is as follows: Step 41: The main core of the source processor group encapsulates the inter-group communication information into a message, sends it to the main core of the target processor group through the NoC network, and determines the NoC transmission path according to the optimal path planning; Step 42: After the main core of the target processor group processes the request, it returns a response.

3. A design device for a multi-core processor architecture, characterized by Based on multi-core processors, including main cores and ordinary cores, All cores are divided into groups, each with a fixed number of cores, and each group is assigned a master core and a common core. The master cores between groups are connected via NoC, which is responsible for inter-group communication. Each core integrates the CPU pipeline, in-core private memory, hardware FIFO queue, and DMA engine, and uses the CPU pipeline to perform calculations and logical task processing; Use private memory within the core to store data required for calculation; The hardware FIFO queue stores the requests of the common core or the responses of the main core; the DMA engine is used to transfer operation or status data between the main core and the common core; Each core in the group is numbered according to its coordinates. Each group integrates an intra-group shared memory and an inter-group communication interface. The intra-group shared memory is used to store the shared data of the processors in the group. The inter-group communication interface is controlled by the master core in the group to send and receive NoC data packets for intra-group communication. The data transmission process between the cores in the group is as follows: Step 31: Submit a request to the main core through the normal core: The normal core writes the request to the local hardware FIFO and marks the target as the main core. After the main core detects the request through interruption or polling, it reads the message from the hardware FIFO. The main core executes the request; Step 32: The main core returns the operation result to the common core: After the main core completes the operation, it determines whether the operation result is a response or data. If the operation result is a response, the result is written into the local hardware FIFO of the master core, and the target is marked as the normal core that issued the request; If the operation result is data, the result data is directly transferred to the private memory of the target core through the DMA engine. Ordinary cores obtain results through interrupts or polling; According to the coordinates of the cores of the source processor group and the target processor group, the optimal transmission path between the groups is planned for inter-group communication.

4. The design device of a multi-core processor architecture according to claim 3, characterized in that the main The core communicates between groups through the NoC. The process is as follows: The main core of the source processor group encapsulates the inter-group communication information into a message and sends it to the main core of the target processor group through the NoC network. The NoC transmission path is determined based on the optimal path planning; The master core of the target processor group processes the request and returns a response.

5. A design device for a multi-core processor architecture, characterized by include: at least one memory and at least one processor; The at least one memory is configured to store a machine-readable program; The at least one processor is configured to call the machine-readable program to execute the method for designing a many-core processor architecture according to claim 1 or 2.

6. A storage medium characterized by The storage medium stores computer instructions, which, when executed by a processor, enable the processor to execute the design method for a many-core processor architecture according to claim 1 or 2.

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