Radar system based on high-speed synchronous serial interface, communication method and device

Abstract

The invention discloses a radar system based on a high-speed synchronous serial interface and a communication method and device, and the system comprises a transmitting end and a plurality of subsystems corresponding to the transmitting end, and the transmitting end is in communication connection with each subsystem through the high-speed synchronous serial interface and a timing signal interface; the sending end comprises a central interface and a timing subsystem; the central interface receives commands and data sent by the display control system, and the timing subsystem generates radar timing synchronization pulses; the communication mode of the sending end and the subsystem is configured to enable signals, synchronous clock signals and serial data signals to transmit differential level signals in a three-wire synchronous serial mode; under the triggering of a radar timing synchronization pulse, a sending end simultaneously sends single-ended signals of enabling, a synchronous clock and serial data to a corresponding subsystem; and realizing time sequence synchronization in the radar system by adopting a running water time sequence mechanism of preprocessing in the current period and taking effect in the next period. According to the invention, high-speed and long-distance reliable communication is realized while the number of cables is reduced, and the hardware complexity and cost are greatly reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of radar, and particularly to a radar system, a communication method, a device, equipment and a medium based on a high-speed synchronous serial interface. Background Art

[0002] A radar system is a relatively complex electronic device, which consists of subsystems with multiple different task functions. Among the subsystems, commands, statuses, and data need to be transmitted within an orderly time to achieve the detection function and performance of the entire radar.

[0003] In the existing communication technologies between radar subsystems: Parallel data interface: Data bits are transmitted simultaneously through multiple data lines. Although it can achieve a relatively high instantaneous bandwidth, the number of its wires is proportional to the number of data bits. When transmitting multiple types of information between radar subsystems, a large number of wires and connector terminals are required, resulting in a significant increase in the volume, weight, and cost of the system. In addition, during long-distance transmission, parallel signals are vulnerable to interference, and the transmission rate needs to be reduced to ensure stability, making it difficult to balance efficiency and reliability. If we want to optimize and match the data transmission requirements between different subsystems, special designs need to be made, increasing the complexity of the system. In addition, once the design is finalized, if we want to increase the number of communication data bits and address coding bits, the number of wires and connector terminal numbers will also increase accordingly, indicating poor scalability of the system.

[0004] Network data interface: Based on bit-stream transmission, the theoretical rate can reach more than 100 Mbps, but due to the encapsulation overhead of network protocols (such as TCP / IP) and the packet exchange mechanism, the actual effective transmission rate is significantly reduced. Especially within the radar pulse repetition period (usually less than 2 ms), it is difficult to complete high-frequency, small-data real-time command interactions and cannot meet the stringent requirements of radar timing synchronization.

[0005] Optical fiber data interface: The optical fiber interface has high bandwidth, low loss, and strong anti-electromagnetic interference ability, but its deployment cost is relatively high, and there are compatibility problems between the physical characteristics of optical fibers (such as fragility and bending radius limitations) and the mechanical structures of radar subsystems (mostly pull-out designs). In addition, the debugging and maintenance complexity of the optical fiber interface is relatively high, restricting its wide application in radar systems.

[0006] Asynchronous serial interface: The asynchronous serial interface uses single-line transmission and has a simple structure, but the communication rate is usually only a few hundred kbps, making it difficult to meet the real-time requirements of massive data exchange between radar subsystems. Its byte-level transmission mechanism is difficult to coordinate with the radar cycle synchronization signal, easily leading to timing deviation and affecting the overall performance of the system. Summary of the Invention

[0007] The present invention provides a radar system, a communication method, a device, equipment and a medium based on a high-speed synchronous serial interface, which solves the problem of realizing high-speed, synchronous and reliable data interaction within the radar repetition period while reducing the system complexity and cost.

[0008] To achieve the above object, the present application adopts the following technical solutions: In a first aspect, a radar system based on a high-speed synchronous serial interface is provided, including: A sending end and a plurality of corresponding subsystems, and the sending end is communicatively connected to each subsystem through a high-speed synchronous serial interface and a timing signal interface; The sending end includes a central interface and a timing subsystem; the central interface receives commands and data sent by the display control system, and the timing subsystem generates radar timing synchronization pulses; The communication mode between the sending end and the subsystem is configured to transmit differential level signals in a three-wire synchronous serial mode of an enable signal, a synchronous clock signal and a serial data signal; Under the trigger of the radar timing synchronization pulse, the sending end simultaneously sends single-ended signals of an enable signal, a synchronous clock and serial data to the corresponding subsystem.

[0009] In a first possible implementation manner of the first aspect, the high-speed synchronous serial interface is configured as a full-duplex communication interface connected by twisted pair wires, and the timing signal interface is configured as a unidirectional interface.

[0010] In a second possible implementation manner of the first aspect, the radar system adopts a pipeline timing mechanism of preprocessing in the current cycle and taking effect in the next cycle, and realizes timing synchronization in the radar system, including: The timing subsystem generates radar timing synchronization pulses and transmits them to all subsystems in the form of differential level signals; When the sending end needs to send data, the enable signal is set from logic 0 to logic 1. After being triggered by the timing synchronization pulse, the serial data is output bit by bit in sequence; after a set clock cycle, the data bit is written at the falling edge of the synchronous clock signal; the single-ended signal generates an anti-interference differential signal through a differential level conversion circuit and is transmitted to the target subsystem through impedance-matched twisted pair wires; where logic 1 represents the working state and logic 0 represents the idle state; The differential level conversion circuit of the subsystem restores the differential signal transmitted by the sending end to a single-ended signal; After the subsystem detects that the enable signal is logic 1, it samples the serial data at each rising edge of the synchronous clock signal until the enable signal changes from logic 1 to logic 0 and then terminates, completing the reception of a frame of data; the serial data is parsed into parallel commands and data according to the protocol and temporarily stored in the buffer; The sub-system performs preprocessing operations other than execution on the parsed commands and data within the radar repetition period of t; after the radar timing synchronization pulse of the t+1 radar repetition period arrives at the sub-system, the preprocessed commands and data become officially effective and drive the sub-system to perform corresponding operations; and optionally send the commands and data executed in the t-1 radar repetition period to the sending end.

[0011] In a second aspect, a communication method for a radar system based on a high-speed synchronous serial interface is provided, including: The timing sub-system generates a radar timing synchronization pulse and transmits it to all sub-systems in the form of a differential level signal; When the sending end needs to send data, the enable signal changes from logic 0 to logic 1. After being triggered by the timing synchronization pulse, the serial data is output bit by bit in sequence; after a set clock cycle, the data bit is written at the falling edge of the synchronous clock signal; the single-ended signal generates an anti-interference differential signal through a differential level conversion circuit and is transmitted to the target sub-system through a twisted pair with impedance matching; among them, logic 1 represents the working state and logic 0 represents the idle state; The differential level conversion circuit of the sub-system restores the differential signal transmitted by the sending end to a single-ended signal; After the sub-system detects that the enable signal is logic 1, it samples the serial data at each rising edge of the synchronous clock signal until the enable signal changes from logic 1 to logic 0 and then terminates, completing the reception of one frame of data; the serial data is parsed into parallel commands and data according to the protocol and temporarily stored in the buffer; The sub-system performs preprocessing operations other than execution on the parsed commands and data within the radar repetition period of t; after the radar timing synchronization pulse of the t+1 radar repetition period arrives at the sub-system, the preprocessed commands and data become officially effective and drive the sub-system to perform corresponding operations; and optionally send the commands and data executed in the t-1 radar repetition period to the sending end.

[0012] In the first possible implementation manner of the second aspect, the preprocessing includes verification; After the transmission of a single frame of data is completed, if the data frame verification of the sub-system is incorrect, the frame of data is discarded and a retransmission is requested.

[0013] In a third aspect, a communication device for a radar system based on a high-speed synchronous serial interface is provided, including: A timing sub-system module for configuring the timing sub-system to generate a radar timing synchronization pulse and transmit it to all sub-systems in the form of a differential level signal; The transmission module is used to configure that when the sending end is about to send data, the enable signal changes from logic 0 to logic 1. After being triggered by the timing synchronization pulse, the serial data is output bit by bit in sequence. After a set clock cycle, the data bit is written at the falling edge of the synchronous clock signal. The single-ended signal is converted into an anti-interference differential signal by the differential level conversion circuit and transmitted to the target subsystem through the twisted pair with impedance matching. Among them, logic 1 represents the working state and logic 0 represents the idle state. The receiving module is used to configure the differential level conversion circuit of the subsystem to restore the differential signal transmitted by the sending end to a single-ended signal. After the subsystem detects that the enable signal is logic 1, it samples the serial data at each rising edge of the synchronous clock signal until the enable signal changes from logic 1 to logic 0 and then terminates, completing the reception of one frame of data. The serial data is parsed into parallel commands and data according to the protocol and temporarily stored in the buffer. The timing module is used to configure the subsystem to perform preprocessing operations other than execution on the parsed commands and data within the t radar repetition period. After the radar timing synchronization pulse of the t + 1 radar repetition period arrives at the subsystem, the preprocessed commands and data become effective and drive the subsystem to perform corresponding operations. And optionally, send the commands and data executed in the t - 1 radar repetition period to the sending end.

[0014] In a fourth aspect, an electronic device is provided, which includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the computer program is executed by the processor, it implements the steps of the method described in the second aspect.

[0015] In a fifth aspect, a readable storage medium is provided, on which a program or instruction is stored. When the program or instruction is executed by a processor, it implements the steps of the method described in the second aspect.

[0016] The radar system based on the high-speed synchronous serial interface of the present invention has the following advantages: The communication method between the sending end and the subsystem of this application is configured as a three-wire synchronous serial mode of the enable signal, synchronous clock signal, and serial data signal and differential transmission technology, which realizes high-speed and long-distance reliable communication while reducing the number of cables. It solves the problems of synchronization, real-time performance, and reliability of communication between radar subsystems within the radar repetition period, and at the same time greatly reduces the hardware complexity and cost.

[0017] The communication method, device, electronic device, and readable storage medium corresponding to the radar system based on the high-speed synchronous serial interface of the present invention can achieve the same technical effects. To avoid repetition, they are not elaborated here. Description of the Drawings

[0018] Figure 1Schematic diagram of the communication interface of a radar system based on a high-speed synchronous serial interface provided by an embodiment of the present application; Figure 2 Schematic diagram of the interface principle between radar subsystems provided by an embodiment of the present application; Figure 3 Timing diagram of a high-speed synchronous serial interface provided by an embodiment of the present application; Figure 4 Timing diagram of high-speed synchronous serial communication with the same repetition frequency in a radar provided by an embodiment of the present application; Figure 5 Schematic flowchart of a communication method for a radar system based on a high-speed synchronous serial interface provided by an embodiment of the present application; Figure 6 Schematic diagram of the structure of a communication device for a radar system based on a high-speed synchronous serial interface provided by an embodiment of the present application; Figure 7 Schematic diagram of the structure of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0019] To further elaborate on the technical means and effects adopted by the present invention to achieve the predetermined purpose, the technical solutions in the embodiments of the present application are clearly described. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of them. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.

[0020] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that such terms can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. generally belong to the same category, and do not limit the number of objects. For example, the first object can be one or more. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally indicates an "or" relationship between the associated objects before and after.

[0021] In the description of the method flow in the specification of the present application and the steps in the flowchart in the drawings of the present invention, it is not necessary to strictly execute according to the step numbers. The execution order of the method steps can be changed. Moreover, some steps can be omitted, multiple steps can be combined into one step for execution, and / or one step can be decomposed into multiple steps for execution.

[0022] The radar system, device, equipment and medium based on a high-speed synchronous serial interface provided by the embodiments of the present application are described in detail as follows in combination with the accompanying drawings and preferred embodiments.

[0023] In the current related technologies, the information exchange communication methods between the subsystems of a radar include parallel data interfaces, network data interfaces, fiber optic data interfaces, asynchronous serial RS485, and asynchronous serial RS232, etc. Traditional interfaces are difficult to be strictly synchronized with the radar timing signals, resulting in the cumulative delay of the commands and data becoming effective. The parallel interface requires a large number of physical lines, and the network and fiber optic interfaces are costly, and the system scalability is poor. For long-distance transmission, the rate needs to be reduced to ensure reliability, and it is difficult to meet the requirements of high rate and long distance simultaneously.

[0024] The existing communication methods have multiple bottlenecks such as efficiency, cost, synchronization, and scalability in the application between the radar subsystems. Based on this, the present invention uses a high-speed synchronous serial interface to realize the information exchange between the radar subsystems, deeply integrates the high-speed synchronous serial interface technology with the timing characteristics of the radar system, can meet the data rate requirements of the information exchange within the radar pulse repetition period, adapt to different communication distance requirements, greatly reduces the number of transmission wires and connectors, and has the advantages of reliable transmission and low cost.

[0025] Please refer to Figure 1 , the embodiment of the present application provides a radar system based on a high-speed synchronous serial interface, as Figure 1 shown, the radar system of the embodiment of the present application includes: A sending end and a plurality of corresponding subsystems, and the sending end is communicatively connected to each subsystem through a high-speed synchronous serial interface and a timing signal interface; The high-speed synchronous serial interface is configured as a full-duplex communication interface connected by twisted pair wires, and the timing signal interface is configured as a unidirectional interface; The sending end includes a central interface and a timing subsystem; the central interface receives the commands and data sent by the display control system, and the timing subsystem generates a radar timing synchronization pulse as the global timing reference; The communication method between the sending end and the subsystems is configured to transmit differential level signals in a three-wire synchronous serial manner of an enable signal, a synchronous clock signal, and a serial data signal; The sending end uses an FPGA to packet and package the commands and data sent by the display control system into commands and data corresponding to each subsystem according to a preset communication protocol; under the trigger of the radar timing synchronization pulse, it simultaneously sends single-ended signals of enable, synchronous clock, and serial data to the corresponding subsystem through a differential level conversion circuit; After each subsystem receives the differential signal, it restores it to a single-ended signal through a differential level conversion circuit, and converts the received serial data into corresponding commands and data according to the communication protocol as the basis for the operation of this subsystem; Among them, a pipeline timing mechanism of preprocessing in the current cycle and taking effect in the next cycle is adopted to achieve timing synchronization in the radar system.

[0026] Exemplarily: The communication interface between radar subsystems is composed as follows Figure 1 As shown in the figure, the line segments with arrows represent twisted pair wire groups, and the arrows represent the signal flow directions. The solid lines are high-speed synchronous serial ports, and the interfaces are full-duplex communication interfaces. The dashed lines are timing signals, and the timing signal interfaces are unidirectional interfaces, from the central interface and the timing subsystem to each of the other subsystems.

[0027] The interface principle between radar subsystems is as follows Figure 2 As shown in the figure, the "central interface and timing subsystem" receives the commands and data sent by the display and control. The FPGA packs these commands and data into the commands and data required by the corresponding subsystems according to the agreed communication protocol, converts the parallel data into serial data, and under the trigger of the "timing signal", the FPGA uses the three ports defined as "enable, synchronous clock, and serial data" to start sending "enable, synchronous clock, and serial data" to the corresponding subsystems simultaneously. After passing through the "differential electrical conversion circuit", three differential level signals are output and transmitted to the opposite-end subsystem through impedance-matched twisted pairs.

[0028] The relevant radar subsystems receive "enable, synchronous clock, and serial data" in differential levels. After passing through the "differential level conversion circuit", three single-ended "enable, synchronous clock, and data bitstreams" are output to the three ports defined by the FPGA respectively. The FPGA receives the "serial data" according to the "enable and synchronous clock", and converts the received "serial data" into commands and data according to the communication protocol as the working basis for this subsystem.

[0029] Furthermore, referring to Figure 5 , the radar system adopts a pipelined timing mechanism of preprocessing in the current cycle and taking effect in the next cycle to achieve timing synchronization in the radar system, including: Step S1, the timing subsystem generates a radar timing synchronization pulse and transmits it to all subsystems in the form of a differential level signal.

[0030] Step S2, when the sending end wants to send data, the enable signal is set from logic 0 to logic 1. After being triggered by the timing synchronization pulse, the serial data is output bit by bit in sequence; after a set clock cycle, the data bit is written at the falling edge of the synchronous clock signal; the single-ended signal generates an anti-interference differential signal through the differential level conversion circuit and is transmitted to the target subsystem through impedance-matched twisted pairs. Among them, logic 1 represents the working state, and logic 0 represents the idle state.

[0031] Referring to Figure 3 , the timing of the high-speed synchronous serial interface is as follows Figure 3As shown in the figure, in the figure, T is the synchronous clock period, bit is the serial data bit, and n is the total number of serial data bits to be sent (usually a multiple of 8). When the serial port does not send data, the "enable" signal port of the FPGA is logic "0", and the "synchronous clock" signal port is logic "1"; when data needs to be sent, the transmitting-end FPGA first changes the "enable" signal from logic "0" to logic "1". After T / 2 clock cycles, at the falling edge of the "synchronous clock" signal, the FPGA writes the data bit to the "serial data" port.

[0032] Step S3, the differential level conversion circuit of the subsystem restores the differential signal transmitted by the transmitting end to a single-ended signal.

[0033] Step S4, after the subsystem detects that the enable signal is logic 1, it samples the serial data at each rising edge of the synchronous clock signal until the enable signal changes from logic 1 to logic 0 and then terminates, completing the reception of one frame of data; the serial data is parsed into parallel commands and data according to the protocol and temporarily stored in the buffer.

[0034] After receiving the logic "1" at the "enable" port as the receiving end, the subsystem samples the data according to the rising edge of the "synchronous clock" sent by the transmitting end. During the period when the "enable" port is logic "1", the receiving end continuously samples the data on the condition of the rising edge of the "synchronous clock" until the "enable" signal becomes logic "0", and then terminates sampling the data. Thus, one data communication (i.e., one frame of data packet) is completed.

[0035] Step S5, the subsystem performs preprocessing operations other than execution on the parsed commands and data within the t radar repetition period; after the radar timing synchronization pulse of the t + 1 radar repetition period arrives at the subsystem, the preprocessed commands and data become effective and drive the subsystem to perform corresponding operations; and optionally, send the commands and data executed in the t - 1 radar repetition period to the transmitting end.

[0036] See Figure 4 , the application timing of the radar with the same repetition frequency for high-speed synchronous serial communication is as Figure 4 shown. In the figure, the radar timing synchronization pulse is Figure 2 the timing signal sent by the "timing subsystem" to each subsystem in differential level. t is the radar repetition period, t0, t1, tn represent the radar cycle order, and one frame of data packet is Figure 3 the data communication carried out using the high-speed synchronous serial interface as shown in

[0037] Triggered by the radar timing synchronization pulse, the central interface sends the control command data packet of the current t cycle to all subsystems simultaneously. When each subsystem receives the data from the central interface, it can send the working commands and data of the t-1 cycle to the central interface. All subsystems only preprocess the received command data within the current t cycle. After receiving the radar timing synchronization pulse of the t+1 cycle, the command data received in the t cycle becomes effective.

[0038] The pipelined working mode of the above pipelined timing mechanism ensures the synchronization of radar data and command status. Moreover, this mode enables the radar not to require dedicated data exchange time, saving radar time resources.

[0039] And in some possible implementation manners, the preprocessing includes operations such as verification. After the transmission of a single-frame data is completed, if the subsystem (receiver) detects an error in the data frame verification, it can discard the frame data and request retransmission. A two-way pipelined communication is formed.

[0040] Based on the above technical solutions, the present application has the following advantages: (1) High-speed synchronous serial communication is used for information exchange between radar subsystems, which can meet the real-time requirements for information exchange between communication radar subsystems; (2) Each subsystem only needs 6 pairs of twisted pairs to achieve two-way real-time communication, and the connector only needs 12 terminals, greatly reducing the transmission wires and connectors, reducing the volume, weight, and cost; high-speed and long-distance reliable communication is achieved while reducing the number of cables; (3) Differential level transmission has stronger anti-interference ability than ordinary single-ended signals, with reliable transmission, low bit error rate, and meets the requirements for high-speed reliable transmission at different communication lengths from several meters to dozens of meters between radar subsystems; (4) The communication mode of the present application enables the radar not to require dedicated command data exchange time, which not only ensures the synchronization of radar data and command status but also saves radar time resources; (5) Using the communication mode of the present application in the radar is simple to debug, has generality, is easy to expand, and is easy to standardize. The communication rate and the number of bits are based on the specific requirements of the radar and can be configured by software.

[0041] Please refer to Figure 5 , corresponding to the above embodiment of the radar system based on a high-speed synchronous serial interface, the embodiment of the present application provides a communication method for a radar system based on a high-speed synchronous serial interface. As shown in the figure, the communication method of the embodiment of the present application includes: The timing subsystem generates a radar timing synchronization pulse and transmits it to all subsystems in the form of a differential level signal; When the sending end needs to send data, the enable signal changes from logic 0 to logic 1. After being triggered by the timing synchronization pulse, the serial data is output bit by bit. After a set clock cycle, the data bit is written at the falling edge of the synchronous clock signal. The single-ended signal is converted into an anti-interference differential signal through a differential level conversion circuit and transmitted to the target subsystem through a twisted pair with impedance matching. Among them, logic 1 represents the working state, and logic 0 represents the idle state. The differential level conversion circuit of the subsystem restores the differential signal transmitted by the sending end to a single-ended signal. After the subsystem detects that the enable signal is logic 1, it samples the serial data at each rising edge of the synchronous clock signal until the enable signal changes from logic 1 to logic 0 and then terminates, completing the reception of a frame of data. The serial data is parsed into parallel commands and data according to the protocol and temporarily stored in the buffer. The subsystem performs preprocessing operations other than execution on the parsed commands and data within the radar repetition period of t. After the radar timing synchronization pulse of the (t + 1) radar repetition period arrives at the subsystem, the preprocessed commands and data become effective and drive the subsystem to perform corresponding operations. And optionally, the commands and data executed in the (t - 1) radar repetition period are sent to the sending end.

[0042] Furthermore, the preprocessing includes verification. After the transmission of a single frame of data is completed, if the data frame verification of the subsystem is incorrect, the frame of data is discarded and a retransmission is requested.

[0043] The above method implements the steps and various processes of the embodiment of the radar system based on the high-speed synchronous serial interface as described above, and can achieve the same technical effects. To avoid repetition, it will not be elaborated here.

[0044] Please refer to Figure 6 , corresponding to the embodiment of the radar system based on the high-speed synchronous serial interface as described above, the embodiment of the present application provides a communication device for a radar system based on a high-speed synchronous serial interface. As shown in the figure, the communication device of the embodiment of the present application includes: The timing subsystem module 1001 is used to configure the timing subsystem to generate a radar timing synchronization pulse and transmit it to all subsystems in the form of a differential level signal. The transmission module 1002 is used to configure that when the sending end needs to send data, the enable signal changes from logic 0 to logic 1. After being triggered by the timing synchronization pulse, the serial data is output bit by bit. After a set clock cycle, the data bit is written at the falling edge of the synchronous clock signal. The single-ended signal is converted into an anti-interference differential signal through a differential level conversion circuit and transmitted to the target subsystem through a twisted pair with impedance matching. Among them, logic 1 represents the working state, and logic 0 represents the idle state. A receiving module 1003 is configured to use a differential level conversion circuit of a subsystem to restore a differential signal transmitted by a transmitting end to a single-ended signal; After the subsystem detects that the enable signal is logic 1, it collects serial data at each rising edge of the synchronous clock signal until the enable signal changes from logic 1 to logic 0 and then terminates, completing the reception of one frame of data; the serial data is parsed into parallel commands and data according to the protocol and temporarily stored in a buffer; A timing module 1004 is configured to use the subsystem to perform preprocessing operations other than execution on the parsed commands and data within the radar repetition period of t; after the radar timing synchronization pulse of the (t + 1) radar repetition period arrives at the subsystem, the preprocessed commands and data become effective and drive the subsystem to perform corresponding operations; and optionally send the commands and data executed in the (t - 1) radar repetition period to the transmitting end.

[0045] Further, the preprocessing includes verification; After the transmission of a single frame of data is completed, if the data frame verification of the subsystem is incorrect, the frame of data is discarded and a retransmission is requested.

[0046] The above device implements the steps and various processes of the above-described embodiment of the radar system communication method based on a high-speed synchronous serial interface, and can achieve the same technical effects. To avoid repetition, it will not be elaborated here.

[0047] See Figure 7 , corresponding to the above-described embodiment of the radar system communication method based on a high-speed synchronous serial interface, an embodiment of the present application provides an electronic device, which includes: a memory, a processor, and a computer program stored on the memory and executable on the processor. When the computer program is executed by the processor, it implements the steps and various processes of the above-described embodiment of the radar system communication method based on a high-speed synchronous serial interface, and can achieve the same technical effects. To avoid repetition, it will not be elaborated here.

[0048] The memory 1009 can be used to store software programs and various data. The memory 1009 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data. Among them, the first storage area may store an operating system, application programs or instructions required for at least one function (such as a sound playback function, an image playback function, etc.). In addition, the memory 1009 may include a volatile memory or a non-volatile memory, or the memory 1009 may include both a volatile memory and a non-volatile memory. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synchlink dynamic random access memory (SLDRAM), and a direct rambus random access memory (DRRAM). The memory 1009 in the embodiments of the present application includes but is not limited to these and any other suitable types of memories.

[0049] The processor 1010 may include one or more processing units; optionally, the processor 1010 integrates an application processor and a modem processor. Among them, the application processor mainly processes operations related to the operating system, user interface, and application programs, etc., and the modem processor mainly processes wireless communication signals, such as a baseband processor. It can be understood that the above modem processor may not be integrated into the processor 1010 either.

[0050] Corresponding to the above embodiments of the communication method of the radar system based on the high-speed synchronous serial interface, the embodiments of the present application also provide a readable storage medium. A program or instruction is stored on the readable storage medium. When the program or instruction is executed by a processor, the steps and various processes of the above embodiments of the communication method of the radar system based on the high-speed synchronous serial interface are implemented, and the same technical effects can be achieved. To avoid repetition, it will not be elaborated here.

[0051] Among them, the processor is the processor in the electronic device described in the embodiments of the present application above. The readable storage medium includes computer-readable storage media such as computer read-only memory ROM, random access memory RAM, magnetic disks, or optical discs, etc.

[0052] It should be noted that in this article, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including that element. In addition, it should be pointed out that the methods and devices in the embodiments of the present application are not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in the reverse order according to the functions involved. For example, the described methods may be performed in an order different from that described, and various steps may also be added, omitted, or combined. Additionally, the features described with reference to certain examples may be combined in other examples.

[0053] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-described embodiment methods can be implemented by means of software plus a necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disc) and includes several instructions for causing a terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present application.

[0054] It can be understood that the embodiments of the present application have been described above in conjunction with the accompanying drawings. However, the present application is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Those skilled in the art know that without departing from the spirit and scope of the present invention, these features and embodiments can be variously changed or equivalently replaced. Additionally, those of ordinary skill in the art, under the inspiration or teaching of the present application, can modify these features and embodiments to adapt to specific situations and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of the present application belong to the scope protected by the present invention.

Claims

1. A radar system based on a high-speed synchronous serial interface, characterized in that Comprising: A transmitting end and a plurality of corresponding subsystems, where the transmitting end is communicatively connected to each subsystem through a high-speed synchronous serial interface and a timing signal interface; The transmitting end includes a central interface and a timing subsystem; The central interface receives commands and data sent by the display and control system, and the timing subsystem generates radar timing synchronization pulses; The communication mode between the transmitting end and the subsystems is configured to transmit differential level signals in a three-wire synchronous serial mode of an enable signal, a synchronous clock signal, and a serial data signal; Triggered by the radar timing synchronization pulse, the transmitting end simultaneously sends single-ended signals of enable, synchronous clock, and serial data to the corresponding subsystems.

2. The radar system based on a high-speed synchronous serial interface according to claim 1, wherein The high-speed synchronous serial interface is configured as a full-duplex communication interface connected by twisted pair wires, and the timing signal interface is configured as a unidirectional interface.

3. The radar system based on a high-speed synchronous serial interface according to claim 1, wherein The radar system adopts a pipeline timing mechanism of current cycle preprocessing and next cycle effective, and realizes timing synchronization in the radar system, including: The timing subsystem generates radar timing synchronization pulses and transmits them to all subsystems in the form of differential level signals; When the transmitting end needs to send data, the enable signal is set from logic 0 to logic 1, and the serial data is output bit by bit; after a set clock cycle, the data bit is written at the falling edge of the synchronous clock signal; the single-ended signal generates an anti-interference differential signal through a differential level conversion circuit and is transmitted to the target subsystem through impedance-matched twisted pair wires; where logic 1 represents the working state and logic 0 represents the idle state; The differential level conversion circuit of the subsystem restores the differential signal transmitted by the transmitting end to a single-ended signal; After the subsystem detects that the enable signal is logic 1, it samples the serial data at each rising edge of the synchronous clock signal until the enable signal changes from logic 1 to logic 0 and then terminates, completing the reception of one frame of data; the serial data is parsed into parallel commands and data according to the protocol and temporarily stored in the buffer; The subsystem performs preprocessing operations other than execution on the parsed commands and data within the t radar repetition period; after the radar timing synchronization pulse of the t + 1 radar repetition period arrives at the subsystem, the preprocessed commands and data become effective formally, driving the subsystem to perform corresponding operations; and optionally sending the commands and data executed in the t - 1 radar repetition period to the transmitting end.

4. A communication method for a radar system based on a high-speed synchronous serial interface, characterized in that, Comprising: The timing subsystem generates radar timing synchronization pulses and transmits them to all subsystems in the form of differential level signals; When the transmitting end needs to send data, the enable signal is set from logic 0 to logic 1, and the serial data is output bit by bit; after a set clock cycle, the data bit is written at the falling edge of the synchronous clock signal; the single-ended signal generates an anti-interference differential signal through a differential level conversion circuit and is transmitted to the target subsystem through impedance-matched twisted pair wires; where logic 1 represents the working state and logic 0 represents the idle state; The differential level conversion circuit of the subsystem restores the differential signal transmitted by the transmitting end to a single-ended signal; After the subsystem detects that the enable signal is logic 1, it samples the serial data at each rising edge of the synchronous clock signal until the enable signal changes from logic 1 to logic 0, at which point the reception of one frame of data is completed; the serial data is parsed into parallel commands and data according to the protocol and temporarily stored in the buffer; The subsystem performs preprocessing operations other than execution on the parsed commands and data within the t radar repetition period; after the radar timing synchronization pulse of the t+1 radar repetition period arrives at the subsystem, the preprocessed commands and data become effective and drive the subsystem to perform corresponding operations; And optionally send the commands and data executed in the t-1 radar repetition period to the sending end.

5. The radar system communication method based on a high-speed synchronous serial interface according to claim 4, characterized in that, The preprocessing includes verification; After the transmission of a single frame of data is completed, if the data frame verification of the subsystem is incorrect, the frame of data is discarded and a retransmission is requested.

6. A radar system communication device based on a high-speed synchronous serial interface, characterized in that, Including: A timing subsystem module for configuring the timing subsystem to generate a radar timing synchronization pulse and transmit it to all subsystems in the form of a differential level signal; A transmission module for configuring the sending end to set the enable signal to change from logic 0 to logic 1 when sending data, and output the serial data bit by bit; after a set clock cycle, write the data bit at the falling edge of the synchronous clock signal; the single-ended signal is converted into an anti-interference differential signal through a differential level conversion circuit and transmitted to the target subsystem through a twisted pair with impedance matching; where logic 1 represents the working state and logic 0 represents the idle state; A receiving module for configuring the differential level conversion circuit of the subsystem to restore the differential signal transmitted by the sending end to a single-ended signal; After the subsystem detects that the enable signal is logic 1, it samples the serial data at each rising edge of the synchronous clock signal until the enable signal changes from logic 1 to logic 0, at which point the reception of one frame of data is completed; the serial data is parsed into parallel commands and data according to the protocol and temporarily stored in the buffer; A timing module for configuring the subsystem to perform preprocessing operations other than execution on the parsed commands and data within the t radar repetition period; after the radar timing synchronization pulse of the t+1 radar repetition period arrives at the subsystem, the preprocessed commands and data become effective and drive the subsystem to perform corresponding operations; and optionally send the commands and data executed in the t-1 radar repetition period to the sending end.

7. The radar system communication device based on a high-speed synchronous serial interface according to claim 6, characterized in that, The preprocessing includes verification; After the transmission of a single frame of data is completed, if the data frame verification of the subsystem is incorrect, the frame of data is discarded and a retransmission is requested.

8. An electronic device, characterized in that, The electronic device includes: a memory, a processor, and a computer program stored on the memory and executable on the processor, and when the computer program is executed by the processor, it implements the steps of the radar system based on a high-speed synchronous serial interface according to any one of claims 4 to 5.

9. A readable storage medium, characterized in that, A program or instruction is stored on the readable storage medium, and when the program or instruction is executed by the processor, it implements the steps of the radar system based on a high-speed synchronous serial interface according to any one of claims 4 to 5.

Images