Display device

Abstract

The present disclosure provides a display device with low power consumption. The display device includes a pixel circuit. The pixel circuit includes a driving transistor, a light-emitting control transistor, and a light-emitting element. The light-emitting control transistor is electrically connected to a first voltage terminal and the driving transistor. The light-emitting element is electrically connected to a second voltage terminal and the driving transistor. The voltage value of the second voltage end is lower than that of the first voltage end. The voltage value of the second voltage end in the compensation stage of the pixel circuit is different from the voltage value of the second voltage end in the light emitting stage of the pixel circuit.

Description

Technical Field

[0001] The present disclosure relates to a display device, and particularly to a display device with low power consumption. Background Art

[0002] In a high-brightness environment, the pixel circuit of a display device has a high-brightness operation requirement. Therefore, a pixel circuit with a light-emitting diode will operate with a high drive current value for a long time. This causes the power consumption of the display device to increase. Summary of the Invention

[0003] The present disclosure is directed to a display device with low power consumption.

[0004] According to an embodiment of the present disclosure, a display device includes a pixel circuit. The pixel circuit includes a driving transistor, a light-emitting control transistor, and a light-emitting element. The light-emitting control transistor is electrically connected to a first voltage terminal and the driving transistor. The light-emitting element is electrically connected to a second voltage terminal and the driving transistor. The voltage value of the second voltage terminal is lower than that of the first voltage terminal. The voltage value of the second voltage terminal in the compensation stage of the pixel circuit is different from the voltage value of the second voltage terminal in the light-emitting stage of the pixel circuit.

[0005] According to an embodiment of the present disclosure, a display device includes a pixel circuit. The pixel circuit includes a light-emitting control transistor, a driving transistor, a light-emitting element, and a scanning transistor. The driving transistor is electrically connected to a first voltage terminal and the light-emitting control transistor. The light-emitting element is electrically connected to a second voltage terminal and the light-emitting control transistor. The voltage value of the second voltage terminal is less than that of the first voltage terminal. The scanning transistor is electrically connected to the driving transistor and receives a scanning signal. The voltage value of the scanning signal in the reset stage of the pixel circuit is the same as the voltage value of the scanning signal in the scanning stage of the pixel circuit.

[0006] Based on the above, on the current path between the first voltage terminal and the second voltage terminal, the pixel circuit includes a driving transistor, a light-emitting control transistor, and a light-emitting element. In a current pixel circuit that meets the high-brightness requirement, at least three transistors and a light-emitting element are included on the current path between the first voltage terminal and the second voltage terminal. Therefore, compared with a current pixel circuit that meets the high-brightness requirement, the pixel circuit of the present disclosure has lower power consumption. In this way, the display device also has lower power consumption. Description of the Drawings

[0007] Figure 1 is a circuit diagram and an operation timing diagram of a pixel circuit of a display device shown according to an embodiment of the present disclosure;

[0008] Figure 2 is a schematic diagram of an operation timing diagram shown according to an embodiment of the present disclosure;

[0009] Figure 3 is a schematic diagram of an operation timing diagram shown in an embodiment of the present disclosure;

[0010] Figure 4 is a schematic diagram of a pixel circuit of a display device shown in an embodiment of the present disclosure;

[0011] Figure 5 is an operation timing diagram shown in an embodiment of the present disclosure;

[0012] Figure 6 is an operation timing diagram shown in an embodiment of the present disclosure;

[0013] Figure 7 is an application scenario diagram of a display device shown in an embodiment of the present disclosure.

[0014] Description of Reference Numerals

[0015] 100, 200, 300: Display device

[0016] A, B: Nodes

[0017] C1, C2: Capacitors

[0018] COMP: Compensation signal

[0019] F1, F2: Frame periods

[0020] EM: Light emission control signal

[0021] ID: Drive current

[0022] IMG: Image

[0023] LE: Light emitting element

[0024] PIMG: Projected image

[0025] PVDD: First voltage terminal

[0026] PVSS: Second voltage terminal

[0027] PX1, PX2: Pixel circuits

[0028] R[1]~R[2N]: Pixel rows

[0029] RST: Reset signal

[0030] SC: Scan signal

[0031] SD: Data signal

[0032] SH: Update stage

[0033] STC: Compensation stage

[0034] STE: Luminescence stage

[0035] STR: Reset stage

[0036] STS: Scanning stage

[0037] TC: Compensation transistor

[0038] TD: Driving transistor

[0039] TE: Luminescence control transistor

[0040] TR: Reset transistor

[0041] TS: Scanning transistor

[0042] t0 to t8: Time points

[0043] VH, VL: Voltage values

[0044] VRST: Reset voltage

[0045] WW: Windshield Detailed implementation manners

[0046] This disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings described below. It should be noted that, for the purpose of clear illustration and easy understanding by the reader, each of the accompanying drawings of this disclosure shows a part of the electronic device, and some elements in each of the accompanying drawings may not be drawn to scale. In addition, the number and size of each device shown in the accompanying drawings are only illustrative and are not intended to limit the scope of this disclosure.

[0047] Certain terms are used throughout the description and the following claims to refer to specific elements. As those skilled in the art will understand, electronic device manufacturers may refer to elements by different names. This document is not intended to distinguish between elements that have different names but the same functions. In the following description and in the claims, the terms "comprising", "including" and "having" are used in an open-ended manner and should therefore be interpreted as meaning "including but not limited to". Therefore, when the terms "comprising", "including" and / or "having" are used in the description of this disclosure, it will indicate the presence of corresponding features, regions, steps, operations and / or elements, but not limited to the presence of one or more corresponding features, regions, steps, operations and / or elements.

[0048] It should be understood that when an element is referred to as being "coupled to", "connected to", or "conducted to" another element, the element can be directly connected to the other element and an electrical connection can be directly established, or there can be intermediate elements between these elements for relaying the electrical connection (indirect electrical connection). In contrast, when an element is referred to as being "directly coupled to", "directly conducted to", or "directly connected to" another element, there are no intermediate elements.

[0049] Although terms such as first, second, third, etc. may be used to describe different constituent elements, such constituent elements are not limited by these terms. The terms are only used to distinguish the constituent elements in the specification from other constituent elements. The scope of the claims may not use the same terms, but may use terms such as first, second, third, etc. relative to the order required for the elements. Thus, in the following description, the first constituent element may be the second constituent element in the scope of the claims.

[0050] The display device of the present disclosure may include a pixel circuit. The pixel circuit may include a light-emitting diode, which may include, for example, an organic light-emitting diode (OLED), a mini light-emitting diode (mini LED), a micro light-emitting diode (micro LED), or a quantum dot light-emitting diode (quantum dot LED, which may include QLED, QDLED), or other suitable materials, or a combination of the above, but not limited thereto. The display device may include, for example, a tiled display device, but not limited thereto. The antenna device may be, for example, a liquid crystal antenna, but not limited thereto. The antenna device may include, for example, an antenna tiling device, but not limited thereto. It should be noted that the electronic device can be any of the foregoing arrangements and combinations, but not limited thereto. In addition, the shape of the electronic device can be rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronic device can have peripheral systems such as a driving system, a control system, a light source system, etc. to support the display device, the antenna device, or the tiling device, but the present disclosure is not limited thereto. The sensing device may include a camera, an infrared sensor, a fingerprint sensor, etc., and the present disclosure is not limited thereto. In some embodiments, the sensing device may further include a flash, an infrared (IR) light source, other sensors, electronic components, or a combination of the above, but not limited thereto.

[0051] In the present disclosure, embodiments use "pixel" or "pixel unit" as a unit for describing a specific area containing at least one functional circuit for at least one specific function. The area of a "pixel" depends on the unit for providing a specific function, and adjacent pixels may share the same part or wire, but may also include its own specific part therein. For example, adjacent pixels may share the same scan line or the same data line, but a pixel may also have its own transistor or capacitor.

[0052] It should be noted that the technical features in the following described different embodiments can be replaced, reorganized, or mixed with each other without departing from the spirit of the present disclosure to form another embodiment.

[0053] Please refer to Figure 1 , Figure 1 is a circuit diagram and an operation timing diagram of a pixel circuit of a display device shown according to an embodiment of the present disclosure. In this embodiment, the display device 100 includes a pixel circuit PX1. The pixel circuit PX1 includes a driving transistor TD, a light-emitting control transistor TE, and a light-emitting element LE. The light-emitting control transistor TE is electrically connected to the first voltage terminal PVDD and the driving transistor TD. The light-emitting element LE is electrically connected to the second voltage terminal PVSS and the driving transistor TD. The voltage value of the second voltage terminal PVSS is lower than the voltage value of the first voltage terminal PVDD. That is to say, the light-emitting control transistor TE, the driving transistor TD, and the light-emitting element LE are connected in series between the first voltage terminal PVDD and the second voltage terminal PVSS.

[0054] It is worth mentioning here that on the current path between the first voltage terminal PVDD and the second voltage terminal PVSS, the pixel circuit PX1 includes a driving transistor TD, a light-emitting control transistor TE, and a light-emitting element LE. Compared with the current pixel circuit that meets the high-brightness requirement (for example, including at least three transistors and a light-emitting element on the current path between the first voltage terminal PVDD and the second voltage terminal PVSS), the pixel circuit PX1 has lower power consumption. In this way, the display device 100 also has lower power consumption.

[0055] For example, the power consumption P1 of the current pixel circuit that meets the high-brightness requirement is as shown in formula (1).

[0056] P1 = (V1 + V2 + V3 + VLED) × IDD... formula (1)

[0057] "V1", "V2", "V3" are represented as the voltage drops of three transistors on the current path of the current pixel circuit. "VLED" is represented as the voltage drop of the light-emitting element of the current pixel circuit. "IDD" is represented as the current value on the current path of the current pixel circuit.

[0058] In this embodiment, the power consumption P2 of the pixel circuit PX1 is as shown in formula (2).

[0059] P2 = (VTD + VTE + VLE) × IDD... formula (2)

[0060] "VTD" is represented as the gate-source voltage of the driving transistor TD. "VTE" is represented as the gate-source voltage of the light-emitting control transistor TE. "VLED" is represented as the voltage across the light-emitting element of the current pixel circuit. "IDD" is represented as the current value on the current path of the current pixel circuit. Therefore, the power consumption P2 of the pixel circuit PX1 can be lower than the power consumption P1 of the current pixel circuit.

[0061] In this embodiment, the operation of the pixel circuit PX1 can be divided into a reset stage STR, a compensation stage STC, and a light-emitting stage STE. The voltage value VH of the second voltage terminal PVSS in the compensation stage STC of the pixel circuit PX1 is different from the voltage value VL of the second voltage terminal PVSS in the light-emitting stage STE of the pixel circuit PX1. Further, the voltage value VH of the second voltage terminal PVSS in the compensation stage STC is higher than the voltage value VL of the second voltage terminal PVSS in the light-emitting stage STE. Therefore, the light-emitting element LE is in a reverse bias state in the compensation stage STC. In the compensation stage STC, the current value of the driving current ID on the current path between the first voltage terminal PVDD and the second voltage terminal PVSS is substantially equal to "0". In this way, the pixel circuit PX1 can avoid the light-emitting element LE being forward-biased and emitting light erroneously in the compensation stage STC.

[0062] In this embodiment, the first terminal of the light-emitting control transistor TE is electrically connected to the first voltage terminal PVDD. The control terminal of the light-emitting control transistor TE receives the light-emitting control signal EM. The first terminal of the driving transistor TD is electrically connected to the anode of the light-emitting element LE. The second terminal of the driving transistor TD is electrically connected to the second terminal of the light-emitting control transistor TE. The cathode of the light-emitting element LE is electrically connected to the second voltage terminal PVSS.

[0063] In this embodiment, the pixel circuit PX1 further includes a compensation transistor TC, a scanning transistor TS, a reset transistor TR, and a capacitor C1. The compensation transistor TC is electrically connected between the control terminal of the driving transistor TD and the first terminal of the driving transistor TD. The first terminal of the compensation transistor TC is electrically connected to the control terminal of the driving transistor TD. The second terminal of the compensation transistor TC is electrically connected to the first terminal of the driving transistor TD. The control terminal of the compensation transistor TC receives the scanning signal SC.

[0064] The first terminal of the scanning transistor TS receives the data signal SD. The second terminal of the scanning transistor TS is electrically connected to the second terminal of the driving transistor TD and the second terminal of the light-emitting control transistor TE. The control terminal of the scanning transistor TS receives the scanning signal SC.

[0065] A first end of a reset transistor TR receives a reset voltage VRST. A second end of the reset transistor TR is electrically connected to a first end of a compensation transistor TC and a control end of a driving transistor TD. A control end of the reset transistor TR receives a reset signal RST.

[0066] A capacitor C1 is electrically connected between a first end of a light-emitting control transistor TE and a control end of the driving transistor TD.

[0067] In this embodiment, the driving transistor TD, the light-emitting control transistor TE, the compensation transistor TC, the scanning transistor TS, and the reset transistor TR can be implemented by P-type transistors respectively, but the present disclosure is not limited thereto.

[0068] In this embodiment, during a reset stage STR between a time point t1 and a time point t2, a voltage value of the reset signal RST is equal to a low voltage value. Voltage values of the scanning signal SC and the light-emitting control signal EM are equal to high voltage values respectively. Therefore, the light-emitting control transistor TE, the compensation transistor TC, and the scanning transistor TS are turned off. The reset transistor TR is turned on to use the reset voltage VRST to reset a voltage value at the control end of the driving transistor TD. Therefore, the driving transistor TD is turned on. In addition, during the reset stage STR, a second voltage terminal PVSS has a voltage value VH. The voltage value VH of the second voltage terminal PVSS during the reset stage STR is different from a voltage value VL of the second voltage terminal PVSS during a light-emitting stage STE. The light-emitting element LE is in a reverse-biased state during the reset stage STR.

[0069] During a compensation stage STC between a time point t3 and a time point t4, a voltage value of the scanning signal SC is equal to a low voltage value. Voltage values of the reset signal RST and the light-emitting control signal EM are equal to high voltage values respectively. Therefore, the light-emitting control transistor TE and the reset transistor TR are turned off. The scanning transistor TS and the compensation transistor TC are turned on. At an initial stage of the compensation stage STC, the driving transistor TD is turned on. Therefore, during the compensation stage STC, the voltage value at the control end of the driving transistor TD is determined by a voltage value of a data signal SD and a threshold voltage value of the driving transistor TD. The voltage value at the control end of the driving transistor TD is substantially equal to an absolute threshold voltage value of the driving transistor TD plus the voltage value of the data signal SD. Therefore, when a driving current ID is generated, the driving current ID can be reduced by the influence of the threshold voltage value of the driving transistor TD.

[0070] In addition, in the compensation stage STC, the second voltage terminal PVSS also has a voltage value VH. That is to say, the voltage value VH of the second voltage terminal PVSS in the reset stage STR is the same as the voltage value VH of the second voltage terminal PVSS in the compensation stage STC. Therefore, the voltage value VH of the second voltage terminal PVSS in the compensation stage STC is different from the voltage value VL of the second voltage terminal PVSS in the light-emitting stage STE. In addition, the light-emitting element LE is in the reverse bias state in the compensation stage STC.

[0071] In the light-emitting stage STE after the time point t5, the voltage value of the light-emitting control signal EM is equal to the low voltage value. The voltage values of the scan signal SC and the reset signal RST are equal to the high voltage value respectively. Therefore, the compensation transistor TC, the scan transistor TS, and the reset transistor TR are turned off. The light-emitting control transistor TE is turned on. The second voltage terminal PVSS has a voltage value VL. The light-emitting element LE is in the forward bias state in the light-emitting stage STE. Therefore, when the light-emitting element LE is in the forward bias state and the light-emitting control transistor TE is turned on, the drive current ID is generated according to the voltage value at the control terminal of the drive transistor TD. Therefore, in the light-emitting stage STE, the light-emitting element LE can emit light based on the voltage value at the control terminal of the drive transistor TD.

[0072] In some embodiments, the drive transistor TD, the light-emitting control transistor TE, the compensation transistor TC, the scan transistor TS, and the reset transistor TR can be implemented by N-type transistors respectively. Therefore, those skilled in the art can change the voltage levels of the reset signal RST, the scan signal SC, and the light-emitting control signal EM according to the types of the drive transistor TD, the light-emitting control transistor TE, the compensation transistor TC, the scan transistor TS, and the reset transistor TR.

[0073] Please refer to Figure 1 and Figure 2 , Figure 2It is a schematic diagram of an operation timing diagram shown according to an embodiment of the present disclosure. In this embodiment, a plurality of pixel circuits PX1 of the display device 100 are grouped into pixel rows R[1] to R[2N]. The second voltage terminal PVSS is provided to a reference electrode (not shown) of the display device 100. During the frame period F1, the time periods of the reset phases STR of the pixel rows R[1] to R[2N] do not overlap with each other. The time periods of the compensation phases STC of the pixel rows R[1] to R[2N] do not overlap with each other. For example, the time period of the reset phase STR of the pixel row R[2] is later than the time period of the reset phase STR of the pixel row R[1], and at least partially overlaps with the time period of the compensation phase STC of the pixel row R[1]. The time period of the reset phase STR of the pixel row R[3] is later than the time period of the reset phase STR of the pixel row R[2], and at least partially overlaps with the time period of the compensation phase STC of the pixel row R[2], and so on.

[0074] In addition, during the frame period F1, the time periods of the light-emitting phases STE of the pixel rows R[1] to R[2N] may at least partially overlap with each other. The time lengths of the light-emitting phases STE of the pixel rows R[1] to R[2N] are the same as each other, but not limited thereto. The second voltage terminal PVSS has a voltage value VL during the light-emitting phase STE. During the reset and compensation periods other than the light-emitting phase STE, the second voltage terminal PVSS has a voltage value VH. The operation timing of the frame period F2 is similar to the operation timing of the frame period F1.

[0075] Please refer to Figure 1 and Figure 3 , Figure 3 It is a schematic diagram of an operation timing diagram shown according to an embodiment of the present disclosure. In this embodiment, a plurality of pixel circuits PX1 of the display device 100 are grouped into pixel rows R[1] to R[2N]. The second voltage terminal PVSS1 is provided to a first reference electrode (not shown) of the display device 100. The second voltage terminal PVSS2 is provided to a second reference electrode (not shown) of the display device 100. In this embodiment, the first reference electrode corresponds to the pixel rows R[1] to R[N]. The second reference electrode corresponds to the pixel rows R[N + 1] to R[2N].

[0076] The periods of the reset phase STR of pixel rows R[1] to R[N] do not overlap with each other. The periods of the compensation phase STC of pixel rows R[1] to R[N] do not overlap with each other. For example, the period of the reset phase STR of pixel row R[2] is later than the period of the reset phase STR of pixel row R[1], and at least partially overlaps with the period of the compensation phase STC of pixel row R[1]. The periods of the light-emitting phase STE of pixel rows R[1] to R[N] may at least partially overlap with each other. The second voltage terminal PVSS1 has a voltage value VL during the light-emitting phase STE of pixel rows R[1] to R[N]. During the reset and compensation periods other than the light-emitting phase STE of pixel rows R[1] to R[N], the second voltage terminal PVSS1 has a voltage value VH.

[0077] The periods of the reset phase STR of pixel rows R[N + 1] to R[2N] do not overlap with each other. The periods of the compensation phase STC of pixel rows R[N + 1] to R[2N] do not overlap with each other. For example, the period of the reset phase STR of pixel row R[N + 2] is later than the period of the reset phase STR of pixel row R[N + 1], and at least partially overlaps with the period of the compensation phase STC of pixel row R[N + 1]. The periods of the light-emitting phase STE of pixel rows R[N + 1] to R[2N] may at least partially overlap with each other. The second voltage terminal PVSS2 has a voltage value VL during the light-emitting phase STE of pixel rows R[N + 1] to R[2N]. During the reset and compensation periods other than the light-emitting phase STE of R[N + 1] to R[2N], the second voltage terminal PVSS1 has a voltage value VH. It should be noted that the time lengths of the light-emitting phase STE of pixel rows R[1] to R[2N] are the same as each other. The second voltage terminal PVSS1 is provided to the first reference electrode of the display device 100. The second voltage terminal PVSS2 is provided to the second reference electrode of the display device 100. The second voltage terminal PVSS1 corresponding to pixel rows R[1] to R[N] and the second voltage terminal PVSS2 corresponding to pixel rows R[N + 1] to R[2N] can be individually controlled. Therefore, the start time points of the light-emitting phase STE of pixel rows R[1] to R[N] and the start time points of the light-emitting phase STE of pixel rows R[N + 1] to R[2N] can be different from each other. In this embodiment, during the reset and compensation periods of frame periods F1 and F2, they can be shortened, and the light-emitting phase STE of multiple pixel circuits PX1 of the display device 100 can be extended. For example, Figure 3 The length of the light-emitting phase STE is approximately Figure 2 Twice the time length of the light-emitting phase STE. In this disclosure, the number of reference electrodes of the display device 100 is not limited, and can be, for example, one, two, or more than two. In this embodiment, the operation of frame period F2 is similar to the operation of frame period F1.

[0078] Please refer to Figure 4, Figure 4 is a schematic diagram of a pixel circuit of a display device according to an embodiment of the present disclosure. In this embodiment, the display device 200 includes a pixel circuit PX2. The pixel circuit PX2 includes a light-emitting control transistor TE, a driving transistor TD, a light-emitting element LE, and a scanning transistor TS. The driving transistor TD is electrically connected to a first voltage terminal PVDD and the light-emitting control transistor TE. The light-emitting element LE is electrically connected to a second voltage terminal PVSS and the light-emitting control transistor TE. The voltage value of the second voltage terminal PVSS is lower than the voltage value of the first voltage terminal PVDD. That is to say, the driving transistor TD, the light-emitting control transistor TE, and the light-emitting element LE are connected in series between the first voltage terminal PVDD and the second voltage terminal PVSS. In addition, the scanning transistor TS is electrically connected to the driving transistor TD and receives a scanning signal SC.

[0079] It is worth mentioning here that on the current path between the first voltage terminal PVDD and the second voltage terminal PVSS, the pixel circuit PX2 includes a driving transistor TD, a light-emitting control transistor TE, and a light-emitting element LE. In current pixel circuits that meet the high-brightness requirement, there are at least three transistors and a light-emitting element on the current path between the first voltage terminal PVDD and the second voltage terminal PVSS. Therefore, compared with current pixel circuits that meet the high-brightness requirement, the pixel circuit PX2 has lower power consumption. In this way, the display device 200 also has lower power consumption.

[0080] In this embodiment, the first end of the driving transistor TD is electrically connected to the first end of the light-emitting control transistor TE. The second end of the driving transistor TD is electrically connected to the first voltage terminal PVDD. The second end of the light-emitting control transistor TE is electrically connected to the anode of the light-emitting element LE. The control end of the light-emitting control transistor TE receives a light-emitting control signal EM. The cathode of the light-emitting element LE is electrically connected to the second voltage terminal PVSS.

[0081] In this embodiment, the pixel circuit PX2 further includes a compensation transistor TC, a reset transistor TR, and capacitors C1, C2. The compensation transistor TC is electrically connected between the control end of the driving transistor TD and the first end of the driving transistor TD. The first end of the compensation transistor TC is electrically connected to the control end of the driving transistor TD. The second end of the compensation transistor TC is electrically connected to the first end of the driving transistor TD. The control end of the compensation transistor TC receives a compensation signal COMP.

[0082] The first end of the reset transistor TR receives a reset voltage VRST. The second end of the reset transistor TR is electrically connected to the first end of the compensation transistor TC and the control end of the driving transistor TD. The control end of the reset transistor TR receives a reset signal RST.

[0083] The capacitor C1 is electrically connected between the second end and the control end of the driving transistor TD.

[0084] The first end of the scanning transistor TS receives the data signal SD. The control end of the scanning transistor TS receives the scanning signal SC. The capacitor C2 is electrically connected between the control end of the driving transistor TD and the second end of the scanning transistor TS.

[0085] In this embodiment, the driving transistor TD, the light-emitting control transistor TE, the compensation transistor TC, the scanning transistor TS, and the reset transistor TR can be respectively implemented by P-type transistors, but the present disclosure is not limited thereto.

[0086] Please refer to Figure 4 and Figure 5 , Figure 5 is an operation timing diagram shown according to an embodiment of the present disclosure. In this embodiment, the operation of the pixel circuit PX2 can be divided into a reset stage STR, a compensation stage STC, a scanning stage STS, and a light-emitting stage STE.

[0087] In this embodiment, during the period from time point t0 to time point t5, the voltage value of the scanning signal SC is equal to the low voltage value.

[0088] In the reset stage STR between time point t1 and time point t2, the voltage value of the reset signal RST is equal to the low voltage value. The voltage values of the compensation signal COMP and the light-emitting control signal EM are respectively equal to the high voltage value. Therefore, the light-emitting control transistor TE and the compensation transistor TC are turned off. The scanning transistor TS and the reset transistor TR are turned on. The reset transistor TR uses the reset voltage VRST to reset the voltage at the second end of the reset transistor TR (i.e., node A). The scanning transistor TS uses the data signal SD to stabilize the voltage at the second end of the scanning transistor TS (i.e., node B).

[0089] In the compensation stage STC between time point t3 and time point t4, the voltage value of the compensation signal COMP is equal to the low voltage value. The voltage values of the reset signal RST and the light-emitting control signal EM are respectively equal to the high voltage value. Therefore, the light-emitting control transistor TE and the reset transistor TR are turned off. The scanning transistor TS and the compensation transistor TC are turned on. At the beginning of the compensation stage STC, the driving transistor TD is turned on. Therefore, in the compensation stage STC, the voltage value at the control end of the driving transistor TD retains the threshold voltage value (e.g., Vth) of the driving transistor TD.

[0090] It should be noted that in the compensation stage STC, the pixel circuit PX2 can use the capacitive coupling of the capacitors C1 and C2 to stabilize the voltage level of node A.

[0091] During the period from time point t5 to time point t6, the voltage value of the scan signal SC is equal to the high voltage value.

[0092] In the scan stage STS between time point t6 and time point t7, the voltage value of the scan signal SC is equal to the low voltage value. That is to say, the voltage value of the scan signal SC in the reset stage STR is the same as the voltage value of the scan signal SC in the scan stage STS. In addition, the voltage value of the scan signal SC in the compensation stage STC is also the same as the voltage value of the scan signal SC in the scan stage STS.

[0093] In the scan stage STS, the voltage values of the reset signal RST, the compensation signal COMP, and the emission control signal EM are respectively equal to the high voltage value. The control terminal (i.e., node A) of the driving transistor TD is floating-connected. The scan transistor TS is turned on. Therefore, in the scan stage STS, the pixel circuit PX2 can couple the voltage value of the data signal SD to the control terminal of the driving transistor TD by using the capacitor C2.

[0094] After time point t8, in the emission stage STE, the voltage value of the emission control signal EM is equal to the low voltage value. The voltage value of the scan signal SC in the emission stage STE is different from the voltage value of the scan signal SC in the scan stage STS. In the emission stage STE, the voltage value of the scan signal SC is equal to the high voltage value. That is to say, the voltage value of the scan signal SC in the emission stage STE is higher than the voltage value of the scan signal SC in the scan stage STS.

[0095] In the emission stage STE, the voltage values of the compensation signal COMP and the reset signal RST are respectively equal to the high voltage value. Therefore, the compensation transistor TC, the scan transistor TS, and the reset transistor TR are turned off. The emission control transistor TE is turned on. The drive current ID is generated according to the voltage value at the control terminal of the driving transistor TD. Therefore, in the emission stage STE, the light-emitting element LE can emit light based on the voltage value at the control terminal of the driving transistor TD.

[0096] In this embodiment, multiple pixel circuits PX2 of the display device 200 are grouped into pixel rows R[1] to R[2N]. During frame period F1, during frame period F1, the time periods of the reset phases STR of pixel rows R[1] to R[2N] at least partially overlap. The time periods of the compensation phases STC of pixel rows R[1] to R[2N] at least partially overlap. The time periods of the scan phases STS of pixel rows R[1] to R[2N] do not overlap with each other. Therefore, the time length between time point t5 and time point t6 changes with different pixel rows R[1] to R[2N]. The emission phase STE is after the scan phase STS. Therefore, the start time points of the emission phases STE of pixel rows R[1] to R[2N] are different from each other. The operation timing of frame period F2 is similar to that of frame period F1. The time lengths of the emission phases STE of pixel rows R[1] to R[2N] are the same as each other, but not limited thereto.

[0097] Please refer to Figure 4 and Figure 6 , Figure 6 is an operation timing diagram shown according to an embodiment of the present disclosure. In this embodiment, the operation of the pixel circuit PX2 can be divided into a reset phase STR, a compensation phase STC, a scan phase STS, and an emission phase STE.

[0098] In this embodiment, during the update phase SH between time point t0 and time point t5, the voltage value of the scan signal SC is equal to the low voltage value.

[0099] During the reset phase STR between time point t1 and time point t2, the voltage value of the reset signal RST is equal to the low voltage value. The voltage values of the compensation signal COMP and the emission control signal EM are respectively equal to the high voltage value. Therefore, the emission control transistor TE and the compensation transistor TC are turned off. The scan transistor TS and the reset transistor TR are turned on. The reset transistor TR uses the reset voltage VRST to reset the voltage at the second end of the reset transistor TR (i.e., node A). The scan transistor TS stabilizes the voltage at the second end of the scan transistor TS (i.e., node B) using the data signal SD.

[0100] During the compensation phase STC between time point t3 and time point t4, the voltage value of the compensation signal COMP is equal to the low voltage value. The voltage values of the reset signal RST and the emission control signal EM are respectively equal to the high voltage value. Therefore, the emission control transistor TE and the reset transistor TR are turned off. The scan transistor TS and the compensation transistor TC are turned on. At the beginning of the compensation phase STC, the driving transistor TD is turned on. Therefore, during the compensation phase STC, the voltage value at the control end of the driving transistor TD retains the threshold voltage value (e.g., Vth) of the driving transistor TD.

[0101] It should be noted that in the compensation stage STC, the pixel circuit PX2 can utilize the capacitive coupling of the capacitors C1 and C2 to stabilize the voltage level of the node A.

[0102] In the scanning stage STS between the time points t4 and t5, the voltage values of the reset signal RST, the compensation signal COMP, and the emission control signal EM are respectively equal to the high voltage value. The control terminal of the driving transistor TD (i.e., the node A) is floating-connected. The scanning transistor TS is turned on. Therefore, in the scanning stage STS, the pixel circuit PX2 can couple the voltage value of the data signal SD to the control terminal of the driving transistor TD by using the capacitor C2.

[0103] In the emission stage STE after the time point t6, the voltage value of the emission control signal EM is equal to the low voltage value. The voltage value of the scanning signal SC in the emission stage STE is different from the voltage value of the scanning signal SC in the scanning stage STS. In the emission stage STE, the voltage value of the scanning signal SC is equal to the high voltage value. That is to say, the voltage value of the scanning signal SC in the emission stage STE is higher than the voltage value of the scanning signal SC in the scanning stage STS.

[0104] In the emission stage STE, the voltage values of the compensation signal COMP and the reset signal RST are respectively equal to the high voltage value. Therefore, the compensation transistor TC, the scanning transistor TS, and the reset transistor TR are turned off. The emission control transistor TE is turned on. The driving current ID is generated based on the voltage value at the control terminal of the driving transistor TD. Therefore, in the emission stage STE, the light-emitting element LE can emit light based on the voltage value at the control terminal of the driving transistor TD.

[0105] It should be noted that the reset stage STR, the compensation stage STC, and the scanning stage STS are carried out in the update stage SH.

[0106] In this embodiment, multiple pixel circuits PX2 of the display device 200 are grouped into pixel rows R[1] to R[2N]. During the frame period F1, the time periods of the update phases SH of two adjacent ones of the pixel rows R[1] to R[2N] may partially overlap. For example, the time periods of the reset phases STR of the pixel rows R[1] to R[2N] do not overlap with each other. The time periods of the compensation phases STC of the pixel rows R[1] to R[2N] do not overlap with each other. The time periods of the scan phases STS of the pixel rows R[1] to R[2N] do not overlap with each other. For example, the time period of the reset phase STR of the pixel row R[2] is later than the time period of the reset phase STR of the pixel row R[1], and at least partially overlaps with the time period of the compensation phase STC of the pixel row R[1]. The time period of the compensation phase STC of the pixel row R[2] is later than the time period of the compensation phase STC of the pixel row R[1], and at least partially overlaps with the time period of the scan phase STS of the pixel row R[1].

[0107] In addition, the time period other than the update phase SH may be the light-emitting phase STE. The light-emitting phase STE of multiple pixel circuits PX2 of the display device 100 can be extended.

[0108] In this embodiment, the operation during the frame period F2 is similar to the operation during the frame period F1.

[0109] Please refer to Figure 7 , Figure 7 which is an application scenario diagram of the display device shown according to an embodiment of the present disclosure. In this embodiment, the display device 300 may include a pixel circuit PX1 as shown in Figure 1 or a pixel circuit PX2 as shown in Figure 4 . Therefore, the display device 300 can meet the high PPI (Pixels Per Inch) and / or high brightness requirements. In this embodiment, the display device 300 can be applied to, for example, a head-up display (HUD) of a vehicle (such as an airplane, a vehicle).

[0110] In this embodiment, the display device 300 can project the image IMG onto the windshield WW to generate a projected image PIMG. Since the display device 300 can meet the display requirements of high PPI and / or high brightness. Therefore, under high ambient brightness, based on the user's visual perception, the projected image PIMG is still clear. In addition, compared with the current pixel circuits, the pixel circuit PX1 as shown in Figure 1 or the pixel circuit PX2 as shown in Figure 4 both have lower power consumption. Therefore, in this embodiment, the power consumption of the display device 300 is also lower.

[0111] In summary, on the current path between the first voltage terminal and the second voltage terminal, the pixel circuit includes a driving transistor, a light-emitting control transistor, and a light-emitting element. Compared with the current pixel circuits that meet the high brightness requirements (for example, including at least three transistors and a light-emitting element on the current path between the first voltage terminal and the second voltage terminal), the pixel circuit of the present disclosure has lower power consumption. In this way, the display device of the present disclosure also has lower power consumption.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, and are not intended to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A display device, characterized in that, The display device includes: A pixel circuit, comprising: driver transistors; a light emitting control transistor electrically connected to the first voltage terminal and the driving transistor; and a light emitting element electrically connected to a second voltage terminal and the driving transistor, wherein a voltage value of the second voltage terminal is lower than a voltage value of the first voltage terminal, The voltage value of the second voltage terminal in the compensation phase of the pixel circuit is different from the voltage value of the second voltage terminal in the light emitting phase of the pixel circuit.

2. The display device according to claim 1, characterized in that, A voltage value of the second voltage terminal in the compensation phase is higher than a voltage value of the second voltage terminal in the light emitting phase.

3. The display device according to claim 1, characterized in that A voltage value of the second voltage terminal in a reset phase of the pixel circuit is different from a voltage value of the second voltage terminal in the light emitting phase.

4. The display device according to claim 3, wherein: A voltage value of the second voltage terminal in the reset phase is the same as a voltage value of the second voltage terminal in the compensation phase.

5. The display device according to claim 1, wherein The pixel circuit further includes: The compensation transistor is electrically connected between the control terminal of the driving transistor and the first terminal of the driving transistor.

6. A display device, characterized in that, The display device includes: A pixel circuit, comprising: light emitting control transistor; a driving transistor electrically connected to the first voltage terminal and the light emitting control transistor; a light emitting element electrically connected to a second voltage terminal and the light emitting control transistor, wherein a voltage value of the second voltage terminal is smaller than a voltage value of the first voltage terminal; and a scanning transistor electrically connected to the driving transistor and receiving a scanning signal, The voltage value of the scan signal in the reset phase of the pixel circuit is the same as the voltage value of the scan signal in the scan phase of the pixel circuit.

7. The display device according to claim 6, wherein A voltage value of the scanning signal in a light emitting phase of the pixel circuit is different from a voltage value of the scanning signal in the scanning phase.

8. The display device according to claim 7, wherein, A voltage value of the scan signal in the light emitting phase is higher than a voltage value of the scan signal in the scanning phase.

9. The display device according to claim 6, wherein A voltage value of the scanning signal in the compensation phase of the pixel circuit is the same as a voltage value of the scanning signal in the scanning phase.

10. The display device according to claim 6, characterized in that, The pixel circuit further includes: The compensation transistor is electrically connected between the control terminal of the driving transistor and the first terminal of the driving transistor.

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