Display device

Abstract

A display device having high integration and high resolution includes: a pixel circuit; and a light emitting element connected between a second node of the pixel circuit and the common voltage line, in which the pixel circuit includes a first transistor connected between the driving voltage line and the second node, in which the first transistor includes a gate electrode connected to the first node and a counter gate electrode connected to the emission line.

Description

[0001] This application claims the priority of, and all benefits derived from, Korean Patent Application No. 10-2024-0013113, filed on January 29, 2024, the content of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present invention relates to a display device, and more particularly, to a display device having high integration and high resolution. Background Art

[0003] An organic light emitting display device includes a display element such as an organic light emitting diode (OLED) whose brightness varies with current. Summary of the Invention

[0004] Aspects of the present invention provide a display device having high integration and high resolution.

[0005] According to an embodiment, a display device includes: a pixel circuit; and a light emitting element connected between a second node of the pixel circuit and a common voltage line, wherein the pixel circuit includes a first transistor connected between a driving voltage line and the second node, and wherein the first transistor includes a gate electrode connected to a first node and a pair of gate electrodes connected to an emission line.

[0006] In an embodiment, the pixel circuit further includes: a second transistor connected between a data line and the first node.

[0007] In an embodiment, the pixel circuit further includes: a third transistor connected between a reference voltage line and the first node.

[0008] In an embodiment, the pixel circuit further includes: a fourth transistor connected between the second node and an initialization voltage line.

[0009] In an embodiment, the pixel circuit further includes: a first capacitor connected between the first node and the second node; and a second capacitor connected between the second node and the driving voltage line.

[0010] In an embodiment, the display device further includes: a first gate line connected to the gate electrode of the second transistor; a second gate line connected to the gate electrode of the third transistor; and a third gate line connected to the gate electrode of the fourth transistor.

[0011] In an embodiment, the data line transmits a data voltage, the emission line transmits an emission signal, the first gate line transmits a first gate signal, the second gate line transmits a second gate signal, and the third gate line transmits a third gate signal.

[0012] In an embodiment, during a first initialization period, each of a second gate signal and a third gate signal is at an active level, and each of a first gate signal and a transmission signal is at an inactive level.

[0013] In an embodiment, during a threshold voltage detection period following the first initialization period, each of the second gate signal and the transmission signal is at an active level, and each of the first gate signal and the third gate signal is at an inactive level.

[0014] In an embodiment, during a data writing period following the threshold voltage detection period, the first gate signal is at an active level, each of the second gate signal, the third gate signal, and the transmission signal is at an inactive level, and a data voltage is applied to a data line.

[0015] In an embodiment, during a second initialization period following the data writing period, the third gate signal is at an active level, and each of the first gate signal, the second gate signal, and the transmission signal is at an inactive level.

[0016] In an embodiment, during a transmission period following the second initialization period, the transmission signal is at an active level, and each of the first gate signal, the second gate signal, and the third gate signal is at an inactive level.

[0017] In an embodiment, when at an inactive level, the transmission signal has the same value as when the first gate signal is at an inactive level or has a value smaller than when the first gate signal is at an inactive level.

[0018] In an embodiment, the capacitance of the second capacitor is greater than the capacitance of the first capacitor.

[0019] In an embodiment, the pixel circuit further includes: a fifth transistor connected between a second node and an anode of the light-emitting element, wherein a fourth transistor is connected between the anode of the light-emitting element and an initialization voltage line.

[0020] In an embodiment, the display device further includes: a first gate line connected to a gate electrode of the second transistor; a second gate line connected to a gate electrode of the third transistor; a third gate line connected to a gate electrode of the fourth transistor; and a fourth gate line connected to a gate electrode of the fifth transistor.

[0021] In an embodiment, the data line transmits a data voltage, the emission line transmits an emission signal, the first gate line transmits a first gate signal, the second gate line transmits a second gate signal, the third gate line transmits a third gate signal, and the fourth gate line transmits a fourth gate signal.

[0022] In an embodiment, during the first initialization period, each of the second gate signal, the third gate signal, and the fourth gate signal is at an active level, and each of the first gate signal and the emission signal is at an inactive level.

[0023] In an embodiment, during the threshold voltage detection period following the first initialization period, each of the second gate signal and the emission signal is at an active level, and each of the first, third, and fourth gate signals is at an inactive level.

[0024] In an embodiment, during a data write period following a threshold voltage detection period, the first gate signal is at an active level, each of the second, third, fourth gate signals and emission signal is at an inactive level, and a data voltage is applied to the data line.

[0025] In an embodiment, during the second initialization period following the data write period, each of the third gate signal and the fourth gate signal is at an active level, and each of the first gate signal, the second gate signal, and the emission signal is at an inactive level.

[0026] In an embodiment, during the emission period following the second initialization period, each of the emission signal and the fourth gate signal is at an active level, and each of the first gate signal, the second gate signal, and the third gate signal is at an inactive level.

[0027] According to an embodiment, a display device includes: a pixel circuit; and a light-emitting element connected between a second node of the pixel circuit and a common voltage line, wherein the pixel circuit includes: a first transistor connected between a driving voltage line and the second node and having a gate electrode connected to a first node and a pair of gate electrodes connected to an emission line; a second transistor having a gate electrode connected to a first gate line and connected between a data line and the first node; a third transistor having a gate electrode connected to a second gate line and connected between a reference voltage line and the first node; a fourth transistor having a gate electrode connected to a third gate line and connected between the second node and an initialization voltage line; a first capacitor connected between the first node and the second node; and a second capacitor connected between the second node and the driving voltage line, wherein, during a first initialization period, each of a second gate signal from the second gate line and a third gate signal from the third gate line is at an active level, and each of a first gate signal from the first gate line and an emission signal from the emission line is at an inactive level, wherein, during a threshold voltage detection period following the first initialization period, each of the second gate signal and the emission signal is at an active level, and each of the first gate signal and the third gate signal is at an inactive level, wherein, during a data writing period following the threshold voltage detection period, the first gate signal is at an active level, each of the second gate signal, the third gate signal, and the emission signal is at an inactive level, and a data voltage is applied to the data line, wherein, during a second initialization period following the data writing period, the third gate signal is at an active level, and each of the first gate signal, the second gate signal, and the emission signal is at an inactive level, and wherein, during an emission period following the second initialization period, the emission signal is at an active level, and each of the first gate signal, the second gate signal, and the third gate signal is at an inactive level.

[0028] According to an embodiment, a display device includes: a pixel circuit; and a light-emitting element connected between a second node of the pixel circuit and a common voltage line, wherein the pixel circuit includes: a first transistor connected between a driving voltage line and the second node and having a gate electrode connected to a first node and a pair of gate electrodes connected to an emission line; a second transistor having a gate electrode connected to a first gate line and connected between a data line and the first node; a third transistor having a gate electrode connected to a second gate line and connected between a reference voltage line and the first node; a fourth transistor having a gate electrode connected to a third gate line and connected between an anode of the light-emitting element and an initialization voltage line; a fifth transistor having a gate electrode connected to a fourth gate line and connected between the second node and the anode of the light-emitting element; a first capacitor connected between the first node and the second node; and a second capacitor connected between the second node and the driving voltage line, wherein, during a first initialization period, each of a second gate signal from the second gate line, a third gate signal from the third gate line, and a fourth gate signal from the fourth gate line is at an active level, and each of a first gate signal from the first gate line and an emission signal from the emission line is at an inactive level, wherein, during a threshold voltage detection period following the first initialization period, each of the second gate signal and the emission signal is at an active level, and each of the first gate signal, the third gate signal, and the fourth gate signal is at an inactive level, wherein, during a data writing period following the threshold voltage detection period, the first gate signal is at an active level, and each of the second gate signal, the third gate signal, the fourth gate signal, and the emission signal is at an inactive level, and a data voltage is applied to the data line, wherein, during a second initialization period following the data writing period, each of the third gate signal and the fourth gate signal is at an active level, and each of the first gate signal, the second gate signal, and the emission signal is at an inactive level, and wherein, during an emission period following the second initialization period, each of the emission signal and the fourth gate signal is at an active level, and each of the first gate signal, the second gate signal, and the third gate signal is at an inactive level.

[0029] However, the present invention is not limited to those embodiments described herein. The above and other aspects of the present invention will become more apparent to those of ordinary skill in the art to which the present invention pertains by referring to the detailed description of the present invention given below.

[0030] According to the foregoing and other embodiments of the present invention, since the conduction and cutoff of the first transistor are controlled by the emission signal, a separate transistor (e.g., an emission control transistor) for controlling the driving current of the driving transistor can be omitted. Therefore, each pixel of the display device can control the driving current of the driving transistor while including fewer transistors. Therefore, each pixel can be advantageously applied to a display device with high integration and high resolution.

[0031] Embodiments of the present invention are not limited to the above embodiments, and other embodiments not described herein will become apparent to those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects and the above and other features of the present invention will become more apparent by describing exemplary embodiments of the present invention in detail with reference to the accompanying drawings, in which:

[0033] Figure 1 is a perspective view of a display device according to an embodiment;

[0034] Figure 2 is a cross-sectional view of a display device according to an embodiment;

[0035] Figure 3 is a plan view of a display panel of a display device according to an embodiment;

[0036] Figure 4 is a block diagram of a display panel and a display driver of a display device according to an embodiment;

[0037] Figure 5 is a circuit diagram of an exemplary pixel of a display device according to an embodiment;

[0038] Figure 6 is for explaining the Figure 5 first gate signal, second gate signal, third gate signal, and emission signal of according to an embodiment;

[0039] Figure 7 is for explaining the Figure 5 display device of according to an embodiment during Figure 6 the first initialization period;

[0040] Figure 8 is for explaining the Figure 5 display device of according to an embodiment during Figure 6 the threshold voltage detection period;

[0041] Figure 9 is for explaining the Figure 5 display device of according to an embodiment during Figure 6 the data writing period;

[0042] Figure 10 is for explaining the Figure 5 display device of according to an embodiment during Figure 6 the second initialization period;

[0043] Figure 11 is a circuit diagram for explaining the operation of the display device of Figure 5 during the emission period of Figure 6 ;

[0044] Figure 12 is a circuit diagram of another exemplary pixel of the display device according to an embodiment;

[0045] Figure 13 is for explaining the Figure 12 first gate signal, second gate signal, third gate signal, fourth gate signal, and emission signal of

[0046] Figure 14 according to an embodiment; Figure 12 is a circuit diagram for explaining the operation of the display device of Figure 13 during the first initialization period of

[0047] Figure 15 is for explaining the Figure 12 display device of Figure 13 during the threshold voltage detection period of

[0048] Figure 16 is for explaining the Figure 12 display device of Figure 13 during the data writing period of

[0049] Figure 17 is for explaining the Figure 12 display device of Figure 13 during the second initialization period of

[0050] Figure 18 is for explaining the Figure 12 display device of Figure 13 during the emission period of ; and

[0051] Figure 19 is a cross-sectional view of the display device according to an embodiment. DETAILED DESCRIPTION

[0052] The present invention will be described more fully hereinafter with reference to the accompanying drawings, which show preferred embodiments of the invention. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0053] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate or intervening layers may be present. Throughout the specification, like reference numerals indicate like components. In the figures, the thicknesses of layers and regions are exaggerated for clarity.

[0054] Although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms may be used to distinguish one element from another. Thus, the first element discussed below may be termed the second element without departing from the teachings of one or more embodiments. The description of an element as a “first” element does not require or imply the existence of a second element or other elements. The terms “first,” “second,” etc. may also be used herein to distinguish different categories or groups of elements. For the sake of brevity, the terms “first,” “second,” etc. may represent “first category (or first group),” “second category (or second group),” etc., respectively.

[0055] It will also be understood that when a layer is referred to as being “on,” “connected to,” or “coupled to” another element, layer, or substrate, it can be directly on the other element, layer, or substrate or intervening elements, layers, or substrates may be present. Similarly, those elements referred to as “under,” “left,” and “right” include cases where they are directly adjacent to other elements or where another layer or other material is interposed therebetween. For this reason, the term “connected” may refer to physical, electrical, and / or fluid connections with or without intervening elements.

[0056] Unless otherwise specified, the illustrated embodiments are to be understood as providing details of features that can vary in some ways in which the present disclosure can be practiced. Thus, unless otherwise specified, the features, components, modules, layers, films, panels, regions, and / or aspects, etc. (hereinafter individually or collectively referred to as “elements”) of the various embodiments can be combined, separated, interchanged, and / or rearranged in other ways without departing from the scope of the invention.

[0057] The features of the various embodiments of the present disclosure can be combined in whole or in part. As will be readily understood by those skilled in the art, various interactions and operations are possible. The various embodiments can be practiced individually or in combination.

[0058] The use of cross-hatching and / or shading in the figures is generally provided to clarify the boundaries between adjacent elements. Thus, unless specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, dimension, scale, commonality between the illustrated elements, and / or any other characteristic, attribute, property, etc.

[0059] In addition, in the drawings, for clarity and / or descriptive purposes, the dimensions and relative dimensions of elements may be exaggerated. When embodiments can be implemented differently, the specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to the described order. Additionally, the same reference numerals denote the same elements.

[0060] Furthermore, the first direction DR1, the second direction DR2, and the third direction DR3 are not limited to directions corresponding to the three axes of a rectangular coordinate system, and thus the first direction DR1, the second direction DR2, and the third direction DR3 can be interpreted in a broader sense. For example, the first direction DR1, the second direction DR2, and the third direction DR3 can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0061] For the purposes of the present disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as, by way of example, XYZ, XY, YZ, or XZ. As used herein, the term "and / or" includes any combination and all combinations of one or more of the associated listed items.

[0062] Spatial relative terms such as "below", "beneath", "under", "lower", "above", "upper", "on", "over", "higher", and "side" (e.g., as in "sidewall") may be used herein for descriptive purposes and thereby describe the relationship of one element to another (other) element as illustrated in the drawings. Except for the orientation depicted in the drawings, spatial relative terms are intended to include different orientations of the device in use, operation, and / or manufacture. For example, if the device in the drawing is flipped, an element described as "below" or "beneath" another element or feature will then be oriented "above" that other element or feature. Thus, the term "below" can include both the above and below orientations. Additionally, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and so the spatial relative descriptors used herein should be interpreted accordingly.

[0063] The terms used in this specification are for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, unless the context clearly dictates otherwise, the singular forms "a" and "the" are intended to include the plural forms as well. Also, when used in this specification, the terms "comprises," "comprising," and / or their variants specify the presence of stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as terms of approximation and not as terms of degree, and are used to interpret the inherent deviations of measured, calculated, and / or provided values that would be recognized by a person of ordinary skill in the art.

[0064] Various embodiments are described herein with reference to cross-sectional views and / or exploded views, which are schematic diagrams of the embodiments and / or intermediate structures. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, the embodiments disclosed herein should not necessarily be construed as limited to the shapes of the particular illustrated regions, but rather include deviations in shapes resulting from, for example, manufacturing. In this manner, the regions illustrated in the figures may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and are thus not intended to be limiting.

[0065] In accordance with the convention in the art, some embodiments are described and illustrated in the figures in terms of functional blocks, units, portions, and / or modules. Those skilled in the art will understand that these blocks, units, portions, and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, and wiring connections, which may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where the blocks, units, portions, and / or modules are implemented by a microprocessor or other similar hardware, they may be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. It is also contemplated that each block, unit, portion, and / or module may be implemented by dedicated hardware, or may be implemented as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions. Additionally, each block, unit, portion, and / or module of some embodiments may be physically separated into two or more interacting and discrete blocks, units, portions, and / or modules without departing from the scope of the present invention. Furthermore, the blocks, units, portions, and / or modules of some embodiments may be physically combined into more complex blocks, units, portions, and / or modules without departing from the scope of the present invention.

[0066] Unless otherwise defined or implied herein, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms, such as those defined in a general dictionary, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and this disclosure, and should not be interpreted in an idealized or overly formal sense unless so expressly defined herein.

[0067] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0068] Figure 1 is a perspective view of a display device 10 according to an embodiment.

[0069] In an embodiment and with reference to Figure 1 , the display device 10 is applicable to portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notepads, e-book readers, portable multimedia players (PMPs), navigation systems, or ultra-mobile PCs. For example, in one embodiment, the display device 10 may be applied to a display unit of a television (TV), a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) device. In another embodiment, the display device 10 may be applied to wearable devices such as smart watches, watch phones, glasses-type displays, or head-mounted displays (HMDs).

[0070] In an embodiment, the display device 10 may have a planar shape similar to a rectangle. For example, the display device 10 may have a planar shape similar to a rectangle having a short side in a first direction DR1 and a long side in a second direction DR2. The corners where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be curved with a predetermined curvature or may be formed at right angles. The planar shape of the display device 10 is not particularly limited and may be formed similarly to other polygons, circles, or ellipses.

[0071] The display device 10 may include a display panel 100, a display driving unit 200, a circuit board 300, a touch driving unit 400, and a power supply unit 500.

[0072] The display panel 100 includes a main area MA and a sub area SBA.

[0073] The main area MA may include a display area DA equipped with pixels for displaying images and a non-display area NDA provided around the display area DA. The display area DA may emit light from a plurality of emission areas or opening areas. For example, in an embodiment, the display panel 100 may include a pixel circuit including a switching device, a pixel defining film defining the emission area or the opening area, and a self-emitting element ED (or referred to as a light-emitting element) (see Figure 5 ).

[0074] For example, the self-emitting element ED may include an organic light-emitting diode (OLED) including an organic light-emitting layer, a quantum dot light-emitting diode (LED) including a quantum dot emission layer, and / or an inorganic LED including an inorganic semiconductor, and a micro LED, but the present invention is not limited thereto.

[0075] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of the main area MA of the display panel 100. The non-display area NDA may include a gate driver (not shown) that supplies a gate signal to a gate line and a fan-out line (not shown) that connects the display driving unit 200 and the display area DA.

[0076] The sub-area SBA may extend from one side of the main area MA and may include a flexible material that can be bent, folded, or curled. For example, when the sub-area SBA is bent, the sub-area SBA may overlap the main area MA in the thickness direction (e.g., in the third direction DR3). The sub-area SBA may include the display driving unit 200 and a pad unit connected to the circuit board 300. In another embodiment, the sub-area SBA may be omitted, and the display driving unit 200 and the pad unit may be provided in the non-display area NDA.

[0077] In an embodiment, the display driving unit 200 may output signals and voltages to drive the display panel 100. The display driving unit 200 may supply a data voltage to a data line. The display driving unit 200 may supply a power voltage to a power line and supply a gate control signal to the gate driver. The display driving unit 200 may be formed as an integrated circuit (IC) and may be mounted on the display panel 100 using a chip on glass (COG), a chip on plastic (COP), or an ultrasonic bonding method. For example, in an embodiment, the display driving unit 200 may be provided in the sub-area SBA and may overlap the main area MA in the thickness direction (or in the third direction DR3) due to the bending of the sub-area SBA. In another embodiment, the display driving unit 200 may be mounted on the circuit board 300.

[0078] In an embodiment, the circuit board 300 may be attached to the pad unit of the display panel 100 using an anisotropic conductive film (ACF), and the leads of the circuit board 300 may be electrically connected to the pad unit of the display panel 100. The circuit board 300 may be a flexible printed circuit board (FPCB), a rigid printed circuit board (PCB), or a flexible film such as a chip on film (COF).

[0079] In an embodiment, the touch driving unit 400 may be mounted on the circuit board 300 and may be electrically connected to the touch sensing unit of the display panel 100. The touch driving unit 400 may supply a touch driving signal to a plurality of touch electrodes of the touch sensing unit and sense a change in capacitance between the touch electrodes. For example, the touch driving signal may be a pulse signal having a predetermined frequency. The touch driving unit 400 may determine the presence and coordinates of an input based on the change in capacitance between the touch electrodes. The touch driving unit 400 may be formed as an IC.

[0080] In an embodiment, the power supply unit 500 may be disposed on the circuit board 300 to supply a power voltage to the display driving unit 200 and the display panel 100. The power supply unit 500 may generate a driving voltage supplied to the driving voltage line VDL (see Figure 3 ), generate an initialization voltage supplied to the initialization voltage line VIL (see Figure 4 ), generate a reference voltage supplied to the reference voltage line VRL (see Figure 5 ), and generate a common voltage supplied to the common voltage line ( Figure 5 "VSL"). In an embodiment, the common voltage of the common voltage line VSL may be supplied to a common electrode commonly shared by the light emitting elements ED of the pixels. The driving voltage may be a high potential voltage for driving the light emitting element ED, and the common voltage may be a low potential voltage for driving the light emitting element ED.

[0081] Figure 2 is a cross-sectional view of the display device 10 according to an embodiment.

[0082] In an embodiment and referring to Figure 2 , the display panel 100 may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a thin film transistor (TFT) layer TFTL, a light emitting element layer EMTL, and a package layer ENC.

[0083] In an embodiment, the substrate SUB may be a base substrate or a base member and may be a flexible substrate that is bendable, foldable, or rollable. For example, in one embodiment, the substrate SUB may include a polymer resin such as polyimide (PI), but the present disclosure is not limited thereto. In another embodiment, the substrate SUB may include glass or a metal material.

[0084] In an embodiment, the TFT layer TFTL may be disposed on the substrate SUB and may include a plurality of TFTs forming a pixel circuit for a pixel. The TFT layer TFTL may further include gate lines, data lines, power lines, gate control lines, fan-out lines connecting the display driving unit 200 and the data lines, and leads connecting the display driving unit 200 and the pad unit. Each of the TFTs may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, if the gate driver is formed on one side of the non-display area NDA of the display panel 100, the gate driver may include TFTs.

[0085] The TFT layer TFTL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The TFTs, gate lines, data lines, and power lines of the TFT layer TFTL may be disposed in the display area DA. The gate control lines and fan-out lines of the TFT layer TFTL may be disposed in the non-display area NDA, and the leads of the TFT layer TFTL may be disposed in the sub-area SBA.

[0086] In an embodiment, the light-emitting element layer EMTL may be disposed on the TFT layer TFTL and may include a light-emitting element ED (see Figure 5 ) in which a pixel electrode, an emission layer, and a common electrode are sequentially stacked to emit light, and a pixel defining film defining a pixel. The light-emitting element ED of the light-emitting element layer EMTL may be disposed in the display area DA.

[0087] For example, in an embodiment, the emission layer may be an organic emission layer including an organic material, and each of the emission layers may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the pixel electrode receives a predetermined voltage through the TFT of the TFT layer TFTL and the common electrode receives a cathode voltage, then holes and electrons may move through the hole transport layer and the electron transport layer, respectively, and recombine in the organic light-emitting layer to emit light. For example, the pixel electrode may be, but is not limited to, an anode, and the common electrode may be, but is not limited to, a cathode.

[0088] In another embodiment, the light-emitting element ED may include a quantum dot LED including a quantum dot emission layer, an inorganic LED including an inorganic semiconductor, or a micro LED.

[0089] In an embodiment, the encapsulation layer ENC may cover the top and sides of the light-emitting element layer EMTL and may protect the light-emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic film and at least one organic film for encapsulating the light-emitting element layer EMTL.

[0090] In an embodiment, the touch sensing unit TSU may be disposed on the encapsulation layer ENC and may include a plurality of touch electrodes for detecting a user's touch input using a capacitive method and touch lines connecting the touch electrodes and the touch driving unit 400. For example, the touch sensing unit TSU may sense a user's touch input using a mutual capacitance or self-capacitance method.

[0091] In another embodiment, the touch sensing unit TSU may be disposed on a separate substrate placed on the display unit DU. In this embodiment, the substrate supporting the touch sensing unit TSU may be a base member encapsulating the display unit DU.

[0092] The touch electrodes of the touch sensing unit TSU may be disposed in a touch sensor area overlapping with the display area DA, and the touch lines of the touch sensing unit TSU may be disposed in a touch peripheral area overlapping with the non-display area NDA.

[0093] In an embodiment, the color filter layer CFL may be disposed on the touch sensing unit TSU and may include a plurality of color filters corresponding to the emission areas. Each of the color filters may selectively transmit light of a specific wavelength and block or absorb light of other wavelengths. The color filter layer CFL may absorb some of the light entering from the outside of the display device 10 to reduce the reflection caused by external light. Therefore, the color filter layer CFL can prevent color distortion caused by the reflection of external light.

[0094] Since the color filter layer CFL is directly disposed on the touch sensing unit TSU, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 can be relatively reduced.

[0095] In an embodiment, the sub-area SBA of the display panel 100 may extend from one side of the main area MA and may include a flexible material that can be bent, folded, or rolled. For example, when the sub-area SBA is bent, the sub-area SBA may overlap with the main area MA in the thickness direction (or in the third direction DR3). The sub-area SBA may include a pad unit electrically connected to the display driving unit 200 and the circuit board 300.

[0096] Figure 3 is a plan view of the display panel 100 of the display device 10 according to an embodiment, and Figure 4 is a block diagram illustrating the display panel 100 and the display driver according to an embodiment.

[0097] Referring to Figure 3 and Figure 4 , the display panel 100 may include a display area DA and a non-display area NDA.

[0098] In an embodiment, the display area DA may include a plurality of pixels PX, a plurality of driving voltage lines VDL, a plurality of gate lines GL, a plurality of emission lines EML, a plurality of data lines DL, and a plurality of common voltage lines VSL, wherein the driving voltage lines VDL, the gate lines GL, the emission lines EML, the data lines DL, and the common voltage lines VSL may be connected to the pixels PX.

[0099] Specifically, the pixel PX may be connected to the gate line GL, the data line DL, the emission line EML, the driving voltage line VDL, and the common voltage line VSL, and each of the pixels PX may include a light-emitting element ED, a capacitor, and at least one transistor.

[0100] In an embodiment, the gate lines GL may extend in a first direction DR1 and may be spaced apart from each other in a second direction DR2 intersecting the first direction DR1. The gate lines GL may be arranged along the second direction DR2 and may sequentially supply gate signals to the pixels PX.

[0101] In an embodiment, the emission lines EML may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2. The emission lines EML may be arranged along the second direction DR2 and may sequentially supply emission signals to the pixels PX.

[0102] In an embodiment, the data lines DL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The data lines DL may be arranged along the first direction DR1 and may supply data voltages to the pixels PX. The data voltages may determine the brightness of the pixels PX.

[0103] In an embodiment, the driving voltage lines VDL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The driving voltage lines VDL may be arranged along the first direction DR1 and may supply driving voltages to the pixels PX. The driving voltages may be high-potential voltages for driving the light-emitting elements ED of the pixels PX.

[0104] In an embodiment, the non-display area NDA may surround the display area DA and may include a gate driver 610, an emission control driver 620, fan-out lines FL, a first gate control line GSL1, and a second gate control line GSL2.

[0105] The fan-out lines FL may extend from the display driving unit 200 to the display area DA and may supply the data voltages received from the display driving unit 200 to the data lines DL.

[0106] The first gate control line GSL1 may extend from the display driving unit 200 to the gate driver 610 and may supply the gate control signal GCS received from the display driving unit 200 to the gate driver 610.

[0107] The second gate control line GSL2 can extend from the display driving unit 200 to the emission control driver 620 and can supply an emission control signal ECS received from the display driving unit 200 to the emission control driver 620.

[0108] In an embodiment, the sub-region SBA can extend from one side of the non-display region NDA and can include the display driving unit 200 and the pad DP. The pad DP can be disposed closer to one edge of the display panel 100 than the display driving unit 200 and can be electrically connected to the circuit board 300 via ACF.

[0109] In an embodiment, the display driving unit 200 can include a timing controller 210 and a data driver 220.

[0110] The timing controller 210 can receive digital video data DATA and timing signals from the circuit board 300. Based on the timing signals, the timing controller 210 can generate a data control signal DCS for controlling the operation timing of the data driver 220, can generate a gate control signal GCS for controlling the operation timing of the gate driver 610, and can generate an emission control signal ECS for controlling the operation timing of the emission control driver 620. The timing controller 210 can also supply the gate control signal GCS to the gate driver 610 via the first gate control line GSL1. The timing controller 210 can supply the emission control signal ECS to the emission control driver 620 via the second gate control line GSL2. The timing controller 210 can supply the digital video data DATA and the data control signal DCS to the data driver 220.

[0111] The data driver 220 can convert the digital video data DATA into an analog data voltage and supply the digital video data DATA to the data line DL via the fan-out line FL. The gate signal from the gate driver 610 can select the pixel PX to which the data voltage is to be supplied, and the selected pixel PX can receive the data voltage via the data line DL.

[0112] In an embodiment, the power supply unit 500 disposed on the circuit board 300 can supply a power voltage to the display driving unit 200 and the display panel 100. The power supply unit 500 can generate a driving voltage supplied to the driving voltage line VDL, generate an initialization voltage supplied to the initialization voltage line VIL, and can generate a common voltage supplied to the common electrode commonly shared by the light-emitting elements ED of the pixel PX.

[0113] In an embodiment, the gate driver 610 may be disposed on one side of the display panel 100 to be located outside the display area DA or on one side of the non-display area NDA, and the emission control driver 620 may be disposed on the other side of the display panel 100 to be located outside the display area DA or on the other side of the non-display area NDA. However, the present invention is not limited thereto. For example, in another embodiment, the gate driver 610 and the emission control driver 620 may be disposed on any one side of the non-display area NDA.

[0114] The gate driver 610 may include a plurality of transistors that generate gate signals based on a gate control signal GCS. The emission control driver 620 may include a plurality of transistors that generate emission signals based on an emission control signal ECS. For example, the transistors in each of the gate driver 610 and the emission control driver 620 may be formed on the same layer as the transistors of the pixel PX. The gate driver 610 supplies gate signals to the gate lines GL, while the emission control driver 620 supplies emission signals to the emission lines EML.

[0115] Figure 5 is a circuit diagram of an exemplary pixel PX of the display device 10 according to an embodiment.

[0116] In an embodiment and referring to Figure 5 , the pixel PX may be connected to a first gate line GWL, a second gate line GRL, a third gate line GIL, an emission line EML, a data line DL, a driving voltage line VDL, a common voltage line VSL, a reference voltage line VRL, and an initialization voltage line VIL.

[0117] In an embodiment, the pixel PX may include a pixel circuit PC and a light-emitting element ED. The pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first capacitor Cst, and a second capacitor Chold.

[0118] The first transistor T1 may include a gate electrode, a source electrode, and a drain electrode and may control the source-drain current (or driving current) depending on the data voltage Vdt applied to its gate electrode. The driving current flowing through the channel region of the first transistor T1 may be proportional to the square of the difference between the source-gate voltage of the first transistor T1, which is the voltage between the source electrode and the gate electrode of the first transistor T1, and the threshold voltage, as given by the following equation:

[0119] Isd = k × (Vsg - Vth) 2 ,

[0120] Where Isd represents the drive current, k represents a proportionality coefficient determined by the structure and physical characteristics of the first transistor T1, Vsg represents the source-gate voltage of the first transistor T1, and Vth represents the threshold voltage of the first transistor T1. The drain electrode of the first transistor T1 can be connected to a drive voltage line VDL that transmits a drive voltage ELVDD, such as a high potential voltage.

[0121] In an embodiment, the first transistor T1 can be a double-gate transistor having, for example, a gate electrode and a pair of gate electrodes for the gate electrode. The gate electrode and the pair of gate electrodes can be arranged to face each other in different layers, with an active layer provided therebetween. The gate electrode of the first transistor T1 can be electrically connected to the first node N1, the pair of gate electrodes of the first transistor T1 can be connected to the emission line EML, the drain electrode of the first transistor T1 can be electrically connected to the drive voltage line VDL, and the source electrode of the first transistor T1 can be electrically connected to the second node N2. The first transistor T1 can be controlled by an emission signal EM applied to the pair of gate electrodes of the first transistor T1. For example, when the emission signal EM applied to the pair of gate electrodes of the first transistor T1 is at an inactive level (e.g., at a low voltage), the first transistor T1 can be turned off regardless of the voltage applied to the gate electrode of the first transistor T1. In one embodiment, when the emission signal EM is at an inactive level and applied to the pair of gate electrodes of the first transistor T1, the threshold voltage of the first transistor T1 can be shifted to increase. Additionally, in another embodiment, when the emission signal EM is at an active level and applied to the pair of gate electrodes of the first transistor T1, the threshold voltage of the first transistor T1 can be shifted to decrease.

[0122] In an embodiment, since the conduction and cutoff of the first transistor T1, which is a drive transistor, are controlled by the emission signal EM, a separate transistor (e.g., an emission control transistor) for controlling the drive current of the first transistor T1 can be omitted. Thus, the pixel PX requires fewer transistors while still allowing control of the drive current of the first transistor T1. Therefore, the pixel PX can be advantageously applied to a display device 10 with high integration and high resolution.

[0123] In an embodiment, the light-emitting element ED may receive a driving current to emit light, wherein the luminance or brightness of the light-emitting element ED may be proportional to the amplitude of the driving current. The light-emitting element ED may be an OLED including a first electrode and a second electrode and an organic emission layer disposed between the first electrode and the second electrode. In another embodiment, the light-emitting element ED may be an inorganic light-emitting element including a first electrode and a second electrode and an inorganic semiconductor disposed between the first electrode and the second electrode. In yet another embodiment, the light-emitting element ED may be a quantum dot light-emitting element including a first electrode and a second electrode and a quantum dot emission layer disposed between the first electrode and the second electrode. In still another embodiment, the light-emitting element ED may be a micro LED. The first electrode of the light-emitting element ED may be electrically connected to the second node N2, and the second electrode of the light-emitting element ED may be connected to the common voltage line VSL. The second electrode of the light-emitting element ED may receive a common voltage ELVSS (e.g., a low-potential voltage) from the common voltage line VSL.

[0124] In an embodiment, the second transistor T2 may be turned on by a first gate signal GW from the first gate line GWL, thereby electrically connecting the data line DL and the first node N1 that is the gate electrode of the first transistor T1. When the second transistor T2 is turned on based on the first gate signal GW, the second transistor T2 may supply a data voltage Vdt to the first node N1. The gate electrode of the second transistor T2 may be electrically connected to the first gate line GWL, the drain electrode of the second transistor T2 may be electrically connected to the data line DL, and the source electrode of the second transistor T2 may be electrically connected to the first node N1.

[0125] In an embodiment, the third transistor T3 may be turned on by a second gate signal GR from the second gate line GRL, thereby electrically connecting the first node N1 and the reference voltage line VRL. The gate electrode of the third transistor T3 may be electrically connected to the second gate line GRL, the drain electrode of the third transistor T3 may be electrically connected to the first node N1, and the source electrode of the third transistor T3 may be electrically connected to the reference voltage line VRL. The reference voltage line VRL may transmit a reference voltage Vref.

[0126] In an embodiment, the fourth transistor T4 may be turned on by a third gate signal GI from the third gate line GIL, thereby electrically connecting the second node N2 and the initialization voltage line VIL. The fourth transistor T4 may be connected in series between the second node N2 and the initialization voltage line VIL. The gate electrode of the fourth transistor T4 may be electrically connected to the third gate line GIL, the drain electrode of the fourth transistor T4 may be electrically connected to the second node N2, and the source electrode of the fourth transistor T4 may be electrically connected to the initialization voltage line VIL. The initialization voltage line VIL may transmit an initialization voltage Vaint. In one embodiment, the initialization voltage Vaint may be less than the reference voltage Vref. Additionally, the initialization voltage Vaint may be less than the common voltage ELVSS.

[0127] In an embodiment, the first capacitor Cst may be electrically connected between the first node N1 and the second node N2. For example, the first electrode of the first capacitor Cst may be electrically connected to the first node N1, and the second electrode of the first capacitor Cst may be electrically connected to the second node N2. Accordingly, the first capacitor Cst may hold the potential difference between the first node N1 and the second node N2.

[0128] In an embodiment, the second capacitor Chold may be electrically connected between the second node N2 and the drive voltage line VDL. For example, the first electrode of the second capacitor Chold may be electrically connected to the second node N2, and the second electrode of the second capacitor Chold may be electrically connected to the drive voltage line VDL. The second capacitor Chold may hold the potential difference between the second node N2 and the drive voltage line VDL. In one embodiment, the capacitance of the second capacitor Chold may be different from the capacitance of the first capacitor Cst. For example, the capacitance of the second capacitor Chold may be greater than the capacitance of the first capacitor Cst.

[0129] Meanwhile, a capacitor Cp connected between the anode (or referred to as the first electrode) and the cathode (or referred to as the second electrode) of the light-emitting element ED may be a parasitic capacitor of the light-emitting element ED.

[0130] In an embodiment, at least one of the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 may be an n-type transistor including an oxide-based active layer. Transistors including an oxide-based active layer may have a coplanar structure with their gate electrodes arranged on top. Transistors including an oxide-based active layer may output a current flowing from their drain electrodes to their source electrodes based on a gate high voltage applied to their gate electrodes.

[0131] Figure 6 is a diagram showing according to an embodiment Figure 5Timing diagrams of a first gate signal GW, a second gate signal GR, a third gate signal GI, and a transmission signal EM.

[0132] In an embodiment and with reference to Figure 6 , the display device 10 may operate based on a first initialization period P1, a threshold voltage detection period P2, a data writing period P3, a second initialization period P4, and a transmission period P5.

[0133] In an embodiment, during each of the first initialization period P1, the threshold voltage detection period P2, the data writing period P3, the second initialization period P4, and the transmission period P5, the first gate signal GW, the second gate signal GR, the third gate signal GI, and the transmission signal EM may each be at an active level or an inactive level. Here, the active level of each of the first gate signal GW, the second gate signal GR, the third gate signal GI, and the transmission signal EM may refer to a voltage level that can turn on the corresponding transistor when applied. In other words, when the first gate signal GW, the second gate signal GR, the third gate signal GI, and the transmission signal EM are at the active level, they may have a voltage greater than the threshold voltage of the corresponding transistor. For example, if the corresponding transistor is an n-type transistor, the active level of each of the first gate signal GW, the second gate signal GR, the third gate signal GI, and the transmission signal EM applied to the gate electrode of the corresponding transistor may refer to a high level (e.g., a positive level or a high voltage level).

[0134] In an embodiment, the inactive level of each of the first gate signal GW, the second gate signal GR, the third gate signal GI, and the transmission signal EM may represent a voltage level that can cut off the corresponding transistor. In other words, each of the first gate signal GW, the second gate signal GR, the third gate signal GI, and the transmission signal EM at the inactive level may have a voltage lower than the threshold voltage of the corresponding transistor. For example, if the corresponding transistor is an n-type transistor, the inactive level of each of the first gate signal GW, the second gate signal GR, the third gate signal GI, and the transmission signal EM applied to the gate electrode of the corresponding transistor may refer to a low level (e.g., a negative level or a low voltage level).

[0135] In another embodiment, if the corresponding transistor is a p-type transistor, the active level and the inactive level of each of the first gate signal GW, the second gate signal GR, the third gate signal GI, and the transmission signal EM applied to the gate electrode of the corresponding transistor may refer to a low level (e.g., a negative level or a low voltage level) and a high level (e.g., a positive level or a high voltage level), respectively.

[0136] In an embodiment, during a first initialization period P1, the second gate signal GR and the third gate signal GI may each be at an active level. However, during the first initialization period P1, the first gate signal GW and the emission signal EM may each be at an inactive level.

[0137] During a threshold voltage detection period P2, the second gate signal GR and the emission signal EM may each be at an active level. However, during the threshold voltage detection period P2, the first gate signal GW and the third gate signal GI may each be at an inactive level.

[0138] During a data write period P3, the first gate signal GW may be at an active level. However, during the data write period P3, the second gate signal GR, the third gate signal GI, and the emission signal EM may each be at an inactive level. Additionally, during the data write period P3, a data voltage Vdt may be applied to the data line DL.

[0139] During a second initialization period P4, the third gate signal GI may be at an active level. However, during the second initialization period P4, the first gate signal GW, the second gate signal GR, and the emission signal EM may each be at an inactive level.

[0140] During an emission period P5, the emission signal EM may be at an active level. However, during the emission period P5, the first gate signal GW, the second gate signal GR, and the third gate signal GI may each be at an inactive level.

[0141] Hereinafter, reference will be made to Figures 7 to 11 to describe an embodiment of the operation of the display device 10, where in Figures 7 to 11 the dotted circles indicate the transistors that are turned on, while the transistors without dotted circles indicate the transistors that are turned off.

[0142] First, according to an embodiment, hereinafter reference will be made to Figure 6 and Figure 7 to describe the operation of the display device 10 during a first initialization period P1, where Figure 7 is a circuit diagram for explaining the operation of the display device 10 in Figure 5 during the first initialization period P1 of Figure 6 the display device 10.

[0143] As Figure 6 illustrated, during the first initialization period P1, the second gate signal GR and the third gate signal GI may each be at an active level. However, during the first initialization period P1, the first gate signal GW and the emission signal EM may each be at an inactive level.

[0144] The second gate signal GR at an active level can be applied to the gate electrode of the third transistor T3 through the second gate line GRL. As a result, the third transistor T3 can be turned on.

[0145] The third gate signal GI at an active level can be applied to the gate electrode of the fourth transistor T4 through the third gate line GIL. As a result, the fourth transistor T4 can be turned on.

[0146] The first gate signal GW at an inactive level can be applied to the gate electrode of the second transistor T2 through the first gate line GWL. As a result, the second transistor T2 can be turned off.

[0147] The emission signal EM at an inactive level can be applied to the pair of gate electrodes of the first transistor T1 through the emission line EML. As a result, the first transistor T1 can be turned off.

[0148] When the third transistor T3 is turned on, the reference voltage Vref can be applied to the first node N1 through the turned-on third transistor T3. Therefore, the gate electrode of the first transistor T1 connected to the first node N1 can be initialized to the reference voltage Vref.

[0149] When the fourth transistor T4 is turned on, the initialization voltage Vaint can be applied to the second node N2 through the turned-on fourth transistor T4. As a result, the source electrode of the first transistor T1 connected to the second node N2 can be initialized to the initialization voltage Vaint.

[0150] The difference between the reference voltage Vref at the first node N1, such as the gate-source voltage of the first transistor T1, and the initialization voltage Vaint at the second node N2 can be greater than the threshold voltage of the first transistor T1. However, as described above, since the emission signal EM at the inactive level is applied to the pair of gate electrodes of the first transistor T1, the first transistor T1 can be turned off. For example, in an embodiment, when the emission signal EM applied to the pair of gate electrodes of the first transistor T1 is at the inactive level, the threshold voltage of the first transistor T1 can be shifted to increase, and as a result, the gate-source voltage of the first transistor T1 can become less than the increased threshold voltage of the first transistor T1. Therefore, when the emission signal EM is at the inactive level, the first transistor T1 can always remain turned off regardless of its gate-source voltage. In an embodiment, the emission signal EM at the inactive level can have a voltage less than or equal to the voltage of the gate signal at the inactive level. For example, the voltage of the emission signal EM at the inactive level can be the same as or less than the voltage of the first gate signal GW at the inactive level. In other words, when the emission signal EM is at the inactive level, the emission signal EM can have the same value as the first gate signal GW when the first gate signal GW is at the inactive level or can have a value smaller than the first gate signal GW when the first gate signal GW is at the inactive level.

[0151] According to an embodiment, hereinafter, reference will be made to Figure 6 and Figure 8 to describe the operation of the display device 10 during the threshold voltage detection period P2, where Figure 8 is a circuit diagram for explaining Figure 5 the operation of the display device 10 in Figure 6 during the threshold voltage detection period P2.

[0152] In an embodiment and as Figure 6 illustrated in, during the threshold voltage detection period P2, the second gate signal GR and the emission signal EM can each be at the active level. However, during the threshold voltage detection period P2, the first gate signal GW and the third gate signal GI can each be at the inactive level.

[0153] The second gate signal GR at the active level can be applied to the gate electrode of the third transistor T3 through the second gate line GRL. As a result, the third transistor T3 can be turned on.

[0154] The emission signal EM at the active level can be applied to the pair of gate electrodes of the first transistor T1 through the emission line EML. As a result, during the threshold voltage detection period P2, as will be described later, the first transistor T1 can be turned on and then turned off.

[0155] The first gate signal GW at an invalid level can be applied to the gate electrode of the second transistor T2 through the first gate line GWL. As a result, the second transistor T2 can be turned off.

[0156] The third gate signal GI at an invalid level can be applied to the gate electrode of the fourth transistor T4 through the third gate line GIL. As a result, the fourth transistor T4 can be turned off.

[0157] Accordingly, in the embodiment, through the turned-on third transistor T3, the reference voltage Vref can be applied to the first node N1, and as a result, the voltage of the gate electrode of the first transistor T1 can be maintained at the reference voltage Vref. The voltage of the source electrode of the first transistor T1 is the initialization voltage Vaint applied during the previous time period (i.e., the first initialization period P1), and since the emission signal EM applied to the gate electrode of the first transistor T1 is at an effective level, the first transistor T1 can be turned on during the threshold voltage detection period P2. Moreover, during the threshold voltage detection period P2, the second node N2 remains floating due to the turned-off fourth transistor T4, thereby allowing the voltage of the second node N2 to gradually increase due to the current flowing through the turned-on first transistor T1. In other words, when the fourth transistor T4 is turned off, the supply of the initialization voltage Vaint to the second node N2 is interrupted, resulting in the voltage of the second node N2 rising and thereby gradually reducing the current flowing through the first transistor T1. As a result, the gate-source voltage of the first transistor T1 gradually decreases until when the gate-source voltage of the first transistor T1 reaches the threshold voltage of the first transistor T1, the first transistor T1 is turned off. Thus, the detected threshold voltage of the first transistor T1 can be reflected in the second node N2. Moreover, the detected threshold voltage of the first transistor T1 can be stored and held in the second node N2 by the first capacitor Cst.

[0158] According to an embodiment, hereinafter, reference will be made to Figure 6 and Figure 9 to describe the operation of the display device 10 during the data writing period P3, where Figure 9 is a circuit diagram for illustrating Figure 5 the operation of the display device 10 during the Figure 6 data writing period P3.

[0159] In the embodiment and as Figure 6 illustrated in

[0160] The first gate signal GW at an effective level can be applied to the gate electrode of the second transistor T2 through the first gate line GWL. As a result, the second transistor T2 can be turned on.

[0161] The second gate signal GR at an inactive level can be applied to the gate electrode of the third transistor T3 through the second gate line GRL. As a result, the third transistor T3 can be turned off.

[0162] The third gate signal GI at an inactive level can be applied to the gate electrode of the fourth transistor T4 through the third gate line GIL. As a result, the fourth transistor T4 can be turned off.

[0163] The emission signal EM at an inactive level can be applied to the pair of gate electrodes of the first transistor T1 through the emission line EML.

[0164] Accordingly, in the embodiment, when the second transistor T2 is turned on, the data voltage Vdt from the data line DL can be applied to the first node N1 through the turned-on second transistor T2. In other words, the data voltage Vdt from the data line DL can be applied to the gate electrode of the first transistor T1. The amplitude of the data voltage Vdt added to the voltage of the first node N1 can be determined by the ratio of the capacitance of the second capacitor Chold to the combined capacitance of the first capacitor Cst and the second capacitor Chold. For example, in the embodiment, the voltage added to the first node N1 can be determined as "data voltage Vdt × (capacitance of the second capacitor Chold / (capacitance of the first capacitor Cst + capacitance of the second capacitor Chold))", where the data voltage Vdt can be a voltage for displaying an image in a predetermined gray scale (or lightness). Moreover, during the data writing period P3, due to the emission signal EM at an inactive level applied to the pair of gate electrodes of the first transistor T1, the first transistor T1 can remain turned off.

[0165] According to an embodiment, hereinafter, reference will be made to Figure 6 and Figure 10 to describe the operation of the display device 10 during the second initialization period P4, where Figure 10 is a circuit diagram for illustrating Figure 5 the operation of the display device 10 during the Figure 6 second initialization period P4.

[0166] As Figure 6 illustrated, during the second initialization period P4, the third gate signal GI can be at an effective level. However, during the second initialization period P4, the first gate signal GW, the second gate signal GR, and the emission signal EM can each be at an inactive level.

[0167] The third gate signal GI at an active level can be applied to the gate electrode of the fourth transistor T4 through the third gate line GIL. As a result, the fourth transistor T4 can be turned on.

[0168] The first gate signal GW at an inactive level can be applied to the gate electrode of the second transistor T2 through the first gate line GWL. As a result, the second transistor T2 can be turned off.

[0169] The second gate signal GR at an inactive level can be applied to the gate electrode of the third transistor T3 through the second gate line GRL. As a result, the third transistor T3 can be turned off.

[0170] The emission signal EM at an inactive level can be applied to the pair of gate electrodes of the first transistor T1 through the emission line EML.

[0171] Accordingly, in the embodiment, when the fourth transistor T4 is turned on, the initialization voltage Vaint from the initialization voltage line VIL can be applied to the second node N2 through the turned-on fourth transistor T4. As a result, the voltage of the second node N2 can be initialized to the initialization voltage Vaint.

[0172] According to the embodiment, hereinafter, reference will be made to Figure 6 and Figure 11 to describe the operation of the display device 10 during the emission period P5, where Figure 11 is a circuit diagram for illustrating Figure 5 the operation of the display device 10 during the Figure 6 emission period P5.

[0173] As Figure 6 illustrated, during the emission period P5, the emission signal EM can be at an active level. However, during the emission period P5, the first gate signal GW, the second gate signal GR, and the third gate signal GI can each be at an inactive level.

[0174] The emission signal EM at an active level can be applied to the pair of gate electrodes of the first transistor T1 through the emission line EML.

[0175] The first gate signal GW at an inactive level can be applied to the gate electrode of the second transistor T2 through the first gate line GWL. As a result, the second transistor T2 can be turned off.

[0176] The second gate signal GR at an inactive level can be applied to the gate electrode of the third transistor T3 through the second gate line GRL. As a result, the third transistor T3 can be turned off.

[0177] The third gate signal GI at an inactive level can be applied to the gate electrode of the fourth transistor T4 through the third gate line GIL. As a result, the fourth transistor T4 can be turned off.

[0178] During the emission period P5, due to the gate-source voltage maintained by the first capacitor Cst and the emission signal EM at an effective level, the first transistor T1 can remain conducting.

[0179] Accordingly, during the emission period P5, the conducting first transistor T1 can enable the driving voltage ELVDD to be applied to the first electrode (i.e., the second node N2) of the light-emitting element ED through the conducting first transistor T1. The amplitude of the driving current flowing into the light-emitting element ED through the conducting first transistor T1 can be determined based on the data voltage Vdt and the threshold voltage of the first transistor T1. As a result, the driving current supplied to the light-emitting element ED can accurately reflect the amplitude of the data voltage Vdt. In other words, the driving current can be accurately compensated by the threshold voltage of the first transistor T1. Accordingly, by compensating the threshold voltage of the first transistor T1 for each pixel PX, the driving current for each pixel PX can be determined, thereby minimizing the brightness deviation between the pixels PX according to the deviation of the threshold voltage of the first transistor T1 between the pixels PX. Therefore, the display quality of the display device 10 can be improved.

[0180] Figure 12 is a circuit diagram of another exemplary pixel PX of the display device 10 according to an embodiment.

[0181] Figure 12 The pixel PX of Figure 5 differs from its counterpart of

[0182] in that it further includes a fifth transistor T5, which will be described below, mainly focusing on the differences.

[0183] The fifth transistor T5 can be turned on by a fourth gate signal EMB from a fourth gate line EMBL that electrically connects the second node N2 and the first electrode of the light-emitting element ED. The gate electrode of the fifth transistor T5 can be electrically connected to the fourth gate line EMBL, the drain electrode of the fifth transistor T5 can be electrically connected to the second node N2, and the source electrode of the fifth transistor T5 can be electrically connected to the first electrode of the light-emitting element ED.

[0184] It should be understood that due to the fifth transistor T5, even if there is significant noise at the second node N2 (i.e., at the source electrode of the first transistor T1), the risk of voltage setting at the second node N2 can be reduced.

[0185] Moreover, a fourth transistor T4 that electrically connects the first electrode of the light-emitting element ED and the initialization voltage line VIL can be turned on by a third gate signal GI from the third gate line GIL. The fourth transistor T4 can be connected in series between the first electrode of the light-emitting element ED and the initialization voltage line VIL, where the gate electrode of the fourth transistor T4 can be electrically connected to the third gate line GIL, the drain electrode of the fourth transistor T4 can be electrically connected to the first electrode of the light-emitting element ED, and the source electrode of the fourth transistor T4 can be electrically connected to the initialization voltage line VIL.

[0186] Figure 13 is a timing diagram for explaining the Figure 12 first gate signal GW, second gate signal GR, third gate signal GI, fourth gate signal EMB, and emission signal EM according to an embodiment.

[0187] In an embodiment and with reference to Figure 13 , the display device 10 can operate based on a first initialization period P1, a threshold voltage detection period P2, a data writing period P3, a second initialization period P4, and an emission period P5.

[0188] During the first initialization period P1, the second gate signal GR, the third gate signal GI, and the fourth gate signal EMB can each be at an active level. However, during the first initialization period P1, the first gate signal GW and the emission signal EM can each be at an inactive level.

[0189] During the threshold voltage detection period P2, the second gate signal GR and the emission signal EM can each be at an active level. However, during the threshold voltage detection period P2, the first gate signal GW, the third gate signal GI, and the fourth gate signal EMB can each be at an inactive level.

[0190] During the data writing period P3, the first gate signal GW can be at an active level. However, during the data writing period P3, the second gate signal GR, the third gate signal GI, the fourth gate signal EMB, and the emission signal EM can each be at an inactive level. Moreover, during the data writing period P3, a data voltage Vdt can be applied to the data line DL.

[0191] During the second initialization period P4, the third gate signal GI and the fourth gate signal EMB can each be at an active level. However, during the second initialization period P4, the first gate signal GW, the second gate signal GR, and the emission signal EM can each be at an inactive level.

[0192] During the emission period P5, the emission signal EM and the fourth gate signal EMB can each be at an active level. However, during the emission period P5, the first gate signal GW, the second gate signal GR, and the third gate signal GI can each be at an inactive level.

[0193] According to an embodiment, hereinafter, reference will be made to Figures 14 to 18 to describe the operation of the display device 10. In Figures 14 to 18 the figure, the dotted circles indicate the transistors that are turned on, and the transistors without the dotted circles indicate the transistors that are turned off.

[0194] First, according to an embodiment, hereinafter, reference will be made to Figure 13 and Figure 14 to describe the operation of the display device 10 during the first initialization period P1, where Figure 14 is a circuit diagram for explaining the operation of the display device 10 of Figure 12 during the first initialization period P1 of Figure 13 the figure.

[0195] As illustrated in Figure 13 the figure, during the first initialization period P1, the second gate signal GR, the third gate signal GI, and the fourth gate signal EMB may each be at an active level. However, during the first initialization period P1, the first gate signal GW and the emission signal EM may each be at an inactive level.

[0196] The second gate signal GR at the active level may be applied to the gate electrode of the third transistor T3 through the second gate line GRL. As a result, the third transistor T3 may be turned on.

[0197] The third gate signal GI at the active level may be applied to the gate electrode of the fourth transistor T4 through the third gate line GIL. As a result, the fourth transistor T4 may be turned on.

[0198] The fourth gate signal EMB at the active level may be applied to the gate electrode of the fifth transistor T5 through the fourth gate line EMBL. As a result, the fifth transistor T5 may be turned on.

[0199] The first gate signal GW at the inactive level may be applied to the gate electrode of the second transistor T2 through the first gate line GWL. As a result, the second transistor T2 may be turned off.

[0200] The emission signal EM at the inactive level may be applied to the pair of gate electrodes of the first transistor T1 through the emission line EML. As a result, the first transistor T1 may be turned off.

[0201] When the third transistor T3 is turned on, the reference voltage Vref may be applied to the first node N1 through the turned-on third transistor T3. Accordingly, the gate electrode of the first transistor T1 connected to the first node N1 may be initialized to the reference voltage Vref.

[0202] When the fourth transistor T4 is turned on, the initialization voltage Vaint can be applied to the anode of the light-emitting element ED through the turned-on fourth transistor T4. As a result, the anode of the light-emitting element ED can be initialized to the initialization voltage Vaint.

[0203] When the fifth transistor T5 is turned on, the initialization voltage Vaint can be applied to the second node N2 through the turned-on fifth transistor T5. As a result, the source electrode of the first transistor T1 connected to the second node N2 can be initialized to the initialization voltage Vaint.

[0204] In addition, the difference between the reference voltage Vref at the first node N1, such as the gate-source voltage of the first transistor T1, and the initialization voltage Vaint at the second node N2 can be greater than the threshold voltage of the first transistor T1. However, as described above, since the emission signal EM at the invalid level is applied to the pair of gate electrodes of the first transistor T1, the first transistor T1 can be turned off. For example, when the emission signal EM applied to the pair of gate electrodes of the first transistor T1 is at the invalid level, the threshold voltage of the first transistor T1 can be shifted to increase, and as a result, the gate-source voltage of the first transistor T1 can become less than the increased threshold voltage of the first transistor T1. Therefore, when the emission signal EM is at the invalid level, the first transistor T1 can always remain turned off regardless of its gate-source voltage. In an embodiment, the emission signal EM at the invalid level can have a voltage less than or equal to the voltage of the gate signal at the invalid level. For example, the voltage of the emission signal EM at the invalid level can be the same as or less than the voltage of the first gate signal GW at the invalid level.

[0205] According to an embodiment, hereinafter, reference will be made to Figure 13 and Figure 15 to describe the operation of the display device 10 during the threshold voltage detection period P2, where Figure 15 is a circuit diagram for explaining Figure 12 the operation of the display device 10 during the Figure 13 threshold voltage detection period P2.

[0206] As Figure 13 illustrated, during the threshold voltage detection period P2, the second gate signal GR and the emission signal EM can each be at the effective level. However, during the threshold voltage detection period P2, the first gate signal GW, the third gate signal GI, and the fourth gate signal EMB can each be at the invalid level.

[0207] The second gate signal GR at the effective level can be applied to the gate electrode of the third transistor T3 through the second gate line GRL. As a result, the third transistor T3 can be turned on.

[0208] The transmission signal EM at an active level can be applied to the pair of gate electrodes of the first transistor T1 through the transmission line EML. As a result, during the threshold voltage detection period P2, as will be described later, the first transistor T1 can be turned on and then turned off.

[0209] The first gate signal GW at an inactive level can be applied to the gate electrode of the second transistor T2 through the first gate line GWL. As a result, the second transistor T2 can be turned off.

[0210] The third gate signal GI at an inactive level can be applied to the gate electrode of the fourth transistor T4 through the third gate line GIL. As a result, the fourth transistor T4 can be turned off.

[0211] The fourth gate signal EMB at an inactive level can be applied to the gate electrode of the fifth transistor T5 through the fourth gate line EMBL. As a result, the fifth transistor T5 can be turned off.

[0212] The reference voltage Vref can be applied to the first node N1 via the turned-on third transistor T3, and as a result, the voltage of the gate electrode of the first transistor T1 can be maintained at the reference voltage Vref. The voltage of the source electrode of the first transistor T1 is the initialization voltage Vaint applied during the previous period (i.e., the first initialization period P1), and since the transmission signal EM applied to the pair of gate electrodes of the first transistor T1 is at an active level, the first transistor T1 can be turned on during the threshold voltage detection period P2. In addition, during the threshold voltage detection period P2, the second node N2 remains floating due to the turned-off fourth transistor T4, allowing the voltage of the second node N2 to gradually increase due to the current flowing through the turned-on first transistor T1. In other words, when the fourth transistor T4 is turned off, the supply of the initialization voltage Vaint to the second node N2 is interrupted, causing the voltage of the second node N2 to rise and thereby gradually reducing the current flowing through the first transistor T1. As a result, the gate-source voltage of the first transistor T1 gradually decreases until when the gate-source voltage of the first transistor T1 reaches the threshold voltage of the first transistor T1, the first transistor T1 is turned off. Then, the detected threshold voltage of the first transistor T1 can be reflected in the second node N2. Moreover, the detected threshold voltage of the first transistor T1 can be stored by the first capacitor Cst and held at the second node N2.

[0213] According to an embodiment, hereinafter, reference will be made to Figure 13 and Figure 16 to describe the operation of the display device 10 during the data writing period P3, where Figure 16 is a circuit diagram for illustrating Figure 12 the operation of the display device 10 during the Figure 13 data writing period P3.

[0214] As Figure 13 As illustrated, during the data writing period P3, the first gate signal GW may be at an active level. However, during the data writing period P3, the second gate signal GR, the third gate signal GI, the fourth gate signal EMB, and the emission signal EM may each be at an inactive level. Also, during the data writing period P3, the data voltage Vdt may be applied to the data line DL.

[0215] The first gate signal GW at the active level may be applied to the gate electrode of the second transistor T2 through the first gate line GWL. As a result, the second transistor T2 may be turned on.

[0216] The second gate signal GR at the inactive level may be applied to the gate electrode of the third transistor T3 through the second gate line GRL. As a result, the third transistor T3 may be turned off.

[0217] The third gate signal GI at the inactive level may be applied to the gate electrode of the fourth transistor T4 through the third gate line GIL. As a result, the fourth transistor T4 may be turned off.

[0218] The fourth gate signal EMB at the inactive level may be applied to the gate electrode of the fifth transistor T5 through the fourth gate line EMBL. As a result, the fifth transistor T5 may be turned off.

[0219] The emission signal EM at the inactive level may be applied to the counter gate electrode of the first transistor T1 through the emission line EML.

[0220] When the second transistor T2 is turned on, the data voltage Vdt from the data line DL may be applied to the first node N1 through the turned-on second transistor T2. In other words, the data voltage Vdt from the data line DL may be applied to the gate electrode of the first transistor T1. The amplitude of the data voltage Vdt added to the voltage at the first node N1 may be determined by the ratio of the capacitance of the second capacitor Chold to the combined capacitance of the first capacitor Cst and the second capacitor Chold. For example, the voltage added to the first node N1 may be determined as "data voltage Vdt * (capacitance of the second capacitor Chold / (capacitance of the first capacitor Cst + capacitance of the second capacitor Chold))", where the data voltage Vdt may be a voltage for displaying an image at a predetermined gray scale (or brightness). Also, during the data writing period P3, due to the emission signal EM at the inactive level applied to the counter gate electrode of the first transistor T1, the first transistor T1 may remain turned off.

[0221] According to an embodiment, hereinafter, reference will be made to Figure 13 and Figure 17 describe the operation of the display device 10 during the second initialization period P4, whereFigure 17 is for explaining Figure 12 the operation of the display device 10 during Figure 13 the second initialization period P4.

[0222] As Figure 13 illustrated, during the second initialization period P4, the third gate signal GI and the fourth gate signal EMB can each be at an active level. However, during the second initialization period P4, the first gate signal GW, the second gate signal GR, and the emission signal EM can each be at an inactive level.

[0223] The third gate signal GI at an active level can be applied to the gate electrode of the fourth transistor T4 through the third gate line GIL. As a result, the fourth transistor T4 can be turned on.

[0224] The fourth gate signal EMB at an active level can be applied to the gate electrode of the fifth transistor T5 through the fourth gate line EMBL. As a result, the fifth transistor T5 can be turned on.

[0225] The first gate signal GW at an inactive level can be applied to the gate electrode of the second transistor T2 through the first gate line GWL. As a result, the second transistor T2 can be turned off.

[0226] The second gate signal GR at an inactive level can be applied to the gate electrode of the third transistor T3 through the second gate line GRL. As a result, the third transistor T3 can be turned off.

[0227] The emission signal EM at an inactive level can be applied to the pair of gate electrodes of the first transistor T1 through the emission line EML.

[0228] When the fourth transistor T4 is turned on, the initialization voltage Vaint from the initialization voltage line VIL can be applied to the anode of the light-emitting element ED through the turned-on fourth transistor T4. Accordingly, the voltage of the anode of the light-emitting element ED can be initialized to the initialization voltage Vaint.

[0229] When the fifth transistor T5 is turned on, the initialization voltage Vaint from the initialization voltage line VIL can be applied to the second node N2 through the turned-on fifth transistor T5. As a result, the voltage of the second node N2 can be initialized to the initialization voltage Vaint.

[0230] According to an embodiment, hereinafter, reference will be made to Figure 13 and Figure 18 to describe the operation of the display device 10 during the emission period P5, where Figure 18 is for explaining Figure 12 the operation of the display device 10 during Figure 13 the emission period P5.

[0231] As Figure 13 As illustrated, during the emission period P5, the emission signal EM and the fourth gate signal EMB can each be at an active level. However, during the emission period P5, the first gate signal GW, the second gate signal GR, and the third gate signal GI can each be at an inactive level.

[0232] The emission signal EM at an active level can be applied to the pair of gate electrodes of the first transistor T1 through the emission line EML.

[0233] The fourth gate signal EMB at an active level can be applied to the gate electrode of the fifth transistor T5 through the fourth gate line EMBL. As a result, the fifth transistor T5 can be turned on.

[0234] The first gate signal GW at an inactive level can be applied to the gate electrode of the second transistor T2 through the first gate line GWL. As a result, the second transistor T2 can be turned off.

[0235] The second gate signal GR at an inactive level can be applied to the gate electrode of the third transistor T3 through the second gate line GRL. As a result, the third transistor T3 can be turned off.

[0236] The third gate signal GI at an inactive level can be applied to the gate electrode of the fourth transistor T4 through the third gate line GIL. As a result, the fourth transistor T4 can be turned off.

[0237] During the emission period P5, due to the gate-source voltage held by the first capacitor Cst and the emission signal EM at an active level, the first transistor T1 can remain turned on.

[0238] Therefore, during the emission period P5, the turned-on first transistor T1 and the turned-on fifth transistor T5 can enable the drive voltage ELVDD to be applied to the first electrode (i.e., the second node N2) of the light-emitting element ED through the turned-on first transistor T1 and the turned-on fifth transistor T5. The amplitude of the drive current flowing into the light-emitting element ED through the turned-on first transistor T1 and the turned-on fifth transistor T5 can be determined based on the data voltage Vdt and the threshold voltage of the first transistor T1. As a result, the drive current supplied to the light-emitting element ED can accurately reflect the amplitude of the data voltage Vdt. In other words, the drive current can be accurately compensated for the threshold voltage of the first transistor T1. Therefore, by compensating for the threshold voltage of the first transistor T1 of each pixel PX, the drive current of each pixel PX can be determined, thereby minimizing the brightness deviation between the pixels PX according to the deviation of the threshold voltage of the first transistor T1 between the pixels PX. Accordingly, the display quality of the display device 10 can be improved.

[0239] Figure 19 This is a cross-sectional view of the display device 10 according to an embodiment.

[0240] In an embodiment and with reference to Figure 19 , the display device 10 may include a substrate SUB, a light-shielding layer BML, a buffer film BF, a TFT layer TFTL, a light-emitting element layer EMTL, and a packaging layer ENC. The light-shielding layer BML, the buffer film BF, the TFT layer TFTL, the light-emitting element layer EMTL, and the packaging layer ENC may be sequentially disposed on the substrate SUB along a third direction DR3. Additionally, the TFT layer TFTL may include Figure 5 the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 of Figure 12 the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 of. For simplicity, only the first transistor T1 is illustrated as being included in the TFT layer TFTL in Figure 19 .

[0241] In an embodiment, the substrate SUB may be a rigid substrate or a flexible substrate that is bendable, foldable, or rollable and may be formed of an insulating material such as glass, quartz, or a polymer material. Examples of the polymer material include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl ester, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), and combinations thereof. In another embodiment, the substrate SUB may include a metal material.

[0242] In an embodiment, the light-shielding layer BML may be disposed on the substrate SUB and may be disposed on the substrate SUB overlapping the active layer ACT. The light-shielding layer BML may be formed of a metal material such as chromium (Cr) or molybdenum (Mo) or a material such as black ink or black dye. The first transistor T1 on the light-shielding layer BML may stabilize the electrical characteristics. For example, performance degradation of an oxide-based transistor can be minimized. However, since the oxide semiconductor is light-sensitive, a change in current due to light from an external source may occur. In one embodiment, the light-shielding layer BML may include the gate electrode pair of the first transistor T1. In another embodiment, the light-shielding layer BML may be the gate electrode pair of the first transistor T1. The light-shielding layer BML may receive the emission signal EM.

[0243] In an embodiment, a buffer film BF may be disposed on a light-shielding layer BML and may cover the entire surface of a substrate SUB including the light-shielding layer BML. The buffer film BF may be a film for protecting the first transistor T1 of the TFT layer TFTL and the emission layer EL of the light-emitting element layer EMTL from moisture penetration through the substrate SUB vulnerable to moisture. The buffer film BF may include a plurality of inorganic films stacked alternately. For example, the buffer film BF may be formed as a multilayer film in which one or more inorganic films such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer are stacked alternately.

[0244] In an embodiment, an active layer ACT may be disposed on the buffer film BF and may include, for example, an oxide semiconductor. For example, the active layer ACT may include indium gallium zinc oxide (IGZO) or indium gallium zinc tin oxide (IGZTO).

[0245] In an embodiment, a gate insulating film GTI may be disposed on the active layer ACT. For example, the gate insulating film GTI may be disposed to overlap with a channel region CH of the active layer ACT and may include at least one of tetraethyl orthosilicate (TEOS), silicon nitride (SiN x ) and silicon oxide (SiO2). For example, the gate insulating film GTI may have a bilayer structure in which a silicon nitride film with a thickness of 40 nm and a TEOS film with a thickness of 80 nm are sequentially stacked.

[0246] In an embodiment, a gate electrode GE may be disposed on the gate insulating film GTI and may be disposed on the gate insulating film GTI to overlap with the channel region CH of the active layer ACT. The gate electrode GE may be formed of Al or Ti. Additionally, the gate electrode GE may have a bilayer or trilayer structure in which Al and Ti are stacked.

[0247] In an embodiment, an interlayer insulating layer ITL may be disposed on the gate electrode GE and may be disposed on the entire surface of the substrate SUB including the gate electrode GE. The interlayer insulating layer ITL may include an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer as an example. Alternatively, the interlayer insulating layer ITL may include a plurality of inorganic films.

[0248] In an embodiment, a source connection electrode SCE and a drain connection electrode DCE may be disposed on the interlayer insulating layer ITL. The source connection electrode SCE may be connected to a source electrode SE of the active layer ACT through a first contact hole CT1 penetrating the interlayer insulating layer ITL. The drain connection electrode DCE may be connected to a drain electrode DE of the active layer ACT through a second contact hole CT2 penetrating the interlayer insulating layer ITL. The source connection electrode SCE and the drain connection electrode DCE may be formed of the same material as the gate electrode GE.

[0249] In an embodiment, a passivation film PAS may be disposed on a source connection electrode SCE and a drain connection electrode DCE, and the passivation film PAS may be disposed on the entire surface of a substrate SUB including an interlayer insulating layer ITL. The passivation film PAS may be formed of the same material as the interlayer insulating layer ITL.

[0250] In an embodiment, a planarization film VA may be disposed on the passivation film PAS to be disposed on the entire surface of the substrate SUB including the passivation film PAS. The planarization film VA may include a film of an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0251] In an embodiment, a light-emitting element layer EMTL including a pixel electrode PE may be disposed on the planarization film VA. The pixel electrode PE may be connected to the source connection electrode SCE through a third contact hole CT3 penetrating the planarization film VA. The pixel electrode PE may be connected to a source electrode SE of an active layer ACT through the source connection electrode SCE.

[0252] In an embodiment, the light-emitting element layer EMTL may include a light-emitting element ED and a bank (or pixel defining film) PDL.

[0253] The light-emitting element ED may include a pixel electrode PE, an emission layer EL, and a common electrode CM. An emission region EA represents a region where holes from the pixel electrode PE and electrons from the common electrode CM recombine in the emission layer EL to emit light. In this case, the pixel electrode PE may be an anode of the light-emitting element ED, and the common electrode CM may be a cathode of the light-emitting element ED.

[0254] According to an embodiment, in a top emission structure that emits light toward the common electrode CM with respect to the emission layer EL, the pixel electrode PE may be formed as a single layer of Mo, Ti, copper (Cu), or Al, or may be formed as a stack of Al and Ti (e.g., Ti / Al / Ti), a stack of Al and indium tin oxide (ITO) (e.g., ITO / Al / ITO), a silver (Ag)-palladium (Pd)-copper (Cu) (APC) alloy, or a stack of an APC alloy and ITO (e.g., ITO / APC / ITO).

[0255] In an embodiment, the bank PDL defines an emission region EA of each pixel PX and may be disposed to expose a part of the pixel electrode PE on the planarization film VA. The bank PDL may cover an edge of the pixel electrode PE. The bank PDL may be formed as an organic film of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0256] In an embodiment, a spacer SPC may be disposed on a bank PDL and may support a mask during the fabrication of an emission layer EL. The spacer SPC may be formed as an organic film of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0257] In an embodiment, an emission layer EL may be formed on a pixel electrode PE and may include an organic material, and may emit light of a specific color. For example, the emission layer EL may include a hole transport layer, an organic material layer, and an electron transport layer. The organic material layer may include a host and a dopant. The organic material layer may include a material capable of emitting light of a specific color and may be formed using a phosphorescent or fluorescent material.

[0258] In an embodiment, a plurality of pixels PX may include a first pixel that emits light of a first color through a first emission region, a second pixel that emits light of a second color through a second emission region, and a third pixel that emits light of a third color through a third emission region.

[0259] In an embodiment, the organic material layer of the first emission layer of the first emission region that emits light of a first color may include a host material containing carbazole biphenyl (CBP) or 1,3-bis(carbazol-9-yl)benzene (mCP) and a dopant material containing at least one of bis(1-phenylisoquinoline)acetylacetonatoiridium(III) (PIQIr(acac)), bis(1-phenylquinoline)acetylacetonatoiridium(III) (PQIr(acac)), tris(1-phenylquinoline)iridium(III) (PQIr), and platinum octaethylporphyrin (PtOEP). In another embodiment, the organic material layer of the first emission layer of the first emission region may include a fluorescent material containing PBD:Eu(DBM)3(Phen) or perylene, but the present invention is not limited thereto.

[0260] In an embodiment, the organic material layer of the second emission layer of the second emission region that emits light of a second color may include a host material containing CBP or mCP and a dopant material containing fac-tris(2-phenylpyridine)iridium(III) (Ir(ppy)3). In another embodiment, the organic material layer of the second emission layer of the second emission region may be composed of a fluorescent material such as tris(8-hydroxyquinoline)aluminum(III) (Alq3), but the present invention is not limited thereto.

[0261] In an embodiment, the organic material layer of the third emission layer of the third emission region that emits light of a third color may include a host material containing CBP or mCP and a dopant material containing (4,6-F2ppy)2Irpic or L2BD111, but the present invention is not limited thereto.

[0262] In an embodiment, the common electrode CM may be disposed on the emission layer EL. For example, the common electrode CM may be disposed on the first emission layer, the second emission layer, and the third emission layer and may be configured to cover the first emission layer, the second emission layer, and the third emission layer. The common electrode CM may be a common layer commonly provided for the first emission layer, the second emission layer, and the third emission layer, and a cover layer may be formed on the common electrode CM.

[0263] According to an embodiment, in a top emission structure, the common electrode CM may be formed of a transparent conductive oxide (TCO) such as ITO or indium zinc oxide (IZO), or a semi-transmissive conductive material such as magnesium (Mg), silver, or an alloy thereof. When the common electrode CM is formed of a semi-transmissive conductive material, due to the microcavity, the common electrode CM can improve the light emission efficiency.

[0264] In an embodiment, the encapsulation layer ENC may be formed on the light-emitting element layer EMTL and may include at least one inorganic film for preventing oxygen or moisture from penetrating the light-emitting element layer EMTL. Additionally, the encapsulation layer ENC may include at least one organic film for protecting the light-emitting element layer EMTL from contaminants such as dust. For example, the encapsulation layer ENC may include a first encapsulation inorganic film TFE1, an encapsulation organic film TFE2, and a second encapsulation inorganic film TFE3.

[0265] In an embodiment, the first encapsulation inorganic film TFE1 may be disposed on the common electrode CM, the encapsulation organic film TFE2 may be disposed on the first encapsulation inorganic film TFE1, and the second encapsulation inorganic film TFE3 may be disposed on the encapsulation organic film TFE2. The first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3 may be formed as a multilayer film of one or more inorganic films alternately stacked such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer. The encapsulation organic film TFE2 may be an organic film of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0266] Moreover, a barrier film may be further disposed between the substrate SUB and the light-shielding layer BML and may be a protective barrier for the first transistor T1 of the TFT layer TFTL and the emission layer EL of the light-emitting element layer EMTL to prevent moisture from penetrating through the substrate SUB susceptible to humidity. In an embodiment, the barrier film may include a plurality of inorganic films alternately stacked. For example, the barrier film may be formed as a multilayer film of one or more inorganic films alternately stacked such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0267] Upon concluding the detailed description, those skilled in the art will understand that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the present invention. Therefore, the disclosed embodiments of the present invention are used only in a general and descriptive sense and not for purposes of limitation. Each component specifically shown in an embodiment of the present invention can be implemented by modification, and such modifications and differences relevant to the application should be construed as being included within the scope of the present invention. Moreover, embodiments or parts of embodiments can be combined in whole or in part without departing from the scope of the present invention.

Claims

1. A display device, comprising: A pixel circuit; And A light-emitting element connected between a second node of the pixel circuit and a common voltage line, wherein The pixel circuit includes a first transistor connected to a driving voltage line and the second node, wherein The first transistor includes a gate electrode connected to a first node and a pair of gate electrodes connected to an emission line.

2. The display device according to claim 1, wherein, The pixel circuit further includes: A second transistor connected to a data line and the first node.

3. The display device according to claim 2, wherein, The pixel circuit further includes: A third transistor connected to a reference voltage line and the first node.

4. The display device according to claim 3, wherein, The pixel circuit further includes: A fourth transistor connected to the second node and an initialization voltage line.

5. The display device according to claim 4, wherein, The pixel circuit further includes: A first capacitor connected to the first node and the second node; and A second capacitor connected to the second node and the driving voltage line.

6. The display device according to claim 5, further comprising: A first gate line connected to a gate electrode of the second transistor; A second gate line connected to a gate electrode of the third transistor; And A third gate line connected to a gate electrode of the fourth transistor.

7. The display device according to claim 6, wherein The data line transmits a data voltage, The emission line transmits an emission signal, The first gate line transmits a first gate signal, The second gate line transmits a second gate signal, and The third gate line transmits a third gate signal.

8. The display device according to claim 7, wherein, During a first initialization period, each of the second gate signal and the third gate signal is at an active level, and each of the first gate signal and the emission signal is at an inactive level.

9. The display device according to claim 8, wherein, During a threshold voltage detection period following the first initialization period, each of the second gate signal and the emission signal is at the active level, and each of the first gate signal and the third gate signal is at the inactive level.

10. The display device according to claim 9, wherein, During a data writing period following the threshold voltage detection period, the first gate signal is at the active level, each of the second gate signal, the third gate signal and the emission signal is at the inactive level, and the data voltage is applied to the data line.

11. The display device according to claim 10, wherein, During a second initialization period following the data writing period, the third gate signal is at the active level, and each of the first gate signal, the second gate signal and the emission signal is at the inactive level.

12. The display device according to claim 11, wherein, During an emission period following the second initialization period, the emission signal is at the active level, and each of the first gate signal, the second gate signal and the third gate signal is at the inactive level.

13. The display device according to claim 7, wherein, When the emission signal is at the inactive level, the emission signal has the same value as the first gate signal when the first gate signal is at the inactive level or has a value smaller than the first gate signal when the first gate signal is at the inactive level.

14. The display device according to any one of claims 5 to 13, wherein The capacitance of the second capacitor is greater than the capacitance of the first capacitor.

15. The display device according to claim 5, wherein, The pixel circuit further includes: A fifth transistor connected to the second node and an anode of the light-emitting element, Among them, the fourth transistor is connected to the anode of the light-emitting element and the initialization voltage line.

16. The display device according to claim 15, further comprising: A first gate line connected to the gate electrode of the second transistor; A second gate line connected to the gate electrode of the third transistor; A third gate line connected to the gate electrode of the fourth transistor; And A fourth gate line connected to the gate electrode of the fifth transistor.

17. The display device according to claim 16, wherein The data line transmits a data voltage, The emission line transmits an emission signal, The first gate line transmits a first gate signal, The second gate line transmits a second gate signal, The third gate line transmits a third gate signal, and The fourth gate line transmits a fourth gate signal.

18. The display device according to claim 17, wherein, During a first initialization period, each of the second gate signal, the third gate signal, and the fourth gate signal is at an active level, and each of the first gate signal and the emission signal is at an inactive level.

19. The display device according to claim 18, wherein, During a threshold voltage detection period following the first initialization period, each of the second gate signal and the emission signal is at the active level, and each of the first gate signal, the third gate signal, and the fourth gate signal is at the inactive level.

20. The display device according to claim 19, wherein, During a data writing period following the threshold voltage detection period, the first gate signal is at the active level, each of the second gate signal, the third gate signal, the fourth gate signal, and the emission signal is at the inactive level, and the data voltage is applied to the data line.

21. The display device according to claim 20, wherein During a second initialization period following the data writing period, each of the third gate signal and the fourth gate signal is at the active level, and each of the first gate signal, the second gate signal, and the emission signal is at the inactive level.

22. The display device according to claim 21, wherein, During an emission period following the second initialization period, each of the emission signal and the fourth gate signal is at the active level, and each of the first gate signal, the second gate signal, and the third gate signal is at the inactive level.

23. A display device, comprising: A pixel circuit; And A light-emitting element connected to a second node of the pixel circuit and a common voltage line, wherein The pixel circuit includes: a first transistor connected to a driving voltage line and the second node, wherein the first transistor has a gate electrode connected to a first node and a pair of gate electrodes connected to an emission line; a second transistor connected to a data line and the first node, wherein the second transistor has a gate electrode connected to a first gate line; a third transistor connected to a reference voltage line and the first node, wherein the third transistor has a gate electrode connected to a second gate line; a fourth transistor connected to the second node and an initialization voltage line, wherein the fourth transistor has a gate electrode connected to a third gate line; a first capacitor connected to the first node and the second node; and a second capacitor connected to the second node and the driving voltage line, wherein During a first initialization period, each of a second gate signal from the second gate line and a third gate signal from the third gate line is at an active level, and each of a first gate signal from the first gate line and a transmission signal from the transmission line is at an inactive level. During a threshold voltage detection period following the first initialization period, each of the second gate signal and the transmission signal is at the active level, and each of the first gate signal and the third gate signal is at the inactive level. During a data writing period following the threshold voltage detection period, the first gate signal is at the active level, each of the second gate signal, the third gate signal, and the transmission signal is at the inactive level, and a data voltage is applied to the data line. During a second initialization period following the data writing period, the third gate signal is at the active level, and each of the first gate signal, the second gate signal, and the transmission signal is at the inactive level, and During a transmission period following the second initialization period, the transmission signal is at the active level, and each of the first gate signal, the second gate signal, and the third gate signal is at the inactive level.

24. A display device includes: A pixel circuit; And A light-emitting element connected to a second node of the pixel circuit and a common voltage line, wherein The pixel circuit includes: a first transistor connected to a driving voltage line and the second node, wherein the first transistor has a gate electrode connected to a first node and a pair of gate electrodes connected to a transmission line; a second transistor connected to a data line and the first node, wherein the second transistor has a gate electrode connected to a first gate line; a third transistor connected to a reference voltage line and the first node, wherein the third transistor has a gate electrode connected to a second gate line; a fourth transistor connected to an anode of the light-emitting element and an initialization voltage line, wherein the fourth transistor has a gate electrode connected to a third gate line; a fifth transistor connected to the second node and the anode of the light-emitting element, wherein the fifth transistor has a gate electrode connected to a fourth gate line; a first capacitor connected to the first node and the second node; and a second capacitor connected to the second node and the driving voltage line, wherein During a first initialization period, each of a second gate signal from the second gate line, a third gate signal from the third gate line, and a fourth gate signal from the fourth gate line is at an active level, and each of a first gate signal from the first gate line and a transmission signal from the transmission line is at an inactive level. During a threshold voltage detection period following the first initialization period, each of the second gate signal and the transmission signal is at the active level, and each of the first gate signal, the third gate signal, and the fourth gate signal is at the inactive level. During a data writing period following the threshold voltage detection period, the first gate signal is at the active level, each of the second gate signal, the third gate signal, the fourth gate signal, and the emission signal is at the inactive level, and a data voltage is applied to the data line. During a second initialization period following the data writing period, each of the third gate signal and the fourth gate signal is at the active level, and each of the first gate signal, the second gate signal, and the emission signal is at the inactive level, and During an emission period following the second initialization period, each of the emission signal and the fourth gate signal is at the active level, and each of the first gate signal, the second gate signal, and the third gate signal is at the inactive level.

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