Time mark information recording device of data and FPGA (Field Programmable Gate Array) chip

Abstract

The invention discloses a data time mark information recording device and an FPGA (Field Programmable Gate Array) chip. The device can comprise a processor module, a crystal oscillator clock, a time mark timing module and a time mark data recording module, the processor module is used for acquiring current time information and sending the current time information to the time mark timing module; the crystal oscillator clock is used for sending a clock signal to the time mark timing module according to a preset period; the time mark timing module is used for counting based on the clock signal to obtain relative time information after receiving the current time information, adding the current time information and the relative time information to obtain real-time time information, and continuously sending the real-time time information to the time mark data recording module; and the time mark data recording module is used for acquiring the acquired industrial signal data, and recording the latest received real-time time information as time mark information to the industrial signal data when the industrial signal data is acquired. Time mark information can be accurately and stably recorded based on a clock signal sent by a crystal oscillator clock.

Description

Technical Field

[0001] This application relates to the technical field of data processing, and particularly to a time stamp information recording device for data and an FPGA chip. Background Art

[0002] Devices usually have a need to collect data from sensors, relays, etc. For example, a device can collect industrial signal data such as digital input data, analog signal data, and Recommended Standard 485 (RS485 for short) communication data. However, the data collected by the device may be abnormal. To trace back the abnormal data, the collected data will be stored, and for the convenience of analysis, the time stamp information (i.e., time marking information) when the data is collected is considered to determine the time when the abnormality occurs and the temporal correlation of the signals of each channel when the data is collected.

[0003] In related technologies, the following method is usually used to record time stamp information for the collected data: when a Field-Programmable Gate Array (FPGA) chip receives the collected data, the current time information input by an external device can be obtained through a network interface, and then the current time information is recorded as the time stamp information of the data. However, in the above method, the time stamp information depends on the external device connected to the network interface. In the case of a network interruption of the external device, it is easy to affect the continuity of the input current time information, resulting in the inability of the FPGA chip to immediately record the time stamp information for the collected data when it receives the data, thereby affecting the subsequent abnormal analysis process. Summary of the Invention

[0004] In view of this, embodiments of this application provide a time stamp information recording device for data and an FPGA chip, aiming to improve the accuracy and stability of recording time stamp information for data.

[0005] In a first aspect, embodiments of this application provide a time stamp information recording device for data. The device includes a processor module, a crystal oscillator clock, a time stamp timing module, and a time stamp data recording module;

[0006] The processor module is configured to obtain current time information and send the current time information to the time stamp timing module;

[0007] The crystal oscillator clock is configured to send a clock signal to the time stamp timing module according to a preset period;

[0008] The time scale timing module is used to, after receiving the current time information, perform counting based on the clock signal to obtain relative time information, add the current time information and the relative time information to obtain real-time time information, and continuously send the real-time time information to the time scale data recording module;

[0009] The time scale data recording module is used to acquire the collected industrial signal data, and when the industrial signal data is acquired, record the latest received real-time time information as time scale information into the industrial signal data.

[0010] In a possible implementation manner, the time scale timing module includes a clock cycle register and a unit time register;

[0011] The processor module is used to send the current time information to the unit time register;

[0012] The crystal oscillator clock is used to send a clock signal to the clock cycle register according to a preset period;

[0013] The clock cycle register is used to perform counting based on the clock signal, and when the count reaches a first value, send a first count signal to the unit time register;

[0014] The unit time register is used to perform counting based on the first count signal to obtain relative time information, add the current time information and the relative time information to obtain real-time time information, and continuously send the real-time time information to the time scale data recording module.

[0015] In a possible implementation manner, the unit time register is further used to clear the relative time information when it reaches the counting unit, and return to execute the step of performing counting based on the first count signal to obtain relative time information.

[0016] In a possible implementation manner, the unit time register includes a plurality of unit time registers, and the counting units corresponding to the plurality of unit time registers increase in adjacent unit levels;

[0017] The unit time register with the smallest counting unit is used to perform counting based on the first count signal to obtain first relative time information, clear the first relative time information when it reaches the counting unit of this unit time register, and simultaneously send a count signal to the unit time register with the corresponding larger adjacent unit level;

[0018] At least one remaining unit time register, which is used to return the step of performing counting based on the first counting signal obtained from the counting signal sent by the unit time register at a smaller adjacent unit level corresponding to it as the first counting signal, until the unit time register with the largest counting unit is cleared;

[0019] The unit time register corresponding to the unit time of the current time information is used to obtain real-time time information by adding the current time information and the relative time information.

[0020] In a possible implementation manner, the time scale timing module further includes an accumulative timing register;

[0021] The clock cycle register is further used to send a second counting signal to the accumulative timing register when the count reaches a second value;

[0022] The accumulative timing register is used to perform counting based on the second counting signal to obtain accumulative time information.

[0023] In a possible implementation manner, the device further includes a register processing module;

[0024] The processor module is used to obtain current time information and send the current time information to the time scale timing module through the register processing module;

[0025] The register processing module is used to convert the format of the time information;

[0026] The time scale timing module is used to receive the time information after format conversion.

[0027] In a possible implementation manner, the device further includes a reset signal processing module;

[0028] The reset signal processing module is used to send a reset signal to the time scale timing module after determining that the current time information is obtained;

[0029] The time scale timing module is further used to clear the previous count when receiving the reset signal.

[0030] In a second aspect, an FPGA chip is provided in an embodiment of the present application. The FPGA chip includes the processor module, the time scale timing module, and the time scale data recording module according to any item in the first aspect.

[0031] In a possible implementation manner, the FPGA chip further includes the register processing module in the first aspect.

[0032] In a possible implementation, the FPGA chip further includes the reset signal processing module described in the first aspect.

[0033] In a third aspect, an embodiment of the present application provides a method for recording time stamp information of data, which is applied to a device for recording time stamp information of data. The device includes a processor module, a crystal oscillator clock, a time stamp timing module, and a time stamp data recording module. The method includes:

[0034] Obtaining current time information through the processor module and sending the current time information to the time stamp timing module;

[0035] Sending a clock signal to the time stamp timing module by the crystal oscillator clock according to a preset period;

[0036] After receiving the current time information through the time stamp timing module, counting by the time stamp timing module based on the clock signal to obtain relative time information, adding the current time information and the relative time information to obtain real-time time information, and continuously sending the real-time time information to the time stamp data recording module;

[0037] Obtaining the collected industrial signal data through the time stamp data recording module, and when the industrial signal data is obtained, recording the latest received real-time time information as the time stamp information into the industrial signal data.

[0038] In a fourth aspect, an embodiment of the present application provides a device for recording time stamp information of data. The device includes a memory and a processor:

[0039] The memory is used for storing a computer program and transmitting the computer program to the processor;

[0040] The processor is used for executing the computer program so that the device executes the method for recording time stamp information of data described in the second aspect above.

[0041] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium. A computer program is stored on the computer-readable storage medium. When the computer program is run, the device running the computer program implements the method for recording time stamp information of data described in the second aspect above.

[0042] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0043] An embodiment of the present application provides a timestamp information recording device for data and an FPGA chip. In this device, it includes a processor module, a crystal oscillator clock, a timestamp timing module, and a timestamp data recording module. Among them, the processor module is used to obtain the current time information and send the current time information to the timestamp timing module; the crystal oscillator clock is used to send a clock signal to the timestamp timing module according to a preset period; the timestamp timing module is used to, after receiving the current time information, perform counting based on the clock signal to obtain relative time information, add the current time information and the relative time information to obtain real-time time information, and continuously send the real-time time information to the timestamp data recording module; the timestamp data recording module is used to obtain the collected industrial signal data, and when obtaining the industrial signal data, record the latest received real-time time information as the timestamp information into the industrial signal data.

[0044] In this way, after obtaining the current time information, counting and addition can be continued on this basis to obtain real-time time information. Only by sending the current time information once can the subsequent real-time time information be timed, which can reduce the dependence on the continuity of the external device inputting the current time information; and the counting depends on the clock signal sent by the crystal oscillator clock, which is not affected by the network and can stably send the clock signal. Therefore, it can ensure the accuracy and stability of the timestamp information recording. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] To more clearly illustrate the technical solutions in this embodiment or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiment or the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0046] Figure 1 It is an application scenario of a timestamp information recording device for data provided by an embodiment of the present application;

[0047] Figure 2 It is a schematic structural diagram of a timestamp information recording device for data provided by an embodiment of the present application;

[0048] Figure 3 It is a schematic structural diagram of a specific timestamp information recording device for data provided by an embodiment of the present application;

[0049] Figure 4 It is a schematic diagram of the timestamp timing module timing provided by an embodiment of the present application;

[0050] Figure 5 It is another schematic diagram of the timestamp timing module timing provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0051] To enable those skilled in the art to better understand the solution of this application, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of this application.

[0052] Currently, the following method is usually adopted to record the time stamp information of the collected data: The FPGA chip has a network interface. When the FPGA chip receives the collected data, it obtains the current time information through the network interface, and then records the current time information as the time stamp information of the data. However, in the above method, the time stamp information depends on the external device connected to the network interface. In the case of a network interruption in the external device, it is easy to affect the continuity of the input current time information, resulting in the inability to immediately record the time stamp information for the data when the FPGA chip receives the collected data, thereby affecting the subsequent abnormal analysis process.

[0053] Based on this, to solve the above problems, the embodiments of this application provide a device for recording the time stamp information of data and an FPGA chip. In this device, it includes a processor module, a crystal oscillator clock, a time stamp timing module, and a time stamp data recording module; among them, the processor module is used to obtain the current time information and send the current time information to the time stamp timing module; the crystal oscillator clock is used to send a clock signal to the time stamp timing module according to a preset period; the time stamp timing module is used to, after receiving the current time information, perform counting based on the clock signal to obtain relative time information, add the current time information and the relative time information to obtain real-time time information, and continuously send the real-time time information to the time stamp data recording module; the time stamp data recording module is used to obtain the collected industrial signal data, and when obtaining the industrial signal data, record the latest received real-time time information as the time stamp information into the industrial signal data.

[0054] In this way, after obtaining the current time information, counting and addition can be continued on this basis to obtain real-time time information. Only by sending the current time information once can the subsequent real-time time information timing be realized, which can reduce the dependence on the continuity of the external device inputting the current time information; and the counting depends on the clock signal sent by the crystal oscillator clock, which is not affected by the network and can stably send the clock signal. Therefore, it can ensure the accuracy and stability of the time stamp information recording.

[0055] For example, the embodiments of this application can be applied to such as Figure 1In the shown scenario. The scenario includes a host computer 101 and a time stamp information recording device 102 for data. The host computer 101 can send the current time information to the time stamp information recording device 102 for data. Based on the current time information, the time stamp information recording device 102 for data can record the time stamp information for the collected industrial signal data by using the implementation manner provided in the embodiments of the present application. Subsequently, the time stamp information recording device 102 for data can send the industrial signal data with the recorded time stamp information to the host computer 101.

[0056] It should be noted that the above scenario is only an example scenario provided by the embodiments of the present application, and the embodiments of the present application are not limited to this scenario.

[0057] Next, in conjunction with the accompanying drawings, the time stamp information recording device for data and the FPGA chip in the embodiments of the present application will be described in detail through embodiments.

[0058] See Figure 2 , this figure is a schematic structural diagram of a time stamp information recording device for data provided by the embodiments of the present application. In conjunction with Figure 2 shown, the time stamp information recording device for data may specifically include a processor module, a crystal oscillator clock, a time stamp timing module, and a time stamp data recording module.

[0059] The processor module is configured to obtain the current time information and send the current time information to the time stamp timing module.

[0060] For ease of understanding, the following will be introduced in detail in conjunction with Figure 3 This is a schematic structural diagram of a specific time stamp information recording device for data provided by the embodiments of the present application. Figure 3

[0061] In some embodiments, the host computer may be connected to the processor module, and the host computer may also be connected to the device through a network interface (which may also be simply referred to as a network port). The host computer can obtain the current time information through the network port, and then the host computer can send the current time information to the processor module. Subsequently, the processor module can send the obtained current time information to the time stamp timing module.

[0062] In some embodiments, the time stamp information recording device for data may be composed of an FPGA chip and a crystal oscillator clock. The FPGA chip may include a processor module, a time stamp timing module, and a time stamp data recording module. For ease of understanding, the time stamp information recording device provided by the embodiments of the present application will be introduced hereinafter by taking this as an example, but it does not limit the device provided by the present application.

[0063] ​The FPGA chip includes an integrated Processing System (PS), which can provide the functions required by the processor module. Therefore, the processor module can be the PS in the FPGA chip.

[0064] As Figure 3 shown, the PS and the host computer can be connected through the Peripheral Component Interconnect Express (PCIE). After receiving the current time information through the network interface, the host computer can send the current time information to the PS of the FPGA chip through the PCIE interface.

[0065] In a possible implementation of the present application, the device may further include a register processing module;

[0066] Correspondingly, the processor module is specifically configured to obtain the current time information and send the current time information to the time scale timing module through the register processing module;

[0067] The register processing module is used to convert the format of the current time information;

[0068] The time scale timing module is used to receive the current time information after format conversion.

[0069] As Figure 3 shown, the PS can be connected to the register processing module through the Advanced eXtensible Interface (AXI bus for short). The PS can actively send the current time information to the register processing module through the AXI bus. The register processing module converts its format and sends the current time information after format conversion to the time scale timing module (it can also be called assigning to the time scale timing module. For specific details, please refer to the description of the following embodiments Figure 5 . It will not be elaborated here).

[0070] Exemplarily, the format of the current time information obtained by the processor module is in string format, such as "14:30:45". The register processing module can convert it into the time format stored in a 32-bit register, converted to "01110 011110101101". The present application does not limit the format before and after conversion, as long as the converted format is readable by the register.

[0071] The crystal oscillator clock is used to send a clock signal to the time scale timing module according to a preset period. Please refer to Figure 3 shown.

[0072] For example, the crystal oscillator clock can be a high-precision clock with low temperature drift. Its frequency can be 125 MHz, and the preset period (which can also be called the clock period) is the reciprocal of the frequency, 8 nanoseconds (ns). A clock signal can be sent every 8 ns. The clock signal can be the rising edge of the clock period, indicating that the crystal oscillator clock can send a rising edge to the time scale timing module every 8 ns.

[0073] It should be noted that the preset period of the above crystal oscillator clock is only an example and can be adjusted according to actual needs. This application does not make any limitations in this regard.

[0074] The time scale timing module is used to, after receiving the current time information, perform counting based on the clock signal to obtain relative time information, add the current time information and the relative time information to obtain real-time time information, and continuously send the real-time time information to the time scale data recording module.

[0075] After receiving the current time information, the time scale timing module can start timing by counting to obtain relative time information. Relative time information refers to the time difference between the current time information and the real-time time information. Therefore, the time scale timing module can add the current time information and the relative time information to obtain real-time time information and continuously send this to the time scale data recording module.

[0076] The time scale data recording module is used to obtain the collected industrial signal data, and when obtaining the industrial signal data, record the latest received real-time time information as time scale information into the industrial signal data.

[0077] Among them, as Figure 3 shown, the industrial signal data can be digital input / output data, analog signal data, and RS485 communication data. This application does not make any limitations on the type and quantity of industrial signal data.

[0078] The time scale data recording module obtains the industrial signal data. Since it has been continuously receiving real-time time information, the latest received real-time time information is the time when the industrial signal data is obtained. Therefore, it can be recorded as time scale information into the industrial signal data (which can also be called the combination of the two), so that the industrial signal data has time scale information. Please refer to Figure 3 shown.

[0079] Continue to refer to Figure 3 , the time scale data recording module can be connected to the PS through the AXI bus. After combining the industrial signal data and the time scale information, the time scale data recording module can send it to the PS through the AXI bus. The PS then forwards the industrial signal data with time scale information to the host computer through the PCIE interface. Subsequently, the host computer sends it to the device through the network port, and the device can store it for subsequent back-check in case of anomalies.

[0080] In a possible implementation manner of the present application, the time scale timing module may include a clock cycle register and a unit time register.

[0081] The processor module is configured to send the current time information to the unit time register.

[0082] The crystal oscillator clock is configured to send a clock signal to the clock cycle register according to a preset period.

[0083] The clock cycle register is configured to count based on the clock signal, and send a first count signal to the unit time register when the count reaches a first value.

[0084] Among them, the clock cycle register can count based on the clock signal sent by the crystal oscillator clock. For example, the clock cycle register can count once when it receives a clock signal.

[0085] The first value can be related to the unit time corresponding to the unit time register. In some embodiments, the unit time register may include a millisecond register, and its unit time is 1 millisecond (ms). Then, after the clock cycle register confirms that it reaches 1 ms based on the crystal oscillator clock, it can send a first count signal to the millisecond register. Then, the first value can be obtained by dividing 1 ms by the preset period. Based on the above example, the preset period can be 8 ns, so the first value can be 125000. That is to say, the clock cycle counts based on the clock signal, and when the count reaches 125000, it can send a first count signal to the millisecond register.

[0086] After the count of the clock cycle register reaches the first value, it can be cleared and the step of counting based on the clock signal and sending a first count signal to the unit time register when the count reaches the first value can be executed again. In this way, the counting of the clock cycle register can be realized based on the clock signal by repeating this process.

[0087] In addition, in some embodiments, the unit time register may further include a microsecond register, etc., and its unit time is 1 microsecond. The first value can be determined based on this, and the present application does not make any limitations in this regard.

[0088] The unit time register is configured to count based on the first count signal to obtain relative time information, add the current time information and the relative time information to obtain real-time time information, and continuously send the real-time time information to the time scale data recording module.

[0089] Exemplarily, in an example where the unit time register includes a millisecond register, counting can be performed based on the first counting signal. The millisecond cycle flag is initially 0. When the first counting signal is received, the millisecond cycle flag of the millisecond register can be set to 1. When the first counting signal is received again, the millisecond cycle flag can be incremented by 1. By repeating this cycle, timing in milliseconds can be achieved.

[0090] In a possible implementation manner of the present application, the unit time register is further configured to clear the relative time information when it reaches the counting unit, and return to execute the step of obtaining the relative time information by counting based on the first counting signal.

[0091] The counting unit refers to the counting period preset for the unit register. In an example where the unit time register includes a millisecond register, its counting unit can be 1 second (s). When the millisecond cycle flag of the millisecond register reaches 1000, it represents 1000 ms, that is, 1 s, and then it can be cleared and re-timed.

[0092] In a possible implementation manner of the present application, the device may further include a reset signal processing module.

[0093] The reset signal processing module is configured to send a reset signal to the time scale timing module after determining that the current time information has been obtained;

[0094] The time scale timing module is further configured to clear the previous count when receiving the reset signal.

[0095] After the current time information is obtained, it indicates that re-counting needs to be performed based on the latest current time information. Therefore, the count of the time scale timing module can be cleared, which can also be referred to as initialization.

[0096] In an example where the time scale timing module includes a clock cycle register and a unit time register, both of them can be initialized. The clock cycle register starts counting again based on the clock signal, and the unit time register starts counting again based on the first counting signal.

[0097] In a possible implementation manner of the present application, the unit time register includes multiple unit time registers, and the counting units corresponding to the multiple unit time registers increase in adjacent unit levels.

[0098] For example, the unit time register may include a millisecond register, a second register, a minute register, and a clock register, and the corresponding counting units are 1 s, 1 minute (min), 1 hour (h), and 23 hours 59 minutes 59 seconds respectively. This example will be used for introduction hereinafter.

[0099] The unit time register with the smallest counting unit is used to count based on the first counting signal to obtain first relative time information, and when the first relative time information reaches the counting unit of this unit time register, it is cleared, and at the same time, a counting signal is sent to the unit time register at the corresponding larger adjacent unit level.

[0100] Based on the above example, the unit time register with the smallest counting unit is the millisecond register. When its millisecond cycle flag reaches 1000, it can be cleared and a counting signal is sent to the second register.

[0101] Based on the above introduction, after the millisecond register is cleared, it can start timing again, which will not be elaborated here.

[0102] See Figure 4 , which is a schematic diagram of the timing of a time scale timing module provided by an embodiment of the present application. As Figure 4 shown, after the time scale timing module receives a reset signal, the clock cycle register and the millisecond register can be initialized. Subsequently, the clock cycle register can count based on the clock signal sent by the crystal oscillator clock, and continue to count when the count does not reach the first value (that is, does not reach 1 ms), and when it reaches the first value, it can send a first counting signal to the millisecond register. The millisecond register can increment the millisecond cycle flag by 1, and continue to count when the count does not reach 1000 (that is, 1 s), and when it reaches, it can send a counting signal to the second register.

[0103] It should be noted that Figure 4 the cumulative timing register in

[0104] is described in detail below, and will not be elaborated here for the time being.

[0105] Based on the above introduction, the remaining at least one unit time register may include a seconds register, a minutes register, and a clock register. The seconds register may count based on the count signal sent by the milliseconds register, increment the second cycle flag by 1, clear it when the second cycle flag reaches 60, i.e., when the count reaches 1 minute, and send a count signal to the minutes register; the minutes register may count based on the count signal sent by the seconds register, increment the minute cycle flag by 1, clear it when the minute cycle flag reaches 60, i.e., when the count reaches 1 hour, and send a count signal to the clock register; the clock register may count based on the count signal sent by the minutes register, increment the hour cycle flag by 1, and clear the seconds register, the minutes register, and the clock register when the hour cycle flag reaches 23, the minute cycle flag reaches 59, and the second cycle flag reaches 59.

[0106] The unit time register corresponding to the unit time of the current time information is used to obtain the real-time time information by adding the current time information and the relative time information.

[0107] The current time information has a corresponding unit time. Taking "14:30:45" in the above example as an example, its corresponding unit time is 1 hour, 1 minute, and 1 second. Therefore, the seconds register, the minutes register, and the clock register are the unit time registers corresponding to the unit time of the current time information. The following will be introduced with this as an example.

[0108] Then these three registers can add the current time information and the relative time information obtained by their respective counts to obtain the real-time time information.

[0109] Combined with Figure 5 This is introduced below. This figure is a schematic diagram of the time scale timing module timing provided by an embodiment of the present application. After receiving the reset signal, the seconds register, the minutes register, and the clock register of the time scale timing module can be initialized. After receiving the current time information, the time scale timing module can assign the current time information to the seconds register, the minutes register, and the clock register. Taking "14:30:45" as an example, the second cycle flag, the minute cycle flag, and the hour cycle flag corresponding to these three registers are respectively assigned to 45, 30, and 14, and each can count based on the method described above until the hour cycle flag reaches 23, the minute cycle flag reaches 59, and the second cycle flag reaches 59, i.e., when it reaches 23:59:59, they are all cleared, which will not be elaborated here.

[0110] It should be noted that the sending of the reset signal depends on the current time information sent by the upper computer for example only. The reset signal can also be sent based on the local time. At this time, the processor module can send the time of sending the reset signal as the current time information to the time stamp timing module, independent of the upper computer, and rely on local time to record the time stamp information.

[0111] In a possible implementation of the present application, the time-stamp timing module may further include a cumulative timing register;

[0112] The clock cycle register is further configured to send a second counting signal to the cumulative timing register when the count reaches a second value.

[0113] The cumulative timing register is used to obtain cumulative time information by counting based on the second counting signal.

[0114] In some embodiments, the cumulative timing register can continue to count based on the second counting signal without being cleared, and the obtained cumulative time information is also the time difference between the current time information and the real-time time information (also called relative time information). However, the difference from the counting performed by the unit time register is that the count of the unit time register will be cleared when it reaches the counting unit, and its final output is the real-time time information, while the count of the cumulative timing register can directly reflect the relative time information without the need for additional calculation.

[0115] The second value and the second counting signal may refer to the introduction of the first value and the first counting signal in the above example, and will not be repeated here.

[0116] For example, in an example where the preset period is 8ns, the cumulative timing register can be a millisecond register, then the second value can be 125000; the cumulative timing register can also be a second register, then the second value can be 125,000,000. This application does not limit the unit time of the cumulative timing register.

[0117] In some embodiments, the processor module may send an enable signal to the cumulative timing register via the AXI bus to trigger the cumulative timing register to start working, for example, the enable signal may be set to 1.

[0118] Continue to see Figure 4 As shown, in the example where the cumulative timing register is a millisecond register, the clock period register can count based on the clock signal sent by the crystal oscillator clock, and continue counting when the count has not reached the second value (that is, when it has not reached 1ms). When the second value is reached, a second counting signal can be sent to the cumulative timing register. When the enable signal also enables the cumulative timing register, the cumulative timing register can set the millisecond period flag +1 and continue counting.

[0119] The embodiment of the present application also provides an FPGA chip, which includes the processor module, the time scale timing module, and the time scale data recording module described in the above embodiment. For details, please refer to the above, and details will not be repeated here.

[0120] In a possible implementation manner, the FPGA chip may further include the register processing module described above.

[0121] In a possible implementation manner, the FPGA chip may further include the reset signal processing module described above.

[0122] It should be noted that the introduction of the register processing module and the reset signal processing module can be found above, and details will not be repeated here.

[0123] Based on the content introduced above, in the embodiment of the present application, after obtaining the current time information, the time scale timing module can continue to obtain the relative time information by counting based on the clock signal sent by the crystal oscillator clock, and then the sum of the two can obtain the real-time time information, which can reduce the dependence on the continuity of the current time information input by the external device. In the case that the external device no longer sends the current time information subsequently, the time scale information can still be well recorded.

[0124] In the related art, only the current time information is directly obtained and recorded into the industrial signal data, and when there is a need to obtain the relative time information after the device is powered on, it cannot be satisfied. However, in the present application, when the device is powered on, the device sends the current time information through the host computer, and the cumulative time information is obtained by counting through the cumulative timing register, and the relative time information does not need to be calculated again for direct backcheck.

[0125] In the related art, the accuracy of the time scale information depends on the current time information input by the external device. If the network interface for inputting the current time information is interfered, it is difficult to ensure the accuracy of the time scale information. However, in the present application, the counting depends on the clock signal sent by the crystal oscillator clock, which is not affected by the network and can stably send the clock signal. Therefore, the accuracy and stability of the time scale information recording can be ensured.

[0126] The embodiment of the present application also correspondingly provides a method for recording the time scale information of data. This method can be applied to a device for recording the time scale information of data. The device includes a processor module, a crystal oscillator clock, a time scale timing module, and a time scale data recording module. The method includes:

[0127] Obtain the current time information through the processor module and send the current time information to the time scale timing module;

[0128] Send a clock signal to the time scale timing module by the crystal oscillator clock according to a preset period;

[0129] After receiving the current time information through the time scale timing module, the relative time information is obtained by counting based on the clock signal through the time scale timing module, the current time information and the relative time information are added to obtain the real-time time information, and the real-time time information is continuously sent to the time scale data recording module;

[0130] The industrial signal data collected is obtained through the time scale data recording module, and when the industrial signal data is obtained, the latest received real-time time information is recorded as the time scale information into the industrial signal data.

[0131] The steps executable by each module can be referred to the description of the above embodiments, which will not be repeated here.

[0132] The embodiment of the present application also provides a time scale information recording device for corresponding data and a computer-readable storage medium for implementing the solution provided by the embodiment of the present application.

[0133] Among them, the time scale information recording device for the data includes a memory and a processor. The memory is used to store a computer program, and the processor is used to execute the computer program so that the device executes the time scale information recording method for the data described in any embodiment of the present application.

[0134] A computer program is stored in the computer-readable storage medium. When the computer program is run, the device running the computer program implements the time scale information recording method for the data described in any embodiment of the present application.

[0135] In the embodiment of the present application, the "first", "second" (if any) in the names such as "first" and "second" are only used as name identifiers and do not represent the first and second in order.

[0136] From the description of the above embodiments, those skilled in the art can clearly understand that all or part of the steps in the above embodiment methods can be implemented by means of software plus a general hardware platform. Based on such an understanding, the technical solution of the present application can be embodied in the form of a software product. The computer software product can be stored in a readable storage medium, such as a read-only memory (ROM) / RAM, magnetic disk, optical disk, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network communication device such as a router) to execute the methods described in each embodiment or some parts of the embodiments of the present application.

[0137] It should be noted that the various embodiments in this specification are described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other, and the key points of each embodiment are the differences from other embodiments. In particular, for the device embodiments, since they are basically similar to the method embodiments, they are described relatively simply, and for the relevant parts, reference can be made to the descriptions in the method embodiments. The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components referred to as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without creative efforts.

[0138] As described above, this is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A time scale information recording device for data, characterized in that, The device includes a processor module, a crystal oscillator clock, a time scale timing module, and a time scale data recording module; The processor module is used to obtain the current time information and send the current time information to the time scale timing module; The crystal oscillator clock is used to send a clock signal to the time scale timing module according to a preset period; The time scale timing module is used to, after receiving the current time information, perform counting based on the clock signal to obtain relative time information, add the current time information and the relative time information to obtain real-time time information, and continuously send the real-time time information to the time scale data recording module; The time scale data recording module is used to obtain the collected industrial signal data, and when the industrial signal data is obtained, record the latest received real-time time information as time scale information into the industrial signal data.

2. The device according to claim 1, wherein the time scale timing module includes a clock cycle register and a unit time register; The processor module is used to send the current time information to the unit time register; The crystal oscillator clock is used to send a clock signal to the clock cycle register according to a preset period; The clock cycle register is used to perform counting based on the clock signal, and send a first counting signal to the unit time register when the count reaches a first value; The unit time register is used to perform counting based on the first counting signal to obtain relative time information, add the current time information and the relative time information to obtain real-time time information, and continuously send the real-time time information to the time scale data recording module.

3. The device according to claim 2, characterized in that The unit time register is further used to clear when the relative time information reaches the counting unit, and return to execute the step of performing counting based on the first counting signal to obtain relative time information.

4. The device according to claim 3, characterized in that, The unit time register includes a plurality of unit time registers, and the counting units corresponding to the plurality of unit time registers increase in adjacent unit levels; The unit time register with the smallest counting unit is used to perform counting based on the first counting signal to obtain first relative time information, clear when the first relative time information reaches the counting unit of this unit time register, and simultaneously send a counting signal to the unit time register with the larger adjacent unit level; The remaining at least one unit time register is used to use the counting signal sent by the unit time register with the smaller adjacent unit level as the first counting signal, return to execute the step of performing counting based on the first counting signal to obtain first relative time information until the unit time register with the largest counting unit is cleared; The unit time register corresponding to the unit time of the current time information is used to add the current time information and the relative time information to obtain real-time time information.

5. The device according to claim 2, characterized in that, The time scale timing module further includes an accumulated timing register; The clock cycle register is further used to send a second counting signal to the accumulated timing register when the count reaches a second value; The accumulated timing register is used to perform counting based on the second counting signal to obtain accumulated time information.

6. The device according to any one of claims 1-5, characterized in that The device also includes a register processing module; The processor module is configured to obtain current time information and send the current time information to the time stamp timing module via the register processing module; The register processing module is used to convert the format of the current time information; The time stamp timing module is used to receive the current time information after format conversion.

7. The method according to claims 1-5, characterized in that The device also includes a reset signal processing module; The reset signal processing module is configured to send a reset signal to the time-stamp timing module after determining that the current time information has been acquired; The time-stamp timing module is further configured to clear the previous count to zero upon receiving the reset signal.

8. A field programmable gate array (FPGA) chip, characterized in that, The FPGA chip includes the processor module, time stamp timing module and time stamp data recording module according to any one of claims 1 to 7.

9. The FPGA chip according to claim 8, characterized in that: The FPGA chip also includes the register processing module described in claim 6.

10. The FPGA chip according to claim 8, wherein The FPGA chip also includes the reset signal processing module according to claim 7.

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