Network card, data transmission method, device and product based on computing link protocol

Abstract

The present application discloses a network card, data transmission method, device and product based on the computing link protocol, which are applied to the field of communication technology, including: an interface control module for receiving a data transmission request sent by a host and sending it to a logic module; a storage control module for receiving the data transmission request through the logic module and writing the data packet descriptor carried in the data transmission request to the transmission queue of the storage device connected to the network card; the logic module for sending the write address of the data packet descriptor to the network interface module; the network interface module for obtaining the data packet stored in the storage device pointed to by the data packet descriptor through the interface control module after receiving the write address of the data packet descriptor, and outputting the data packet to the outside; the interface control module uses the computing link protocol to enable the storage device connected to the network card and the host memory to be uniformly addressed and used. Applying the solution of the present application can effectively reduce the delay of the network card in sending data.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a network card, data transmission method, device and product based on a computing link protocol. Background Art

[0002] Traditional FPGA (Field Programmable Gate Array)-based network cards can connect to hosts using the PCIe (Peripheral Component Interconnect Express) protocol interface. However, as computing systems evolve, the demand for high bandwidth, low latency, and efficient data transmission continues to grow, and traditional PCIe-based interconnect technology is increasingly unable to meet these demands.

[0003] In summary, how to effectively reduce the delay in sending data by a network card is a technical problem that those skilled in the art urgently need to solve. Summary of the Invention

[0004] The present application provides a network card, data transmission method, device and product based on a computing link protocol to effectively reduce the delay of the network card in sending data.

[0005] This application provides a network card based on the Compute Link Protocol, including:

[0006] The interface control module is used to receive a data transmission request from the host and send it to the logic module;

[0007] a storage control module, configured to receive the data transmission request through the logic module, and write the data packet descriptor carried in the data transmission request into a transmission queue of a storage device connected to the network card;

[0008] The logic module is configured to send the write address of the data packet descriptor to the network interface module;

[0009] The network interface module is configured to, after receiving the write address of the data packet descriptor, obtain the data packet stored in the storage device pointed to by the data packet descriptor through the interface control module, and output the data packet to the outside;

[0010] The interface control module is an interface control module that uses a computing link protocol, so that the storage device connected to the network card and the host memory are uniformly addressed and used.

[0011] The present application provides a data transmission method based on a computing link protocol, which is applied to an interface control module in a network card based on the computing link protocol as described above, including:

[0012] receiving a data transmission request sent by a host and sending the request to a logic module, so that the storage control module receives the data transmission request through the logic module, writes a data packet descriptor carried in the data transmission request to a transmission queue of a storage device connected to the network card, and sends a write address of the data packet descriptor to the network interface module;

[0013] After the network interface module receives the write address of the data packet descriptor, the network interface module obtains the data packet stored in the storage device pointed to by the data packet descriptor through communication with the network interface module, and sends the data packet to the network interface module, so that the network interface module outputs the data packet externally;

[0014] The interface control module is an interface control module that uses a computing link protocol, so that the storage device connected to the network card and the host memory are uniformly addressed and used.

[0015] The present application provides an electronic device, comprising:

[0016] memory for storing computer programs;

[0017] A processor is used to implement the steps of the data transmission method based on the computing link protocol as described above when executing the computer program.

[0018] The present application provides a computer program product, including a computer program, which implements the steps of the data transmission method based on the computing link protocol as described above when the computer program is executed by a processor.

[0019] This application solution takes into account that the Compute Link Protocol is an innovative high-speed interconnection technology that can provide a more efficient and flexible connection method for processors, accelerators and storage devices, and can achieve more excellent performance and lower latency, thereby meeting the high bandwidth and low latency requirements of modern computing applications. However, there is currently no network card that supports the Compute Link Protocol. This application solution implements a network card based on the Compute Link Protocol. Specifically, the hardware of the network card can be implemented by an FPGA accelerator card, for example, with a storage device mounted on the outside of the FPGA and controlled by a storage control module on the FPGA.

[0020] The interface control module inside the network card is connected to the host using the computing link protocol, and can receive data sending requests sent by the host and send them to the logic module. It should be noted that since the interface control module is an interface control module that uses the computing link protocol, the storage device connected to the network card and the host memory are uniformly addressed and used. This means that during the operation of the network card of the present application scheme, there is no need for address conversion. When the data packet descriptor is obtained through the data sending request sent by the host, the data packet descriptor can be directly written to the sending queue of the storage device according to the write address of the data sending request. The operation is simple and convenient. When the data packet descriptor is subsequently used to obtain the data packet, there is no need for address conversion. The operation is simple and convenient, which is conducive to reducing transmission delay.

[0021] Furthermore, in the present invention, the process of writing the packet descriptor and triggering the network interface module (i.e., triggering the NIC doorbell) using the packet descriptor occurs simultaneously, rather than as two separate steps as in conventional solutions. Specifically, in response to a data send request from the host, the interface control module sends it to the logic module, enabling the logic module to trigger the NIC doorbell. Specifically, the logic module sends the write address of the packet descriptor to the network interface module. Simultaneously, the logic module also sends the data send request to the storage control module, enabling the storage control module to write the packet descriptor included in the data send request to the send queue of the storage device connected to the NIC. Because these two processes occur simultaneously, the latency of sending packets is significantly reduced. Finally, after receiving the write address of the packet descriptor, the network interface module, through the interface control module, retrieves the data packet stored in the storage device pointed to by the packet descriptor and outputs the data packet. Furthermore, because both the packet descriptor and the data packet are stored in the storage device mounted on the NIC, the network card of the present invention takes very little time to read the packet descriptor and the data packet, which also helps reduce the latency of the NIC sending data.

[0022] In summary, the present application solution can effectively reduce the delay in sending data by the network card. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0024] Figure 1 This is a schematic diagram of the structure of a traditional FPGA-based network card;

[0025] Figure 2A schematic diagram of the structure of a network card based on the computing link protocol provided in a specific embodiment of the present invention;

[0026] Figure 3 A schematic structural diagram of a network card based on a computing link protocol provided in another specific embodiment of the present invention;

[0027] Figure 4 A schematic diagram of a structure in which multiple sending queues are set in a storage device according to another specific embodiment of the present invention;

[0028] Figure 5 Schematic diagram of the structure of a conversion module in a specific embodiment of the present invention;

[0029] Figure 6 A schematic diagram of the structure of the connection between the network card and the host in a specific embodiment of the present invention;

[0030] Figure 7 This is a flowchart of a data transmission method based on a computing link protocol in a specific embodiment of the present invention;

[0031] Figure 8 This is a schematic structural diagram of an electronic device in a specific embodiment of the present invention;

[0032] Figure 9 This is a schematic structural diagram of a computer-readable storage medium of the present invention. DETAILED DESCRIPTION

[0033] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0034] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0035] See Figure 1 , Figure 1This diagram illustrates the architecture of a traditional FPGA-based network interface card (NIC). First, the host stores the network packet to be sent in host memory and writes the packet's address and length in host memory as a descriptor into the transmit queue (tx_queue). The NIC doorbell is then triggered using the Base Address Register (BAR), writing the descriptor's location in the transmit queue into the NIC's doorbell register. After the NIC doorbell is triggered, the PCIe terminal (PCIE_ED IP) initiates a DMA (Direct Memory Access) read operation to the host. This first reads the packet's descriptor from host memory into the FPGA. Based on the descriptor's contents, a DMA read operation is then initiated to the host, transferring the packet from host memory to the FPGA, and finally sending the packet to the network. The FPGA internally consists of two parts: a PCIe terminal with DMA functionality and the network interface card (NIC) logic. The DMA_rd_desc port of the PCIe terminal can receive the DMA read descriptor sent by the NIC, and the DMA_rd_AVMM port of the PCIe terminal can write the DMA read data to the NIC. With the development of computing systems, the requirements for high bandwidth, low latency and efficient data transmission are getting higher and higher. Figure 1 This traditional PCIe-based interconnect technology is increasingly unable to meet demand.

[0036] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Figure 2 , Figure 2 A schematic diagram of the structure of a network card based on the computing link protocol provided in a specific embodiment of the present invention may include:

[0037] The interface control module 10 is used to receive a data transmission request from the host and send it to the logic module 20;

[0038] The storage control module 30 is configured to receive a data transmission request through the logic module 20 and write the data packet descriptor carried in the data transmission request to a transmission queue of the storage device connected to the network card;

[0039] The logic module 20 is configured to send the write address of the data packet descriptor to the network interface module 40;

[0040] The network interface module 40 is configured to, after receiving the write address of the data packet descriptor, obtain the data packet stored in the storage device pointed to by the data packet descriptor through the interface control module 10 and output the data packet to the outside;

[0041] The interface control module 10 is an interface control module 10 using a computing link protocol, so that the storage device connected to the network card and the host memory are uniformly addressed and used.

[0042] In the present application, the hardware implementation of the network card can be set according to actual needs. For example, it can usually be implemented by an FPGA accelerator card. The network card is externally mounted with a storage device, which serves as an HDM (Host-managed Device Memory) and can be controlled by the network interface module 40 on the network card, that is, by the HDM_controller module on the network card. The storage device can be, for example, a DDR4 (Double Data Rate 4th Generation) storage device. In the present application, data packets and data packet descriptors are stored in the storage device.

[0043] The network card needs to use the computing link protocol to connect to the host. Due to the use of the computing link protocol, the storage device mounted on the network card and the host memory can be uniformly addressed and used. This means that during the operation of the network card of this application, there is no need to perform address conversion on the address of the data packet descriptor and the address of the data packet, which is conducive to improving efficiency and reducing the delay in the network card sending data.

[0044] The specific type of the compute link protocol can be set and adjusted according to actual needs to meet the requirements of the present application, so that the storage device connected to the network card and the host memory can be uniformly addressed and used. For example, in one specific implementation, the CXL (Compute Express Link) protocol is a high-speed interconnect technology that can provide a more efficient and flexible connection method for processors, accelerators, and storage devices. The emergence of the CXL architecture has brought revolutionary changes to computer hardware design and system optimization, achieving superior performance and lower latency, thereby meeting the urgent needs of modern computing applications for high bandwidth and low latency. Therefore, the compute link protocol described in this application can be specifically the CXL protocol, and for example, specifically the CXL type 2 mode.

[0045] The interface control module 10 is an interface terminal using the computing link protocol, which may be specifically the CXL protocol. When the type 2 mode is used, the interface control module 10 is specifically a CXL type 2 terminal IP, which may be recorded as cxl_type2_ed ip.

[0046] The interface control module 10 can receive data transmission requests from the host and send them to the logic module 20. The data packet descriptor carried in the data transmission request is the content that will be written to the transmit queue. The destination address of the data transmission request, i.e., the write address of the data packet descriptor, determines the specific location in the transmit queue where the data packet descriptor is written. The data packet descriptor typically consists of the starting address and length of the data packet, which is used to locate the storage location of the data packet.

[0047] The storage control module 30 , also known as the HDM_controller module, may receive a data transmission request through the logic module 20 , and then write the data packet descriptor carried in the data transmission request into a transmission queue of the storage device connected to the network card.

[0048] In a specific embodiment of the present invention, the storage control module 30 may be specifically configured to:

[0049] Receive the data packet descriptor carried in the data transmission request from the write data channel through the logic module 20, and receive the write address of the data packet descriptor from the write address channel;

[0050] Based on the write address of the data packet descriptor, the data packet descriptor is written into a sending queue of a storage device connected to the network card.

[0051] This embodiment takes into account that the interface control module 10 can typically be a CXL type 2 terminal IP, specifically connected to the storage control module 30 using an AXI bus port to control the reading and writing of the external storage device. In this embodiment, the storage control module 30 specifically receives the data packet descriptor carried in the data transmission request via the write data channel and receives the write address of the data packet descriptor via the write address channel.

[0052] For easier understanding, please refer to Figure 3 , Figure 3In the example, the interface control module 10 is specifically a CXL type2 terminal IP, and the port for connecting to the storage control module 30 through the logic module 20 is an AXI bus port, and three channels of the AXI bus port are shown, namely the AW channel, the W channel, and the B channel, where the AW channel is the write address channel, the W channel is the write data channel, and the B channel is the write confirmation channel. Accordingly, the write address channel AW, the write data channel W, and the write confirmation channel B of the storage control module 30 can be connected to the corresponding channels of the storage control module 30 through the logic module 20. Therefore, in this embodiment, the logic module 20 can obtain the data packet descriptor carried in the data transmission request from the write data channel, and determine the write address of the data packet descriptor from the write address channel. After the data packet descriptor and the write address of the data packet descriptor are transmitted to the storage control module 30, the storage control module 30 can write the data packet descriptor to the corresponding position of the sending queue of the storage device according to the write address. In addition, other channels of the AXI bus port, such as the read data channel, etc., do not need to pass through the logic module 20, but can be directly connected to the storage control module 30. Figure 3 It is not shown in the figure for the sake of ease of viewing.

[0053] In addition to being written to the transmit queue by the storage control module 30, the data packet descriptor also needs to be used by the logic module 20 to trigger the network interface module 40, effectively triggering the doorbell of the network interface module 40. This allows the network interface module 40 to obtain the corresponding data packet through the interface control module 10 and thus output the data packet. Furthermore, in the present application, the process of writing the data packet descriptor to the transmit queue and triggering the doorbell occur simultaneously, rather than as two separate steps as in conventional solutions. This significantly reduces the latency of transmitting data packets.

[0054] In a specific embodiment of the present invention, the logic module 20 is provided with a first register and a second register. The value in the first register is the starting physical address of the send queue of the storage device, and the value in the second register is the space size of the send queue of the storage device. The logic module 20 is specifically used to:

[0055] Based on the values ​​of the first register and the second register, it is determined whether the write address of the data packet descriptor belongs to the address range of the transmit queue of the storage device. If yes, the write address of the data packet descriptor is sent to the doorbell register in the network interface module 40.

[0056] In this implementation, the logic module 20 specifically implements address judgment based on the values ​​of the first register and the second register, thereby determining whether the doorbell needs to be triggered.

[0057] For example, in a specific scenario, the external storage device of the network card has an address space of 4GB, and the physical address range is, for example, 0x100000000 to 0x1ffffffff. The starting physical address of the sending queue is, for example, 0x100000000, and the entire sending queue occupies, for example, 0x400000 bytes of space. It can be seen that in this example, the starting physical address of the sending queue is, for example, 0x100000000, and the ending physical address is 0x1003fffff, then 0x100000000 needs to be stored in the first register and 0x400000 needs to be stored in the second register. It can also be seen that in this example, the starting physical address of the sending queue is exactly the starting physical address of the entire address space of the storage device.

[0058] For example, in a specific scenario, host software needs to send a data packet with a starting physical address of 0x101000000 and a length of 1024 bytes. The host can use (0x101000000) and (1024) as the packet descriptor for the data packet and write the packet descriptor into the transmit queue via a data send request. Furthermore, if the destination address of the data send request is 0x100001000, the logic module 20 can determine, based on the values ​​of the first register (0x100000000) and the second register (0x400000), that the write address of the packet descriptor (0x100001000) falls within the address range of the transmit queue of the memory device, i.e., the address range of 0x100000000 to 0x1003fffff. Therefore, the logic module 20 sends the write address of the packet descriptor to the doorbell register in the network interface module 40, thereby triggering the doorbell.

[0059] In addition, it can be understood that if, based on the values ​​of the first register and the second register, it is determined that the address on the AW channel does not belong to the address range of the sending queue of the storage device, it means that the data packet descriptor is not currently being written and there is no need to trigger the doorbell, that is, the logic module 20 does not need to write the doorbell register, but only needs to transmit the write address of the AW channel and the write data of the W channel from the interface control module 10 to the storage control module 30.

[0060] The storage device can be provided with multiple transmit queues. For example, in actual applications, it can support thousands of transmit queues to send data packets independently. Since multiple transmit queues are provided, in actual applications, in order to facilitate the determination of which transmit queue the data packet descriptor that currently needs to be written should be written to, these transmit queues in the storage device can be of the same size and continuously addressed. In other words, the storage device is provided with multiple transmit queues that are continuously addressed, and the storage space occupied by each transmit queue is of the same size, so that based on the write address of the data packet descriptor, the specific write location of the data packet descriptor can be determined conveniently and quickly. Figure 4 , is a structural diagram of a specific embodiment in which a plurality of sending queues are provided in a storage device, the occupied space size of each sending queue remains consistent, and the addresses of the sending queues remain continuous, that is, Figure 4 In the example, the addressing is continuous from send queue 0 to send queue 2. Figure 4 Only three sending queues are shown in the figure, and in actual applications there may be more sending queues.

[0061] In a specific embodiment of the present invention, the logic module 20 sends the write address of the data packet descriptor to the doorbell register in the network interface module 40, including:

[0062] The logic module 20 calculates the difference between the write address of the data packet descriptor and the value of the first register, determines the transmit queue number and pointer based on the difference, and sends the transmit queue number and pointer to the doorbell register in the network interface module 40;

[0063] The sending queue number indicates the number of the sending queue to which the data packet descriptor needs to be written, and the pointer indicates the position where the data packet descriptor is written into the sending queue.

[0064] This implementation method takes into account that the space occupied by each sending queue remains consistent, and the addresses of each sending queue remain continuous, forming a continuous sending queue space. Therefore, through the difference between the write address of the data packet descriptor and the value of the first register, it is possible to easily determine which specific sending queue the data packet descriptor should be written to, and the specific location of the sending queue where it should be written.

[0065] Still taking the above embodiment in which the memory device has a 4GB address space and a physical address range of 0x100000000 to 0x1ffffffff as an example, the starting physical address of the sending queue is 0x100000000 and the ending physical address is 0x1003fffff.

[0066] For example, in one scenario, 1024 transmit queues are supported, which are recorded as transmit queue 0 to transmit queue 1023. The addresses from transmit queue 0 to transmit queue 1023 are continuous. Each transmit queue supports the storage of 0x100 packet descriptors, that is, it supports the storage of 256 packet descriptors. Each packet descriptor occupies 0x10 bytes, so in this example, each transmit queue occupies 0x1000 bytes. Since there are a total of 1024 transmit queues, the entire transmit queue space needs to occupy 0x400000 bytes of space. Therefore, the starting physical address of the transmit queue is 0x100000000, and the ending physical address is 0x1003fffff.

[0067] For example, if the host software needs to write the data packet descriptor to the location of the first data packet descriptor in the send queue 1, the destination address of the data send request, that is, the write address of the data packet descriptor, needs to be 0x100001000. Figure 3 In the example, the address of the AW channel of the interface control module 10 is 0x100001000 at this time, so that after the logic module 20 receives the write address 0x100001000 of the data packet descriptor through the AW channel of the interface control module 10, the logic module 20 calculates the difference between the write address 0x100001000 of the data packet descriptor and the value 0x100000000 of the first register, and the obtained difference is 0x1000. Since the difference is less than the value 0x400000 in the second register, the doorbell needs to be triggered.

[0068] In this embodiment, when the doorbell is triggered, the sending queue number and pointer are determined based on the difference, and then the sending queue number and pointer are sent to the doorbell register in the network interface module 40.

[0069] It should be noted that when determining the transmit queue number and pointer based on the difference, the transmit queue number and pointer are determined specifically in accordance with the address rules of the transmit queue (the size of each transmit queue, and the space occupied by a single data packet descriptor in each transmit queue). In the above embodiment, after obtaining the difference, the value from the 22nd bit to the 12th bit in the difference is used as the transmit queue number, and the value from the 11th bit to the 4th bit is used as the pointer. In the above specific example, the difference is specifically 0x1000, and the value from the 22nd bit to the 12th bit is 1, that is, the determined transmit queue number is 1, and the value from the 11th bit to the 4th bit is 0, so the determined pointer is 0, so in this example, the data packet descriptor will be written to the 0th position (the first position) in transmit queue 1.

[0070] In addition, it can be understood that in this embodiment, the logic module 20 specifically writes the sending queue number and pointer to the doorbell register in the network interface module 40, which is equivalent to using the sending queue number and pointer to describe the position of the data packet descriptor in the sending queue, that is, to describe the write address of the data packet descriptor. This is because when the doorbell is usually triggered, it is triggered according to the sending queue number and pointer. Therefore, this embodiment enables the present application solution to use the usual network interface module 40 design without the need for additional adjustments to the network interface module 40, thereby improving the convenience of implementation of the present application solution.

[0071] In a specific embodiment of the present invention, the network card further includes a conversion module 50. The network interface module 40 is specifically used to:

[0072] After receiving the write address of the data packet descriptor, a first descriptor is generated and sent to the interface control module 10 through the conversion module 50, so that the interface control module 10 reads the data packet descriptor from the transmit queue of the storage device based on the first descriptor and feeds it back to the network interface module 40 through the conversion module 50;

[0073] After receiving the data packet descriptor, a second descriptor is generated and sent to the interface control module 10 through the conversion module 50, so that the interface control module 10 reads the data packet pointed to by the data packet descriptor from the transmit queue of the storage device based on the second descriptor, and feeds the data packet back to the network interface module 40;

[0074] Output the received data packets.

[0075] Among them, the source address of the first descriptor is the first address in the network interface module 40, the destination address of the first descriptor is the write address of the data packet descriptor, and the first descriptor carries the length of the data packet descriptor; the data packet descriptor includes the starting address and data packet length of the data packet stored in the storage device pointed to by the data packet descriptor; the source address of the second descriptor is the second address in the network interface module 40, the destination address of the second descriptor is the starting address of the data packet, and the second descriptor carries the length of the data packet.

[0076] In this embodiment, after the doorbell is triggered, that is, after the network interface module 40 receives the write address of the data packet descriptor, through interaction with the interface control module 10, the network interface module 40 first uses the interface control module 10 to obtain the content of the data packet descriptor, and then uses the interface control module 10 to obtain the content of the data packet, thereby outputting the data packet to the outside.

[0077] Specifically, in the example above, the write address of the packet descriptor is 0x100001000. The network interface module 40 is a NIC module, which generates a first descriptor. The destination address of the first descriptor is the write address 0x100001000 of the packet descriptor, while the source address of the first descriptor is an address in the network interface module 40, referred to as the first address, specifically set to 0x8000, for example, with a length of 0x10 bytes (i.e., the length of the packet descriptor). After generating the first descriptor, the network interface module 40 sends the first descriptor to the conversion module 50, which then sends it to the interface control module 10. The interface control module 10 reads the packet descriptor, which is 0x10 bytes long, from position 0 in the transmit queue 1 of the storage device according to the address 0x100001000, and then feeds it back to the network interface module 40 through the conversion module 50.

[0078] In a specific embodiment of the present invention, the conversion module 50 may be specifically configured to:

[0079] Sending the destination address of the first descriptor and the length of the data packet descriptor to the interface control module 10, and storing the source address of the first descriptor;

[0080] After receiving the data packet descriptor fed back by the interface control module 10, the data packet descriptor is stored in the source address of the first descriptor;

[0081] Sending the destination address and data packet length of the second descriptor to the interface control module 10 and storing the source address of the second descriptor;

[0082] After receiving the data packet fed back by the interface control module 10 , it is stored in the source address of the second descriptor.

[0083] This embodiment takes into account that the interface control module 10 only needs to use the destination address of the first descriptor and the length of the data packet descriptor to read the data packet descriptor accordingly. Therefore, the conversion module 50 only needs to send the destination address of the first descriptor and the length of the data packet descriptor to the interface control module 10, and store the source address of the first descriptor locally. Subsequently, when the conversion module 50 receives the data packet descriptor feedback from the interface control module 10, it can store the data packet descriptor to the source address of the first descriptor according to the source address of the first descriptor.

[0084] For example Figure 5The following is a schematic diagram of the structure of the conversion module 50 in a specific embodiment. The conversion module 50 is provided with a first-in, first-out storage unit (FIFO) that can be used to store the source address of the first descriptor and the source address of the second descriptor. In the above example, the conversion module 50 specifically sends the first descriptor's destination address 0x100001000 and the packet descriptor's length 0x10 bytes to the interface control module 10. Based on the first descriptor's destination address 0x100001000, the interface control module 10 reads the packet descriptor at this address from the storage device's transmit queue. The conversion module 50 stores the first descriptor's source address 0x8000 in the FIFO. When the conversion module 50 receives the packet descriptor from the interface control module 10, it reads the first descriptor's source address 0x8000 from the FIFO and writes the packet descriptor to address 0x8000 in the network interface module 40, thereby ensuring that the packet descriptor is received by the network interface module 40.

[0085] After receiving the data packet descriptor, the network interface module 40 generates a second descriptor and sends it to the interface control module 10 through the conversion module 50 , so that the interface control module 10 reads the corresponding data packet based on the second descriptor and feeds the data packet back to the network interface module 40 .

[0086] In the example above, the contents of the data packet descriptor are (0x101000000) and (1024). Based on the contents of the data packet descriptor, the network interface module 40 generates a second descriptor. The destination address of the second descriptor is the starting address of the data packet, 0x101000000, and the source address of the second descriptor is the address in the network interface module 40, referred to as the second address, specifically set to 0x4000, with a length of 1024 bytes (i.e., the length of the data packet). After generating the second descriptor, the network interface module 40 sends the second descriptor to the conversion module 50, which then sends it to the interface control module 10. The interface control module 10 reads the 1024-byte data packet from the storage device according to the address 0x101000000, and then feeds it back to the network interface module 40 through the conversion module 50.

[0087] In a specific embodiment, considering that the interface control module 10 only needs to use the destination address of the second descriptor and the length of the data packet to read the data packet accordingly, the conversion module 50 only needs to send the destination address of the second descriptor and the length of the data packet to the interface control module 10, and store the source address of the second descriptor locally. Subsequently, when the conversion module 50 receives the data packet feedback from the interface control module 10, it can store the data packet at the source address of the second descriptor according to the source address of the second descriptor.

[0088] exist Figure 5 In the example, the conversion module 50 is provided with a first-in, first-out storage unit (FIFO), which can be used to store the source address of the first descriptor and the source address of the second descriptor. In the above example, the conversion module 50 specifically sends the destination address 0x101000000 and length 1024 of the second descriptor to the interface control module 10, so that the interface control module 10 reads 1024 bytes of data from the storage device based on the destination address 0x101000000 of the second descriptor as the read data packet. The source address 0x4000 of the second descriptor is then stored in the FIFO. When the conversion module 50 receives the data packet feedback from the interface control module 10, it can read the source address 0x4000 of the second descriptor from the FIFO and write the data packet to the address 0x4000 of the network interface module 40, so that the data packet is received by the network interface module 40.

[0089] In a specific embodiment of the present invention, the conversion module 50 is provided with a third register and a fourth register. The value in the third register is the starting physical address of the storage device, and the value in the fourth register is the space size of the storage device. The conversion module 50 is further configured to:

[0090] determining, based on the values ​​of the third register and the fourth register, whether the destination address of the first descriptor falls within the address range of the storage device;

[0091] If yes, outputting a first signal indicating that the memory device needs to be read to the interface control module 10;

[0092] If not, outputting a second signal indicating that the host memory needs to be read to the interface control module 10;

[0093] determining, based on the values ​​of the third register and the fourth register, whether the destination address of the second descriptor falls within the address range of the storage device;

[0094] If yes, output a first signal to the interface control module 10;

[0095] If not, a second signal is output to the interface control module 10 .

[0096] In this embodiment, the conversion module 50 can also determine whether the destination address of the first descriptor belongs to the address range of the storage device, and can also determine whether the destination address of the second descriptor belongs to the address range of the storage device. Figure 5 In the example, the conversion module 50 is specifically provided with a comparator, and the judgment can be achieved through the comparator.

[0097] For example, in the above example, the physical address range of the storage device is 0x100000000 to 0x1ffffffff, then the value in the third register is the starting physical address of the storage device 0x100000000, and the value in the fourth register is the space size of the storage device 0x100000000. In the above example, the destination address of the first descriptor is the write address 0x100001000 of the data packet descriptor. It can be seen that the destination address of the first descriptor belongs to the address range of the storage device. In this embodiment, at this time, a first signal indicating that the storage device needs to be read will be output to the interface control module 10. Conversely, if it does not belong to the address range of the storage device, in this embodiment, at this time, a second signal indicating that the host memory needs to be read will be output to the interface control module 10. The above is explained using the first descriptor as an example. The judgment process principle of the second descriptor is the same as this and will not be repeated.

[0098] It can be seen that in this embodiment, the output of the first signal and the second signal can enable the interface control module 10 to effectively determine whether it is currently necessary to read the storage device or the host memory.

[0099] Furthermore, in a specific embodiment of the present invention, outputting the first signal indicating that the memory device needs to be read to the interface control module 10 may include:

[0100] A first signal indicating that the memory device needs to be read is output to the interface control module 10 through a read address receiving channel of the AEIB bus provided by the interface control module 10 .

[0101] This embodiment takes into account that the bus provided by the interface control module 10 is usually an AXI bus, for example Figure 3 In a specific embodiment, the interface control module 10 is connected to the conversion module 50 via an AXI bus. The AR channel of the AXI bus can be connected to the read descriptor interface (DMA_rd_desc) of the network interface module 40 through the conversion module 50 to receive the first descriptor and the second descriptor. The R channel can also be connected to the read data interface (DMA_rd_AVMM) of the network interface module 40 through the conversion module 50 to feed back the data packet descriptor and the data packet to the network interface module 40.

[0102] In this embodiment, the first signal indicating that the memory device needs to be read is output to the interface control module 10 through the read address receiving channel of the AXI bus provided by the interface control module 10, that is, the AR channel. Figure 5 In a specific implementation manner, the transmission of the first signal or the second signal is realized through the ARuser signal line of the AR channel, that is, the read address user-defined signal. When the 5th position of the ARuser signal is 1, it is the first signal, indicating that the storage device needs to be read at this time, and when the 5th position of the ARuser signal is 0, it is the second signal, indicating that the host memory needs to be read at this time. Figure 5 In a specific implementation manner, the address signal of the AR channel can be used to transmit the address.

[0103] In a specific embodiment of the present invention, after receiving the data packet descriptor fed back by the interface control module 10, storing the source address of the first descriptor includes:

[0104] The data packet descriptor fed back by the receiving interface control module 10 is converted into a bus format supported by the network interface module 40 and stored in the source address of the first descriptor;

[0105] After receiving the data packet fed back by the interface control module 10, the source address stored in the second descriptor includes:

[0106] After receiving the data packet fed back by the interface control module 10 , the data packet is converted into a bus format supported by the network interface module 40 and then fed back to the network interface module 40 .

[0107] This embodiment takes into account that the interface control module 10 usually uses the AXI bus, which is different from the one used by the network interface module 40. For example, the network interface module 40 usually uses the AVMM bus. In order to improve the convenience of implementation of the solution of this application and reduce the adjustment of the interface control module 10 and the network interface module 40, this embodiment takes into account that the bus format conversion can be achieved through the conversion module 50. Specifically, after receiving the data packet descriptor fed back by the interface control module 10, the conversion module 50 can perform bus format conversion, that is, convert it into a bus format supported by the network interface module 40, and then store the data packet descriptor to the source address of the first descriptor. Similarly, for the data packet fed back by the interface control module 10, the conversion module 50 can perform bus format conversion, that is, convert it into a bus format supported by the network interface module 40, and then store the data packet to the source address of the second descriptor.

[0108] exist Figure 5 In the example, the conversion module 50 is provided with a conversion unit, which is connected to the R channel of the AXI bus provided by the interface control module 10. Figure 5 It is recorded as the R channel of AXI, and after the bus format conversion is performed on the data, the data output to the network interface module 40 is the data in the AVMM bus format, so as to support the bus format requirements of the network interface module 40.

[0109] In a specific embodiment of the present invention, the network interface module 40 has multiple Ethernet optical ports for outputting data packets, thereby effectively improving data output efficiency. The network card can mount multiple storage devices to provide sufficient storage space. Figure 6 , is a structural diagram of the connection between the network card and the host in a specific implementation method, Figure 6 In the network card, the network card is connected to the central processing unit in the host through the CXL protocol, and has 4 DIMM memory slots, so that 4 storage devices can be placed. For example, in one case, a maximum of 256GB DDR4 storage device can be installed. Figure 6 The network card is implemented using FPGA and shows two 100G Ethernet optical ports.

[0110] In a specific embodiment of the present invention, the network interface module 40 may also be used to:

[0111] After the data packet is successfully output, a confirmation message indicating the successful output is fed back to the host through the interface control module 10;

[0112] When the data packet output fails, the interface control module 10 feeds back a prompt message indicating the output failure to the host so that the host initiates retransmission of the data packet.

[0113] In this embodiment, the network interface module 40 is provided with a fault-tolerant retransmission mechanism. After the data packet is successfully output, confirmation information indicating the successful output can be fed back to the host through the interface control module 10. Correspondingly, when the data packet output fails, prompt information indicating the output failure is fed back to the host through the interface control module 10, so that the host can initiate retransmission of the data packet.

[0114] The present application solution takes into account that the Compute Link Protocol is an innovative high-speed interconnection technology that can provide a more efficient and flexible connection method for processors, accelerators and storage devices, and can achieve more excellent performance and lower latency, thereby meeting the high bandwidth and low latency requirements of modern computing applications. However, there is currently no network card that supports the Compute Link Protocol. The present application solution implements a network card based on the Compute Link Protocol. Specifically, the hardware of the network card can be implemented by an FPGA accelerator card, for example, with a storage device mounted on the outside of the FPGA, and can be controlled by the storage control module 30 on the FPGA.

[0115] The interface control module 10 inside the network card is connected to the host using a computing link protocol, and can receive a data sending request sent by the host and send it to the logic module 20. It should be noted that since the interface control module 10 is an interface control module 10 using a computing link protocol, the storage device connected to the network card and the host memory are uniformly addressed and used. This means that during the operation of the network card of the present application, there is no need for address conversion. When a data packet descriptor is obtained through a data sending request sent by the host, the data packet descriptor can be directly written to the sending queue of the storage device according to the write address of the data sending request. The operation is simple and convenient. When the data packet descriptor is subsequently used to obtain a data packet, there is no need for address conversion. The operation is simple and convenient, which is conducive to reducing transmission delay.

[0116] Furthermore, in the present solution, the process of writing the packet descriptor and triggering the network interface module 40 (i.e., triggering the NIC doorbell) using the packet descriptor are performed simultaneously, rather than as two separate steps as in conventional solutions. Specifically, in response to a data send request from the host, the interface control module 10 transmits it to the logic module 20, enabling the logic module 20 to trigger the NIC doorbell. Specifically, the logic module 20 transmits the write address of the packet descriptor to the network interface module 40. Simultaneously, the logic module 20 also transmits the data send request to the storage control module 30, instructing the storage control module 30 to write the packet descriptor included in the data send request to the send queue of the storage device connected to the NIC. Because these two processes occur simultaneously, the latency of sending packets is significantly reduced. Finally, after receiving the write address of the packet descriptor, the network interface module 40, through the interface control module 10, retrieves the data packet stored in the storage device pointed to by the packet descriptor and outputs the data packet. In addition, since the data packet descriptor and data packet are both stored in a storage device mounted on the network card, the network card of the present application takes a very short time to read the data packet descriptor and data packet, which is also beneficial to reducing the delay in the network card sending data.

[0117] In summary, the present application solution can effectively reduce the delay in sending data by the network card.

[0118] Corresponding to the above network card embodiment, the embodiment of the present invention further provides a data transmission method based on the computing link protocol, which can be referenced in conjunction with the above. The data transmission method based on the computing link protocol can be applied to the interface control module in the network card based on the computing link protocol in any of the above embodiments, which can be referenced in conjunction with the above embodiment. Figure 7 , including the following steps:

[0119] Step S701: Receive a data sending request sent by the host and send it to the logic module, so that the storage control module receives the data sending request through the logic module, and writes the data packet descriptor carried in the data sending request to the sending queue of the storage device connected to the network card, and enables the logic module to send the write address of the data packet descriptor to the network interface module.

[0120] Step S702: After the network interface module receives the write address of the data packet descriptor, it obtains the data packet stored in the storage device pointed to by the data packet descriptor through communication with the network interface module, and sends the data packet to the network interface module so that the network interface module outputs the data packet.

[0121] The interface control module is an interface control module that uses a computing link protocol, so that the storage device connected to the network card and the host memory are uniformly addressed and used.

[0122] Corresponding to the above embodiments, embodiments of the present invention further provide an electronic device, a computer-readable storage medium, and a computer program product, which can be referred to in correspondence with the above.

[0123] See also Figure 8 As shown, the electronic device may include:

[0124] Memory 801, used for storing computer programs;

[0125] The processor 802 is configured to execute a computer program to implement the steps of the data transmission method based on the computing link protocol in any of the above embodiments.

[0126] The computer program product includes a computer program / instruction, which, when executed by a processor, implements the steps of the data transmission method based on the computing link protocol in any of the above embodiments.

[0127] See Figure 9 The computer-readable storage medium 90 stores a computer program 91. When executed by a processor, the computer program 91 implements the steps of the data transmission method based on the computing link protocol in any of the above-described embodiments. The computer-readable storage medium 90 herein includes random access memory (RAM), internal memory, read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, removable disks, or any other form of storage medium known in the art.

[0128] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0129] The above is a detailed introduction to a network card, data transmission method, device and product based on the computing link protocol provided by this application. Specific examples are used herein to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the scope of protection of this application.

Claims

1. A network card based on a computing link protocol, characterized in that: include: The interface control module is used to receive a data transmission request from the host and send it to the logic module; a storage control module, configured to receive the data transmission request through the logic module, and write the data packet descriptor carried in the data transmission request into a transmission queue of a storage device connected to the network card; The logic module is configured to send the write address of the data packet descriptor to the network interface module; The network interface module is configured to, after receiving the write address of the data packet descriptor, obtain the data packet stored in the storage device pointed to by the data packet descriptor through the interface control module, and output the data packet to the outside; Wherein, the interface control module is an interface control module using a computing link protocol, so that the storage device connected to the network card and the host memory are uniformly addressed and used; The network card also includes a conversion module; The network interface module is specifically used for: After receiving the write address of the data packet descriptor, generating a first descriptor and sending the first descriptor to the interface control module through the conversion module, so that the interface control module reads the data packet descriptor from the transmit queue of the storage device based on the first descriptor and feeds the first descriptor back to the network interface module through the conversion module; After receiving the data packet descriptor, generating a second descriptor and sending the second descriptor to the interface control module through the conversion module, so that the interface control module reads the data packet pointed to by the data packet descriptor from the transmit queue of the storage device based on the second descriptor, and feeds the data packet back to the network interface module; Outputting the received data packet externally; The source address of the first descriptor is a first address in the network interface module, the destination address of the first descriptor is a write address of the data packet descriptor, and the first descriptor carries the length of the data packet descriptor; the data packet descriptor includes the starting address and data packet length of the data packet stored in the storage device pointed to by the data packet descriptor; the source address of the second descriptor is a second address in the network interface module, the destination address of the second descriptor is the starting address of the data packet, and the second descriptor carries the length of the data packet.

2. The network card based on the computing link protocol according to claim 1, characterized in that: The logic module is provided with a first register and a second register, the value in the first register is the starting physical address of the sending queue of the storage device, and the value in the second register is the space size of the sending queue of the storage device; The logic module is specifically used for: determining, based on the values ​​of the first register and the second register, whether the write address of the data packet descriptor falls within the address range of the transmit queue of the storage device; If yes, the write address of the data packet descriptor is sent to the doorbell register in the network interface module.

3. The network card based on the computing link protocol according to claim 2, characterized in that: The storage device is provided with a plurality of continuously addressed sending queues, and the storage space occupied by each sending queue is consistent in size.

4. The network card based on the computing link protocol according to claim 3, characterized in that: Sending the write address of the data packet descriptor to the doorbell register in the network interface module includes: Calculating a difference between a write address of the data packet descriptor and a value of the first register, determining a send queue number and a pointer based on the difference, and sending the send queue number and the pointer to a doorbell register in a network interface module; The sending queue number indicates the number of the sending queue to which the data packet descriptor needs to be written, and the pointer indicates the position where the data packet descriptor is written into the sending queue.

5. The network card based on the computing link protocol according to claim 1, characterized in that: The storage control module is specifically used for: Receiving, through the logic module, a data packet descriptor carried in the data sending request from a write data channel, and receiving a write address of the data packet descriptor from a write address channel; Based on the write address of the data packet descriptor, the data packet descriptor is written into a sending queue of a storage device connected to the network card.

6. The network card based on the computing link protocol according to claim 1, characterized in that: The network interface module is further configured to: After the data packet is successfully output, feedback confirmation information indicating successful output is sent to the host through the interface control module; When the data packet fails to be output, prompt information indicating the output failure is fed back to the host through the interface control module so that the host initiates retransmission of the data packet.

7. The network card based on the computing link protocol according to claim 6, characterized in that: The conversion module is specifically used for: sending the destination address of the first descriptor and the length of the data packet descriptor to the interface control module, and storing the source address of the first descriptor; After receiving the data packet descriptor fed back by the interface control module, storing it in the source address of the first descriptor; Sending the destination address of the second descriptor and the data packet length to the interface control module, and storing the source address of the second descriptor; After receiving the data packet fed back by the interface control module, the data packet is stored in the source address of the second descriptor.

8. The network card based on the computing link protocol according to claim 7, characterized in that: The conversion module is provided with a first-in first-out storage unit, and the first-in first-out storage unit is used to store the source address of the first descriptor and the source address of the second descriptor.

9. The network card based on the computing link protocol according to claim 7, characterized in that: The conversion module is provided with a third register and a fourth register, the value in the third register is the starting physical address of the storage device, and the value in the fourth register is the space size of the storage device. The conversion module is further configured to: determining, based on the values ​​of the third register and the fourth register, whether the destination address of the first descriptor falls within the address range of the storage device; If yes, outputting a first signal indicating that the memory device needs to be read to the interface control module; If not, outputting a second signal indicating that the host memory needs to be read to the interface control module; determining, based on the values ​​of the third register and the fourth register, whether the destination address of the second descriptor falls within the address range of the storage device; If yes, outputting the first signal to the interface control module; If not, the second signal is output to the interface control module.

10. The network card based on the computing link protocol according to claim 9, characterized in that: Outputting a first signal indicating that the memory device needs to be read to the interface control module includes: A first signal indicating that the memory device needs to be read is output to the interface control module through a read address receiving channel of the advanced extensible interface bus provided by the interface control module.

11. The network card based on the computing link protocol according to claim 7, characterized in that: After receiving the data packet descriptor fed back by the interface control module, storing it in the source address of the first descriptor includes: receiving the data packet descriptor fed back by the interface control module, converting the data packet descriptor into a bus format supported by the network interface module, and storing the data packet descriptor at the source address of the first descriptor; After receiving the data packet fed back by the interface control module, storing the data packet in the source address of the second descriptor includes: After receiving the data packet fed back by the interface control module and converting it into a bus format supported by the network interface module, the data packet is fed back to the network interface module.

12. A data transmission method based on a computing link protocol, characterized in that: An interface control module applied to a network card based on a computing link protocol according to any one of claims 1 to 11, comprising: receiving a data transmission request sent by a host and sending the request to a logic module, so that the storage control module receives the data transmission request through the logic module, writes a data packet descriptor carried in the data transmission request to a transmission queue of a storage device connected to the network card, and sends a write address of the data packet descriptor to the network interface module; After the network interface module receives the write address of the data packet descriptor, the network interface module obtains the data packet stored in the storage device pointed to by the data packet descriptor through communication with the network interface module, and sends the data packet to the network interface module, so that the network interface module outputs the data packet externally; Wherein, the interface control module is an interface control module using a computing link protocol, so that the storage device connected to the network card and the host memory are uniformly addressed and used; The network card also includes a conversion module; The network interface module is specifically used for: After receiving the write address of the data packet descriptor, generating a first descriptor and sending the first descriptor to the interface control module through the conversion module, so that the interface control module reads the data packet descriptor from the transmit queue of the storage device based on the first descriptor and feeds the first descriptor back to the network interface module through the conversion module; After receiving the data packet descriptor, generating a second descriptor and sending the second descriptor to the interface control module through the conversion module, so that the interface control module reads the data packet pointed to by the data packet descriptor from the transmit queue of the storage device based on the second descriptor, and feeds the data packet back to the network interface module; Outputting the received data packet externally; The source address of the first descriptor is a first address in the network interface module, the destination address of the first descriptor is a write address of the data packet descriptor, and the first descriptor carries the length of the data packet descriptor; the data packet descriptor includes the starting address and data packet length of the data packet stored in the storage device pointed to by the data packet descriptor; the source address of the second descriptor is a second address in the network interface module, the destination address of the second descriptor is the starting address of the data packet, and the second descriptor carries the length of the data packet.

13. An electronic device, characterized in that: include: memory for storing computer programs; A processor is used to implement the steps of the data transmission method based on the computing link protocol as claimed in claim 12 when executing the computer program.

14. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the data transmission method based on the computing link protocol as claimed in claim 12 are implemented.

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