Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel comprises a substrate, the substrate comprises a display area and a functional area, the functional area comprises a light-transmitting area, the light-transmitting area comprises a plurality of pixel units, the pixel units can emit white light, each pixel unit comprises at least one sub-pixel, each pixel unit further comprises a cathode, and the cathode is arranged on the display area. The positive projections of the multiple cathodes on the substrate are separated from one another, the positive projection of the effective light-emitting area of each sub-pixel on the substrate is located in the range of the positive projection of the cathode of the corresponding pixel unit on the substrate, the display panel further comprises a connecting structure, the connecting structure and the cathodes are arranged on the same layer, and the connecting structure is located in the range of the positive projection of the effective light-emitting area of each sub-pixel on the substrate. And different cathodes are connected through the connecting structures. The opening area of the cathode layer in the light-transmitting region is increased, and the transparency of the light-transmitting region is improved.

Description

[0001] This application is a divisional application of the patent application with the application date of February 22, 2021, the application number of 202180000267.9, and the patent title of "A display panel, a display device, and a method for manufacturing a display panel". Technical Field

[0002] The present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device. Background Art

[0003] OLED (Organic light-emitting diode) display technology has advantages such as high brightness, low power consumption, fast response, and high clarity. With the development and maturity of OLED (Organic light-emitting diode) display technology, OLED display devices are becoming increasingly popular among users. Summary of the Invention

[0004] In a first aspect, embodiments of the present disclosure provide a display panel, including a substrate. The substrate includes a display area and a functional area. The display area is located on one side of the functional area. The functional area includes a light-transmitting area. The light-transmitting area includes a plurality of pixel units. Each of the plurality of pixel units includes at least one sub-pixel. Each pixel unit further includes a cathode. The orthographic projections of the plurality of cathodes on the substrate are separated from each other. The orthographic projection of the effective light-emitting area of each sub-pixel on the substrate is within the orthographic projection of the cathode of the corresponding pixel unit on the substrate. The display panel further includes a connection structure. The plurality of cathodes are connected through the connection structure. The plurality of cathodes and the connection structure in the light-transmitting area form a mesh structure. The mesh structure includes a plurality of openings. Each opening is surrounded by the cathode and the connection structure. The plurality of cathodes are configured to provide the same common voltage.

[0005] In some embodiments, the functional area further includes a transition area and a pixel circuit area. The pixel circuit area is disposed around the light-transmitting area. The transition area is disposed between the pixel circuit area and the light-transmitting area. The transition area and the pixel circuit area share a cathode. The orthographic projection of the cathode on the substrate in the part of the transition area and the pixel circuit area is a solid figure.

[0006] In some embodiments, the display panel further includes a plurality of winding lines. The winding lines extend along the edge of the light-transmitting area. The winding lines are connected to the pixel circuits located in the pixel circuit area through the trace lines located in the transition area.

[0007] In some of these embodiments, it further includes a first gate layer located between the semiconductor layer and the anode layer. The first gate layer includes a plurality of first connection lines located in the transition region. Both ends of each first connection line among the plurality of first connection lines are respectively connected to the corresponding winding. The dimension of each first connection line in the second direction is greater than the dimension in the first direction. The first direction and the second direction intersect. The plurality of first connection lines are arranged along the first direction and are parallel to each other.

[0008] In some of these embodiments, it further includes a semiconductor layer. In the transition region, the semiconductor layer includes a plurality of redundant patterns. The redundant patterns are spaced apart and arranged in an array. The orthographic projection of the first connection line on the substrate is separated from the orthographic projection of the redundant pattern on the substrate.

[0009] In some of these embodiments, it further includes a second gate layer located between the first gate layer and the anode layer. The second gate layer includes a plurality of second connection lines located in the transition region. Both ends of each second connection line among the plurality of second connection lines are respectively connected to the corresponding winding. The dimension of the second connection line in the second direction is greater than the dimension in the first direction. The orthographic projection of the second connection line on the substrate is separated from the orthographic projection of the redundant pattern on the substrate and the orthographic projection of the first connection line on the substrate.

[0010] In some of these embodiments, the ratio of the distance between adjacent two first connection lines to the distance between adjacent two second connection lines is 0.8 - 1.2.

[0011] In some of these embodiments, the sub - pixels corresponding to each pixel unit include two green sub - pixels, one red sub - pixel and one blue sub - pixel. The two green sub - pixels are arranged along the second direction. The effective light - emitting region of the blue sub - pixel is located between the effective light - emitting regions of the two green sub - pixels in the second direction.

[0012] In some of these embodiments, the center lines of the effective light - emitting regions of the two green sub - pixels along the second direction approximately coincide. The effective light - emitting regions of the blue sub - pixel and the red sub - pixel are located on the same side of the center line.

[0013] In some of these embodiments, the orthographic projection of the edge of the cathode on the substrate is separated from the orthographic projection of the effective light - emitting region of the corresponding sub - pixel on the substrate, and the edge of the cathode overlaps with the orthographic projection of the anode of the corresponding sub - pixel on the substrate.

[0014] In some of these embodiments, the orthographic projection of the anode of the sub - pixels included in each pixel unit on the substrate is located within the orthographic projection of the cathode of the corresponding pixel unit on the substrate.

[0015] In some embodiments, the edge of the anode's orthographic projection on the substrate coincides with the edge portion of the corresponding cathode's orthographic projection on the substrate.

[0016] In some embodiments, in the region outside the overlapping region of the anode's orthographic projection on the substrate and the corresponding cathode's orthographic projection on the substrate, the orthographic projection of the cathode edge on the substrate extends linearly.

[0017] In some embodiments, the edges of the cathode are all chamfered, and the chamfer of the cathode edge is greater than 30 degrees.

[0018] In some embodiments, the connection structure is a transparent conductive material.

[0019] In some embodiments, the material of the conductive connection structure is indium tin oxide.

[0020] In some embodiments, there is also an interlayer insulating layer located between the second gate layer and the anode layer. In the transition region, the interlayer insulating layer includes a plurality of vias, and the orthographic projection of each via on the substrate overlaps with the orthographic projection of one of the redundant patterns on the substrate.

[0021] In some embodiments, there is also a first metal layer located between the interlayer insulating layer and the anode layer. In the transition region, the first metal layer includes a plurality of third jumper lines. The dimension of the third jumper line in the first direction is greater than the dimension in the second direction. The included angle between the orthographic projection of the third jumper line on the substrate and the orthographic projection of the first jumper line on the substrate is 80 - 100 degrees, and the orthographic projection of the third jumper line on the substrate is separated from the orthographic projection of the redundant pattern on the substrate.

[0022] In some embodiments, there is also a transparent wire layer located between the first metal layer and the anode layer. The transparent wire layer includes a transparent trace extending along the first direction and a first redundant trace. The transparent trace and the first redundant trace are separated. The transparent wire layer also includes a plurality of second redundant traces extending along the second direction.

[0023] In some embodiments, each anode is connected to a transparent trace through an anode hole. The transparent trace is connected to a pixel circuit disposed in the pixel circuit region, and the first redundant trace and the second redundant trace are connected.

[0024] In a second aspect, the present application provides a display device, including the display panel according to any one of the first aspect, and a screen - under camera is disposed in the light - transmissive area.

[0025] Each pixel unit in the light-transmitting area of the embodiments of the present disclosure includes a cathode. The orthographic projections of multiple cathodes on the substrate are separated from each other. The orthographic projection of the effective light-emitting area of each sub-pixel on the substrate is located within the orthographic projection of the cathode of the corresponding pixel unit on the substrate. The display panel further includes a connection structure, which is disposed on the same layer as the cathode, and different cathodes are connected through the connection structure. In this way, the embodiments of the present disclosure increase the opening area of the cathode layer in the light-transmitting area, which helps to improve the transparency of the light-transmitting area. Description of the Drawings

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings required for the description of the embodiments of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0027] Figure 1 It is a schematic structural diagram of a display substrate in an embodiment of the present disclosure;

[0028] Figure 2 It is a schematic stacked diagram of an anode and a cathode in an embodiment of the present disclosure;

[0029] Figure 3 It is a schematic stacked diagram of an anode and a cathode in another embodiment of the present disclosure;

[0030] Figure 4 It is a schematic stacked diagram of an anode and a cathode in another embodiment of the present disclosure;

[0031] Figure 5 It is a schematic stacked diagram of an anode and a cathode in another embodiment of the present disclosure;

[0032] Figure 6 It is a schematic stacked diagram of an anode and a cathode in another embodiment of the present disclosure;

[0033] Figure 7 It is a schematic stacked diagram of an anode and a cathode in another embodiment of the present disclosure;

[0034] Figure 8 It is a schematic stacked diagram of an anode and a cathode in another embodiment of the present disclosure;

[0035] Figure 9 It is a schematic stacked diagram of an anode and a cathode in another embodiment of the present disclosure;

[0036] Figure 10 It is a schematic connection diagram of a cathode and a connection structure in an embodiment of the present disclosure;

[0037] Figure 11Schematic diagram of the stack of the anode and the cathode in another embodiment of the present disclosure;

[0038] Figure 12 is Figure 11 Schematic diagram of the connection between the cathode and the trace in the illustrated embodiment;

[0039] Figure 13 Schematic diagram of the structure of the semiconductor layer in an embodiment of the present disclosure;

[0040] Figure 14 Schematic diagram of the stack of the semiconductor layer and the first gate layer in an embodiment of the present disclosure;

[0041] Figure 15 Schematic diagram of the stack of the semiconductor layer, the first gate layer and the second gate layer in an embodiment of the present disclosure;

[0042] Figure 16 Schematic diagram of the stack of the semiconductor layer, the first gate layer and the second gate layer in an embodiment of the present disclosure;

[0043] Figure 17 Schematic diagram of the stack of the semiconductor layer, the first gate layer, the second gate layer and the first metal layer in an embodiment of the present disclosure;

[0044] Figure 18 Schematic diagram of the stack of the semiconductor layer, the first gate layer, the second gate layer, the first metal layer and the first planarization layer in an embodiment of the present disclosure;

[0045] Figure 19 Schematic diagram of the stack of the semiconductor layer, the first gate layer, the second gate layer, the first metal layer, the first planarization layer and the transparent trace in an embodiment of the present disclosure;

[0046] Figure 20 Schematic diagram of the stack of the semiconductor layer, the first gate layer, the second gate layer, the first metal layer, the first planarization layer, the transparent trace, the second planarization layer in an embodiment of the present disclosure;

[0047] Figure 21 Schematic diagram of the stack of the semiconductor layer, the first gate layer, the second gate layer, the first metal layer, the first planarization layer, the transparent trace, the second planarization layer and the anode in an embodiment of the present disclosure;

[0048] Figure 22 Schematic diagram of the stack of the semiconductor layer, the first gate layer, the second gate layer, the first metal layer, the first planarization layer, the transparent trace, the second planarization layer, the anode and the pixel defining layer in an embodiment of the present disclosure;

[0049] Figure 23 Schematic diagram of the pixel structure in the light-transmitting region in an embodiment of the present disclosure. Detailed implementation manners

[0050] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without making creative efforts belong to the scope of protection of the present disclosure.

[0051] The present disclosure provides a display panel.

[0052] As Figure 1 shown, in one embodiment, the display panel includes a substrate, and the substrate includes a display area 10. In some of these embodiments, the display area 10 includes a plurality of pixel units. The specific structure of the display area 10 may refer to the setting of the display area 10 of the display panel in the related art and will not be elaborated here.

[0053] The substrate further includes a functional area, and the functional area includes a light-transmitting area 11. The light-transmitting area 11 has higher transparency relative to the display area 10 so as to provide for the arrangement of other components corresponding to the light-transmitting area 11.

[0054] Exemplarily, an under-screen camera may be provided in the light-transmitting area 11. Correspondingly, in this embodiment, the light-transmitting area 11 is set to be circular or approximately circular to adapt to the shape of the camera. Since the light-transmitting area 11 has higher transparency, it is helpful to improve the imaging effect. Obviously, the application scope of the light-transmitting area 11 is not limited thereto. For example, it can also be applied to transparent display devices, etc., and will not be further limited here.

[0055] The light-transmitting area 11 includes a plurality of pixel units, and the pixel units are capable of emitting white light. Each pixel unit includes at least one sub-pixel. Please continue to refer to Figure 1 , and each pixel unit further includes a cathode 101. The orthographic projections of the plurality of cathodes 101 on the substrate are separated from each other.

[0056] The orthographic projection of the effective light-emitting area of each sub-pixel on the substrate is within the orthographic projection of the cathode 101 of the corresponding pixel unit on the substrate. As Figure 10 shown, the display panel further includes a connection structure 101A. The connection structure 101A is provided on the same layer as the cathode 101, and different cathodes 101 are connected through the connection structure 101A.

[0057] The light-emitting unit of the sub-pixel includes a cathode 101, a light-emitting layer, and an anode 102 that are sequentially stacked. More specifically, in the direction from the anode 102 to the cathode 101, between the anode 102 and the cathode 101, there may be a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer that are sequentially stacked. In some embodiments, an electron blocking layer may be further provided between the hole transport layer and the light-emitting layer, and a hole blocking layer may be further provided between the light-emitting layer and the electron transport layer. It should be understood that, generally, in order to ensure the display effect, the injected electrons are excessive. Generally speaking, an electron blocking layer needs to be provided, and the hole blocking layer can be omitted.

[0058] It should be understood that the cathode 101 of the light-emitting unit is usually a whole-surface structure. Please refer to Figure 1 , for example, in the display area 10, the anode 102 of the light-emitting unit is patterned, while the cathode 101 of the light-emitting unit is a whole-surface structure. In other words, in the display area 10, the cathode 101 is not patterned. The cathode 101 not only covers the anode 102 but also covers the area outside the anode 102. The whole-surface cathode 101 has a certain light-blocking effect on the light, affecting the light transmittance of the structure.

[0059] In this embodiment, in the light-transmitting area 11, the cathode layer is composed of a plurality of independent cathodes 101 obtained by patterning. Please continue to refer to Figure 1 , in the light-transmitting area 11, the black-filled pattern represents the stacked structure of the cathode 101 and the anode 102, that is, the cathode 101 covers the area where the anode 102 is located, and other cathode materials are removed to a certain extent to reduce the light blocking, so as to improve the transparency of the light-transmitting area 11. As Figure 10 shown, the cathodes 101 are electrically connected through the connection structure 101A to provide the same common voltage to form a common electrode.

[0060] In this way, in the embodiment of the present disclosure, by controlling that the positive projection of the effective light-emitting area of each sub-pixel in the light-transmitting area 11 on the substrate is within the positive projection of the cathode 101 of the corresponding pixel unit on the substrate, the normal operation of the light-emitting unit is not affected. At the same time, since the cathode layer is composed of a plurality of cathodes 101, in other areas, due to the absence of cathode materials, the opening area of the cathode 101 layer in the light-transmitting area 11 is increased, which helps to improve the transparency of the light-transmitting area 11.

[0061] In some of these embodiments, the orthographic projection of the edge of the cathode 101 on the substrate is separated from the orthographic projection of the effective light-emitting area of the corresponding sub-pixel on the substrate, and the edge of the cathode 101 overlaps with the orthographic projection of the anode 102 of the corresponding sub-pixel on the substrate, avoiding occupying more space. In this way, while ensuring the display effect, it helps to increase the opening area of the cathode 101 and improve the light transmittance.

[0062] In some of these embodiments, the orthographic projection of the anode 102 of the sub-pixels included in the pixel unit on the substrate is located within the orthographic projection of the cathode 101 of the pixel unit on the substrate. It can be understood that the multiple sub-pixels of each pixel unit are arranged corresponding to the same cathode 101, and the positions of the multiple sub-pixels of the same pixel unit are relatively close, which helps to increase the opening area of the cathode 101 and improve the light transmittance.

[0063] As Figures 2 to 9 shown, in this embodiment, the sub-pixels of each pixel can be arranged in different ways. Correspondingly, the anodes 102 of the sub-pixels are arranged in different ways. For different arrangements, the cathode 101 of each sub-pixel of each pixel unit is the effective light-emitting area of the pixel, improving the applicability to different types of display substrates.

[0064] In some of these embodiments, the orthographic projection of the edge of the anode 102 on the substrate coincides with a part of the edge of the orthographic projection of the corresponding cathode 101 on the substrate.

[0065] It can be understood that when observing along the direction perpendicular to the substrate, a part of the edge of the cathode 101 of a pixel unit overlaps with a part of the edge of the anode 102 of the sub-pixels included in the pixel unit. In this way, since the orthographic projection of the anode 102 on the substrate is within the range of the orthographic projection of the cathode 101 on the substrate, the electron injection effect can be ensured without affecting the display effect. At the same time, by controlling the existence of an overlapping area between the edges of the anode 102 and the cathode 101, the area of the cathode 101 can be reduced as much as possible, which helps to increase the area of the opening area corresponding to the cathode 101 and improve the light transmittance.

[0066] In some of these embodiments, in the area outside the overlapping area of the orthographic projection of the anode 102 on the substrate and the orthographic projection of the corresponding cathode 101 on the substrate, the orthographic projection of the edge of the cathode 101 on the substrate extends in a straight line.

[0067] It can be understood that a part of the edge of the cathode 101 extends along the edge of the anode 102, and the other part of the edge extends in a straight line to reduce the area of the cathode 101 and improve the light transmittance of the display substrate.

[0068] In some of these embodiments, chamfering treatment is performed on the edges of the cathode 101, and the edge chamfer of the cathode 101 is greater than 30 degrees.

[0069] As shown in Figure 2 , Figure 3 , Figure 7 and Figure 8 shown, there may be sharp corners at certain positions of the anode 102. If the cathode 101 extends completely along the edge of the anode 102 in this area, a sharp corner structure will also be formed. In addition, at the position where the edge of the cathode 101 is separated from the edge of the anode 102, the cathode 101 may also generate sharp corners.

[0070] Those skilled in the art found that during the implementation of the technical solution of the present disclosure, the sharp corner structure may aggravate the diffraction of light, affecting the display effect and the imaging effect of the under-screen camera. Therefore, in this embodiment, the edges of the cathode 101 are all chamfered to reduce the possibility of light diffraction. In some embodiments, the edge chamfer of the cathode 101 is greater than 30 degrees, which can reduce the possible light diffraction phenomenon.

[0071] As shown in Figure 10 shown, in some embodiments, a plurality of cathodes 101 and connection structures 101A in the light-transmitting area 11 form a mesh structure. The mesh structure includes a plurality of openings, and each opening is surrounded by the cathode 101 and the connection structure 101A, which can increase the opening area of the light-transmitting area 11, thereby improving the light transmittance of the light-transmitting area 11. In some embodiments, the materials of the cathode 101 and the connection structure 101A are the same, which helps to reduce the contact resistance between the cathode 101 and the connection structure 101A and improve the light-emitting efficiency.

[0072] As shown in Figure 11 shown, in some embodiments, the orthographic projection of the cathode 101 on the substrate completely overlaps with the orthographic projection of the anode 102 on the substrate. Correspondingly, their edges also completely overlap. It can be understood that the number and position of the cathode 101 and the anode 102 are in one-to-one correspondence, and their shapes and sizes are also the same. In this way, the opening area corresponding to the cathode 101 can be maximally increased, and the light transmittance of the display substrate can be improved.

[0073] As shown in Figure 12 shown, the cathodes 101 corresponding to each anode 102 can also be connected through the connection structure 101A to provide a common voltage.

[0074] As shown in Figure 1 shown, in some embodiments, a plurality of cathodes 101 are arranged in a first direction to form a row of cathodes 101, and multiple rows of cathodes 101 are arranged in a second direction. In this embodiment, one of the first direction and the second direction can be the extension direction of the scan line in the display panel, and the other can be the extension direction of the data line in the display panel. Exemplarily, in this embodiment, the first direction is Figure 1The horizontal direction shown in Figure 1 is the vertical direction shown in . The included angle between the first direction and the second direction is 80 - 100 degrees. The adjacent two rows of cathodes 101 are arranged with a dislocation in the first direction. It can be understood that the positions of the adjacent two rows of cathodes 101 are not aligned in the second direction, which helps to increase the number of cathodes 101 per unit area, improve the space utilization rate, and thus improve the resolution of the display panel.

[0075] As Figure 1 shown, in some embodiments, the functional area further includes a transition area 12 and a pixel circuit area 13. The pixel circuit area 13 is arranged around the light-transmitting area 11, and the transition area 12 is arranged between the pixel circuit area 13 and the light-transmitting area 11. The transition area 12 and the pixel circuit area 13 share a cathode 101. The orthographic projection of the cathode 101 on the substrate in the part of the transition area 12 and the pixel circuit area 13 is a solid pattern. Here, the solid pattern refers to the entire surface structure that has not been patterned.

[0076] As Figure 1 shown, in this embodiment, the transition area 12 is generally annular and surrounds the light-transmitting area 11. The inner contour of the pixel circuit area 13 is circular, and the outer contour is an irregular pattern. The pixel circuit area 13 surrounds the transition area 12. It should be understood that the edges of the transition area 12 and the pixel circuit area 13 in this embodiment are only used to exemplarily illustrate the approximate boundary positions between the areas, and are not actual demarcation structures.

[0077] Please refer to Figure 1 and Figure 13 simultaneously. In some embodiments, the display substrate further includes a semiconductor layer 201. In the transition area 12, the semiconductor layer 201 includes a plurality of redundant patterns 201A (dummy). The redundant patterns 201A are arranged at intervals and in an array. In this embodiment, a plurality of redundant patterns 201A are further provided, and the redundant patterns 201A are used for auxiliary positioning to assist in improving the accuracy of the exposure position of the wiring.

[0078] Please refer to Figure 1 and Figure 14 simultaneously. In some embodiments, the display panel further includes a plurality of arc-shaped winding lines 202. The winding lines 202 extend along the edge of the light-transmitting area 11. The winding lines 202 are connected to the pixel circuits located in the pixel circuit area 13 through the wiring located in the transition area 12.

[0079] It can be understood that the driving circuit is not provided in the light-transmitting area 11 in this embodiment. The driving circuits of the pixel units in the light-transmitting area 11 are all provided in the pixel circuit area 13. The driving circuits in the pixel circuit area 13 are connected to the light-emitting units located in the light-transmitting area 11 through the wiring located in the transition area 12, which helps to further improve the transparency of the light-transmitting area 11.

[0080] As shown in Figure 14 and Figure 15 the above-mentioned routing lines include a first jumper wire 203 and a second jumper wire 204.

[0081] As shown in Figure 14 in some embodiments, the display substrate further includes a first gate layer located between the semiconductor layer 201 and the anode 102 layer. The first gate layer includes a plurality of first jumper wires 203 located in the transition region 12. The upper dimension of the first jumper wire 203 in the second direction is greater than the dimension in the first direction. The plurality of first jumper wires 203 are arranged along the first direction and are parallel to each other. The orthographic projection of the first jumper wire 203 on the substrate is separated from the orthographic projection of the redundant pattern 201 on the substrate.

[0082] As shown in Figure 14 it can be understood that the first jumper wire 203 is located between two adjacent columns of redundant patterns 201 along the second direction. In this way, it helps to improve the uniformity of the structural thickness at different positions of the display panel.

[0083] As shown in Figure 15 in some embodiments, it further includes a second gate layer located between the first gate layer and the anode 102 layer. The second gate layer includes a plurality of second jumper wires 204 located in the transition region 12. The second jumper wire 204 extends along the second direction. The orthographic projection of the second jumper wire 204 on the substrate is separated from the orthographic projection of the redundant pattern 201 on the substrate and the orthographic projection of the first jumper wire 203 on the substrate.

[0084] As shown in Figure 15 similar to the setting manner of the first jumper wire 203, the second jumper wire 204 in this embodiment is also arranged between two adjacent columns of redundant patterns 201 along the second direction, and the first jumper wire 203 and the second jumper wire 204 are located between different columns of redundant patterns 201, which helps to improve the thickness uniformity of different regions of the display panel. The ratio of the distance between two adjacent first jumper wires 203 to the distance between two adjacent second jumper wires 204 is 0.8 - 1.2, which helps to further improve the thickness uniformity of different regions of the display substrate.

[0085] It should be understood that Figure 15 in, the second jumper wire 204 is represented by a dotted line only to indicate the position of the second jumper wire 204 and does not represent the actual structure of the second jumper wire 204.

[0086] The above-mentioned first jumper wire 203 and second jumper wire 204 are mainly used to realize the electrical connection of the pixel circuit. It should be understood that due to the existence of the light-transmitting region 11, there is a gap in the pixel circuit in the second direction, as shown in Figure 14 and Figure 15As shown, both ends of the first adapter wire 203 and the second adapter wire 204 are respectively connected to the winding 202, and the other ends are connected to the pixel circuit. Along the second direction, on the other side of the light-transmitting area 11, there is also provided a first adapter wire 203 and a second adapter wire 204 correspondingly connected to the winding 202. In this way, the electrical connection of the pixel circuits on the opposite sides of the light-transmitting area 11 is realized. At the same time, avoiding the setting of wiring in the light-transmitting area 11 helps to further improve the transparency of the light-transmitting area 11.

[0087] In some embodiments, it further includes an interlayer insulating layer located between the second gate layer and the anode 102 layer. In the transition area 12, the interlayer insulating layer includes a plurality of vias 205, and the orthographic projection of each via 205 on the substrate overlaps with the orthographic projection of a redundant pattern 201 on the substrate. By controlling the overlapping of the positions of the vias 205 in the interlayer insulating layer and the orthographic projection of the redundant pattern 201, it helps to improve the uniformity of the thickness of the display panel.

[0088] As Figure 17 shown, in some embodiments, it further includes a first metal layer located between the interlayer insulating layer and the anode 102 layer. In the transition area 12, the first metal layer includes a plurality of third adapter wires 206. The size of the third adapter wire 206 in the first direction is larger than that in the second direction. The included angle between the orthographic projection of the third adapter wire 206 on the substrate and the orthographic projection of the first adapter wire 206 on the substrate is 80 - 100 degrees, and the orthographic projection of the third adapter wire 206 on the substrate is separated from the orthographic projection of the redundant pattern 201 on the substrate. Similar to the functions of the first adapter wire 203 and the second adapter wire 204, the third adapter wire 206 is used to realize the connection of the pixel circuit in the first direction.

[0089] In this embodiment, similar to the setting method of the first adapter wire 203 and the second adapter wire 204, in this embodiment, the third adapter wire 206 is located between two adjacent rows of redundant patterns 201 along the first direction, which helps to improve the uniformity of the thickness of the display panel.

[0090] As Figure 18 shown, on the side of the first metal layer away from the substrate, a first planar layer (not labeled) can be provided as needed.

[0091] As Figure 19 shown, in some embodiments, it further includes a transparent wire layer located between the first metal layer and the anode 102. The transparent wire layer includes a transparent trace 207 extending along the first direction and a first redundant trace 208. The transparent trace 207 and the first redundant trace 208 are separated. The transparent wire layer further includes a plurality of second redundant traces 209 extending along the second direction.

[0092] As Figure 19As shown, in some of these embodiments, each anode 102 is connected to a transparent trace 207 through an anode via. The transparent trace 207 is connected to the pixel circuit disposed in the pixel circuit region 13, and the first redundant trace 208 and the second redundant trace 209 are connected.

[0093] In this embodiment, the first redundant trace 208 and the second redundant trace 209 are used to balance the thickness of different regions of the display panel, improve the uniformity of the thickness of different structures, and contribute to improving the display effect.

[0094] As Figure 20 shown, the display substrate further includes a second planarization layer (not labeled) to improve the flatness of the anode 102 fabricated subsequently.

[0095] As Figure 21 shown, the anode 102 is disposed on the side of the second planarization layer away from the substrate, and the anode 102 is connected to a transparent trace 207 through an anode via.

[0096] As Figure 22 shown, on the side of the anode away from the substrate, a pixel defining layer (not labeled) is further disposed to define the range of the effective light-emitting region of each pixel.

[0097] As Figure 23 shown, in some of these embodiments, each pixel unit includes a plurality of sub-pixels. The orthographic projections of the anodes of the plurality of sub-pixels on the substrate are separated from each other. Exemplarily, the sub-pixels corresponding to each pixel unit include two green sub-pixels G, one red sub-pixel R, and one blue sub-pixel B. The two green sub-pixels G are arranged along the second direction, and the effective light-emitting region of the blue sub-pixel B is located between the effective light-emitting regions of the two green sub-pixels G in the second direction.

[0098] The pixel unit in this embodiment includes four sub-pixels. Exemplarily, they can be RGGB (red, green, green, blue) sub-pixels respectively. There are overlapping regions between the edges of the anode 102 and the edges of the cathodes 101 of these four sub-pixels.

[0099] In some of these embodiments, the center lines of the effective light-emitting regions of the two green sub-pixels G along the second direction approximately coincide, and the effective light-emitting regions of the blue sub-pixel B and the red sub-pixel R are located on the same side of the center line.

[0100] In the second direction, the distances from the effective light-emitting region of the blue sub-pixel B to the effective light-emitting regions of the two green sub-pixels G are approximately equal. The effective light-emitting region of the red sub-pixel R does not overlap with the effective light-emitting region of the blue sub-pixel B in the first direction, and the effective light-emitting region of the red sub-pixel R overlaps with the effective light-emitting region of one green sub-pixel G in the first direction.

[0101] In the second direction, the effective light-emitting area of the red sub-pixel R is located on the side of the effective light-emitting area of the blue sub-pixel B away from the green sub-pixel G, the anode holes of some blue sub-pixels B are located on one side of the effective light-emitting area of the blue sub-pixel B in the second direction, and the anode holes of some blue sub-pixels B are located on the other side.

[0102] like Figure 23 As shown, for the pixel unit at the upper left corner, the anode hole of the blue sub-pixel B is located on the left, while for the pixel unit at the lower right corner, the anode hole of the blue sub-pixel B is located on the right.

[0103] An embodiment of the present disclosure provides a method for manufacturing a display panel, which is used to manufacture any of the above display panels. The method includes the step of forming a cathode 101. The step of forming the cathode 101 includes:

[0104] forming a cathode material layer;

[0105] Burning the cathode material layer with a laser to pattern the cathode material layer;

[0106] Use plasma air knife to remove residual particles from the cathode material layer.

[0107] In this embodiment, the cathode material layer is patterned by laser etching to form a cathode layer, and a plasma air knife is further used to remove residual particles to ensure the quality of the formed cathode pattern.

[0108] In some embodiments, the orthographic projection of the cathode 101 on the substrate is an asymmetric shape.

[0109] During the implementation of the present invention, those skilled in the art discovered that cathode 101 can be patterned by pre-masking with an open mask or an FMM mask. However, due to the limitations of the mesh used, the resulting cathode 101 pattern must be symmetrical, resulting in a reduced aperture ratio. The related process requires the use of specialized cathode materials, resulting in low single-layer transmittance and increased light diffraction.

[0110] In this embodiment, cathode 101 is formed by laser etching and patterning, and the resulting cathode 101 has an asymmetric structure. Compared to a symmetric cathode 101, the asymmetric structure helps reduce light diffraction and helps increase the aperture ratio, that is, improve light transmittance. In addition, laser etching and patterning can be implemented based on conventional cathode 101 materials, such as MgAg (magnesium silver alloy), which also helps to control costs.

[0111] It should be understood that laser ablation etching generates a relatively large amount of heat. During implementation, the pixel defining layer can be used as a buffer to reduce the possible impact of the heat generated during etching.

[0112] In some embodiments, the step of using laser ablation to pattern the cathode material layer includes:

[0113] Placing the display substrate including the cathode material layer on the processing platform of the laser etching equipment;

[0114] Using the laser etching equipment to capture the alignment marks on the display substrate;

[0115] According to the positions of the alignment marks and the cathode, using laser ablation to pattern the cathode material layer to form an image of the cathode.

[0116] In this embodiment, during the process of patterning the cathode material layer to form the cathode, first use the laser etching equipment to capture the alignment marks, and then according to the relative positions of the alignment marks and the cathode in the preset drawing, ablate the cathode material layer outside the cathode, and the remaining cathode material layer forms a patterned cathode pattern at the specified position.

[0117] Taking the aperture ratio of the opening area of other structures as m, the aperture ratio of the opening area corresponding to the cathode 101 as n, and the opening area corresponding to the cathode 101 being within the range of the opening area of other structures, the light transmittance of the cathode 101 as x, and the transmittance without the light blocking layer as C.

[0118] When the cathode 101 is not patterned, the light transmittance Tr.1 = C * [m * x], and when the cathode 101 is patterned, the light transmittance Tr.2 = C * [(m - n) * x + n * 1]. Where Tr.1 and Tr.2 are the corresponding light transmittances. Further, Tr.2 / Tr.1 = 1 + (1 - x)n / (mx) can be obtained.

[0119] In one embodiment, for example, taking m = 92.35%, n = 86.78%, and x = 55% as an example, after calculation, Tr.2 / Tr.1 is approximately equal to 1.77. It can be seen that the light transmittance of the display substrate increases significantly.

[0120] In some embodiments, the connection structure 101A can be set on the same layer and made of the same material as the cathode 101. Specifically, it can be formed simultaneously when patterning the cathode 101 material layer to obtain the cathode 101, that is, the cathode 101 and the connection structure 101A are fabricated through a single lithography process, which helps to save production costs and production processes.

[0121] In the process of implementing the technical solution of the present disclosure, the technical personnel found that, affected by factors such as the processing technology, the width of the connection structure 101A provided on the same layer and with the same material as the cathode 101 needs to be greater than 5 micrometers. After further research, it was found that this solution would lead to a reduction in the light transmittance of the display substrate and may also cause an increase in light diffraction, affecting the display effect and the imaging effect of the under-screen camera.

[0122] In some other embodiments, each cathode 101 is electrically connected through the connection structure 101A, and the connection structure 101A and the cathode 101 are formed by different lithography processes respectively.

[0123] In this embodiment, the connection structure 101A between the cathodes 101 is a transparent conductive connection structure 101A, and the transparent conductive connection structure 101A is fabricated separately. That is to say, in this embodiment, an independent and insulated cathode 101 needs to be formed by one lithography process, and a transparent conductive connection structure 101A connecting the cathodes 101 also needs to be formed by one lithography process.

[0124] The material of the transparent conductive connection structure 101A can be selected as a material with a relatively high transparency such as ITO (indium tin oxide). By realizing the electrical connection between the cathodes 101 through the transparent conductive connection structure 101A, the light transmittance of the display substrate can be further improved.

[0125] The present disclosure also provides a display device.

[0126] In one embodiment, the display device includes the display panel in any one of the above display panel embodiments, and a camera is provided in the light-transmitting area 11.

[0127] Since the display device of this embodiment includes all the technical solutions of the above display panel embodiments, at least all the above technical effects can be achieved, which will not be elaborated here.

[0128] The above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present disclosure, and all should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display panel, comprising a substrate, the substrate including a display area and a functional area, the display area being located on one side of the functional area, the functional area including a light-transmitting area, the light-transmitting area including a plurality of pixel units, each of the plurality of pixel units including at least one sub-pixel, each pixel unit further including a cathode, the orthographic projections of the plurality of cathodes on the substrate being separated from each other, the orthographic projection of the effective light-emitting area of each sub-pixel on the substrate being within the orthographic projection of the cathode of the corresponding pixel unit on the substrate, the display panel further including a connection structure, the plurality of cathodes being connected through the connection structure, the plurality of cathodes and the connection structure in the light-transmitting area forming a mesh structure, the mesh structure including a plurality of openings, each opening being surrounded by the cathode and the connection structure, the plurality of cathodes being configured to provide the same common voltage.

2. The display panel according to claim 1, wherein, The functional area further includes a transition area and a pixel circuit area, the pixel circuit area being disposed around the light-transmitting area, the transition area being disposed between the pixel circuit area and the light-transmitting area, the transition area and the pixel circuit area sharing a cathode, the orthographic projection of the cathode on the substrate in the part of the transition area and the pixel circuit area being a solid figure.

3. The display panel according to claim 2, wherein, The display panel further includes a plurality of winding lines, the winding lines extending along the edge of the light-transmitting area, the winding lines being connected to pixel circuits located in the pixel circuit area through routing lines located in the transition area.

4. The display panel according to claim 3, wherein, It further includes a first gate layer located between the semiconductor layer and the anode layer, the first gate layer including a plurality of first transfer lines located in the transition area, both ends of each first transfer line in the plurality of first transfer lines being respectively connected to the corresponding winding line, the dimension of each first transfer line in the second direction being greater than the dimension in the first direction, the first direction and the second direction intersecting, the plurality of first transfer lines being arranged along the first direction and being parallel to each other.

5. The display panel according to claim 4, wherein, It further includes a semiconductor layer, in the transition area, the semiconductor layer including a plurality of redundant patterns, the redundant patterns being spaced apart and arranged in an array, the orthographic projection of the first transfer line on the substrate being separated from the orthographic projection of the redundant pattern on the substrate.

6. The display panel according to claim 4, wherein, It further includes a second gate layer located between the first gate layer and the anode layer, the second gate layer including a plurality of second transfer lines located in the transition area, both ends of each second transfer line in the plurality of second transfer lines being respectively connected to the corresponding winding line, the dimension of the second transfer line in the second direction being greater than the dimension in the first direction, the orthographic projection of the second transfer line on the substrate being separated from the orthographic projection of the redundant pattern on the substrate and the orthographic projection of the first transfer line on the substrate.

7. The display panel according to claim 6, wherein, The ratio of the distance between adjacent two first transfer lines to the distance between adjacent two second transfer lines is 0.8 - 1.

2.

8. The display panel according to claim 1, wherein, The sub-pixels corresponding to each pixel unit include two green sub-pixels, one red sub-pixel and one blue sub-pixel, the two green sub-pixels being arranged along the second direction, and the effective light-emitting area of the blue sub-pixel being located between the effective light-emitting areas of the two green sub-pixels in the second direction.

9. The display panel according to claim 8, wherein, The center lines of the effective light-emitting regions of the two green sub-pixels along the second direction substantially coincide, and the effective light-emitting regions of the blue sub-pixel and the red sub-pixel are located on the same side of the center line.

10. The display panel according to claim 1, wherein, The orthographic projection of the edge of the cathode on the substrate is separated from the orthographic projection of the effective light-emitting region of the corresponding sub-pixel on the substrate, and the edge of the cathode overlaps with the orthographic projection of the anode of the corresponding sub-pixel on the substrate.

11. The display panel according to claim 1, wherein, The orthographic projection of the anode of the sub-pixels included in each pixel unit on the substrate is located within the orthographic projection of the cathode of the corresponding pixel unit on the substrate.

12. The display panel according to claim 11, wherein, The orthographic projection of the edge of the anode on the substrate coincides with the edge portion of the orthographic projection of the corresponding cathode on the substrate.

13. The display panel according to claim 12, wherein, In the region outside the overlapping region of the orthographic projection of the anode on the substrate and the orthographic projection of the corresponding cathode on the substrate, the orthographic projection of the cathode edge on the substrate extends in a straight line.

14. The display panel according to claim 13, wherein, The edges of the cathode are all chamfered, and the chamfer of the edge of the cathode is greater than 30 degrees.

15. The display panel according to any one of claims 1 to 14, wherein, The connection structure is a transparent conductive material.

16. The display panel according to claim 15, wherein, The material of the conductive connection structure is indium tin oxide.

17. The display panel according to claim 6, wherein, It further includes an interlayer insulating layer located between the second gate layer and the anode layer. In the transition region, the interlayer insulating layer includes a plurality of vias, and the orthographic projection of each via on the substrate overlaps with the orthographic projection of one of the redundant patterns on the substrate.

18. The display panel according to claim 17, wherein, It further includes a first metal layer located between the interlayer insulating layer and the anode layer. In the transition region, the first metal layer includes a plurality of third transfer lines. The dimension of the third transfer line in the first direction is greater than the dimension in the second direction. The angle between the orthographic projection of the third transfer line on the substrate and the orthographic projection of the first transfer line on the substrate is 80-100 degrees, and the orthographic projection of the third transfer line on the substrate is separated from the orthographic projection of the redundant pattern on the substrate.

19. The display panel according to claim 18, wherein, It further includes a transparent wire layer located between the first metal layer and the anode layer. The transparent wire layer includes a transparent trace extending along the first direction and a first redundant trace, and the transparent trace and the first redundant trace are separated. The transparent wire layer further includes a plurality of second redundant traces extending along the second direction.

20. The display panel according to claim 19, wherein, Each anode is connected to a transparent trace through an anode hole. The transparent trace is connected to a pixel circuit disposed in the pixel circuit region, and the first redundant trace and the second redundant trace are connected.

21. A display device, comprising the display panel according to any one of claims 1 to 20, wherein a screen-under camera is provided in the light-transmitting region.

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