Display panel and display device

Abstract

The invention provides a display panel and a display device, the display panel is provided with a first area and a second area, the transmittance of the first area is greater than that of the second area, and the second area comprises a first sub-area adjacent to the first area in a first direction. The display panel further comprises a first signal line and a pixel circuit, the first signal line is arranged in the second area, the first signal line comprises first sub-segments located on the two sides of the first area in the second direction and a first winding part connected with the first sub-segments, and the first winding part comprises second sub-segments which extend in the second direction and are at least partially located in the first sub-areas. The first direction intersects the second direction. The pixel circuits are arranged in the second area, the multiple pixel circuits are arranged in an array mode in the first direction and the second direction, and the multiple pixel circuits arranged side by side in the second direction jointly form a circuit column. In the thickness direction of the display panel, at least part of the adjacent second sub-segments and the adjacent circuit columns are arranged in an overlapping mode.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and in particular, to a display panel and a display device. Background Art

[0002] In a display device, since it is necessary to integrate photosensitive components such as a front camera, a fingerprint recognition element, and an infrared sensing element, etc., a hole is provided in the display panel to form a photosensitive function area. In this way, external light can enter the photosensitive component below the display panel through the photosensitive function area on the display panel. However, the existence of the photosensitive function area will affect the internal wiring layout mode of the display panel. Summary of the Invention

[0003] Embodiments of the present application provide a display panel and a display device, which can meet the wiring layout requirements.

[0004] In a first aspect, an embodiment of the present application provides a display panel. The display panel has a first area and a second area, and the transmittance of the first area is greater than that of the second area. The second area includes a first sub-area adjacent to the first area in a first direction. The display panel further includes a first signal line and a pixel circuit. The first signal line is disposed in the second area. The first signal line includes a first sub-segment located on both sides of the first area in a second direction, and a first winding portion connecting the first sub-segments. The first winding portion includes a second sub-segment extending in the second direction and at least partially located in the first sub-area. The first direction intersects the second direction.

[0005] The pixel circuit is disposed in the second area. A plurality of pixel circuits are arranged in an array in the first direction and the second direction. A plurality of pixel circuits arranged in sequence in the second direction together form a circuit column. Among them, in the thickness direction of the display panel, at least some adjacent second sub-segments and adjacent circuit columns are overlapped with each other.

[0006] In a second aspect, an embodiment of the present application provides a display device, and the display device includes the display panel in any of the foregoing embodiments.

[0007] Embodiments of the present application provide a display panel and a display device. In the thickness direction of the display panel, at least some adjacent second sub-segments and adjacent circuit columns are overlapped with each other, that is, there is no projection of a circuit column corresponding to the projection between at least some adjacent second sub-segments. This design reduces the distance between adjacent second sub-segments and increases the distribution density of a plurality of second sub-segments in a unit area. On this basis, more second sub-segments can be integrated in a smaller area, so that more second sub-segments are arranged in the first sub-area and on the same layer, thereby reducing the occupation of other areas or film layer spaces by the second sub-segments and meeting the wiring layout requirements of the display panel. Description of the Drawings

[0008] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0009] Figure 1 It is a schematic structural diagram of a display panel provided by an embodiment of the present application;

[0010] Figure 2 It is a simplified partial structural diagram of another display panel provided by an embodiment of the present application;

[0011] Figure 3 is Figure 2 a partial structural diagram in

[0012] Figure 4 It is a simplified partial structural diagram of another display panel provided by an embodiment of the present application;

[0013] Figure 5 It is a circuit schematic diagram of a pixel circuit in a display panel provided by an embodiment of the present application;

[0014] Figure 6 It is a simplified partial structural diagram of another display panel provided by an embodiment of the present application;

[0015] Figure 7 It is a circuit schematic diagram of a pixel circuit of another display panel provided by an embodiment of the present application;

[0016] Figure 8 It is a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present application;

[0017] Figure 9 It is a schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present application;

[0018] Figure 10 It is a schematic layout structure diagram of a display panel provided by an embodiment of the present application;

[0019] Figure 11 It is a simplified partial structural diagram of another display panel provided by an embodiment of the present application;

[0020] Figure 12a and 12b are simplified partial structural diagrams of two display panels provided by an embodiment of the present application;

[0021] Figure 13 It is a simplified partial structural diagram of another display panel provided by an embodiment of the present application;

[0022] Figure 14It is a schematic diagram of the layout structure of a display panel provided by an embodiment of the present application;

[0023] Figure 15 It is a schematic diagram of a partial simple structure of another display panel provided by an embodiment of the present application;

[0024] Figure 16 It is a schematic diagram of a partial simple structure of another display panel provided by an embodiment of the present application;

[0025] Figure 17 It is a schematic diagram of a partial simple structure of another display panel provided by an embodiment of the present application;

[0026] Figure 18 It is a schematic diagram of a partial simple structure of another display panel provided by an embodiment of the present application;

[0027] Figure 19a and Figure 19b It is a simplified diagram of the relationship between the wiring structure and the circuit column in a partial area of a display panel provided by an embodiment of the present application;

[0028] Figure 20 It is a schematic diagram of a partial simple structure of another display panel provided by an embodiment of the present application;

[0029] Figure 21 It is a schematic diagram of a partial simple structure of another display panel provided by an embodiment of the present application;

[0030] Figure 22 It is a schematic diagram of a partial simple structure of another display panel provided by an embodiment of the present application;

[0031] Figure 23a and Figure 23b It is a simplified diagram of the relationship between the wiring structure and the circuit column in a partial area of a display panel provided by an embodiment of the present application;

[0032] Figure 24 It is a schematic diagram of the structure of a display device provided by an embodiment of the present application.

[0033] Marking description:

[0034] 10. First signal line; 11. First sub-segment; 12. First winding part; 13. Second sub-segment; 14. Third sub-segment;

[0035] 200. Circuit column; 20. Pixel circuit;

[0036] 30. First line segment; 31. First type of wiring; 32. Second type of wiring; 33. Third type of wiring; 34. First wiring; 35. Second wiring;

[0037] 41. Substrate; 42. First conductor layer; 43. Second conductor layer; 44. Third conductor layer; 45. Fourth conductor layer; 46. Fifth conductor layer; 47. Low-temperature polysilicon active layer; 48. Oxide active layer;

[0038] 51. First reset signal line; 52. Second reset signal line; 53. Third reset signal line;

[0039] 60. Second signal line;

[0040] 70. Third signal line; 71. Second winding portion; 72. Fourth sub-segment;

[0041] 80. Second line segment;

[0042] 90. Fourth signal line; 91. Third winding portion; 92. Fifth sub-segment; 93. Sixth sub-segment;

[0043] R. Fan-out line;

[0044] P. Light-emitting unit;

[0045] A1. First region; A2. Second region; A21. First sub-region; A22. Second sub-region; A3. Third region; A31. Fan-out region;

[0046] X. First direction; Y. Second direction; Z. Thickness direction. Detailed implementation manners

[0047] The features and exemplary embodiments of various aspects of the present application will be described in detail below. To make the objectives, technical solutions and advantages of the present application clearer and more understandable, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by showing examples of the present application.

[0048] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0049] To meet specific photosensitive functions, a photosensitive functional area is provided in the display panel, and some wiring structures extend to the position where the photosensitive functional area is located. Usually, in order to reduce the influence of this part of the wiring on the photosensitive effect and meet the requirements of the wiring layout, the wiring structure is provided with a winding structure that bypasses the photosensitive functional area. However, due to the design limitations of the display panel itself, in at least some areas on the periphery of the photosensitive functional area, there may be only a small space size for placing the winding structure. On this basis, if a conventional winding method is used in this area, it may not be able to meet the layout space requirements of all the winding structures.

[0050] In view of the above problems, in a first aspect, please refer to Figures 1 to 3 , an embodiment of the present application provides a display panel. The display panel has a first area A1 and a second area A2. The transmittance of the first area A1 is greater than that of the second area A2. The second area A2 includes a first sub-area A21 adjacent to the first area A1 in a first direction X. The display panel further includes a first signal line 10 and a pixel circuit 20. The first signal line 10 is disposed in the second area A2. The first signal line 10 includes a first sub-segment 11 located on both sides of the first area A1 along a second direction Y, and a first winding portion 12 connecting the first sub-segments 11. The first winding portion 12 includes a second sub-segment 13 extending along the second direction Y and at least partially located in the first sub-area A21. The first direction X intersects the second direction Y.

[0051] The pixel circuit 20 is disposed in the second area A2. A plurality of pixel circuits 20 are arranged in an array in the first direction X and the second direction Y. A plurality of pixel circuits 20 arranged side by side in the second direction Y together form a circuit column 200. Among them, in the thickness direction Z of the display panel, at least some adjacent second sub-segments 13 and adjacent circuit columns 200 are respectively overlapped. Among them, in Figure 2Among them, the first region A1 and the first sub-region A21 are both schematically shown by thin dotted lines, the pixel circuit 20 located in the first sub-region A21 is schematically shown by a thick dotted line, and the second sub-segment 13 is schematically shown by a thick solid line.

[0052] The display panel is used for subsequent preparation to form a display device. The display panel is a device for realizing the display function. In addition to the display panel, the display device may further include a photosensitive component such as a front camera, a fingerprint recognition element, and an infrared sensing element. The photosensitive component is disposed on the backlight side of the display panel and is used to realize specific functions such as fingerprint recognition and under-screen photography.

[0053] Regarding the specific light-emitting method of the display panel and the specific type of the display device, the embodiments of the present application do not make any limitations. The display panel may include an organic light-emitting functional layer. In this case, the display device may be an organic light-emitting display device. Alternatively, the display panel may include micro light-emitting diodes. In this case, the display device may be a micro light-emitting display device.

[0054] The display panel has a first region A1 and a second region A2. The second region A2 is the main region of the display panel for realizing the display function. Taking the display panel including an organic light-emitting functional layer as an example, the organic light-emitting functional layer may include a plurality of light-emitting units, and at least some of the light-emitting units are located in the second region A2. The first region A1 is the photosensitive functional region of the display panel, and the transmittance of the first region A1 is greater than that of the second region A2. In the subsequent formed display device, a photosensitive component may be disposed at a position corresponding to the first region A1 on the back of the display panel. Among them, according to different actual needs, no light-emitting unit may be provided in the first region A1, or a light-emitting unit may also be provided, that is, the first region A1 may only meet the photosensitive needs and not realize the light-emitting function, or the first region A1 may also meet both the photosensitive needs and realize the light-emitting function.

[0055] Regarding the specific morphology of the first region A1 and the second region A2 and the specific positional relationship between the two, the embodiments of the present application do not make any limitations. Exemplarily, the first region A1 may be circular, square, oval, or other regular or irregular shapes. Similarly, the outer contour of the first region A1 may be circular, square, or other regular or irregular shapes. Among them, the second region A2 may be disposed to surround the first region A1.

[0056] The first sub-region A21 is a local region in the second region A2. The first sub-region A21 is adjacently disposed to the first region A1. The "adjacently disposed" mentioned here means that the first sub-region A21 is the region in the second region A2 that is closest to the first region A1 in the first direction X. There may be other regions such as a non-display region between the first sub-region A21 and the first region A1, or there may be no other regions. The embodiments of the present application do not make any limitations in this regard.

[0057] The first sub-region A21 can have various sizes and shapes. For example, the shape of the first sub-region A21 can be the same as that of the first region A1, or they can also have different shapes. Among them, in the figure, a case where the first region A1 has a circular structure and the first sub-region A21 has a square structure is shown.

[0058] The first signal line 10 is a wiring structure that transmits a specific signal and needs to extend around the first region A1. The first signal line 10 is disposed within the first region A1. The first sub-segment 11 is the main part of the first signal line 10. The first sub-segment 11 extends along the second direction Y and is located on both sides of the first region A1. The first winding portion 12 is a partial structure of the first signal line 10 for avoiding the first region A1. The first winding portion 12 includes a second sub-segment 13. The second sub-segment 13 extends along the second direction Y and is located on one side of the first region A1 along the first direction X. Among them, the first direction X can represent the row direction of the display panel, and the second direction Y can represent the column direction of the display panel. Optionally, the first direction X and the second direction Y are perpendicular to each other.

[0059] The second sub-segment 13 is at least partially located within the first sub-region A21. Limited by the layout of the display panel, the spatial size of the first sub-region A21 is small. On this basis, if the second sub-segments 13 in multiple first signal lines 10 adopt the layout method in the related art, it is impossible to meet the placement requirements of all the second sub-segments 13 within the first sub-region A21, so that some first sub-segments 11 need to be arranged in other regions of the second region A2, increasing the winding length and occupying the space of other regions, or arranging different first sub-segments 11 in different film layers, thereby occupying the internal space of other film layers.

[0060] In view of this, in the embodiments of the present application, the positional relationship between the second sub-segment 13 and the pixel circuit 20 is adjusted, so that multiple second sub-segments 13 can be arranged within the first sub-region A21 and in the same layer. Specifically, the pixel circuit 20 is a circuit structure that drives the display panel to achieve a light-emitting function. The pixel circuit 20 includes a thin-film transistor and a storage capacitor cst. Among them, the pixel circuit 20 can have various forms. For example, the pixel circuit 20 can have a 7T1C circuit structure, that is, the pixel circuit 20 includes seven thin-film transistors and one storage capacitor cst, or the pixel circuit 20 can also have an 8T1C or 8T2C circuit structure, etc.

[0061] A plurality of pixel circuits 20 arranged side by side in the second direction Y together form a circuit column 200. The plurality of circuit columns 200 are arranged side by side in the first direction X. In the embodiment of the present application, in the thickness direction Z of the display panel, at least part of the adjacent second sub-segments 13 and the adjacent circuit columns 200 are respectively overlapped, that is, there is no projection of a circuit column 200 corresponding to the projections between at least part of the adjacent second sub-segments 13. This design reduces the distance between adjacent second sub-segments 13 and increases the distribution density of a plurality of second sub-segments 13 in a unit area. On this basis, more second sub-segments 13 can be integrated in a smaller area, so that more second sub-segments 13 are arranged in the first sub-region A21 and on the same layer, thereby reducing the occupation of other regions or film layer spaces by the second sub-segments 13 and meeting the routing layout requirements of the display panel.

[0062] It should be noted that the "projection of adjacent second sub-segments 13" mentioned in the embodiment of the present application refers to: on any plane perpendicular to the thickness direction Z of the display panel, the orthographic projections of two adjacent second sub-segments 13 on this plane, and the "projection of the circuit column 200" is the same. And the "overlapping arrangement" mentioned in the embodiment of the present application refers to: on any plane perpendicular to the thickness direction Z of the display panel, at least part of the orthographic projections of adjacent second sub-segments 13 on this plane respectively overlap with the orthographic projections of adjacent circuit columns 200 on this plane. Further optionally, in the thickness direction Z of the display panel, any adjacent second sub-segments 13 and adjacent circuit columns 200 are respectively overlapped.

[0063] In addition, the "adjacent second sub-segments 13" mentioned in the embodiment of the present application refers to: there are no other second sub-segments 13 between these two second sub-segments 13. And the "adjacent circuit columns 200" mentioned in the embodiment of the present application refers to: there are no other circuit columns 200 between these two circuit columns 200. The same applies to the "adjacent" mentioned later in the present application and will not be repeated.

[0064] In some embodiments, as Figures 1 to 3 shown, the display panel further includes a first line segment 30 that is on the same layer as and insulated from the second sub-segment 13. The first line segment 30 extends along the second direction Y and is located on both sides of the second sub-segment 13. In the thickness direction Z of the display panel, the second sub-segment 13 and the first line segment 30 are respectively overlapped with the same circuit column 200.

[0065] The first sub-segment 11 is used to transmit a signal different from the first signal line 10. Therefore, the first line segment 30 and the second sub-segment 13 need to be insulated from each other. Among them, the first line segment 30 and the second sub-segment 13 are located in the same film layer, that is, both include the same material and are formed together in the same process.

[0066] Since the main structure in the second sub-segment 13 is located within the first sub-region A21, and there is usually a certain distance between the two edges of the first sub-region A21 and the second region A2 in the second direction, there will be a certain area between the edge position of the second region A2 in the second direction and the first sub-region A21 where the second sub-segment 13 is not provided.

[0067] In view of this, in the embodiment of the present application, a first line segment 30 is added in the display panel. The first line segment 30 has the same extending direction as the second sub-segment 13 and is located on both sides of the second sub-segment 13. In this way, different regions of the second region A2 in the second direction Y can have the same or similar routing structures, thereby reducing the display differences caused by different wiring methods and improving the display uniformity of the display panel. Further, the first line segment 30 can also be used to transmit a specific signal, thereby improving the transmission reliability of the specific signal in the display panel.

[0068] It should be noted that for different first line segments 30 arranged side by side in the first direction X, different first line segments 30 can be used to transmit different signals, or can also be used to transmit the same signal. The embodiment of the present application does not limit this. Optionally, two first line segments 30 located on both sides of the first sub-region A21 and corresponding to the same circuit column 200 are used to transmit the same signal.

[0069] In some embodiments, as Figure 2 shown, at least part of the first line segments 30 are used to transmit the first power signal pvee.

[0070] Taking the display panel including an organic light-emitting functional layer as an example, the organic light-emitting functional layer includes a plurality of light-emitting units. The display panel usually has a cathode and an anode arranged on both sides of the light-emitting unit. The cathode and the anode jointly control whether the light-emitting unit emits light. Among them, the cathodes corresponding to different light-emitting units can be connected together and the cathode is used to receive the first power signal pvee.

[0071] It should be noted that according to different internal routing design forms of the display panel, all the first line segments 30 can be used to transmit the first power signal pvee. In this case, all the first line segments 30 are used to transmit the same signal. Or part of the first line segments 30 can be used to transmit the first power signal pvee, and part of the first line segments 30 can be used to transmit other signals. In this case, some different first line segments 30 are used to transmit different signals; of course, the first line segments 30 can also be all used to transmit other power signals except pvee.

[0072] In the embodiments of the present application, by overlapping at least some adjacent second sub-segments 13 and adjacent circuit columns 200 respectively, the pitch between adjacent second sub-segments 13 is reduced, so that more second sub-segments 13 are arranged within the first sub-region A21, meeting the layout requirements of multiple second sub-segments 13. On this basis, in the embodiments of the present application, first line segments 30 are also arranged on both sides of the second sub-segments 13, and the first line segments 30 are arranged to transmit the first power signal pvee. This design helps to improve the display uniformity of the display panel on the one hand and the transmission reliability of the first power signal pvee on the other hand, thereby further improving the display effect of the display panel.

[0073] In some alternative embodiments, all the first line segments 30 are used to transmit the first power signal pvee, that is, in the embodiments of the present application, the first line segments 30 located on both sides of any second sub-segment 13 are used to transmit the first power signal pvee, which helps to further improve the transmission reliability of the first power signal pvee.

[0074] In some embodiments, as Figure 4 shown, some of the first line segments 30 are used to transmit a reset signal, and the first line segments 30 for transmitting the first power signal pvee and the first line segments 30 for transmitting the reset signal are arranged alternately in the first direction X.

[0075] Both the first power signal pvee and the reset signal are constant voltage signals. The reset signal is used to reset a specific node or structure to restore it to its initial state. The reset signal can have multiple types. For example, some reset signals can be used to reset the anode, or some reset signals can be used to reset the first node N1 to achieve the reset of the lower plate c1 of the storage capacitor cst and the control terminal of the driving transistor M3, or some reset signals can also reset the second node N2 to adjust the bias state of the driving transistor M3. Among them, the driving transistor M3 is a thin film transistor used for driving functions in the pixel circuit 20.

[0076] In the embodiments of the present application, in addition to being able to transmit the first power signal pvee, the first line segments 30 can also be used to transmit the reset signal. This design helps to improve the transmission reliability of the first power signal pvee and the transmission reliability of the reset signal. Among them, for the multiple first line segments 30 for transmitting the reset signal, all the first line segments 30 can transmit the same type of reset signal, or at least some different first line segments 30 can also transmit different types of reset signals.

[0077] Further, the first segments 30 for transmitting the first power signal pvee and the first segments 30 for transmitting the reset signal are arranged alternately in the first direction X. That is, for any two adjacent first segments 30, one of the first segments 30 is used to transmit the first power signal pvee, and the other first segment 30 is used to transmit the reset signal. With this design, the multiple first segments 30 for transmitting the first power signal pvee can be spaced apart at different regions of the display panel along the first direction X, reducing the excessive aggregation of the multiple first segments 30 for transmitting the first power signal pvee in the first direction X, thereby improving the transmission reliability of the first power signal pvee at different regions of the display panel along the first direction X. Similarly, this design also helps to improve the transmission reliability of the reset signal at different regions of the display panel along the first direction X.

[0078] In some embodiments, referring to Figure 4 and Figure 5 , the multiple first segments 30 for transmitting the reset signal include a first type of trace 31 and a second type of trace 32. The first type of trace 31 is used to transmit the first reset signal vref1, and the second type of trace 32 is used to transmit the second reset signal vref2. Among them, the pixel circuit 20 includes a first reset transistor M5, a second reset transistor M7, and a driving transistor M3. The first pole of the first reset transistor M5 receives the first reset signal vref1, and the second pole is electrically connected to the control terminal of the driving transistor M3. The first pole of the second reset transistor M7 receives the second reset signal vref2, and the second pole is electrically connected to the anode.

[0079] The first reset transistor M5, the second reset transistor M7, and the driving transistor M3 are all thin film transistors in the pixel circuit 20. The first reset transistor M5 and the second reset transistor M7 are both switching transistors. Among them, each thin film transistor includes a first pole, a second pole, and a control terminal, and the control terminal is used to control the conduction or non - conduction between the first pole and the second pole.

[0080] The pixel circuit 20 in the embodiment of the present application can have a circuit structure of 7T1C. Combining with the circuit diagram, it can be seen that the first pole and the second pole of the first reset transistor M5 respectively receive the first reset signal vref1 and are electrically connected to the first node N1, and the first node N1 is electrically connected to both the control terminal of the driving transistor M3 and the lower plate c1 of the storage capacitor cst. On this basis, the first reset transistor M5 is used to control whether the first reset signal vref1 is written into the first node N1, and is written into the control terminal of the driving transistor M3 and the lower plate c1 of the storage capacitor cst respectively through the first node N1. Thus, the first reset signal vref1 is a specific signal for realizing the reset of the control terminal of the driving transistor M3 and the reset of the lower plate c1 of the storage capacitor cst.

[0081] The first pole and the second pole of the second reset transistor M7 respectively receive the second reset signal vref2 and are electrically connected to the anode. The second reset transistor M7 is used to control whether the second reset signal vref2 is written to the anode. Thus, the second reset signal vref2 is a specific signal for realizing the reset of the anode.

[0082] In the embodiment of the present application, the first line segment 30 for transmitting the reset signal at least includes a first type of trace 31 and a second type of trace 32. By setting the first type of trace 31 to transmit the first reset signal vref1 and setting the second type of trace 32 to transmit the second reset signal vref2, there are longitudinal traces on the same layer as the second sub-segment 13 corresponding to both the first reset signal vref1 and the second reset signal vref2. This not only helps to improve the transmission reliability of the first reset signal vref1 but also helps to improve the transmission reliability of the second reset signal vref2, thereby improving the operation reliability of the pixel circuit 20.

[0083] Regarding the specific positional relationship between the multiple first type of traces 31 and the multiple second type of traces 32, the embodiment of the present application does not limit. Optionally, the multiple first type of traces 31 and the multiple second type of traces 32 are alternately distributed in the first direction X, that is, there is a second type of trace 32 between adjacent first type of traces 31, and there is a first type of trace 31 between adjacent second type of traces 32.

[0084] In other embodiments, please refer to Figure 6 and Figure 7 , the multiple first line segments 30 for transmitting the reset signal include a second type of trace 32 and a third type of trace 33. The second type of trace 32 is used to transmit the second reset signal, and the third type of trace 33 is used to transmit the third reset signal. Among them, the pixel circuit 20 includes a second reset transistor M7, a third reset transistor M8, and a driving transistor M3. The first pole of the second reset transistor M7 receives the second reset signal vref2, and the second pole is electrically connected to the anode. The first pole of the third reset transistor M8 receives the third reset signal dvh, and the second pole is electrically connected to the first pole of the driving transistor M3.

[0085] The pixel circuit 20 in the embodiment of the present application can have a circuit structure of 8T1C. Combining with the circuit diagram, it can be seen that the first pole and the second pole of the second reset transistor M7 respectively receive the second reset signal vref2 and are electrically connected to the anode. The second reset transistor M7 is used to control whether the second reset signal vref2 is written to the anode. Thus, the second reset signal vref2 is a specific signal for realizing the reset of the anode.

[0086] The first pole and the second pole of the third reset transistor M8 respectively receive the third reset signal dvh and are electrically connected to the second node N2, and the second node N2 is electrically connected to the first pole of the driving transistor M3. On this basis, the third reset transistor M8 is used to control whether the third reset signal dvh is written to the second node N2, and is written to and the first pole of the driving transistor M3 through the second node N2, thereby adjusting the bias state of the driving transistor M3 and improving the hysteresis characteristic of the driving transistor M3.

[0087] In the embodiment of the present application, the first line segment 30 for transmitting the reset signal at least includes a second type of trace 32 and a third type of trace 33. By setting the second type of trace 32 to transmit the second reset signal vref2 and setting the third type of trace 33 to transmit the third reset signal dvh, longitudinal traces on the same layer as the second sub-segment 13 exist corresponding to both the second reset signal vref2 and the third reset signal dvh. This not only helps improve the transmission reliability of the second reset signal vref2 but also helps improve the transmission reliability of the third reset signal dvh, thereby improving the operation reliability of the pixel circuit 20.

[0088] It should be noted that for the 8T1C circuit structure mentioned in the embodiment of the present application, longitudinal traces can be correspondingly set for both the second reset signal vref2 and the third reset signal dvh, while the first reset signal vref1 can be provided with a horizontal trace arranged on a different layer from the second sub-segment 13 and without a longitudinal trace. For the 7T1C circuit structure mentioned in the foregoing embodiment, since there is no third reset signal dvh, longitudinal traces can be correspondingly set for both the first reset signal vref1 and the second reset signal vref2.

[0089] In summary, combining the above two embodiments, it can be seen that the present application can flexibly adjust the types of reset signals in the first line segment 30 according to the types of pixel circuits 20 in the display panel, thereby improving the transmission reliability of specific types of reset signals. Among them, the above two embodiments are only two specific embodiments given for two common circuit structures and the corresponding common film layer layout methods for these two circuit structures, but the present application is not limited thereto. Exemplarily, in some other embodiments, multiple first line segments 30 for transmitting the reset signal can also transmit the same signal, that is, the first line segment 30 is only used to transmit the first power signal pvee and one type of reset signal.

[0090] In some embodiments, please refer to Figure 4 、 Figure 6 、 Figure 8 and Figure 9, the first winding portion 12 further includes a third sub-segment 14 extending along the first direction X. One end of the third sub-segment 14 is connected to the first sub-segment 11, and the other end is connected to the second sub-segment 13. The display panel includes a substrate 41, a first conductor layer 42 disposed on one side of the substrate 41, and a second conductor layer 43 located on the side of the first conductor layer 42 facing away from the substrate 41. The third sub-segment 14 is located within the first conductor layer 42, and the first sub-segment 11, the second sub-segment 13, and the first line segment 30 are all located within the second conductor layer 43.

[0091] The third sub-segment 14 is a wiring structure in the first winding portion 12 for connecting the first sub-segment 11 and the second sub-segment 13. In a single first signal line 10, the number of the third sub-segments 14 and the first sub-segments 11 is both two. The two third sub-segments 14 are respectively connected to the two first sub-segments 11, and the two third sub-segments 14 are respectively connected to both ends of the second sub-segment 13 in the second direction Y.

[0092] The third sub-segment 14 extends along the first direction X. Considering that if the first sub-segment 11 and the third sub-segment 14 are arranged in the same film layer, it is easy to cause the risk of contact interference between the third sub-segment 14 and the first line segment 30, the second sub-segment 13 in other first signal lines 10, and the first sub-segment 11. Therefore, in the embodiment of the present application, the third sub-segment 14 is arranged in a different film layer relative to the first sub-segment 11, the second sub-segment 13, and the first line segment 30, so as to reduce the interference risk of the third sub-segment 14 relative to other wiring structures and improve the reliability of signal transmission of each.

[0093] Specifically, the display panel includes a substrate 41, a first conductor layer 42, and a second conductor layer 43 that are sequentially stacked. The substrate 41 is a functional film layer that plays a supporting role. Both the first conductor layer 42 and the second conductor layer 43 include conductor materials. In addition to the first conductor layer 42 and the second conductor layer 43, the display panel may further include other conductor film layers. Among them, other conductor film layers may be included between the substrate 41 and the first conductor layer 42, other conductor film layers may also be included between the first conductor layer 42 and the second conductor layer 43, and a conductor film layer may also be included on the side of the second conductor layer 43 facing away from the substrate 41. The embodiment of the present application does not limit this.

[0094] Further, in the embodiments of the present application, the third sub-segment 14 is located within the first conductor layer 42, and the first sub-segment 11, the second sub-segment 13, and the first line segment 30 are all located within the second conductor layer 43. That is, the first sub-segment 11, the second sub-segment 13, and the first line segment 30 having the same extending direction are arranged in the same film layer, while the third sub-segment 14 having a different extending direction is arranged in a different film layer. In this way, the third sub-segment 14 can be connected to the first sub-segment 11 and the second sub-segment 13 through vias, and at the same time, the risk of contact interference of the third sub-segment 14 with respect to the first sub-segment 11, the second sub-segment 13, and the first line segment 30 can be reduced, improving the reliability of signal transmission for each.

[0095] In some embodiments, referring to Figure 4 , Figure 5 , Figure 8 and Figure 10 , the display panel further includes a first reset signal line 51 and a second reset signal line 52 extending along the first direction X. The first reset signal line 51 transmits a first reset signal vref1 and is electrically connected to a part of the first line segment 30. The second reset signal line 52 transmits a second reset signal vref2 and is electrically connected to a part of the first line segment 30. The first reset signal line 51 and the second reset signal line 52 are in the same layer and are located on the side of the first conductor layer 42 facing the substrate 41.

[0096] The first reset signal line 51 is a lateral trace for transmitting the first reset signal vref1. The first reset signal line 51 is electrically connected to a part of the first line segment 30, so that a part of the first line segment 30 can also transmit the first reset signal vref1. On this basis, the first line segments 30 located on both sides of the second sub-segment 13 can be respectively connected to the two first reset signal lines 51. In this way, even if the two first line segments 30 are not directly in contact and connected, they can still be used to transmit the same first reset signal vref1, meeting the transmission requirement of the first reset signal vref1. And since the first reset signal vref1 has both horizontal traces and vertical traces at the same time, the trace structure for transmitting the first reset signal vref1 can be in a mesh structure, thereby reducing the corresponding signal voltage drop and improving the reliability of signal transmission.

[0097] Similarly, the second reset signal line 52 is a horizontal trace for transmitting the second reset signal vref2. The second reset signal line 52 is electrically connected to a part of the first segment 30, so that the part of the first segment 30 can also transmit the second reset signal vref2. On this basis, the first segments 30 located on both sides of the second sub-segment 13 can be respectively connected to the two second reset signal lines 52. In this way, even if the two first segments 30 are not directly in contact and connected, they can still be used to transmit the same second reset signal vref2, meeting the transmission requirement of the second reset signal vref2. And since the second reset signal vref2 has both horizontal and vertical traces, the trace structure for transmitting the second reset signal vref2 can be a mesh structure, thereby reducing the corresponding signal voltage drop and improving the reliability of signal transmission.

[0098] In the embodiment of the present application, by providing the first reset signal line 51 and the second reset signal line 52 extending along the first direction X, the signal transmission requirement of the corresponding first segment 30 can be met, and at the same time, it helps to reduce the signal voltage drop of the first reset signal vref1 and the second reset signal vref2, improving the reliability of signal transmission. Further, considering that the first reset signal line 51 and the second reset signal line 52 have the same extension direction, both signal lines are selected to be disposed on the side of the first conductor layer 42 facing the substrate 41, thereby reducing the risk of contact interference between the first reset signal line 51 and the second reset signal line 52 relative to other vertical traces, and setting the two signal lines on the same layer helps to reduce the space occupied by other film layers, facilitating the thinning design of the display panel.

[0099] For the specific film layer form in the display panel in the embodiment of the present application, the embodiment of the present application does not make any restrictions. Combining the foregoing content, the pixel circuit 20 in the embodiment of the present application can have a 7T1C circuit structure. Further, for example, the display panel provided in the embodiment of the present application can be applicable to the LTPS (Low Temperature Poly-Silicon) technology. Specifically, the LTPS technology only includes LTPS-TFTs, that is, the display panel only includes thin film transistors using low temperature poly-silicon as the active layer.

[0100] On this basis, as Figure 8 and Figure 10 shown, the display panel may include a low temperature poly-silicon active layer 47, a fourth conductor layer 45, a third conductor layer 44, a first conductor layer 42, and a second conductor layer 43 stacked in sequence along the direction away from the substrate 41. Among them, the control terminal of the thin film transistor and the lower electrode c1 of the storage capacitor cst are both located in the fourth conductor layer 45, while the upper electrode of the storage capacitor cst, the first reset signal line 51, and the second reset signal line 52 are all located in the third conductor layer 44.

[0101] In some other embodiments, refer to Figure 6 , Figure 7 , Figure 9 and Figure 11 , the display panel further includes a second reset signal line 52 and a third reset signal line 53 extending along the first direction X. The second reset signal line 52 transmits a second reset signal vref2 and is electrically connected to a part of the first segment 30. The third reset signal line 53 transmits a third reset signal dvh and is electrically connected to a part of the first segment 30. The second reset signal line 52 and the third reset signal line 53 are on the same layer and are located on the side of the first conductor layer 42 facing the substrate 41.

[0102] The second reset signal line 52 is a horizontal trace for transmitting the second reset signal vref2. The second reset signal line 52 is electrically connected to a part of the first segment 30, so that a part of the first segment 30 can also transmit the second reset signal vref2. On this basis, the first segments 30 located on both sides of the second sub-segment 13 can be respectively connected to two second reset signal lines 52. In this way, even if the two first segments 30 are not directly connected in contact, they can still be used to transmit the same second reset signal vref2, meeting the transmission requirement of the second reset signal vref2. And because the second reset signal vref2 has both horizontal and vertical traces, the trace structure for transmitting the second reset signal vref2 can be a mesh structure, thereby reducing the corresponding signal voltage drop and improving the reliability of signal transmission.

[0103] Similarly, the third reset signal line 53 is a horizontal trace for transmitting the third reset signal dvh. The third reset signal line 53 is electrically connected to a part of the first segment 30, so that a part of the first segment 30 can also transmit the third reset signal dvh. On this basis, the first segments 30 located on both sides of the second sub-segment 13 can be respectively connected to two third reset signal lines 53. In this way, even if the two first segments 30 are not directly connected in contact, they can still be used to transmit the same third reset signal dvh, meeting the transmission requirement of the third reset signal dvh. And because the third reset signal dvh has both horizontal and vertical traces, the trace structure for transmitting the third reset signal dvh can be a mesh structure, thereby reducing the corresponding signal voltage drop and improving the reliability of signal transmission.

[0104] In the embodiments of the present application, by providing a second reset signal line 52 and a third reset signal line 53 extending along the first direction X, the signal transmission requirements corresponding to the first line segment 30 can be met. At the same time, it also helps to reduce the signal voltage drop of the second reset signal vref2 and the third reset signal dvh, improving the reliability of signal transmission. Further, considering that the second reset signal line 52 and the third reset signal line 53 have the same extension direction, both signal lines are selected to be disposed on the side of the first conductor layer 42 facing the substrate 41, thereby reducing the risk of contact interference between the second reset signal line 52 and the third reset signal line 53 relative to other longitudinal traces. And setting the two signal lines on the same layer helps to reduce the space occupied by other film layers, facilitating the thinning design of the display panel.

[0105] Regarding the specific film layer form in the display panel in the embodiments of the present application, the embodiments of the present application do not make any restrictions. Combining the foregoing content, it can be seen that the pixel circuit 20 in the embodiments of the present application can have a circuit structure of 8T1C. Further, for example, the display panel provided by the embodiments of the present application can be applicable to LTPO (Low Temperature Polysilicon Oxide) technology. Specifically, LTPO technology is only a hybrid product of LTPS-TFT and IGZO (Indium Gallium Zinc Oxide)-TFT, that is, the display panel includes both thin film transistors using low temperature polysilicon as the active layer and transistors using metal oxides as the active layer.

[0106] On this basis, as Figure 9 and Figure 11 shown, the display panel may include a low temperature polysilicon active layer 47, a fourth conductor layer 45, a third conductor layer 44, a metal oxide active layer 48, a fifth conductor layer 46, a first conductor layer 42, and a second conductor layer 43 that are sequentially stacked in a direction away from the substrate 41. Among them, the control terminals of some thin film transistors and the lower electrode c1 of the storage capacitor cst are both located in the fourth conductor layer 45, the upper electrode of the storage capacitor cst, the second reset signal line 52, and the third reset signal line 53 are all located in the third conductor layer 44, and the control terminals of other thin film transistors are located in the fifth conductor layer 46. Among them, the first reset signal vref1 only corresponds to the horizontal traces located in the third conductor layer 44 and does not include the vertical traces disposed in the second conductor layer 43.

[0107] In some embodiments, as Figure 10As shown, the pixel circuit 20 includes a driving transistor M3. The distance D1 between adjacent second sub-segments 13 in the first direction X, and the distance D2 between two driving transistors M3 in two adjacent pixel circuits 20 in the first direction X, where D2 > D1.

[0108] As can be seen from the accompanying drawings, the lower plate c1 of the storage capacitor cst is multiplexed as the control terminal of the driving transistor M3. On this basis, the distance D2 can represent the distance between two lower plates c1 in adjacent pixel circuits 20 in the first direction X, while the distance D1 can represent the distance between two corresponding second sub-segments 13 in adjacent pixel circuits 20 in the first direction X.

[0109] In the embodiment of the present application, D2 > D1 indicates that the projections of adjacent second sub-segments 13 in the thickness direction Z of the display panel are all located between the projections of adjacent lower plates c1. This design enables the second sub-segment 13 to correspond to the edge region of the pixel circuit 20 in the first direction X, thereby reducing the overlapping area of the second sub-segment 13 with the structure at the central region of the pixel circuit 20, such as the driving transistor M3, reducing its adverse effects on the operation of the pixel circuit 20, and improving the light-emitting reliability of the display panel.

[0110] It should be noted that the solution provided in the embodiment of the present application is applicable to Figure 9 the case where adjacent pixel circuits 20 shown adopt a mirror design, that is, adjacent pixel circuits 20 in the first direction X are symmetrically arranged with respect to a virtual straight line parallel to the second direction Y. Specifically, a virtual straight line is provided between adjacent pixel circuits 20 in the first direction X, and the distance between the lower plate c1 of the storage capacitor cst of one of the adjacent pixel circuits 20 and the virtual straight line in the first direction X is equal to the distance between the lower plate c1 of the storage capacitor cst of the other adjacent pixel circuit 20 and the virtual straight line in the first direction X. On this basis, the adjacent second sub-segments 13 corresponding to adjacent pixel circuits 20 are respectively arranged on both sides of the virtual straight line. Further optionally, the adjacent second sub-segments 13 are at the same distance from the virtual straight line in the first direction X.

[0111] In some embodiments, the pixel circuit 20 includes a driving transistor M3, and the adjacent second sub-segments 13 are located on the same side of the driving transistor in the first direction X and are at the same distance from the corresponding driving transistor M3 in the first direction X.

[0112] It should be noted that the "located on the same side of the driving transistor" mentioned in the embodiment of the present application means: on the same side of the control terminal of the driving transistor M3 in the first direction X, that is, on the same side of the lower plate c1 of the storage capacitor cst in the first direction X.

[0113] In the embodiment of the present application, the second sub-segment 13 is not arranged overlapping with the driving transistor M3, but is located on one side of the driving transistor. This design enables the second sub-segment 13 to correspond to the edge region of the pixel circuit 20 in the first direction X, thereby reducing the overlapping area of the second sub-segment 13 with the structure at the central region of the pixel circuit 20, such as the driving transistor M3, reducing its adverse effect on the operation of the pixel circuit 20, and improving the light-emitting reliability of the display panel.

[0114] Furthermore, adjacent second sub-segments 13 are respectively located on the same side of the corresponding driving transistor, and have the same distance from the corresponding driving transistor M3 in the first direction X, that is, different second sub-segments 13 are respectively arranged corresponding to the same region of the corresponding pixel circuit 20. This helps to improve the position reliability of the multiple second sub-segments 13 relative to the pixel circuit 20 and reduces the design and preparation difficulty of the second sub-segments 13.

[0115] It should be noted that the solution provided in the embodiment of the present application is applicable to the case where the projected morphologies of adjacent pixel circuits 20 in the thickness direction Z of the display panel are the same. On this basis, the solution provided in the embodiment of the present application helps to further improve the structural similarity of the display panel at different positions of the pixel circuit 20, thereby further reducing the design and preparation difficulty of the display panel.

[0116] In some embodiments, as Figure 10 shown, the display panel further includes a second signal line 60. The second signal line 60 extends along the second direction Y and is located in the second region A2. The second signal line 60 is located on either side of the first region A1 in the first direction X. The pixel circuit 20 includes a storage capacitor cst. In the thickness direction Z of the display panel, the projections of the second sub-segment 13 and the second signal line 60 are respectively arranged on both sides of the storage capacitor cst in the first direction X.

[0117] Similar to the first signal line 10, the second signal line 60 is also located in the second region A2 and extends along the second direction Y. However, the difference is that the second signal line 60 is completely located on either side of the first region A1 in the first direction X, that is, the extension path of the second signal line 60 does not need to avoid the design of the first region A1. Among them, the first signal line 10 and the second signal line 60 can be used to transmit the same signal, or they can also transmit different signals respectively. The embodiment of the present application does not limit this. Optionally, both the first signal line 10 and the second signal line 60 are used to transmit data signals.

[0118] For multiple second signal lines 60, the multiple second signal lines 60 can be disposed on different sides of the first region A1 along the first direction X, and some of the second signal lines 60 can extend through the first sub-region A21, that is, some of the second signal lines 60 can be overlapped with the second sub-segment 13 in the same circuit column 200. Further, since the second signal line 60 and the second sub-segment 13 can have the same extending direction, they can be disposed on the same layer. On this basis, in order to reduce the influence between the second signal line 60 and the second sub-segment 13 and meet the respective layout requirements of the two, the embodiments of the present application also adjust the positions of the two relative to the pixel circuit 20.

[0119] Specifically, the pixel circuit 20 includes a storage capacitor cst, and the projections of the second sub-segment 13 and the second signal line 60 are located on both sides of the projection of the storage capacitor cst along the first direction X. The storage capacitor cst includes a lower plate c1 and an upper plate on a side of the lower plate c1 away from the substrate 41, and the "projection of the storage capacitor cst" mentioned in the embodiments of the present application refers to: the projection of the lower plate c1 in the thickness direction Z of the display panel.

[0120] In the embodiments of the present application, by corresponding the projections of the second sub-segment 13 and the second signal line 60 to be located on both sides of the projection of the storage capacitor cst, the second sub-segment 13 and the second signal line 60 overlapped with a single circuit column 200 can have a certain distance in the first direction X, thereby reducing the risk of contact interference between the second sub-segment 13 and the second signal line 60 and reducing the risk of signal interference between the two, and improving the operation reliability of the display panel.

[0121] In some embodiments, please refer to Figure 12a and Figure 12b , the number of the first regions A1 is multiple, the multiple first regions A1 are spaced along the first direction X, and a first sub-region A21 is disposed between adjacent first regions A1.

[0122] There are multiple first regions A1, and the sizes and shapes of different first regions A1 can be the same, or the sizes and shapes of different first regions A1 can also be different. Among them, Figure 12a shows a case where two first regions A1 have the same shape and are both circular, and Figure 12b shows a case where one of the first regions A1 is oval and the other first region A1 is circular.

[0123] In the display device, photosensitive components are correspondingly disposed on the back of the display panel and corresponding to the multiple first regions A1. Since there can be multiple size relationships between a single photosensitive component and a single first region A1, the multiple first regions A1 can be correspondingly disposed with the same photosensitive component, or the multiple first regions A1 can also be correspondingly disposed with different photosensitive elements.

[0124] A plurality of first regions A1 are arranged at intervals along a first direction X. Under normal circumstances, the region between adjacent first regions A1 often has a relatively small size in the first direction X, and it is often very difficult for the size of this region to meet the requirements of a conventional wire-wrapping design scheme. Especially for Figure 12b the first region A1 in the shape of an ellipse, the elliptical setting makes a larger number of first signal lines 10 need to bypass the first region A1. Therefore, a larger number of wire-wrapping structures need to be integrated between adjacent first regions A1, resulting in an increase in the difficulty of wire-wrapping design.

[0125] In view of this, in the embodiment of the present application, the wire-wrapping method in the region between adjacent first regions A1 is adjusted, so that at least some adjacent second sub-segments 13 and adjacent circuit columns 200 are respectively overlapped, thereby reducing the distance between adjacent second sub-segments 13, enabling more second sub-segments 13 to be arranged between adjacent first regions A1, so as to meet the actual wire-wrapping needs. Further, on the premise of meeting the wire-wrapping needs, the size of some spaces between adjacent first regions A1 can be selectively reduced, so as to increase the area of other display regions in the display panel and improve the display effect.

[0126] It should be noted that in the embodiment of the present application, the wire-wrapping structures corresponding to all the first regions A1 can be only arranged in the first sub-region A21 between adjacent first regions A1, or some wire-wrapping structures are arranged in the first sub-region A21 between adjacent first regions A1, and some wire-wrapping structures are arranged in the region around the first region A1 and not between adjacent first regions A1. The embodiment of the present application does not limit this.

[0127] In addition, the embodiment of the present application only provides the case where the first sub-region A21 is located between adjacent first regions A1. However, in some other embodiments, the first sub-region A21 can also be located on one side of the first region A1 along the first direction X and not in the region between adjacent first regions A1, as long as at least some adjacent second sub-segments 13 and adjacent circuit columns 200 are respectively overlapped in this region.

[0128] In some embodiments, the display panel further includes a light-emitting unit P, and the pixel circuit 20 located in the first sub-region A21 is electrically connected to the light-emitting unit P; and / or, the light-emitting unit P located in the first region A1 is electrically connected to the pixel circuit 20 in the first sub-region A21.

[0129] Combined with the accompanying drawings and the foregoing content, it can be seen that both the second sub-segments 13 and the pixel circuits 20 exist in the first sub-region A21. For the pixel circuit 20, the pixel circuit 20 located in the first sub-region A21 can be used to control the light-emitting unit P. On this basis, there can be various positional relationships between the pixel circuit 20 located in the first sub-region A21 and the corresponding light-emitting unit P.

[0130] Specifically, in one case, at least some of the pixel circuits 20 in the first sub-region A21 can be used to control the light-emitting units P in the first sub-region A21. In this case, in the thickness direction Z of the display panel, the projection of the pixel circuits 20 in the first sub-region A21 overlaps with the projection of the corresponding light-emitting units P. In another case, light-emitting units P are provided in the first region A1, and at least some of the pixel circuits 20 in the first sub-region A21 are used to control the light-emitting units P in the first region A1. In this case, in the thickness direction Z of the display panel, the projections of the pixel circuits 20 in the first sub-region A21 and the corresponding light-emitting units P are misaligned.

[0131] In the embodiments of the present application, the pixel circuits 20 located in the first sub-region A21 can be used to control the light-emitting units P located in the first sub-region A21 to achieve the light-emitting function, or can also be used to control the light-emitting units P located in the first region A1 to achieve the light-emitting function. On this basis, the relative positional relationship between the pixel circuits 20 located in the first sub-region A21 and the corresponding light-emitting units P can be flexibly adjusted to meet different display requirements.

[0132] Of course, in another embodiment, the pixel circuits 20 in the first sub-region A21 are virtual pixel circuits 20.

[0133] Different from the above embodiments, the pixel circuits 20 in the first sub-region A21 are not used to control the light-emitting units P. The virtual pixel circuits 20 located in the first sub-region A21 can maintain the same or similar circuit structure, function, and performance as the effective pixel circuits 20 in other regions, so as to match the performance of the effective pixel circuits 20 and improve the stability and consistency of the display panel.

[0134] It should be noted that although the virtual pixel circuits 20 do not control the light-emitting units P, in order to improve circuit consistency, the signal traces for transmitting the data signal data and the signal traces for transmitting the second power supply signal pvdd also need to pass through the virtual pixel circuits 20, that is, need to pass through the first sub-region A21. On this basis, the second sub-segment 13 can extend through the pixel circuits 20 in the first sub-region A21, so that the position where the pixel circuits 20 are located can have the same trace layout form as the position where the pixel circuits 20 in other regions are located, improving the consistency of the display panel.

[0135] In some embodiments, please refer to Figures 13 to 15, the second region A2 further includes a second sub-region A22. The second sub-region A22 is located on one side of the first region A1 in the first direction X, and there is no overlap between the first sub-region A21 and the second sub-region A22. The display panel further includes a third signal line 70 disposed in the second region A2. The third signal line 70 extends along the second direction Y and includes a second winding portion 71. The second winding portion 71 includes a fourth sub-segment 72 that extends along the second direction Y and is located in the second sub-region A22. Wherein, in the thickness direction Z of the display panel, adjacent fourth sub-segments 72 are alternately arranged with an interval; or, adjacent fourth sub-segments 72 are alternately arranged with adjacent circuit columns 200.

[0136] Similar to the first sub-region A21, the second sub-region A22 is also a region located on the periphery of the hole region and requires a winding structure. The first sub-region A21 and the second sub-region A22 are both located on one side of the first region A1 along the first direction X. The first sub-region A21 and the second sub-region A22 can have various positional relationships. Taking the example that both the first sub-region A21 and the second sub-region A22 exist on the periphery of a single first region A1, the first sub-region A21 and the second sub-region A22 can be respectively located on both sides of the first region A1, or the first sub-region A21 can also be located between the first region A1 and the second sub-region A22, or the second sub-region A22 can also be located between the first region A1 and the first sub-region A21. Further, as Figure 13 and Figure 15 shown, when the display panel includes multiple first regions A1, the first sub-region A21 can be located between adjacent first regions A1, and the second sub-region A22 can be located in the region on the periphery of the first region A1 and between non-adjacent first regions A1.

[0137] Similar to the first signal line 10, the main structure in the third signal line 70 also needs to extend along the second direction Y, and the third signal line 70 needs to bypass the first region A1. However, the difference is that the first winding portion 12 in the first signal line 10 is located in the first sub-region A21, and the second winding portion 71 in the third signal line 70 is located in the second sub-region A22. The second winding portion 71 includes a fourth sub-segment 72 that extends along the second direction Y and is located in the second sub-region A22. Optionally, the fourth sub-segment 72 is arranged on the same layer as the second sub-segment 13, that is, both include the same material and are formed together in the same process.

[0138] In the embodiment of the present application, the display panel includes at least two regions for setting the winding structure, namely the first sub-region A21 and the second sub-region A22. Combining the foregoing content, it can be seen that in the first sub-region A21, at least some adjacent second sub-segments 13 are alternately arranged with adjacent circuit columns 200, which helps to increase the distribution density of the second sub-segments 13 in the first sub-region A21, so that more winding structures can be arranged in the first sub-region A21.

[0139] On this basis, considering that a relatively large number of winding structures can be provided in the first sub-region A21, a relatively small number of winding structures can be provided in the second sub-region A22. Thus, as shown in Figure 13 and Figure 14 , it can be selected to overlap two adjacent fourth sub-segments 72 with two circuit columns 200 arranged at intervals. Of course, in some other cases, for situations such as too many windings or too small an area of the second sub-region A22, as shown in Figure 15 , it can also be selected to overlap an adjacent fourth sub-segment 72 with an adjacent circuit column 200, so as to meet the layout requirements in different situations, with strong flexibility and practicability.

[0140] In some embodiments, as shown in Figure 13 and Figure 15 , the display panel further includes a second line segment 80 that is on the same layer as the fourth sub-segment 72 and is insulated. The second line segment 80 extends along the second direction Y and is located between adjacent fourth sub-segments 72. Among them, in the thickness direction Z of the display panel, the second line segment 80 and the fourth sub-segment 72 are respectively overlapped with different circuit columns 200.

[0141] In the embodiment of the present application, for the case where there is a relatively large distance between adjacent fourth sub-segments 72 in the second sub-region A22, the second line segment 80 is added in the display panel in the embodiment of the present application. Different from the first line segment 30, the second line segment 80 can extend through the second sub-region A22. In this way, both the second line segment 80 and the fourth sub-segment 72 can exist in the second sub-region A22 at the same time. Further, by overlapping the two with different circuit columns 200 respectively, the second line segment 80 and the fourth sub-segment 72 can be spaced apart in the first direction X, thereby reducing the risk of contact interference between the two, so that the second line segment 80 and the fourth sub-segment 72 can be arranged on the same layer. Optionally, in the second sub-region A22, a plurality of second line segments 80 and a plurality of fourth sub-segments 72 are alternately distributed in the first direction X.

[0142] In some alternative embodiments, the display panel further includes a third line segment. Two third line segments are arranged on both sides of the fourth sub-segment 72 along the second direction Y, and both of them are overlapped with the same circuit column 200. Further optionally, the second line segment 80 and the third line segment are respectively overlapped with different circuit columns 200.

[0143] The specific type of the signal transmitted by the second line segment 80 is not limited in the embodiment of the present application. In some embodiments, at least part of the second line segment 80 is used to transmit a first power supply signal pvee; and / or, at least part of the second line segment 80 is used to transmit a reset signal.

[0144] In the embodiments of the present application, at least one of the longitudinal traces for transmitting the first power signal pvee and the reset signal can extend through the second sub-region A22, which helps to improve the reliability of the corresponding signal transmission. Further optionally, when the second line segment 80 and the third line segment exist in the display panel at the same time, one of the second line segment 80 and the third line segment is used to transmit the first power signal pvee, and the other is used to transmit the reset signal.

[0145] In some embodiments, referring to Figure 2 and Figure 16 , the display panel further includes a third region A3, the third region A3 is disposed around the second region A2, and the third region A3 includes a fan-out region A31 located on one side of the second region A2 along the second direction Y. The display panel further includes a fourth signal line 90, the fourth signal line 90 is located on either side of the first region A1 along the first direction X, and the fourth signal line 90 is electrically connected to a fan-out line R located in the fan-out region A31 through a third winding portion 91. The third winding portion 91 is located in the second region A2, and the third winding portion 91 includes a fifth sub-segment 92 extending along the first direction X and a sixth sub-segment 93 extending along the second direction Y. Among them, Figure 16 Six sixth sub-segments 93 are shown in

[0146] and the three sixth sub-segments 93 on the left are adjacent to each other, and the three sixth sub-segments 93 on the right are adjacent to each other.

[0147] As can be seen in combination with the drawings, the fan-out region A31 is a local region of the third region A3 located at the lower border position of the display panel. The size of the fan-out region A31 in the first direction X is often smaller than the size of the second region A2 in the first direction X, and there may be an overlap between the first region A1 and the fan-out region A31 in the second direction Y. The fourth signal line 90 is a longitudinal trace for transmitting a specific signal in the display panel, and the fourth signal line 90 is a sub-signal line located on either side of the first region A1 along the first direction X. Among them, the fourth signal line 90 can transmit the same type of signal as the first signal line 10, or the two can also transmit different types of signals.

[0148] In the embodiment of the present application, a fan-out line R is provided in the fan-out region A31. By providing a third winding portion 91, and setting the third winding portion 91 to include a fifth sub-segment 92 extending in the first direction X and a sixth sub-segment 93 extending in the second direction Y, the third winding portion 91 can have a certain extension dimension in the first direction X and also have a certain extension dimension in the second direction Y. On this basis, the fan-out line R is inclined, and only by means of the third winding portion 91 can the electrical connection between the fourth signal line 90 and the wiring structure located in the fan-out region A31 be satisfied. Further, the third winding portion 91 is located in the second region A2, rather than in the third region A3, which helps to reduce the size of the third region A3, save the wiring space at the lower border of the display panel, and helps to achieve a narrow border effect.

[0149] It should be noted that Figure 16 shows that the fan-out line R is connected to the sixth sub-segment 93. Among them, the fan-out line R and the sixth sub-segment 93 are usually located in different film layers, and in order to better distinguish the two wiring structures, Figure 16 the fan-out line R and the sixth sub-segment 93 are respectively indicated by thick lines and un-bolded lines.

[0150] In addition, in addition to the fourth signal line 90 being able to be electrically connected to the fan-out line R through the third winding portion 91, the first signal line 10 can also be electrically connected to the wiring structure located in the fan-out region A31 through the third winding portion 91, or if the first signal line 10 and the corresponding fan-out line R can correspond in the second direction Y, they can also be electrically connected to each other by a direct connection method without passing through the third winding portion 91.

[0151] In some embodiments, in the thickness direction Z of the display panel, at least part of the adjacent sixth sub-segments 93 and the adjacent circuit columns 200 are overlapped and arranged respectively.

[0152] In the embodiment of the present application, in addition to adjusting the winding structure around the first region A1, the winding structure near the fan-out region A31 in the second region A2 can also be adjusted and designed. At least part of the adjacent sixth sub-segments 93 are arranged to overlap with the adjacent circuit columns 200 respectively, which helps to reduce the distance between the adjacent sixth sub-segments 93, improve the distribution density of multiple sixth sub-segments 93 in a unit area, and meet the wiring layout requirements in the display panel.

[0153] In some embodiments, please refer to Figures 16 to 19. The display panel further includes a first line segment 30 that is on the same layer as the second sub-segment 13 and the sixth sub-segment 93 and is insulated. The first line segment 30 extends along the second direction Y and is located on both sides of the second sub-segment 13. Among them, the first line segment 30 is located on the side of the sixth sub-segment 93 facing the second sub-segment 13, and in the thickness direction Z of the display panel, the first line segment 30 and the sixth sub-segment 93 are respectively overlapped with the same circuit column 200. In Figure 16 and Figure 17 In order to facilitate the distinction between the first line segment 30 and the fan-out line R, the first line segment 30 is schematically shown in the form of a dotted line.

[0154] It should be noted that in Figures 16 to 1 9 only the part of the sixth sub-segment 93 corresponding to the first line segment 30 is schematically shown, but the sixth sub-segment 93 corresponding to the first sub-segment 11 and the sixth sub-segment 93 corresponding to other wiring structures are not shown. In addition, taking the first signal line 10 as a data line for transmitting a data signal data as an example, in Figures 16 to 18 only the part of the data line including the second sub-segment 13 is shown, but other data lines are not shown.

[0155] In the embodiment of the present application, the third winding portion 91 includes a sixth sub-segment 93, and the sixth sub-segment 93 and the first line segment 30 can be on the same layer and have the same extension direction. On this basis, in order to reduce the interference effect between the sixth sub-segment 93 and the first line segment 30, the embodiment of the present application sets the first line segment 30 on the side of the sixth sub-segment 93 facing the second sub-segment 13, that is, at least part of the first line segment 30 does not extend to the edge position of the second area A2 close to the fan-out area A31, so as to achieve the interval between the sixth sub-segment 93 and the first line segment 30 and meet the insulation requirements of the two.

[0156] It should be noted that Figures 16 to 1 9 shows different wiring methods in a variety of different display panels on the premise that at least part of the adjacent sixth sub-segments 93 and the adjacent circuit columns 200 are respectively overlapped. Specifically, Figure 16 shows the case where the display panel only includes one first area A1, and the first sub-area A21 is located on at least one side of the first area A1 along the first direction X. In this case, at least part of the sixth sub-segments 93 can be respectively overlapped with the first line segment 30 with respect to the same circuit column 200.

[0157] And Figure 17 and Figure 18All show that the display panel includes a plurality of first regions A1, and a first sub-region A21 is located between adjacent first regions A1, and a second sub-region A22 is located on the same side of all the first regions A1. Among them, both the first line segment 30 and the second line segment 80 are schematically shown in the form of dotted lines. In this case, all the first line segments 30 can be used to transmit the first power signal pvee, or some of the first line segments 30 are used to transmit the first power signal pvee, and some of the first line segments 30 are used to transmit the reset signal.

[0158] Further, as Figure 17 shown, some of the sixth sub-segments 93 and the first line segment 30 are respectively overlapped with the same circuit column 200, and some of the sixth sub-segments 93 and the second line segment 80 are respectively overlapped with the same circuit column 200. Or as Figure 18 shown, the sixth sub-segments 93 can only be respectively overlapped with the second line segment 80 with the same circuit column 200, and each of the sixth sub-segments 93 is not respectively overlapped with the first line segment 30 with the same circuit column 200.

[0159] Figure 19a shows the relationship between a plurality of second sub-segments 13 and a plurality of circuit columns 200 in the embodiment of the present application. At least some adjacent second sub-segments 13 and adjacent circuit columns 200 are respectively overlapped. Figure 19b shows the relationship between a plurality of sixth sub-segments 93 and a plurality of circuit columns 200. At least some adjacent sixth sub-segments 93 and adjacent circuit columns 200 are respectively overlapped.

[0160] In addition, in combination with Figure 17 and FIG. 19, it can be seen that Figure 17 shows the situation where at least some adjacent fourth sub-segments 72 and adjacent circuit columns 200 are respectively overlapped. Of course, in some other embodiments, on the basis of Figure 17 , at least some adjacent fourth sub-segments 72 and spaced circuit columns 200 can be respectively overlapped. Similarly, in combination with Figure 18 and FIG. 19, it can be seen that Figure 18 shows the situation where at least some adjacent fourth sub-segments 72 and spaced circuit columns 200 are respectively overlapped. Of course, in some other embodiments, on the basis of Figure 18 , at least some adjacent fourth sub-segments 72 and adjacent circuit columns 200 can be respectively overlapped.

[0161] In some embodiments, please refer to Figures 20 to 2 3. In the thickness direction Z of the display panel, at least some adjacent sixth sub-segments 93 and spaced circuit columns 200 are respectively overlapped. Among them, Figures 20 to 2Only a part of the sixth sub-segment 93 corresponding to the first line segment 30 is schematically shown in 3, but the sixth sub-segment 93 corresponding to the first sub-segment 11 and the sixth sub-segment 93 corresponding to other wiring structures are not shown. In addition, taking the first signal line 10 as an example of a data trace for transmitting a data signal data, in Figures 20 to 2 Only a part of the data trace including the second sub-segment 13 is shown in 3, but other data traces are not shown.

[0162] In the embodiment of the present application, in view of the situation that the area for setting the third winding portion 91 in the second region A2 may have a relatively large spatial dimension, etc., the positions of adjacent sixth sub-segments 93 can be flexibly adjusted so that at least some adjacent sixth sub-segments 93 are respectively overlapped with the spaced circuit columns 200, thereby increasing the distance between adjacent sixth sub-segments 93 and reducing the manufacturing difficulty.

[0163] It should be noted that different display panels may respectively have different wiring methods. On this basis, in some specific wiring methods, at least some adjacent sixth sub-segments 93 can be selected to be respectively overlapped with adjacent circuit columns 200, while in some other wiring methods, at least some adjacent sixth sub-segments 93 can be selected to be respectively overlapped with the spaced circuit columns 200, so as to respectively match the winding requirements of different display panels, with strong flexibility.

[0164] In some embodiments, please refer to Figures 1 to 3 and Figure 20 , the display panel further includes a first line segment 30 that is on the same layer as the second sub-segment 13 and the sixth sub-segment 93 and is insulated. The first line segment 30 extends along the second direction Y and is located on both sides of the second sub-segment 13. Among them, two adjacent first line segments 30 are respectively a first trace 34 and a second trace 35. The first trace 34 is located on the side of the sixth sub-segment 93 facing the second sub-segment 13. In the thickness direction Z of the display panel, the projections of the first trace 34 and the sixth sub-segment 93 respectively overlap with the same circuit column 200. The second trace 35 is located between adjacent sixth sub-segments 93 and extends to the fan-out region A31.

[0165] In the embodiment of the present application, the projections of adjacent second sub-segments 13 and the projections of adjacent circuit columns 200 overlap respectively. The projections of adjacent sixth sub-segments 93 and the projections of the circuit columns 200 arranged at intervals overlap respectively. On this basis, the first line segment 30 can include two types, namely the first trace 34 and the second trace 35. Among them, the projection of the first trace 34 overlaps with the projection of the second sub-segment 13 and the projection of the sixth sub-segment 93 with respect to the projection of the same circuit column 200. Therefore, in the embodiment of the present application, the first trace 34 is arranged on the side of the sixth sub-segment 93 facing the second sub-segment 13 to meet the insulation requirement between the first trace 34 and the sixth sub-segment 93. For the second trace 35, since the second trace 35 is located between the sixth sub-segments 93, even if the second trace 35 extends into the fan-out area A31, it will not interfere with the sixth sub-segment 93. Thus, the second trace 35 can extend into the fan-out area A31 to increase the extension length of the second trace 35 and the reliability of the corresponding signal transmission.

[0166] In some embodiments, the first trace 34 is used to transmit the first power signal pvee, and the second trace 35 is used to transmit the reset signal. In other words, the longitudinal trace for transmitting the first power signal pvee will not extend into the fan-out area A31 to meet the placement requirement of the sixth sub-segment 93, while the longitudinal trace for transmitting the reset signal can extend into the fan-out area A31.

[0167] In the embodiment of the present application, the presence of the sixth sub-segment 93 does not affect the extension path of the second trace 35. Thus, the second trace 35 can extend into the fan-out area A31 and overlap with more pixel circuits 20 in a single circuit column 200 respectively, thereby improving the transmission reliability of the reset signal in the second trace 35.

[0168] It should be noted that Figures 20 to 2 3 shows different wiring methods in a variety of different display panels on the premise that at least some adjacent sixth sub-segments 93 and the spaced circuit columns 200 overlap respectively. Specifically, Figure 20 shows the case where the display panel only includes one first area A1, and the first sub-area A21 is located on at least one side of the first area A1 along the first direction. In this case, at least some sixth sub-segments 93 can overlap with the first line segment 30 with respect to the same circuit column 200 respectively.

[0169] While Figure 21 and Figure 22All show that the display panel includes a plurality of first regions A1, and the first sub-region A21 is located between adjacent first regions A1, and the second sub-region A22 is located on the same side of all the first regions A1. In this case, all the first line segments 30 may include a first trace 34 and a second trace 35. The first trace 34 is used to transmit a first power signal pvee, and the second trace 35 is used to transmit a reset signal.

[0170] Further, as Figure 21 shown, a part of the sixth sub-segment 93 and the first line segment 30 are respectively overlapped and arranged with respect to the same circuit column 200, and a part of the sixth sub-segment 93 and the second line segment 80 are respectively overlapped and arranged with respect to the same circuit column 200. Or as Figure 22 shown, all the sixth sub-segments 93 may be only overlapped and arranged with respect to the second line segment 80 respectively with respect to the same circuit column 200, and each sixth sub-segment 93 is not overlapped and arranged with the first line segment 30 respectively with respect to the same circuit column 200.

[0171] Figure 23a Shows the relationship between a plurality of second sub-segments 13 and a plurality of circuit columns 200 in the embodiment of the present application. At least some adjacent second sub-segments 13 and adjacent circuit columns 200 are respectively overlapped and arranged. Figure 23b Shows the relationship between a plurality of sixth sub-segments 93 and a plurality of circuit columns 200. At least some adjacent sixth sub-segments 93 and spaced circuit columns 200 are respectively overlapped and arranged.

[0172] In addition, combining Figure 21 and FIG. 23, it can be seen that Figure 21 shows the situation where at least some adjacent fourth sub-segments 72 and adjacent circuit columns 200 are respectively overlapped and arranged. Of course, in some other embodiments, on the basis of Figure 21 , at least some adjacent four sub-segments 72 and spaced circuit columns 200 can be respectively overlapped and arranged. Similarly, combining FIG. 23 and Figure 24 , it can be seen that FIG. 23 shows the situation where at least some adjacent four sub-segments 72 and spaced circuit columns 200 are respectively overlapped and arranged. Of course, in some other embodiments, on the basis of FIG. 19, at least some adjacent fourth sub-segments 72 and adjacent circuit columns 200 can be respectively overlapped and arranged.

[0173] In some embodiments, the first signal line 10 and the fourth signal line 90 are both used to transmit data signals data.

[0174] In an embodiment of the present application, both the first signal line 10 and the fourth signal line 90 are longitudinal traces for transmitting a data signal data. Moreover, the first signal line 10 needs to extend and avoid the first region A1. Thus, the first signal line 10 includes a first winding portion 12 on the periphery of the first region A1. For the fourth signal line 90, in order to enable the fourth signal line 90 to receive the data signal data transmitted by the trace structure in the fan-out region A31, a third winding portion 91 located in the second region A2 is additionally provided, and the transmission of the data signal data is achieved through the third winding portion 91. Further, for these two longitudinal traces for transmitting the data signal data, the embodiment of the present application also adjusts other longitudinal traces, such that only the signal trace corresponding to the first line segment 30 needs to be truncated to meet the placement requirements of the winding structures corresponding to the first signal line 10 and the fourth signal line 90, thereby simplifying the design and manufacturing difficulty of the internal wiring of the display panel.

[0175] In a second aspect, please refer to Figure 24 , an embodiment of the present application provides a display device, and the display device includes the display panel in any of the foregoing embodiments.

[0176] It should be noted that the display device provided in the embodiment of the present application has the beneficial effects of the display panel in any of the foregoing embodiments. For specific details, please refer to the description of the beneficial effects of the display panel above. The embodiment of the present application does not limit this. In addition, in addition to the display panel, the display device may further include a middle frame, and at least a part of the middle frame surrounds the periphery of the display panel to protect the display panel.

[0177] Although the disclosed embodiments of the present application are as above, the described content is only an embodiment adopted for the convenience of understanding the present application, and is not intended to limit the present invention. Any person skilled in the art within the technical field to which the present application pertains, without departing from the spirit and scope disclosed by the present application, can make any modifications and changes in the form of implementation and details, but the protection scope of the present application shall still be subject to the scope defined by the appended claims.

[0178] As described above, this is only the specific implementation manner of the present application. Those skilled in the art can clearly understand that for the convenience and brevity of description, the replacement of other connection manners described above can refer to the corresponding processes in the foregoing method embodiments, which will not be elaborated here. It should be understood that the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of various equivalent modifications or replacements, and these modifications or replacements should be covered within the protection scope of the present application.

Claims

1. A display panel, characterized in that, The display panel has a first region and a second region, the transmittance of the first region being greater than that of the second region. The second region includes a first sub-region adjacently disposed to the first region in a first direction. The display panel further includes: A first signal line disposed in the second region. The first signal line includes first sub-segments located on both sides of the first region along a second direction, and a first winding portion connecting the first sub-segments. The first winding portion includes a second sub-segment extending along the second direction and at least partially located in the first sub-region. The first direction intersects the second direction. Pixel circuits disposed in the second region, and a plurality of the pixel circuits are arranged in an array in the first direction and the second direction. A plurality of the pixel circuits arranged side by side in the second direction together form a circuit column. Wherein, in the thickness direction of the display panel, at least part of the adjacent second sub-segments and the adjacent circuit columns are respectively overlapped.

2. The display panel according to claim 1, wherein It further includes a first line segment that is on the same layer as the second sub-segment and is insulated therefrom. The first line segment extends along the second direction and is located on both sides of the second sub-segment. Wherein, in the thickness direction of the display panel, the second sub-segment and the first line segment are respectively overlapped with the same circuit column.

3. The display panel according to claim 2, characterized in that, At least part of the first line segment is used to transmit a first power signal.

4. The display panel according to claim 3, wherein The first line segments adjacent in the first direction are all used to transmit the first power signal, and the projections of the adjacent first line segments respectively overlap with the projections of the adjacent circuit columns.

5. The display panel according to claim 3, wherein Part of the first line segment is used to transmit a reset signal. The first line segments for transmitting the first power signal and the first line segments for transmitting the reset signal are alternately arranged in the first direction.

6. The display panel according to claim 5, characterized in that, The plurality of first line segments for transmitting the reset signal include a first type of trace and a second type of trace. The first type of trace is used to transmit a first reset signal, and the second type of trace is used to transmit a second reset signal. Wherein, the pixel circuit includes a first reset transistor, a second reset transistor, and a driving transistor. A first pole of the first reset transistor receives the first reset signal, and a second pole is electrically connected to a control end of the driving transistor. A first pole of the second reset transistor receives the second reset signal, and a second pole is electrically connected to an anode.

7. The display panel according to claim 5, wherein The plurality of first line segments for transmitting the reset signal include a second type of trace and a third type of trace. The second type of trace is used to transmit a second reset signal, and the third type of trace is used to transmit a third reset signal. Wherein, the pixel circuit includes a second reset transistor, a third reset transistor, and a driving transistor. A first pole of the second reset transistor receives the second reset signal, and a second pole is electrically connected to an anode. A first pole of the third reset transistor receives the third reset signal, and a second pole is electrically connected to a first pole of the driving transistor.

8. The display panel according to claim 6 or 7, characterized in that, The first winding portion further includes a third sub-segment extending along the first direction. One end of the third sub-segment is connected to the first sub-segment, and the other end is connected to the second sub-segment. The display panel includes a substrate, a first conductor layer disposed on one side of the substrate, and a second conductor layer located on the side of the first conductor layer facing away from the substrate. The third sub-segment is located within the first conductor layer, and the first sub-segment, the second sub-segment, and the first line segment are all located within the second conductor layer.

9. The display panel according to claim 8, wherein, It further includes a first reset signal line and a second reset signal line extending along the first direction. The first reset signal line transmits a first reset signal and is electrically connected to a part of the first line segment. The second reset signal line transmits a second reset signal and is electrically connected to a part of the first line segment. The first reset signal line and the second reset signal line are on the same layer and are located on the side of the first conductor layer facing the substrate; or, The display panel further includes a second reset signal line and a third reset signal line extending along the first direction. The second reset signal line transmits a second reset signal and is electrically connected to a part of the first line segment. The third reset signal line transmits a third reset signal and is electrically connected to a part of the first line segment. The second reset signal line and the third reset signal line are on the same layer and are located on the side of the first conductor layer facing the substrate.

10. The display panel according to claim 1, characterized in that, The pixel circuit includes a driving transistor. The distance along the first direction between adjacent second sub-segments is D1, and the distance along the first direction between two driving transistors in adjacent two pixel circuits is D2, where D2 > D1.

11. The display panel according to claim 1, wherein The pixel circuit includes a driving transistor. Adjacent second sub-segments are located on the same side of the corresponding driving transistor along the first direction and have the same distance from the corresponding driving transistor in the first direction.

12. The display panel according to claim 1, wherein It further includes a second signal line that extends along the second direction and is located in the second region. The second signal line is located on either side of the first region along the first direction; The pixel circuit includes a storage capacitor. In the thickness direction of the display panel, the projections of the second sub-segment and the second signal line are disposed on both sides of the projection of the storage capacitor along the first direction.

13. The display panel according to claim 1, characterized in that, The number of the first regions is multiple, and the multiple first regions are arranged at intervals along the first direction. A first sub-region is provided between adjacent first regions.

14. The display panel according to claim 1, wherein, It further includes a light-emitting unit. The pixel circuit located within the first sub-region is electrically connected to the light-emitting unit; and / or, the light-emitting unit located within the first region is electrically connected to the pixel circuit within the first sub-region.

15. The display panel according to claim 1, wherein The pixel circuit within the first sub-region is a virtual pixel circuit.

16. The display panel according to claim 1, wherein The second region further includes a second sub-region that is located on one side of the first region in the first direction, and there is no overlap between the first sub-region and the second sub-region; The display panel further includes a third signal line disposed within the second region. The third signal line extends along the second direction and includes a second winding portion. The second winding portion includes a fourth sub-segment that extends along the second direction and is located within the second sub-region; Wherein, in the thickness direction of the display panel, two adjacent fourth sub-segments overlap with two circuit columns arranged at intervals; or, an adjacent fourth sub-segment overlaps with an adjacent circuit column.

17. The display panel according to claim 16, wherein It further includes a second line segment that is on the same layer as the fourth sub-segment and is insulated, and the second line segment extends along the second direction and is located between adjacent fourth sub-segments; Wherein, in the thickness direction of the display panel, the second line segment and the fourth sub-segment respectively overlap with different circuit columns.

18. The display panel according to claim 17, wherein At least a part of the second line segment is used to transmit a first power signal; and / or, at least a part of the second line segment is used to transmit a reset signal.

19. The display panel according to claim 1, wherein It further includes a third region, the third region surrounds the second region, and the third region includes a fan-out region located on one side of the second region along the second direction; The display panel further includes a fourth signal line, the fourth signal line is located on any one side of the first region along the first direction, and the fourth signal line is electrically connected to a fan-out line located in the fan-out region through a third winding portion, the third winding portion is located in the second region, and the third winding portion includes a fifth sub-segment extending along the first direction and a sixth sub-segment extending along the second direction.

20. The display panel according to claim 19, wherein, In the thickness direction of the display panel, at least a part of adjacent sixth sub-segments and adjacent circuit columns respectively overlap.

21. The display panel according to claim 19, wherein It further includes a first line segment that is on the same layer as the second sub-segment and the sixth sub-segment and is insulated, and the first line segment extends along the second direction and is located on both sides of the second sub-segment; Wherein, the first line segments are all located on the side of the sixth sub-segment facing the second sub-segment, and in the thickness direction of the display panel, the first line segment and the sixth sub-segment respectively overlap with the same circuit column.

22. The display panel according to claim 19, wherein, In the thickness direction of the display panel, at least a part of adjacent sixth sub-segments and spaced-apart circuit columns respectively overlap.

23. The display panel according to claim 22, wherein It further includes a first line segment that is on the same layer as the second sub-segment and the sixth sub-segment and is insulated, and the first line segment extends along the second direction and is located on both sides of the second sub-segment; Wherein, two adjacent first line segments are respectively a first trace and a second trace, the first trace is located on the side of the sixth sub-segment facing the second sub-segment, and in the thickness direction of the display panel, the projection of the first trace and the sixth sub-segment respectively overlap with the same circuit column, and the second trace is located between adjacent sixth sub-segments and extends to the fan-out region.

24. The display panel according to claim 22, wherein The first trace is used to transmit a first power signal, and the second trace is used to transmit a reset signal.

25. The display panel according to claim 19, wherein Both the first signal line and the fourth signal line are used to transmit data signals.

26. A display device, characterized in that, It includes the display panel according to any one of claims 1 to 25.

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