Display device

Abstract

The invention discloses a display device. The display device includes: a substrate on which a plurality of pixels are disposed in a column direction and a row direction; a light emitting diode disposed in each of the plurality of pixels; a first anode reset line disposed in each row in which some pixels among the plurality of pixels are located; and a second anode reset line disposed in each row in which remaining pixels among the plurality of pixels are located.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2024-0012479, filed on January 26, 2024, which is incorporated herein by reference in its entirety as if fully set forth herein. Technical Field

[0002] The present disclosure relates to a display device. Background Art

[0003] An image display device for implementing various information on a screen is a core technology in the information and communication era and is being developed to be thinner, lighter, more portable, and have higher performance. Therefore, a display device that can be manufactured in a light and thin form has received attention.

[0004] Representative examples of display devices include a liquid crystal display (LCD) device, a quantum dot display (QDD) device, a field emission display (FED) device, and an organic light emitting display (OLED) device.

[0005] Among these display devices, unlike an LCD device, an OLED device is a self-emitting display device and thus does not require a separate light source. Therefore, an OLED device has the advantages of being light in weight and thin in shape. In addition, an OLED device has an advantage in power consumption due to its low-voltage driving characteristics and has excellent color implementation performance, a high response speed, a wide viewing angle, and a high contrast ratio (CR). Therefore, an OLED device is currently being developed as a next-generation display device. Summary of the Invention

[0006] Accordingly, the present disclosure relates to a display device that substantially overcomes one or more problems caused by the limitations and disadvantages of the related art.

[0007] An object of the present disclosure is to provide a display device that is driven in a variable refresh rate (VRR) manner and can prevent defects from occurring in a display panel due to the appearance of ripples in an anode reset voltage VAR.

[0008] The objects to be achieved by the present disclosure are not limited to the above objects, and other objects not mentioned herein will be clearly understood by those skilled in the art from the following description.

[0009] Some of the other advantages, objects, and features of the present invention will be set forth in part in the following description, and some of these advantages, objects, and features will become apparent to those of ordinary skill in the art after studying the following, or may be learned by practice of the present invention. These objects and other advantages of the present invention can be realized and obtained by the structures specifically pointed out in the specification, the claims, and the drawings.

[0010] To achieve these objects and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, a display device includes: a substrate on which a plurality of pixels are disposed in a column direction and a row direction; light emitting diodes disposed in each of the plurality of pixels; a first anode reset line disposed in each row in which some of the plurality of pixels are located; and a second anode reset line disposed in each row in which the remaining pixels of the plurality of pixels are located.

[0011] In another aspect of the present disclosure, a display device includes: a substrate on which a plurality of pixels are disposed in a column direction and a row direction; light emitting diodes disposed in the plurality of pixels; and a first anode reset line and a second anode reset line disposed in each pixel row. The first anode reset line and the second anode reset line are disposed in the (2k - 1)th pixel row in this order, where k is a natural number. The second anode reset line and the first anode reset line are disposed in the 2kth pixel row in this order. The first anode reset line and another adjacent first anode reset line are connected to each other to have a mesh structure, and the second anode reset line and another adjacent second anode reset line are connected to each other to have a mesh structure.

[0012] In yet another aspect of the present disclosure, a display device includes: a substrate on which a plurality of pixels are disposed in a column direction and a row direction; light emitting diodes disposed in the plurality of pixels; a first anode reset line disposed in the 2kth pixel row, where k is a natural number; and a second anode reset line disposed in the (2k - 1)th pixel row. A first pixel disposed in the 2kth pixel row and a second pixel disposed in the (2k + 1)th pixel row are connected to the first anode reset line. A third pixel disposed in the (2k - 1)th pixel row and a third pixel disposed in the 2kth pixel row are connected to the second anode reset line.

[0013] In still another aspect of the present disclosure, a display device includes: a substrate on which a plurality of pixels are disposed in a column direction and a row direction; light emitting diodes disposed in the plurality of pixels; a first anode reset line disposed in each odd pixel row and connecting pixels of different colors among the light emitting diodes; and a second anode reset line disposed in each even pixel row and connecting pixels of the same color among the light emitting diodes.

[0014] It should be understood that the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the claimed disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

[0016] Figure 1 is a block diagram showing a display device according to an embodiment of the present disclosure;

[0017] Figure 2 is a circuit diagram of a pixel included in a display device according to an embodiment of the present disclosure;

[0018] Figure 3 is a sectional view showing a display device according to an embodiment of the present disclosure;

[0019] Figure 4 is a diagram for explaining an operation method of a display device according to the present disclosure;

[0020] Figure 5 is a layout diagram showing an anode reset line of a display device according to an embodiment of the present disclosure;

[0021] Figure 6 is a layout diagram showing the circuit configuration of each pixel and the anode reset line in a display device according to an embodiment of the present disclosure;

[0022] Figure 7 is an exemplary sectional view showing the connection relationship of the anode reset line;

[0023] Figure 8 is a layout diagram showing an anode reset line of a display device according to another embodiment of the present disclosure;

[0024] Figure 9 is a layout diagram showing the circuit configuration of each pixel and the anode reset line in a display device according to another embodiment of the present disclosure;

[0025] Figure 10 is an exemplary sectional view showing the connection relationship of the anode reset line;

[0026] Figure 11 is a layout diagram showing an anode reset line of a display device according to still another embodiment of the present disclosure; and

[0027] Figure 12It is a layout diagram showing the circuit configuration of each pixel and the anode reset line in a display device according to another embodiment of the present disclosure. Detailed Embodiment

[0028] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings. The same reference numerals will be used throughout the drawings to refer to the same or similar components as much as possible.

[0029] When describing the present disclosure, when it is determined that a detailed description of the known technology associated with the present disclosure may unnecessarily obscure the gist of the present disclosure, its description will be omitted. In addition, the names of the components used in the following description are selected for ease of writing the specification and may be different from the names of the components of the actual product.

[0030] In the drawings for illustrating the exemplary embodiments of the present disclosure, for example, the shapes, sizes, ratios, angles, and quantities shown are given by way of example and are therefore not limited to the present disclosure. Throughout this application, the same reference numerals denote the same components.

[0031] Furthermore, in the following description of the present disclosure, when the known functions and configurations incorporated herein may instead obscure the subject matter of the present disclosure, their detailed descriptions will be omitted.

[0032] Unless used together with the term "only", the terms "comprising", "comprising of", and / or "having" used in this application do not exclude the presence or addition of other elements. Unless the context clearly indicates otherwise, the singular form is also intended to include the plural form.

[0033] When explaining the components included in the various embodiments of the present disclosure, even if not explicitly stated, these components are interpreted as including an error range.

[0034] In the description of the various embodiments of the present disclosure, when describing the positional relationship, for example, when using "above", "over", "below", "next to", etc. to describe the positional relationship between two parts, unless the terms "directly" or "closely" are used, one or more other parts may be located between these two parts.

[0035] In the description of the various embodiments of the present disclosure, when describing the time relationship, for example, when using "after", "subsequently", "next", "before", etc. to describe the time relationship between two actions, unless used together with the terms "directly" or "merely", the actions may not occur continuously.

[0036] It is understood that although terms such as "first" and "second" may be used herein to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one element from another. Therefore, in this application, unless otherwise mentioned, the element represented by "first" may be the same as the element represented by "second" without exceeding the technical scope of the present disclosure.

[0037] The corresponding features of various embodiments of the present disclosure may be partially or wholly combined or combined with each other, and various technical linkages and operation modes may be carried out. These various embodiments may be executed independently of each other or may be executed in association with each other.

[0038] Hereinafter, a display device according to an embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0039] Figure 1 is a block diagram showing a display device according to an embodiment of the present disclosure.

[0040] As Figure 1 shown, a display device according to an embodiment of the present disclosure may include: a display panel 100, a data driving circuit 400, a gate driving circuit 300, a power supply unit 500, and a timing controller 200.

[0041] A plurality of pixels P may be provided on the display panel 100. The plurality of pixels P may be provided in an area where a plurality of data lines DL and a plurality of gate lines GL intersect each other. The pixels P provided in the same horizontal row may constitute a pixel row. The pixels P provided in a pixel row may be connected to one gate line GL, and one gate line GL may include at least one scan line and at least one light emitting line. For example, each pixel P may be connected to one data line DL, at least one scan line, and at least one light emitting line. However, the embodiments of the present disclosure are not limited thereto.

[0042] The data driving circuit 400 may drive the data lines DL. The gate driving circuit 300 may drive the gate lines GL. The power supply unit 500 may provide the power required to drive each of the plurality of pixels P.

[0043] The plurality of pixels P may commonly receive a high-potential driving voltage ELVDD and a low-potential driving voltage ELVSS from the power supply unit 500. The plurality of pixels P may receive a bias voltage Vobs and an initialization voltage Vini from a power supply line VL, but are not limited thereto.

[0044] The transistor or thin film transistor (TFT) constituting the pixel P may be implemented as an oxide TFT including an oxide semiconductor layer. Considering electron mobility and process variations, the oxide TFT may be advantageous in terms of the enlargement of the display panel 100. However, embodiments of the present disclosure are not limited thereto. The semiconductor layer of the TFT may be formed of amorphous silicon, polysilicon, or the like.

[0045] Each pixel P may include an organic light emitting diode (OLED), a driving TFT configured to supply current to the organic light emitting diode, a switching TFT configured to supply a data voltage to the driving TFT, and a storage capacitor configured to store the data voltage supplied to the driving TFT. The storage capacitor may hold the data voltage during one frame period.

[0046] Each pixel P may further include one or more TFTs and a storage capacitor to compensate for variations in the threshold voltage of the driving TFT.

[0047] A touch sensor may be provided on the display panel 100. The touch input may be sensed using the touch sensor or through the pixel P. The touch sensor may be implemented as an on-cell type or an in-cell type touch sensor provided on the screen of the display panel, or may be implemented as an in-cell type touch sensor built into the display panel 100. However, embodiments of the present disclosure are not limited thereto.

[0048] The timing controller 200 may control the driving timings of the data driving circuit 400 and the gate driving circuit 300. The timing controller 200 may rearrange the digital video data RGB input from the outside according to the resolution of the display panel 100 and may supply the rearranged digital video data to the data driving circuit 400.

[0049] In addition, the timing controller 200 may generate a data control signal DDC for controlling the operation timing of the data driving circuit 400 and a gate control signal GDC for controlling the operation timing of the gate driving circuit 300 based on timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE.

[0050] The timing controller 200 may multiply the input frame frequency by "i", and may control the operation timing of the display panel driver at a frame frequency of "input frame frequency × i" Hz (where i is a positive integer greater than 0). In the National Television Standards Committee (NTSC) system, the input frame frequency may be 60 Hz, and in the Phase Alternating Line (PAL) system, the input frame frequency may be 50 Hz. However, embodiments of the present disclosure are not limited thereto.

[0051] The data driving circuit 400 may convert digital video data RGB input from the timing controller 200 into analog data voltages based on a data control signal DDC and may provide the analog data voltages to each of the data lines DL.

[0052] The data driving circuit 400 may include one or more source driver integrated circuits (ICs) SIC. The source driver IC may convert the digital video data of an input image into analog gamma-compensated voltages under the control of the timing controller 200 to generate data voltages, and may output the data voltages to the data lines DL. The source driver IC may be mounted on a flexible printed circuit board that can be bent, such as chip on film (COF), or may be directly adhered to the substrate in the non-active area of the display panel 100 through a COG process.

[0053] The COF may be adhered to the pad area of the display panel 100 and the source PCB through an anisotropic conductive film (ACF). The input pins of the COF may be electrically connected to the output terminals (pads) of the source PCB. The output pins of the COF may be electrically connected to the data pads formed on the substrate of the display panel 100 through the ACF.

[0054] Although one data driving circuit 400 is shown as being disposed on one side of the display panel 100 in Figure 1 , the number and placement location of the data driving circuits 400 are not limited thereto. For example, the data driving circuit 400 may be composed of multiple integrated circuits (ICs), and the multiple ICs may be separately disposed on one side of the display panel 100.

[0055] The gate driving circuit 300 may generate a scan signal and a light emission signal based on a gate control signal GDC. The gate driving circuit 300 may include at least one scan driver 310 and a light emission driver 320.

[0056] To drive at least one scan line SCL connected to each pixel row, at least one scan driver 310 may generate a scan signal SC and may provide the scan signal SC to the gate lines GL in a row-sequential manner. At least one scan driver 310 may output scan pulses in response to a start pulse and a shift clock from the timing controller 200 and may shift the scan pulses according to the shift clock timing.

[0057] To drive at least one light emission line EML connected to each pixel row, the light emission driver 320 may generate a light emission signal EM and may provide the light emission signal EM to the light emission lines in a row-sequential manner. The light emission driver 320 may output light emission control signal pulses in response to a start pulse and a shift clock from the timing controller 200, and may sequentially shift the light emission control signal pulses according to the shift clock.

[0058] The scan signal SC may include scan pulses that swing between a gate-on voltage VGL and a gate-off voltage VGH. The emission control signal EM may include emission control signal pulses that swing between a gate-on voltage VEL and a gate-off voltage VEH. The scan pulses may select pixels P of a row to which a data voltage Vdata is to be written. The emission control signal EM may define the emission time of the pixels P.

[0059] Gate lines GL may supply the scan signal SC and the emission control signal EM to a plurality of pixels P, and data lines DL may supply the data voltage Vdata to the plurality of pixels P. According to various embodiments, the gate lines GL may include a plurality of scan lines SCL for supplying the scan signal SC and a plurality of emission control signal lines EML for supplying the emission control signal EM.

[0060] The power supply unit 500 may generate a direct current (DC) power supply required to drive the pixel array of the display panel 100 and the display panel driver using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, or a boost converter. However, embodiments of the present disclosure are not limited thereto.

[0061] The power supply unit 500 may receive a DC input voltage from a host system and may generate DC voltages such as a gate-on voltage VGL and VEL, a gate-off voltage VGH and VEH, a high potential drive voltage EVDD, and a low potential drive voltage EVSS.

[0062] The gate-on voltages VGL and VEL and the gate-off voltages VGH and VEH may be supplied to a level shifter and a gate driver circuit 300. The high potential drive voltage ELVDD and the low potential drive voltage ELVSS may be commonly supplied to the pixels P.

[0063] The plurality of pixels P of the display panel 100 may include at least a first pixel, a second pixel, and a third pixel. The first pixel, the second pixel, and the third pixel may emit light of different colors. For example, the first pixel may be a red pixel, the second pixel may be a blue pixel, and the third pixel may be a green pixel. However, embodiments of the present disclosure are not limited thereto.

[0064] The sizes of the plurality of pixels P may be the same as or different from each other. Considering the color balance or lifespan of the organic light-emitting diodes (OLEDs) included in each of the first pixel, the second pixel, and the third pixel, the sizes of the first pixel, the second pixel, and the third pixel may be designed to be different from each other.

[0065] To achieve lower power consumption, a display device according to the present disclosure may adopt a variable refresh rate (VRR) technique that changes the driving frequency.

[0066] For example, the timing controller 200 may generate signals such that the pixels P can be driven at various refresh rates. For example, the timing controller 200 may generate signals related to driving such that the pixels P can be driven in a variable refresh rate (VRR) mode or the pixels P can be driven to be switchable between a first refresh rate and a second refresh rate. For example, the timing controller 200 may simply change the speed of the clock signal, may generate a synchronization signal to generate a horizontal blanking or a vertical blanking, or may drive the gate driver circuit 300 in a mask manner, thereby driving the pixels P at various refresh rates.

[0067] Therefore, in order to change the driving frequency, driving needs to be performed in the anode reset frame. In order to perform driving in the anode reset frame, each pixel may be configured to provide an anode reset voltage VAR.

[0068] Figure 2 is a circuit diagram of a pixel included in a display device according to an embodiment of the present disclosure.

[0069] As Figure 2 shown, each pixel P may include a pixel driving circuit and a light emitting unit.

[0070] The pixel driving circuit may include a first transistor T1 to a seventh transistor T7, a storage capacitor Cstg, and a driving transistor D-TFT. The light emitting unit may include an organic light emitting diode OLED.

[0071] The first transistor T1 to the seventh transistor T7, and the driving transistor D-TFT may be implemented as different types of transistors. For example, one of the first transistor T1 to the seventh transistor T7, and the driving transistor D-TFT may be a transistor using an oxide semiconductor as an active layer. Since the oxide semiconductor material has a low off-current, the oxide semiconductor material may be suitable for a switching transistor that maintains a short on-time and a long off-time. In another example, another one of the first transistor T1 to the seventh transistor T7, and the driving transistor D-TFT may be a transistor using low temperature polycrystalline silicon (LTPS) as an active layer. Since the polycrystalline silicon material has a high mobility and thus exhibits low power consumption and excellent reliability, the polycrystalline silicon material may be suitable for the driving transistor D-TFT.

[0072] The first transistor T1 to the seventh transistor T7, and the driving transistor D-TFT may be an N-type transistor or a P-type transistor. In an N-type transistor, since the carriers are electrons, electrons can flow from the source electrode to the drain electrode, and current can flow from the drain electrode to the source electrode. In a P-type transistor, since the carriers are holes, holes can flow from the source electrode to the drain electrode, and current can flow from the source electrode to the drain electrode. For example, one of the first transistor T1 to the seventh transistor T7, and the driving transistor D-TFT may be an N-type transistor, and another one of the first transistor T1 to the seventh transistor T7, and the driving transistor D-TFT may be a P-type transistor.

[0073] The pixel driving circuit may include a driving transistor D-TFT, the first transistor T1 to the seventh transistor T7, and a storage capacitor Cstg.

[0074] The driving transistor D-TFT may include a first node N1, a second node N2, and a third node N3. In the driving transistor D-TFT, the second node N2 may be a gate node, the first node N1 may be a source node or a drain node, and the third node N3 may be a drain node or a source node. Hereinafter, for ease of description, the driving transistor D-TFT will be described by way of example. In the driving transistor D-TFT, the second node N2 is a gate node, the first node N1 is a source node, and the third node N3 is a drain node. However, the embodiments of the present disclosure are not limited thereto.

[0075] The gate electrode of the driving transistor D-TFT may be connected to the second node N2, and the first electrode of the driving transistor D-TFT may be connected to the first node N1. The second electrode of the driving transistor D-TFT may be connected to the third node N3. The driving transistor D-TFT may be controlled according to the voltage of the second node N2 to control the current flowing through the organic light-emitting diode OLED.

[0076] The first transistor T1 may be connected between the second node N2 and the third node N3. The first transistor T1 may be controlled to switch between the second node N2 and the third node N3 in response to the first scan signal Scan1(n).

[0077] The second transistor T2 may be connected to the first node N1. The second transistor T2 may be controlled to supply the data voltage Vdata to the first node N1 in response to the second scan signal Scan2(n).

[0078] The third transistor T3 may be connected to the first node N1. The third transistor T3 may be controlled to supply the high-potential driving voltage ELVDD provided through the high-potential driving voltage line to the first node N1 in response to the light emission control signal EM(n).

[0079] The fourth transistor T4 can be connected between the third node N3 and the fourth node N4. The fourth transistor T4 can be controlled to switch between the third node N3 and the fourth node N4 in response to the light emission control signal EM(n).

[0080] The fifth transistor T5 can be connected to the second node N2. The fifth transistor T5 can be controlled to supply the initialization voltage Vini to the second node N2 in response to the fourth scan signal Scan4(n).

[0081] The sixth transistor T6 can be connected to the fourth node N4. The sixth transistor T6 can be controlled to supply the anode reset voltage VAR to the fourth node N4 in response to the third scan signal Scan3(n).

[0082] The seventh transistor T7 can be connected to the first node N1. The seventh transistor T7 can be controlled to supply the bias voltage Vobs to the first node N1 in response to the third scan signal Scan3(n). The hysteresis phenomenon of the driving transistor D-TFT can be improved by adjusting the gate-source voltage Vgs flowing through the driving transistor D-TFT with the bias voltage Vobs. For example, the threshold voltage Vth of the driving transistor D-TFT can be changed by applying the bias voltage Vobs.

[0083] The storage capacitor Cstg can be connected between the high-potential driving voltage terminal providing the high-potential driving voltage ELVDD and the second node N2. The storage capacitor Cstg can store the data voltage Vdata. For example, the storage capacitor Cstg can store the data voltage Vdata during one frame period.

[0084] The organic light-emitting diode OLED can include an anode and a cathode. The anode of the organic light-emitting diode OLED can be connected to the fourth node N4. The cathode of the organic light-emitting diode OLED can be connected to the low-potential driving voltage line providing the low-potential driving voltage ELVSS.

[0085] The organic light-emitting diode OLED can include one of an organic light-emitting layer, an inorganic light-emitting layer, and a quantum dot light-emitting layer, or can include a stacked or combined structure of an organic light-emitting layer (or inorganic light-emitting layer) and a quantum dot light-emitting layer. For example, the organic light-emitting diode can include an anode, an organic layer, and a cathode. In another example, in addition to the organic light-emitting diode, a micro light-emitting diode (micro-LED), a mini-LED, or a quantum dot light-emitting diode (QLED) including quantum dots (QD) can be further used.

[0086] The organic light-emitting diode OLED can output light corresponding to one of various colors such as red, green, and blue, or can output white light.

[0087] Figure 3 is a cross-sectional view showing a display device according to an embodiment of the present disclosure.

[0088] The display device according to an embodiment of the present disclosure may include a device substrate 105. The device substrate 105 may include an insulating material. For example, the device substrate 105 may include glass or plastic. However, the embodiments of the present disclosure are not limited thereto. The device substrate 105 may have a multi-layer structure. However, the embodiments of the present disclosure are not limited thereto. For example, the device substrate 105 may have a structure in which a first substrate layer 101, a substrate insulating layer 102, and a second substrate layer 103 are stacked. The second substrate layer 103 may include the same material as the first substrate layer 101. However, the embodiments of the present disclosure are not limited thereto. For example, the first substrate layer 101 and the second substrate layer 103 may include a polymer material such as polyimide (PI). However, the embodiments of the present disclosure are not limited thereto. The substrate insulating layer 102 may include an insulating material. Accordingly, in the display device according to an embodiment of the present disclosure, the device substrate 105 may be flexible. Accordingly, in the display device according to an embodiment of the present disclosure, damage to the device substrate 105 due to bending stress may be prevented.

[0089] The device substrate 105 may include an active area, a bending area, and a pad area. An image to be provided to a user may be implemented in the active area. For example, the active area may include a plurality of pixel areas PA. Each pixel area PA may implement a specific color. For example, a light-emitting diode 600 may be disposed in each pixel area PA. The light-emitting diode 600 may emit light of a specific color. For example, the light-emitting diode 600 may include a first electrode 610, a light-emitting layer 620, and a second electrode 630 stacked on the device substrate 105.

[0090] The first electrode 610 may include a conductive material. The first electrode 610 may be made of a material having a high reflectivity. For example, the first electrode 610 may include a metal such as aluminum (Al) or silver (Ag). However, the embodiments of the present disclosure are not limited thereto. The first electrode 610 may have a multi-layer structure. For example, the first electrode 610 may have a structure in which a reflective electrode made of a metal is interposed between transparent electrodes made of a transparent conductive material such as ITO or IZO. However, the embodiments of the present disclosure are not limited thereto.

[0091] The light-emitting layer 620 may generate light having a brightness corresponding to the voltage difference between the first electrode 610 and the second electrode 630. For example, the light-emitting layer 620 may include a light-emitting material layer (EML) 622 containing a light-emitting material. The light-emitting material may include an organic material, an inorganic material, or a hybrid material. For example, the display device according to an embodiment of the present disclosure may be an organic light-emitting display device in which the light-emitting layer 620 includes a light-emitting material layer 622 made of an organic material. However, the embodiments of the present disclosure are not limited thereto. The light-emitting layer 620 may include an inorganic light-emitting material. For example, the light-emitting layer 620 may be made of a material including quantum dots, micro-LEDs, or mini-LEDs. However, the embodiments of the present disclosure are not limited thereto.

[0092] The light-emitting layer 620 may have a multilayer structure. For example, the light-emitting layer 620 may include at least one of a first common layer 621 located between the first electrode 610 and the light-emitting material layer 622 or a second common layer 623 located between the light-emitting material layer 622 and the second electrode 630. Each of the first common layer 621 and the second common layer 623 may include at least one of a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron transport layer (ETL), or an electron injection layer (EIL). However, the embodiments of the present disclosure are not limited thereto. For example, in the display device according to an embodiment of the present disclosure, the first common layer 621 may include at least one of a hole injection layer (HIL), an electron blocking layer (EBL), or a hole transport layer (HTL), and the second common layer 623 may include at least one of an electron transport layer (ETL), a hole blocking layer (HBL), or an electron injection layer (EIL).

[0093] The second electrode 630 may include a conductive material. The second electrode 630 may include a material different from that of the first electrode 610. However, the embodiments of the present disclosure are not limited thereto. For example, the second electrode 630 may be a transparent electrode made of a transparent conductive material such as ITO or IZO. The second electrode 630 may have a higher transmittance than the first electrode 610. Accordingly, in the display device according to an embodiment of the present disclosure, the light generated by the light-emitting layer 620 may be emitted through the second electrode 630.

[0094] A driving circuit can be provided in each pixel region PA. The driving circuit can generate a driving current supplied to the light-emitting diode 600. The driving circuit can be electrically connected to the signal lines GL, DL, ELVDD, and ELVSS. For example, each pixel region PA can be constituted by the signal lines GL, DL, ELVDD, and ELVSS. The signal lines GL, DL, ELVDD, and ELVSS can transmit various signals for implementing an image. For example, the signal lines GL, DL, ELVDD, and ELVSS can include a gate line GL for applying a gate signal, a data line DL for applying a data signal, and power voltage supply lines ELVDD and ELVSS for providing a power voltage. However, embodiments of the present disclosure are not limited thereto. The driving circuit can generate a driving current corresponding to the data signal in response to the gate signal. The operation of the light-emitting diode 600 can be maintained during one frame period. For example, the driving circuit can include a first thin-film transistor 210 and a second thin-film transistor 220. However, embodiments of the present disclosure are not limited thereto.

[0095] The first thin-film transistor 210 can be electrically connected to the light-emitting diode 600. The first thin-film transistor 210 can supply a driving current corresponding to the data signal to the light-emitting diode 600. For example, the first thin-film transistor 210 can be disposed between the light-emitting diode 600 and one of the power voltage supply lines ELVDD and ELVSS. The first thin-film transistor 210 can include a first semiconductor layer 211, a first insulating film 212, a first gate electrode 213, a second insulating film 214, a first source electrode 215, and a first drain electrode 216.

[0096] The first semiconductor layer 211 can be disposed close to the device substrate 105. The first semiconductor layer 211 can include a semiconductor material. For example, the first semiconductor layer 211 can include silicon. The first semiconductor layer 211 can include a polycrystalline semiconductor. For example, the first semiconductor layer 211 can include low-temperature polycrystalline silicon (LTPS). However, embodiments of the present disclosure are not limited thereto. In another example, the first semiconductor layer 211 can include an oxide semiconductor. The first semiconductor layer 211 can include a first source region, a first drain region, and a first channel region. The first channel region can be disposed between the first source region and the first drain region. The first channel region can have a lower conductivity than the first source region and the first drain region. For example, the first source region and the first drain region can include conductive impurities having a higher concentration than the concentration of the first channel region.

[0097] A first insulating film 212 may be provided on the first semiconductor layer 211. The first insulating film 212 may extend to the outside of the first semiconductor layer 211. For example, the side surface of the first semiconductor layer 211 may be covered by the first insulating film 212. The first insulating film 212 may include an insulating material. For example, the first insulating film 212 may include silicon oxide (SiO) and / or silicon nitride (SiN). However, the embodiments of the present disclosure are not limited thereto. The silicon oxide (SiO) may include silicon dioxide (SiO2). The first insulating film 212 may include a material having a high dielectric constant. For example, the first insulating film 212 may include a material such as hafnium oxide (HfO). However, the embodiments of the present disclosure are not limited thereto. The first insulating film 212 may be a gate insulating film, but is not limited thereto.

[0098] A first gate electrode 213 may be provided on the first insulating film 212. The first gate electrode 213 may include a conductive material. For example, the first gate electrode 213 may include a single layer or multiple layers including aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), tungsten (W), or an alloy thereof. However, the embodiments of the present disclosure are not limited thereto. The first gate electrode 213 may be insulated from the first semiconductor layer 211 through the first insulating film 212. The first gate electrode 213 may overlap with the first channel region of the first semiconductor layer 211. For example, the first channel region of the first semiconductor layer 211 may have conductivity corresponding to the voltage applied to the first gate electrode 213.

[0099] A second insulating film 214 may be provided on the first gate electrode 213. The second insulating film 214 may extend to the outside of the first gate electrode 213. For example, the side surface of the first gate electrode 213 may be covered by the second insulating film 214. The second insulating film 214 may extend along the first insulating film 212. The second insulating film 214 may include an insulating material. For example, the second insulating film 214 may include silicon oxide (SiO). However, the embodiments of the present disclosure are not limited thereto. The second insulating film 214 may be an interlayer insulating film, but is not limited thereto.

[0100] A first source electrode 215 may be provided on the second insulating film 214. The first source electrode 215 may be insulated from the first gate electrode 213 through the second insulating film 214. The first source electrode 215 may include a material different from that of the first gate electrode 213. However, the embodiments of the present disclosure are not limited thereto. The first source electrode 215 may include a conductive material. For example, the first source electrode 215 may include a single layer or multiple layers including aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), tungsten (W), or an alloy thereof. However, the embodiments of the present disclosure are not limited thereto. The first source electrode 215 may be electrically connected to the first source region of the first semiconductor layer 211.

[0101] The first drain electrode 216 may be disposed on the second insulating film 214. The first drain electrode 216 may include a conductive material. For example, the first drain electrode 216 may include a single layer or multiple layers including aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), tungsten (W), or an alloy thereof. However, embodiments of the present disclosure are not limited thereto. The first drain electrode 216 may be insulated from the first gate electrode 213 through the second insulating film 214. The first drain electrode 216 may include a material different from that of the first gate electrode 213. However, embodiments of the present disclosure are not limited thereto. For example, the first drain electrode 216 may include the same material as the first source electrode 215. The first drain electrode 216 may be formed by the same process as the first source electrode 215. The first drain electrode 216 may be electrically connected to the first drain region of the first semiconductor layer 211. The first drain electrode 216 may be separated from the first source electrode 215.

[0102] The specific positions of the first source electrode 215 and the first drain electrode 216 will be described later.

[0103] The second thin film transistor 220 may be electrically connected to the first thin film transistor 210. The second thin film transistor 220 may transmit a data signal to the first gate electrode 213 of the first thin film transistor 210 in response to a scan signal. For example, the second thin film transistor 220 may be disposed between the data line DL and the first gate electrode 213 of the first thin film transistor 210. The structure of the second thin film transistor 220 may be the same as that of the first thin film transistor 210. However, embodiments of the present disclosure are not limited thereto. For example, the second thin film transistor 220 may include a second semiconductor layer 221, a fourth insulating film 224, a second gate electrode 223, a second source electrode 225, and a second drain electrode 226.

[0104] The second semiconductor layer 221 may include a semiconductor material. The second semiconductor layer 221 may include the same material or a different material from that of the first semiconductor layer 211. For example, the second semiconductor layer 221 may be an oxide semiconductor, such as IGZO. In another example, the second semiconductor layer 221 may include low temperature polycrystalline silicon (LTPS).

[0105] The second semiconductor layer 221 and the first semiconductor layer 211 may be disposed on different layers. For example, the first protective film 130 may be disposed on the second insulating film 214, and the second semiconductor layer 221 may be disposed on the first protective film 130. The first protective film 130 may include silicon oxide (SiOx) or silicon nitride (SiNx). However, embodiments of the present disclosure are not limited thereto. Therefore, in the display device according to embodiments of the present disclosure, damage to the second semiconductor layer 221 caused by the process of forming the first semiconductor layer 211 can be prevented.

[0106] The second semiconductor layer 221 may include a second source region, a second drain region, and a second channel region. The second channel region may be disposed between the second source region and the second drain region. The second source region and the second drain region may have a lower resistance than the second channel region. For example, the second source region and the second drain region may include a region where an oxide semiconductor is made conductive. The second channel region may be a region where the oxide semiconductor is not made conductive.

[0107] A fourth insulating film 224 may be disposed on the second semiconductor layer 221. The fourth insulating film 224 may include an insulating material. The fourth insulating film 224 may include the same material as the first insulating film 212. However, embodiments of the present disclosure are not limited thereto. For example, the fourth insulating film 224 may have a multilayer structure. However, embodiments of the present disclosure are not limited thereto.

[0108] A second gate electrode 223 may be disposed on the fourth insulating film 224. For example, the second gate electrode 223 may overlap with the second channel region of the second semiconductor layer 221. The second gate electrode 223 may include a conductive material. For example, the second gate electrode 223 may include a single layer or multiple layers including aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), tungsten (W), or an alloy thereof. However, embodiments of the present disclosure are not limited thereto. The second gate electrode 223 may include the same material as the first gate electrode 213. However, embodiments of the present disclosure are not limited thereto. The second gate electrode 223 may be insulated from the second semiconductor layer 221 through the fourth insulating film 224. For example, the second channel region of the second semiconductor layer 221 may have conductivity corresponding to the voltage applied to the second gate electrode 223.

[0109] A second protective film 150 may be disposed on the fourth insulating film 224. The second protective film 150 may include silicon oxide (SiOx) or silicon nitride (SiNx). However, embodiments of the present disclosure are not limited thereto.

[0110] A second source electrode 225 may be disposed on the second protective film 150. The second source electrode 225 may include a conductive material. For example, the second source electrode 225 may include aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), tungsten (W), or an alloy thereof. However, embodiments of the present disclosure are not limited thereto. The second source electrode 225 may include the same material as the first source electrode 215. However, embodiments of the present disclosure are not limited thereto. The second source electrode 225 may be insulated from the second gate electrode 223 by the fourth insulating film 224. The second source electrode 225 may include a material different from that of the second gate electrode 223. The second source electrode 225 may be electrically connected to the second source region of the second semiconductor layer 221. For example, the fourth insulating film 224 and the second protective film 150 may include a second source contact hole to partially expose the second source region of the second semiconductor layer 221. The second source electrode 225 may include a region overlapping with the second source region of the second semiconductor layer 221. For example, the second source electrode 225 may contact the second source region of the second semiconductor layer 221 within the second source contact hole.

[0111] A second drain electrode 226 may be disposed on the second protective film 150. The second drain electrode 226 may include a conductive material. For example, the second drain electrode 226 may include a single layer or a double layer including aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), tungsten (W), or an alloy thereof. However, embodiments of the present disclosure are not limited thereto. The second drain electrode 226 may include the same material as the first drain electrode 216. However, embodiments of the present disclosure are not limited thereto. The second drain electrode 226 may be insulated from the second gate electrode 223 by the fourth insulating film 224. The second drain electrode 226 may include a material different from that of the second gate electrode 223. However, embodiments of the present disclosure are not limited thereto. For example, the second drain electrode 226 may include the same material as the second source electrode 225. However, embodiments of the present disclosure are not limited thereto. The second drain electrode 226 may be formed by the same process as the second source electrode 225. The second drain electrode 226 may be electrically connected to the second drain region of the second semiconductor layer 221. The second drain electrode 226 may be separated from the second source electrode 225. For example, the fourth insulating film 224 and the second protective film 150 may include a second drain contact hole to partially expose the second drain region of the second semiconductor layer 221. The second drain electrode 226 may include a region overlapping with the second drain region of the second semiconductor layer 221. For example, the second drain electrode 226 may contact the second drain region of the second semiconductor layer 221 within the second drain contact hole.

[0112] The second thin film transistor 220 may further include an auxiliary layer 232 located below the second semiconductor layer 221. The auxiliary layer 232 may overlap with the second semiconductor layer 221. For example, the auxiliary layer 232 may include a single layer or multiple layers containing aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), nickel (Ni), neodymium (Nd), tungsten (W), or an alloy thereof. However, the embodiments of the present disclosure are not limited thereto. The auxiliary layer 232 may prevent light from reaching the second semiconductor layer 221, thereby increasing the lifespan of the second thin film transistor 220. For example, the auxiliary layer 232 may be a light-shielding layer, but is not limited thereto. For example, the auxiliary layer may be formed below the first thin film transistor 210. The auxiliary layer may be disposed on the buffer layer 112. When forming the auxiliary layer, an insulating film may be further formed on the buffer layer 112. The insulating film may be made of the same material as the auxiliary layer 232. However, the embodiments of the present disclosure are not limited thereto. The auxiliary layer may prevent light from reaching the first semiconductor layer 211, thereby increasing the lifespan of the first thin film transistor 210.

[0113] A buffer film 110 may be disposed between the device substrate 105 and the driving circuit in each pixel region PA. The buffer film 110 may prevent contamination caused by the device substrate 105 during the process of forming the driving circuit. For example, the buffer film 110 may cover the active area of the device substrate 105. For example, the buffer film 110 may completely cover the active area of the device substrate 105. In each pixel region PA, the buffer film 110 may be disposed between the device substrate 105 and the first semiconductor layer 211. The buffer film 110 may include an insulating material. For example, the buffer film 110 may include an inorganic insulating material such as silicon oxide (SiO) or silicon nitride (SiN). However, the embodiments of the present disclosure are not limited thereto. The buffer film 110 may have a multi-layer structure. For example, the buffer film 110 may have a structure in which a first buffer layer 111 and a second buffer layer 112 including a different material from the first buffer layer 111 are stacked. However, the embodiments of the present disclosure are not limited thereto.

[0114] The first protective film 130 may prevent damage to the first thin film transistor 210 due to external impact and moisture. In each pixel region PA, the first protective film 130 may extend between the auxiliary layer 232 and the second semiconductor layer 221. Therefore, in the display device according to the embodiments of the present disclosure, damage to the first thin film transistor 210 due to external impact and moisture can be effectively prevented.

[0115] In each pixel region PA, a second protective film 150 may be provided between the fourth insulating film 224 and the second source electrode 225, and between the fourth insulating film 224 and the second drain electrode 226. The second protective film 150 may prevent damage to the second semiconductor layer 221 due to external shock and moisture. For example, the second protective film 150 may extend along the fourth insulating film 224 to the outside of the second semiconductor layer 221. The second protective film 150 may include a material different from that of the fourth insulating film 224. For example, the fourth protective film 150 may include silicon nitride (SiN). However, embodiments of the present disclosure are not limited thereto. Therefore, in a display device according to an embodiment of the present disclosure, damage to the second semiconductor layer 221 due to external shock and moisture can be effectively prevented.

[0116] In each pixel region PA, a first source electrode 215 of the first thin film transistor may be provided on the second protective film 150. The first source electrode 215 may include a conductive material. For example, the first source electrode 215 may include a single layer or multiple layers including aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), tungsten (W), or an alloy thereof. However, embodiments of the present disclosure are not limited thereto. The first source electrode 215 may include a material different from that of the first gate electrode 213. However, embodiments of the present disclosure are not limited thereto. The first source electrode 215 may be electrically connected to the first source region of the first semiconductor layer 211. For example, the first insulating film 212, the second insulating film 214, the first protective film 130, the fourth insulating film 224, and the second protective film 150 may include a first contact hole to partially expose the first source region of the first semiconductor layer 211 of the first thin film transistor 210. The first source electrode 215 may include a region overlapping with the first source region of the first semiconductor layer 211. For example, the first source electrode 215 may contact the first source region of the first semiconductor layer 211 within the first source contact hole.

[0117] In each pixel region PA, a first drain electrode 216 of the first thin film transistor may be disposed on the second protective film 150. The first drain electrode 216 may include a conductive material. For example, the first drain electrode 216 may include a single layer or multiple layers including aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), tungsten (W), or an alloy thereof. However, embodiments of the present disclosure are not limited thereto. The first drain electrode 216 may include a material different from that of the first gate electrode 213. However, embodiments of the present disclosure are not limited thereto. For example, the first drain electrode 216 may include the same material as the first source electrode 215. However, embodiments of the present disclosure are not limited thereto. The first drain electrode 216 may be formed by the same process as the first source electrode 215. The first drain electrode 216 may be electrically connected to a first drain region of the first semiconductor layer 211. The first drain electrode 216 may be separated from the first source electrode 215. For example, the first insulating film 212, the second insulating film 214, the first protective film 130, the fourth insulating film 224, and the second protective film 150 may include a first contact hole to partially expose the first drain region of the first semiconductor layer 211. The first drain electrode 216 may include a region overlapping with the first drain region of the first semiconductor layer 211. For example, the first drain electrode 216 may contact the first drain region of the first semiconductor layer 211 within the first contact hole.

[0118] The light emitting diode 600 in each pixel region PA may be disposed on the transistor in the corresponding pixel region PA. For example, the first thin film transistor 210 and the second thin film transistor 220 in each pixel region PA may be disposed between the device substrate 105 and the first electrode 610 in the corresponding pixel region PA. Therefore, in the display device according to embodiments of the present disclosure, the area occupied by each pixel region PA may be minimized. Therefore, the display device according to embodiments of the present disclosure may exhibit improved resolution.

[0119] In each pixel region PA, a first protective layer 160 and a second protective layer 170 may be provided between the driving circuit and the light-emitting diode 600. For example, the first electrode 610, the light-emitting layer 620, and the second electrode 630 in each pixel region PA may be provided on the second protective layer 170 in the corresponding pixel region PA. The first protective layer 160 and the second protective layer 170 may reduce or eliminate steps caused by the transistors. For example, in each pixel region PA, the upper surface of the second protective layer 170 facing the light-emitting diode 600 may be a flat surface. The first protective layer 160 and the second protective layer 170 may include an insulating material. For example, the first protective layer 160 and the second protective layer 170 may include an organic insulating material. The second protective layer 170 may include a material different from that of the first protective layer 160. Therefore, in the display device according to an embodiment of the present disclosure, steps caused by the transistors can be effectively reduced or eliminated.

[0120] In each pixel region PA, an intermediate electrode 510 may be provided between the first protective layer 160 and the second protective layer 170. The light-emitting diode 600 may be electrically connected to the first drain electrode 216 of the first thin-film transistor 210 via the intermediate electrode 510. For example, the intermediate electrode 510 may penetrate the first protective layer 160 to connect to the first drain electrode 216, and the first electrode 610 of the light-emitting diode 600 may penetrate the second protective layer 170 to connect to the intermediate electrode 510. The intermediate electrode 510 may include a region overlapping with the first drain electrode 216 and a region overlapping with the first electrode 610. For example, the intermediate electrode 510 may be provided between the first drain electrode 216 and the first electrode 610. The intermediate electrode 510 may be in contact with the first drain electrode 216. For example, the intermediate electrode 510 may be in direct contact with the first drain electrode 216. The first electrode 610 may be in contact with the intermediate electrode 510. For example, the first electrode 610 may be in direct contact with the intermediate electrode 510. The intermediate electrode 510 may include a conductive material. For example, the intermediate electrode 510 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), or tungsten (W). The intermediate electrode 510 may include a material different from that of the first drain electrode 216 and the first electrode 610. However, the embodiments of the present disclosure are not limited thereto.

[0121] In each pixel region PA, a bank 180 may be provided on the second protective layer 170. The bank 180 may include an insulating material. For example, the bank 180 may be made of a material including a black pigment or an organic material such as benzocyclobutene resin, polyimide resin, acrylic resin, or photosensitive polymer. However, embodiments of the present disclosure are not limited thereto. If the bank 180 is made of a material including a black pigment or a black dye, the bank 180 may be a black bank. If the bank 180 is made of a material including a black pigment or a black dye, light from the outside may be blocked, and the brightness of the display device may be further improved. The bank 180 may include a material different from that of the first protective layer 160 and the second protective layer 170. The bank 180 may cover the edge of the first electrode 610. The light-emitting layer 620 and the second electrode 630 in each pixel region PA may be provided on a part of the first electrode 610 exposed by the bank 180. For example, the bank 180 may define a light-emitting region within each pixel region PA.

[0122] In each pixel region PA, a spacer 181 may be provided on the bank 180. The spacer 181 may be formed to have a width smaller than that of the bank 180. The spacer 181 may include an insulating material. For example, the spacer 181 may include an organic insulating material. The spacer 181 may be formed of the same material as the bank 180. However, embodiments of the present disclosure are not limited thereto. The spacer 181 may prevent damage to the bank 180 and the light-emitting material layer 622 formed in adjacent pixel regions PA due to the fine metal mask.

[0123] The light-emitting layer 620 in each pixel region PA may extend onto the bank 180 and the spacer 181. Each pixel region PA may display a color different from that of an adjacent pixel region PA. For example, the light-emitting material layer 622 in each pixel region PA may be separated from the light-emitting material layer 622 in an adjacent pixel region PA. The light-emitting material layer 622 in each pixel region PA may include an end portion located within the corresponding pixel region PA. The light-emitting material layer 622 may be formed using a fine metal mask (FMM). The end portion of each light-emitting material layer 622 may be provided on the bank 180 and the spacer 181. The first common layer 621 and the second common layer 622 of each light-emitting layer 620 may extend along the surface of the bank 180. For example, the first common layer 621 and the second common layer 623 in each pixel region PA may be connected to the first common layer 621 and the second common layer 623 in an adjacent pixel region PA. Therefore, in the display device according to embodiments of the present disclosure, process efficiency may be improved.

[0124] The voltage provided to the second electrode 630 in each pixel region PA may be the same as the voltage provided to the second electrode 630 in an adjacent pixel region PA. For example, the second electrode 630 in each pixel region PA may be connected to the second electrode 630 in a pixel region PA adjacent to the bank 180. Thus, the display device according to an embodiment of the present disclosure may control the brightness of each pixel region PA by applying a gate signal and a data signal to the corresponding pixel region PA. The second electrode 630 in each pixel region PA may be in contact with the second electrode 630 in an adjacent pixel region PA.

[0125] In each pixel region PA, an encapsulation member 700 may be disposed on the light-emitting diode 600. The encapsulation member 700 may prevent damage to the light-emitting diode 600 due to external impact and moisture. The encapsulation member 700 may have a multilayer structure. However, embodiments of the present disclosure are not limited thereto. For example, the encapsulation member 700 may include a first encapsulation layer 710, a second encapsulation layer 720, and a third encapsulation layer 730. However, embodiments of the present disclosure are not limited thereto. The first encapsulation layer 710, the second encapsulation layer 720, and the third encapsulation layer 730 may include an insulating material. The second encapsulation layer 720 may include a material different from that of the first encapsulation layer 710 and the third encapsulation layer 730. However, embodiments of the present disclosure are not limited thereto. For example, the first encapsulation layer 710 and the third encapsulation layer 730 may include an inorganic insulating material, and the second encapsulation layer 720 may include an organic insulating material. Thus, in the display device according to an embodiment of the present disclosure, damage to the light-emitting diode 600 due to external impact and moisture may be effectively prevented. The step caused by the light-emitting diode 600 in each pixel region PA may be removed by the encapsulation member 700. For example, the upper surface of the encapsulation member 700 facing the device substrate 105 may be a flat surface.

[0126] A touch unit may be provided on the encapsulation member 700. The touch unit may detect touches of a user and / or a tool. For example, the touch unit may include touch electrodes 811 and 822 and a bridging electrode 812. The touch electrodes 811 and 822 may be arranged parallel to each other. The bridging electrode 812 may interconnect the touch electrodes 811 and 822. The touch electrodes 811 and 822 and the bridging electrode 812 may include a conductive material. For example, the touch electrodes 811 and 822 and the bridging electrode 812 may include a single layer or a double layer including aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), tungsten (W), or an alloy thereof. However, embodiments of the present disclosure are not limited thereto. The touch electrodes 811 and 822 and the bridging electrode 812 may overlap with the active area of the device substrate 105. The light-emitting diodes 600 in each pixel area PA may be provided outside the touch electrodes 811 and 822 and the bridging electrode 812. For example, the touch electrodes 811 and 822 and the bridging electrode 812 may overlap with the bank 180. In each pixel area PA, the touch electrodes 811 and 822 and the bridging electrode 812 may be separated from the light-emitting diodes 600. Therefore, in the display device according to an embodiment of the present disclosure, the light emitted from each light-emitting diode 600 in a direction perpendicular to the upper surface of the device substrate 105 may not be blocked by the touch electrodes 811 and 822 and the bridging electrode 812. Therefore, in the display device according to an embodiment of the present disclosure, it is possible to prevent the brightness of each pixel area PA from being reduced due to the touch electrodes 811 and 822 and the bridging electrode 812.

[0127] A touch insulating film 830 may be provided between the bridging electrode 812 and the touch electrodes 811 and 822. The touch insulating film 830 may include an insulating material. For example, the touch insulating film 830 may include a material such as silicon oxide (SiOx) or silicon nitride (SiNx). However, embodiments of the present disclosure are not limited thereto. The second touch electrode 822 may be provided on the same layer as the first touch electrode 811. For example, the touch electrodes 811 and 822 may be provided on the touch insulating film 830 covering the bridging electrode 812. The touch insulating film 830 may include touch contact holes to partially expose the bridging electrode 812. The touch electrode 811 may be connected to the corresponding bridging electrode 812 through one of the touch contact holes.

[0128] A touch buffer film 800 may be provided between the encapsulation member 700 and the elements 811, 812, and 822 of the touch unit. The touch buffer film 800 may prevent damage to the encapsulation member 700 and the light-emitting diodes 600 due to the process of forming the touch electrodes 811 and 822 and the bridging electrode 812. The touch buffer film 800 may include an insulating material. For example, the touch buffer film 800 may include a material such as silicon oxide (SiOx) or silicon nitride (SiNx). However, embodiments of the present disclosure are not limited thereto.

[0129] An insulating film 890 may be provided on elements 811, 812, and 822 of the touch unit. The insulating film 890 may prevent damage to the elements 811, 812, and 822 of the touch unit due to external impact and moisture.

[0130] Figure 4 is a diagram for explaining an operation method of a display device according to the present disclosure.

[0131] Refer to Figure 1 and Figure 2 The display device according to the present disclosure may adopt a variable refresh rate (VRR) technology to achieve low power consumption. The VRR technology with a changed frequency may be used to drive the display device.

[0132] For example, the display device may be driven at 120 Hz and then may be driven at 60 Hz. If the display device is driven while changing the frequency, visibility must be reduced when changing the frequency. Therefore, when the display device is driven at 120 Hz and then at 60 Hz, an intermediate frequency (80 Hz, 48 Hz, etc.) may be used to reduce visibility.

[0133] To use the intermediate frequency, the display device needs to be driven using an anode reset frame. For example, the anode reset frame may be set to 4 ms (Scan3 240 Hz). However, the embodiments of the present disclosure are not limited thereto.

[0134] To implement driving using the anode reset frame, an anode reset line ARL for supplying an anode reset signal VAR to an anode of each pixel P may be required.

[0135] Figure 5 is a layout diagram showing an anode reset line of a display device according to an embodiment of the present disclosure.

[0136] Figure 6 is a layout diagram showing a circuit configuration of each pixel and an anode reset line in a display device according to an embodiment of the present disclosure.

[0137] In a display device according to an embodiment of the present disclosure, when an organic light emitting diode OLED emits light, different anode reset lines ARL may be connected to a plurality of pixels P to improve a voltage deviation of a fourth node N4 and improve current leakage and color change.

[0138] For example, a first pixel and a second pixel may be connected to a first anode reset line ARL1, and a third pixel may be connected to a second anode reset line ARL2.

[0139] The first anode reset line ARL1 and the second anode reset line ARL2 can be provided in each pixel row such that the first anode reset line ARL1 is connected to the first pixel and the second pixel, and the second anode reset line ARL2 is connected to the third pixel.

[0140] As Figure 5 and Figure 6 shown in, the first anode reset line ARL1 and the second anode reset line ARL2 can be provided in each pixel row. The first pixel and the second pixel provided in the corresponding pixel row can be connected to the first anode reset line ARL1 provided in the corresponding pixel row. The third pixel provided in the corresponding pixel row can be connected to the second anode reset line ARL2 provided in the corresponding pixel row. However, the embodiments of the present disclosure are not limited thereto. Each of the first pixel and the second pixel can be one of a red pixel R and a blue pixel B, but is not limited thereto. The third pixel can be a green pixel G, but is not limited thereto.

[0141] For example, the red pixel R provided in the corresponding pixel row and the blue pixel B provided in the corresponding pixel row can be connected to the first anode reset line ARL1, and the green pixel G provided in the corresponding pixel row can be connected to the second anode reset line ARL2.

[0142] In another example, the red pixel R provided in the corresponding pixel row and the green pixel G provided in the corresponding pixel row can be connected to the first anode reset line ARL1, and the blue pixel B provided in the corresponding pixel row can be connected to the second anode reset line ARL2.

[0143] In yet another example, the blue pixel B provided in the corresponding pixel row and the green pixel G provided in the corresponding pixel row can be connected to the first anode reset line ARL1, and the red pixel R provided in the corresponding pixel row can be connected to the second anode reset line ARL2.

[0144] Although it is shown in Figure 5 that the first pixel and the second pixel provided in the corresponding pixel row are connected to the first anode reset line ARL1 and the third pixel provided in the corresponding pixel row is connected to the second anode reset line ARL2, the embodiments of the present disclosure are not limited thereto. In another example, the first pixel and the second pixel provided in the next pixel row can be connected to the first anode reset line ARL1 provided in the corresponding pixel row, and the third pixel provided in the next pixel row can be connected to the second anode reset line ARL2 provided in the corresponding pixel row.

[0145] As Figure 6 shown in, the first pixel and the second pixel provided in the corresponding pixel row can be connected to the first anode reset line ARL1, and the third pixel provided in the corresponding pixel row can be connected to the second anode reset line ARL2.

[0146] According to an embodiment of the present disclosure, two anode reset lines may be provided in each pixel. For example, the two anode reset lines may individually apply an anode reset voltage to a green pixel G, a red pixel R, and a blue pixel B. Accordingly, the degree of freedom in voltage setting may be increased, thereby improving the performance of the display panel.

[0147] As Figure 6 shown, an anode reset line for providing an anode reset voltage to an organic light-emitting diode OLED may be provided in each pixel. In order to provide a uniform anode reset voltage to all pixels of the display device, the anode reset line may be formed in a mesh structure.

[0148] For example, the anode reset lines of the pixels may be electrically connected to each other through a connection line TM1 and a connection line SD1. The connection line TM1 is made of the same material as at least one gate electrode of a thin film transistor constituting each pixel, and the connection line SD1 is made of the same material as at least one source electrode / drain electrode of the thin film transistor.

[0149] Figure 7 is an exemplary cross-sectional view showing the connection relationship of the anode reset lines.

[0150] Figure 7 Exemplarily shown are a driving transistor D-TFT and a sixth transistor T6 that provide an anode reset voltage VAR to a fourth node N4 in the circuit diagram of the pixel described with reference to Figure 2 For example, a light-shielding layer 17 may be provided on the device substrate 105 at a position below the driving transistor D-TFT. A plurality of buffer layers 11 and 12 may be provided on the light-shielding layer 17. The plurality of buffer layers 11 and 12 may include an inorganic insulating material. However, the embodiments of the present disclosure are not limited thereto. The plurality of buffer layers 11 and 12 may prevent moisture from penetrating through the interface of the device substrate 105. The buffer layers 11 and 12 may correspond to

[0151] the buffer layers 111 and 112 shown in Figure 3 A sixth transistor T6 including a first semiconductor layer 1, a first insulating film 2, and a first gate electrode 3 may be formed on the plurality of buffer layers 11 and 12.

[0152] A driving transistor D-TFT including a second semiconductor layer 4, a first insulating film 2, and a second gate electrode 5 may be formed on the plurality of buffer layers 11 and 12 above the light-shielding layer 17.

[0153]

[0154] ​A second insulating film 6 may be provided on the entire surface of the device substrate 105 on which the first gate electrode 3 and the second gate electrode 5 are formed. A metal layer 7 (corresponding to TM1 shown in Figure 6 ) may be provided on the second insulating film 6 at a position above the second gate electrode 5, so that a storage capacitor Cstg can be formed between the second gate electrode 5 of the driving transistor D-TFT and the metal layer 7. The metal layer 7 may be a gate electrode, but is not limited thereto. For example, the metal layer 7 may be provided on the second gate electrode 5 and may be a third gate electrode.

[0155] A first protective film 8, a second protective film 9, and a third protective film 10 may be formed on the entire surface of the device substrate 105 on which the metal layer 7 is formed.

[0156] A connection line 26 (corresponding to SD1 shown in Figure 6 ), a first anode reset line ARL1, and a second anode reset line ARL2 may be provided on the third protective film 10. The connection line 26 may be electrically connected to the metal layer 7 (TM1) on the driving transistor D-TFT. For example, contact holes may be formed in the first protective film 8, the second protective film 9, and the third protective film 10, and the connection line 26 may be provided to be electrically connected to the metal layer 7 (TM1) on the driving transistor D-TFT through the contact holes. In addition, a fourth protective film 16 may be provided on the connection line 26, the first anode reset line ARL1, and the second anode reset line ARL2.

[0157] Figure 8 is a layout diagram showing an anode reset line of a display device according to another embodiment of the present disclosure.

[0158] Figure 9 is a layout diagram showing a circuit configuration of each pixel and an anode reset line in a display device according to another embodiment of the present disclosure.

[0159] As shown in Figure 8 and Figure 9 , green pixels G, blue pixels B, green pixels G, red pixels R, green pixels G, and blue pixels B may be arranged in this order in the (2k - 1)th pixel row (k is a natural number). For example, one pixel may include a red pixel R, a green pixel G, a blue pixel B, and a green pixel G. However, the embodiments of the present disclosure are not limited thereto.

[0160] Green pixels G, red pixels R, green pixels G, blue pixels B, green pixels G, and red pixels R may be arranged in this order in the 2kth pixel row. However, the embodiments of the present disclosure are not limited thereto.

[0161] For ease of description, although reference is made to Figure 8 and Figure 9Pixels of corresponding colors of embodiments of the present disclosure are described, but embodiments of the present disclosure are not limited thereto. In another embodiment, blue pixels B, green pixels G, blue pixels B, red pixels R, blue pixels B, and green pixels G may be arranged in this order in the (2k - 1)th pixel row, and blue pixels B, red pixels R, blue pixels B, green pixels G, blue pixels B, and red pixels R may be arranged in this order in the 2kth pixel row.

[0162] In another embodiment, red pixels R, green pixels G, red pixels R, blue pixels B, red pixels R, and green pixels G may be arranged in this order in the (2k - 1)th pixel row, and red pixels R, blue pixels B, red pixels R, green pixels G, red pixels R, and blue pixels B may be arranged in this order in the 2kth pixel row.

[0163] In two adjacent pixel rows, two pixels of the same color may be arranged vertically, and the remaining two pixels of different colors may be arranged alternately vertically.

[0164] The second anode reset line ARL2 may be arranged in the (2k - 1)th pixel row, and the first anode reset line ARL1 may be arranged in the 2kth pixel row.

[0165] The first pixel and the second pixel arranged in two adjacent pixel rows may be connected to the first anode reset line ARL1, and the two third pixels arranged in two adjacent pixel rows may be connected to the second anode reset line ARL2.

[0166] According to an embodiment of the present disclosure, the red pixel R and the blue pixel B arranged vertically in two adjacent pixel rows may be connected to the first anode reset line ARL1. The two green pixels G arranged vertically in two adjacent pixel rows may be connected to the second anode reset line ARL2. However, embodiments of the present disclosure are not limited thereto.

[0167] For example, the red pixel R and the green pixel G arranged vertically in two adjacent pixel rows may be connected to the first anode reset line ARL1, and the two blue pixels B arranged vertically in two adjacent pixel rows may be connected to the second anode reset line ARL2.

[0168] In another example, the blue pixel B and the green pixel G arranged vertically in two adjacent pixel rows may be connected to the first anode reset line ARL1, and the two red pixels R arranged vertically in two adjacent pixel rows may be connected to the second anode reset line ARL2.

[0169] In a display device according to another embodiment of the present disclosure, the number of the first anode reset line ARL1 and the second anode reset line ARL2 can be reduced to half, so that the overlapping capacitance formed due to the overlap between the anode reset line and the signal line of GIP can be reduced. In addition, the ripple occurring in the anode reset voltage VAR provided through the anode reset line due to the coupling effect of the overlapping capacitance can be reduced.

[0170] Therefore, due to the reduction of the ripple of the anode reset voltage VAR, banding defects can be prevented from occurring in the central portion of the display panel. For example, a central banding (CBM) defect can be prevented from occurring at the center of the display panel.

[0171] According to another embodiment of the present disclosure, the first anode reset line ARL1 and the second anode reset line ARL2 can be provided in each pixel row. Two adjacent first anode reset lines ARL1 can be connected to each other, and two adjacent second anode reset lines ARL2 can be connected to each other. Thus, the first anode reset line ARL1 and the second anode reset line ARL2 can be each provided in a mesh structure. Therefore, the overlapping capacitance can be reduced, and the ripple of the anode reset voltage VAR can be reduced. As a result, banding defects can be prevented from occurring in the central portion of the display panel. In addition, since the first anode reset line ARL1 and the second anode reset line ARL2 are each formed as lines for forming a mesh structure, the capacitance between the lines can be reduced, and a separate line does not need to be provided, thus simplifying the process.

[0172] As Figure 9 shown, an anode reset line for providing an anode reset voltage to the organic light-emitting diode OLED can be provided in each pixel. In order to provide a uniform anode reset voltage to all pixels of the display device, the anode reset line can be formed in a mesh structure.

[0173] For example, the anode reset lines of the pixels can be electrically connected to each other via a connection line TM1 and a connection line SD1. The connection line TM1 is made of the same material as at least one gate electrode of the thin-film transistors constituting each pixel, and the connection line SD1 is made of the same material as at least one source electrode / drain electrode of the thin-film transistors.

[0174] In this configuration, the connection line SD1 can be cut such that a high-potential driving voltage ELVDD is provided to one side of the connection line SD1, and the other side of the connection line SD1 is used as the first anode reset line ARL1 or the second anode reset line ARL2 for providing the anode reset voltage VAR.

[0175] Figure 10 is an exemplary cross-sectional view showing the connection relationship of the anode reset lines.

[0176] Figure 10 Exemplarily shown in reference toFigure 2 In the circuit diagram of the described pixel, the driving transistor D-TFT and the sixth transistor T6 that supply the anode reset voltage VAR to the fourth node N4. Figure 10 The circuit diagram of each pixel shown in Figure 2 may be substantially the same as the circuit diagram shown in

[0177] For example, the light-shielding layer 17 may be provided on the device substrate 105 at a position below the driving transistor D-TFT. A plurality of buffer layers 11 and 12 may be provided on the light-shielding layer 17. The plurality of buffer layers 11 and 12 may include an inorganic insulating material. However, the embodiments of the present disclosure are not limited thereto. The plurality of buffer layers 11 and 12 may prevent moisture from penetrating through the interface of the device substrate 105. The buffer layers 11 and 12 may correspond to Figure 3 the buffer layers 111 and 112 shown in

[0178] The sixth transistor T6 including the first semiconductor layer 1, the first insulating film 2, and the first gate electrode 3 may be formed on the plurality of buffer layers 11 and 12.

[0179] The driving transistor D-TFT including the second semiconductor layer 4, the gate insulating film 2, and the second gate electrode 5 may be formed on the plurality of buffer layers 11 and 12 above the light-shielding layer 17.

[0180] The second insulating film 6 may be provided on the entire surface of the device substrate 105 on which the first gate electrode 3 and the second gate electrode 5 are formed. The metal layer 7 may be provided on the second insulating film 6 at a position above the second gate electrode 5. Thus, the storage capacitor Cstg may be formed between the second gate electrode 5 of the driving transistor D-TFT and the metal layer 7. For example, the metal layer 7 may be a gate electrode. However, the embodiments of the present disclosure are not limited thereto. For example, the metal layer 7 may be provided on the second gate electrode 5 and may be a third gate electrode.

[0181] The first protective film 8, the second protective film 9, and the third protective film 10 may be provided on the entire surface of the device substrate 105 on which the metal layer 7 is formed.

[0182] A connection line 26 may be provided on the third protective film 10. The connection line 26 may electrically connect the first semiconductor layer 1 of the sixth transistor T6 of a corresponding pixel to the first semiconductor layer 1' of the sixth transistor T6' of an adjacent pixel. For example, contact holes may be formed in the first protective film 8, the second protective film 9, and the third protective film 10 such that a part of the first semiconductor layer 1 of the sixth transistor T6 of a corresponding pixel and a part of the first semiconductor layer 1' of the sixth transistor T6' of an adjacent pixel are exposed. The connection line 26 may be provided on the third protective film 10 to electrically connect the first semiconductor layer 1 of the sixth transistor T6 of a corresponding pixel to the first semiconductor layer 1' of the sixth transistor T6' of an adjacent pixel through the contact holes. The connection line 26 may connect a corresponding pixel to an adjacent pixel in a vertical direction. For example, when a corresponding pixel is a blue pixel, a vertically adjacent pixel is a red pixel. Thus, the blue pixel and the red pixel may be connected to the connection line 26 in the vertical direction.

[0183] In addition, a fourth protective film 16 may be provided on the connection line 26.

[0184] According to the present disclosure, the metal layer 7 and the connection line 26 may not be connected to each other. One side of the metal layer 7 may be connected to a line to which a high potential driving voltage ELVDD is applied, and the other side of the metal layer 7 may be connected to the connection line 26. For example, the metal layer 7 may be cut such that one side of the metal layer 7 is provided with the high potential driving voltage ELVDD, and the other side of the metal layer 7 is configured to provide an anode reset voltage VAR to the connection line 26. For example, the other side of the metal layer 7 may be connected to the connection line 26 in a vertical direction.

[0185] Figure 11 is a layout diagram of an anode reset line of a display device according to another embodiment of the present disclosure.

[0186] Figure 12 is a layout diagram of a circuit configuration of each pixel and an anode reset line in a display device according to another embodiment of the present disclosure.

[0187] As Figure 11 and Figure 12 shown, green pixels G, blue pixels B, green pixels G, red pixels R, green pixels G, and blue pixels B may be arranged in this order in the (2k - 1)th pixel row. However, embodiments of the present disclosure are not limited thereto.

[0188] Green pixels G, red pixels R, green pixels G, blue pixels B, green pixels G, and red pixels R may be arranged in this order in the 2kth pixel row. However, embodiments of the present disclosure are not limited thereto.

[0189] For ease of description, although reference is made to Figure 11 and Figure 12Pixels of the corresponding color of the embodiment are described, but the embodiments of the present disclosure are not limited thereto. As referred to above Figure 8 and Figure 9 As described, in two adjacent pixel rows, two pixels of the same color may be arranged in the vertical direction, and the other two pixels of different colors may be arranged in the vertical direction. Such an arrangement may be repeated in an alternating manner.

[0190] The first anode reset line ARL1 and the second anode reset line ARL2 may be arranged in each pixel row.

[0191] The first anode reset line ARL1 and the second anode reset line ARL2 may be arranged in the (2k−1)-th pixel row in this order, and the second anode reset line ARL2 and the first anode reset line ARL1 may be arranged in the 2k-th pixel row in this order.

[0192] In addition, the first pixel and the second pixel arranged in the corresponding pixel row may be connected to the first anode reset line ARL1. The third pixel arranged in the corresponding pixel row may be connected to the second anode reset line ARL2.

[0193] According to another embodiment of the present disclosure, when the anode reset line is arranged, two adjacent first anode reset lines ARL1 may be connected to each other such that the two adjacent first anode reset lines ARL1 may have a mesh structure.

[0194] In addition, two adjacent second anode reset lines ARL2 may be connected to each other such that the two adjacent second anode reset lines ARL2 may also have a mesh structure.

[0195] Therefore, when the first anode reset line ARL1 and the second anode reset line ARL2 are arranged in each pixel row, the adjacent first anode reset lines ARL1 are connected to each other to have a mesh structure, and the adjacent second anode reset lines ARL2 are connected to each other to have a mesh structure. As a result, the ripple of the anode reset voltage VAR can be reduced. Therefore, banding defects in the central portion of the display panel can be prevented.

[0196] According to the present disclosure, the connection relationship of the anode reset line may be substantially the same as that referred to in Figure 10 the description.

[0197] A display device according to various embodiments of the present disclosure can be applied to mobile devices, video phones, smart watches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, sliding devices, variable devices, electronic organizers, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop personal computers (PCs), laptop PCs, netbook computers, workstations, navigation devices, automotive navigation devices, automotive display devices, automotive devices, theater devices, theater display devices, TVs, wallpaper display devices, signage devices, game consoles, laptops, displays, cameras, camcorders, household appliances, and the like.

[0198] A display device according to various embodiments of the present disclosure can be described as follows.

[0199] A display device according to various embodiments of the present disclosure may include: a substrate on which a plurality of pixels are disposed in a column direction and a row direction; light-emitting diodes disposed in each of the plurality of pixels; a first anode reset line disposed in each row in which some of the plurality of pixels are located; and a second anode reset line disposed in each row in which the remaining pixels of the plurality of pixels are located.

[0200] According to various embodiments of the present disclosure, the plurality of pixels may include: a first pixel connected to the first anode reset line; a second pixel connected to the first anode reset line; and a third pixel connected to the second anode reset line.

[0201] According to various embodiments of the present disclosure, the first pixel disposed in a corresponding pixel row and the second pixel disposed in a next pixel row may be connected to the first anode reset line. The third pixel disposed in the corresponding pixel row and the third pixel disposed in the next pixel row may be connected to the second anode reset line.

[0202] According to various embodiments of the present disclosure, the first anode reset line and the second anode reset line may be disposed in each pixel row.

[0203] According to various embodiments of the present disclosure, the first anode reset line and another adjacent first anode reset line may be connected to each other to have a mesh structure. The second anode reset line and another adjacent second anode reset line may be connected to each other to have a mesh structure.

[0204] According to various embodiments of the present disclosure, a first pixel and a second pixel provided in a corresponding pixel row may be connected to the first anode reset line. A third pixel provided in the corresponding pixel row may be connected to the second anode reset line.

[0205] According to various embodiments of the present disclosure, each of the plurality of pixels may include one or more transistors, a driving transistor, and a storage capacitor.

[0206] According to various embodiments of the present disclosure, a semiconductor layer of each of the driving transistor and the one or more transistors is an oxide semiconductor layer or a low-temperature polycrystalline silicon semiconductor layer.

[0207] According to various embodiments of the present disclosure, the driving transistor may be connected to a second node. The one or more transistors may include: a first transistor connected between the second node and a third node; a second transistor connected to a first node; a third transistor connected to the first node; a fourth transistor connected between the third node and a fourth node; a fifth transistor connected to the second node; a sixth transistor connected to the fourth node; and a seventh transistor connected to the first node.

[0208] According to various embodiments of the present disclosure, the display device may further include a storage capacitor connected between a high-potential driving voltage terminal and the second node.

[0209] According to various embodiments of the present disclosure, the light-emitting diode may be connected between the fourth node and a low-potential driving voltage terminal.

[0210] According to various embodiments of the present disclosure, the first anode reset line may be provided in the 2k-th pixel row, where k is a natural number. The second anode reset line may be provided in the (2k - 1)-th pixel row.

[0211] According to various embodiments of the present disclosure, a third pixel, a second pixel, a third pixel, a first pixel, a third pixel, and a second pixel may be provided in the 2k-th pixel row in this order. A third pixel, a first pixel, a third pixel, a second pixel, a third pixel, and a first pixel may be provided in the (2k - 1)-th pixel row in this order.

[0212] According to various embodiments of the present disclosure, a second pixel and a first pixel in a vertical direction provided in two adjacent pixel rows may be connected to the first anode reset line. A third pixel and another third pixel in a vertical direction provided in two adjacent pixel rows may be connected to the second anode reset line.

[0213] According to various embodiments of the present disclosure, each of the plurality of pixels may include one or more transistors and a driving transistor. The first anode reset line or the second anode reset line includes the same material as the source electrode and the drain electrode of one of the one or more transistors and the driving transistor.

[0214] A display device according to various embodiments of the present disclosure may include: a substrate on which a plurality of pixels are arranged in a column direction and a row direction; a light emitting diode disposed in the plurality of pixels; and a first anode reset line and a second anode reset line disposed in each pixel row. The first anode reset line and the second anode reset line may be arranged in this order in the (2k-1)th pixel row, where k is a natural number. The second anode reset line and the first anode reset line may be arranged in this order in the 2kth pixel row. The first anode reset line and another adjacent first anode reset line may be connected to each other to have a mesh structure, and the second anode reset line and another adjacent second anode reset line may be connected to each other to have a mesh structure.

[0215] A display device according to various embodiments of the present disclosure may include: a substrate on which a plurality of pixels are arranged in a column direction and a row direction; a light emitting diode disposed in the plurality of pixels; a second anode reset line disposed in the (2k-1)th pixel row, where k is a natural number; and a first anode reset line disposed in the 2kth pixel row. The third pixel disposed in the (2k-1)th pixel row and the third pixel disposed in the 2kth pixel row may be connected to the second anode reset line. The first pixel disposed in the 2kth pixel row and the second pixel disposed in the (2k+1)th pixel row may be connected to the first anode reset line.

[0216] A display device according to various embodiments of the present disclosure may include: a substrate on which a plurality of pixels are arranged in a column direction and a row direction; a light emitting diode disposed in the plurality of pixels; a first anode reset line disposed in each odd pixel row and connecting pixels of different colors among the light emitting diodes; and a second anode reset line disposed in each even pixel row and connecting pixels of the same color among the light emitting diodes.

[0217] According to various embodiments of the present disclosure, each of the plurality of pixels may include one or more transistors, a driving transistor, and a storage capacitor.

[0218] According to various embodiments of the present disclosure, the semiconductor layer of the driving transistor and each of the one or more transistors is an oxide semiconductor layer or a low-temperature polycrystalline silicon semiconductor layer.

[0219] According to various embodiments of the present disclosure, the display device may further include: a packaging member disposed on the light-emitting diode; and a touch unit disposed on the packaging member.

[0220] According to various embodiments of the present disclosure, in two adjacent pixel rows, two pixels of the same color may be disposed in the vertical direction, and the remaining two pixels of different colors may be disposed in an alternating manner in the vertical direction.

[0221] According to various embodiments of the present disclosure, the third pixel, the first pixel, the third pixel, the second pixel, the third pixel, and the first pixel may be disposed in this order in the odd pixel rows, and the third pixel, the second pixel, the third pixel, the first pixel, the third pixel, and the second pixel may be disposed in this order in the even pixel rows.

[0222] As is apparent from the above description, according to the present disclosure, the voltage deviation and color change of the anode can be improved by applying different anode reset voltages to a plurality of pixels.

[0223] According to the present disclosure, in a display device driven in a VRR manner, the anode reset line for supplying the anode reset voltage to the anode of the light-emitting diode can be minimized or can be arranged in a mesh structure. Accordingly, the overlapping capacitance formed due to the overlap between the anode reset line of the GIP and the signal line can be reduced.

[0224] According to the present disclosure, it is possible to prevent ripples from occurring in the anode reset voltage VAR supplied through the anode reset line due to the coupling effect of the overlapping capacitance.

[0225] According to the present disclosure, since the ripples of the anode reset voltage VAR are reduced, it is possible to prevent banding defects from occurring in the central portion of the display panel.

[0226] According to the present disclosure, since the overlapping capacitance formed due to the overlap between the anode reset line and the signal line of the GIP is reduced and ripples are prevented from occurring in the anode reset voltage VAR supplied through the anode reset line, the defect rate of the display device can be reduced. Accordingly, the amount of energy consumed in manufacturing the display device can be reduced, and the amount of greenhouse gases generated during the manufacturing process can be reduced. Therefore, the present disclosure has environmental / social / governance (ESG) effects.

[0227] Those skilled in the art will understand that various modifications and substitutions can be made from the above description without departing from the technical idea of the present disclosure. Therefore, the technical scope of the present disclosure is defined by the appended claims, rather than by the detailed description of the present disclosure.

Claims

1. A display device, comprising: a substrate, on which a plurality of pixels are provided in a column direction and a row direction; light-emitting diodes, which are provided in each of the plurality of pixels; a first anode reset line, which is provided in each row in which some of the plurality of pixels are located; and a second anode reset line, which is provided in each row in which the remaining pixels of the plurality of pixels are located.

2. The display device according to claim 1, wherein the plurality of pixels include: a first pixel, which is connected to the first anode reset line; a second pixel, which is connected to the first anode reset line; and a third pixel, which is connected to the second anode reset line.

3. The display device according to claim 2, wherein the first pixel provided in a corresponding pixel row and the second pixel provided in a next pixel row are connected to the first anode reset line, and wherein the third pixel provided in the corresponding pixel row and the third pixel provided in the next pixel row are connected to the second anode reset line.

4. The display device according to claim 2, wherein the first anode reset line and the second anode reset line are provided in each pixel row.

5. The display device according to claim 4, wherein the first anode reset line and another adjacent first anode reset line are connected to each other to have a mesh structure, and wherein the second anode reset line and another adjacent second anode reset line are connected to each other to have a mesh structure.

6. The display device according to claim 4, wherein the first pixel and the second pixel provided in a corresponding pixel row are connected to the first anode reset line, and wherein the third pixel provided in the corresponding pixel row is connected to the second anode reset line.

7. The display device according to claim 1, wherein each of the plurality of pixels includes one or more transistors, a driving transistor, and a storage capacitor.

8. The display device according to claim 7, wherein a semiconductor layer of each of the driving transistor and the one or more transistors is an oxide semiconductor layer or a low-temperature polycrystalline silicon semiconductor layer.

9. The display device according to claim 8, wherein the driving transistor is connected to a second node, and wherein the one or more transistors include: a first transistor, which is connected between the second node and a third node; a second transistor, which is connected to a first node; a third transistor, which is connected to the first node; a fourth transistor, which is connected between the third node and a fourth node; a fifth transistor, which is connected to the second node; a sixth transistor, which is connected to the fourth node; and a seventh transistor, which is connected to the first node.

10. The display device according to claim 9, further comprising a storage capacitor, which is connected between a high-potential driving voltage terminal and the second node.

11. The display device according to claim 9, wherein the light-emitting diode is connected between the fourth node and a low-potential driving voltage terminal.

12. The display device according to claim 1, wherein the first anode reset line is provided in the 2k-th pixel row, where k is a natural number, and wherein the second anode reset line is provided in the (2k - l)-th pixel row.

13. The display device according to claim 12, wherein third pixels, first pixels, third pixels, second pixels, third pixels, and first pixels are arranged in this order in the (2k - l)-th pixel row, and wherein third pixels, second pixels, third pixels, first pixels, third pixels, and second pixels are arranged in this order in the 2k-th pixel row.

14. The display device according to claim 13, wherein the second pixels and the first pixels in the vertical direction provided in two adjacent pixel rows are connected to the first anode reset line, and wherein the third pixels and another third pixel in the vertical direction provided in two adjacent pixel rows are connected to the second anode reset line.

15. The display device according to claim 1, wherein each of the plurality of pixels includes one or more transistors and a driving transistor, and wherein the first anode reset line or the second anode reset line includes the same material as the source electrode and the drain electrode of one of the one or more transistors and the driving transistor.

16. A display device, comprising: a substrate on which a plurality of pixels are provided in a column direction and a row direction; a light-emitting diode provided in the plurality of pixels; and a first anode reset line and a second anode reset line provided in each pixel row, wherein the first anode reset line and the second anode reset line are arranged in this order in the (2k - 1)-th pixel row, where k is a natural number, wherein the second anode reset line and the first anode reset line are arranged in this order in the 2k-th pixel row, wherein the first anode reset line and another adjacent first anode reset line are connected to each other to have a mesh structure, and wherein the second anode reset line and another adjacent second anode reset line are connected to each other to have a mesh structure.

17. The display device according to claim 16, wherein third pixels, first pixels, third pixels, second pixels, third pixels, and first pixels are arranged in this order in the (2k - 1)-th pixel row, and wherein third pixels, second pixels, third pixels, first pixels, third pixels, and second pixels are arranged in this order in the 2k-th pixel row.

18. A display device, comprising: a substrate on which a plurality of pixels are provided in a column direction and a row direction; a light-emitting diode provided in the plurality of pixels; a second anode reset line provided in the (2k - 1)-th pixel row, where k is a natural number; and a first anode reset line provided in the 2k-th pixel row, The third pixel provided in the (2k - 1)-th pixel row and the third pixel provided in the 2k-th pixel row are connected to a second anode reset line, and the first pixel provided in the 2k-th pixel row and the second pixel provided in the (2k + 1)-th pixel row are connected to a first anode reset line.

19. The display device according to claim 18, wherein the third pixel, the first pixel, the third pixel, the second pixel, the third pixel, and the first pixel are provided in the (2k - 1)-th pixel row in this order, and wherein the third pixel, the second pixel, the third pixel, the first pixel, the third pixel, and the second pixel are provided in the 2k-th pixel row in this order.

20. A display device, comprising: a substrate, on which a plurality of pixels are provided in a column direction and a row direction; light-emitting diodes, which are provided in the plurality of pixels; a first anode reset line, which is provided in each odd pixel row and connects pixels of different colors among the light-emitting diodes; and a second anode reset line, which is provided in each even pixel row and connects pixels of the same color among the light-emitting diodes.

21. The display device according to claim 1, 16, 18, or 20, wherein each of the plurality of pixels includes one or more transistors, a driving transistor, and a storage capacitor, and wherein the semiconductor layer of each of the driving transistor and the one or more transistors is an oxide semiconductor layer or a low-temperature polycrystalline silicon semiconductor layer.

22. The display device according to claim 1, 16, 18, or 20, further comprising: a packaging member, which is provided on the light-emitting diodes; and a touch unit, which is provided on the packaging member.

23. The display device according to claim 20, wherein in two adjacent pixel rows, two pixels of the same color are provided in a vertical direction, and the remaining two pixels of different colors are provided in an alternating manner in the vertical direction.

24. The display device according to claim 20, wherein the third pixel, the first pixel, the third pixel, the second pixel, the third pixel, and the first pixel are provided in the odd pixel row in this order, and wherein the third pixel, the second pixel, the third pixel, the first pixel, the third pixel, and the second pixel are provided in the even pixel row in this order.

Images