Display panel and display device

Abstract

The invention provides a display panel and a display device, and relates to the technical field of display, the display panel comprises a display area and a non-display area, the non-display area comprises a binding area, and the display panel comprises a substrate, a first conductive layer, a passivation layer and an anode layer which are stacked in sequence; in the binding area, the first conductive layer comprises a plurality of signal lines which are arranged at intervals, the anode layer comprises a plurality of anode patterns, and the anode patterns are electrically connected with the corresponding signal lines through conductive via holes of the passivation layer; a blocking structure is arranged on the surface of the side, away from the substrate, of the passivation layer in a gap area between adjacent signal lines, and in the first direction, a height difference exists between the surface of the side, away from the substrate, of the blocking structure and the surface of the side, close to the substrate, of the anode pattern. The first direction is the arrangement direction of the substrate and the first conductive layer.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of display technologies, and more particularly, to a display panel and a display device. Background Art

[0002] In recent years, large-size transparent OLEDs have become a new growth point in scenarios such as subway windows (e.g., station announcements, advertising displays) because they can combine transparent display and dynamic content switching functions. Among them, the top-gate oxide TFT has become the preferred technical solution for large-size OLEDs due to its high conduction current, high aperture ratio, and excellent TFT stability.

[0003] However, in large-size transparent OLED products, due to the RC Delay problem of signal transmission, a wiring technology using low-resistance metal and silicon oxide (SiO2) as a passivation layer is required. Since the film quality of silicon oxide is loose, water vapor is likely to diffuse laterally through the passivation layer, resulting in the formation of a lateral leakage current between signal lines at the passivation layer interface in the bonding area of the display panel after water vapor infiltration, and then leading to abnormal induced voltage and triggering electrical compensation bright lines (Sense bright lines), significantly reducing the panel yield. Therefore, how to improve the compensation yield of the display panel has become an urgent problem to be solved in this field. Summary of the Invention

[0004] The embodiments of the present application aim to provide a display panel and a display device, aiming to solve the problem of how to improve the compensation yield of the display panel.

[0005] In a first aspect of the embodiments of the present application, a display panel is provided, including a display area and a non-display area, the non-display area includes a bonding area, and the display panel includes a substrate, a first conductive layer, a passivation layer, and an anode layer stacked in sequence;

[0006] In the bonding area, the first conductive layer includes a plurality of signal lines arranged at intervals, the anode layer includes a plurality of anode patterns, and the anode patterns are electrically connected to the corresponding signal lines through conductive vias of the passivation layer;

[0007] In a gap area between adjacent signal lines, a blocking structure is provided on a surface of the passivation layer facing away from the substrate, and there is a height difference between a surface of the blocking structure facing away from the substrate and a surface of the anode pattern close to the substrate in a first direction, and the first direction is the arrangement direction of the substrate and the first conductive layer.

[0008] In an optional embodiment, the blocking structure is a groove formed by the surface of the passivation layer away from the substrate recessing towards the substrate;

[0009] In the first direction, the distance from the bottom of the groove to the substrate is less than the distance from the surface of the anode pattern close to the substrate to the substrate.

[0010] In an optional embodiment, the orthographic projection of the groove on the substrate is located inside the gap region between the adjacent signal lines.

[0011] In an optional embodiment, the groove at least partially penetrates the passivation layer.

[0012] In an optional embodiment, the display panel further includes a buffer layer disposed between the substrate and the first conductive layer, and the groove penetrates the passivation layer and the buffer layer.

[0013] In an optional embodiment, the blocking structure is a protrusion protruding from the surface of the passivation layer away from the substrate in a direction away from the substrate, and the distance from the surface of the protrusion away from the substrate to the substrate is greater than the distance from the surface of the anode pattern away from the substrate to the substrate.

[0014] In an optional embodiment, the orthographic projection of the protrusion on the substrate is located inside the gap region between the adjacent signal lines, or the orthographic projection of the protrusion on the substrate coincides with the gap region between the adjacent signal lines.

[0015] In an optional embodiment, the passivation layer further includes a plurality of passivation structures, and the anode pattern forms an electrical connection with the signal line through the conductive vias on the passivation structures, and the orthographic projection of the passivation structures on the substrate at least covers the orthographic projections of the anode pattern and the signal line on the substrate;

[0016] The surface of the passivation structure facing away from the substrate is flush with the surface of the anode pattern close to the substrate, and the blocking structure is formed between adjacent passivation structures.

[0017] In an optional embodiment, the display panel further includes:

[0018] An adhesive layer disposed on the side of the anode layer away from the substrate, and the adhesive layer at least covers the surface of the anode pattern facing away from the substrate and the surface of the blocking structure facing away from the substrate;

[0019] A chip - on - film disposed on the side of the adhesive layer away from the substrate.

[0020] A second aspect of the embodiments of the present application provides a display device, and the display device includes the display panel according to any one of the first aspects of the embodiments of the present application.

[0021] Beneficial effects:

[0022] The present application provides a display panel and a display device. The display panel includes a display area and a non-display area. The non-display area includes a bonding area. The display panel includes a substrate, a first conductive layer, a passivation layer, and an anode layer that are sequentially stacked; in the bonding area, the first conductive layer includes a plurality of signal lines arranged at intervals, the anode layer includes a plurality of anode patterns, and the anode patterns are electrically connected to the corresponding signal lines through conductive vias in the passivation layer; in the gap area between adjacent signal lines, a blocking structure is provided on the surface of the passivation layer facing away from the substrate. In a first direction, there is a height difference between the surface of the blocking structure facing away from the substrate and the surface of the anode pattern close to the substrate. The first direction is the arrangement direction of the substrate and the first conductive layer. By providing a blocking structure located in the passivation layer in the gap area between adjacent signal lines, and there is a height difference between the blocking structure and the anode pattern, water vapor is blocked by the blocking structure when diffusing along the surface of the passivation layer, thereby avoiding lateral leakage between signal lines, and further preventing the induced voltage from being interfered, effectively improving the electrical compensation bright line phenomenon, and significantly improving the panel yield. Description of the drawings

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0024] Figure 1 It is a schematic structural diagram of a blocking structure provided as a groove penetrating the passivation layer in a display panel proposed in an embodiment of the present application;

[0025] Figure 2 It is a schematic structural diagram of a blocking structure provided as a groove partially penetrating the passivation layer in a display panel proposed in an embodiment of the present application;

[0026] Figure 3 It is a schematic structural diagram of a blocking structure provided as a groove penetrating the passivation layer and the buffer layer in a display panel proposed in an embodiment of the present application;

[0027] Figure 4 It is a schematic structural diagram of a blocking structure provided as a protrusion in a display panel proposed in an embodiment of the present application;

[0028] Figure 5 It is a schematic structural diagram of a blocking structure provided as a protrusion in another display panel proposed in an embodiment of the present application.

[0029] Explanation of the accompanying drawings: 11, substrate; 12, buffer layer; 13, first conductive layer; 131, signal line; 14, passivation layer; 141, passivation structure; 142, blocking structure; 1421, groove; 1422, protrusion; 15, anode layer; 151, anode pattern; 16, bonding layer; 17, flip chip film. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0031] In the drawings, the sizes of components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, any implementation of the present disclosure is not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and any implementation of the present disclosure is not limited to the shapes or values shown in the drawings.

[0032] In recent years, large-size transparent OLEDs have become a growing market for applications such as subway windows (for station announcements and advertising) due to their ability to combine transparent displays with dynamic content switching. Top-gate oxide TFTs, with their high on-current, high aperture ratio, and excellent TFT stability, have become the preferred technology for large-size OLEDs.

[0033] In related technologies, large-scale transparent OLED products require a wiring technology that uses low-resistance metal and silicon oxide (SiO2) as a passivation layer due to RC delay issues in signal transmission. Due to the looseness of the silicon oxide film, water vapor easily diffuses laterally through the passivation layer. This causes water vapor to penetrate the bonding area of the display panel, leading to lateral leakage current between the signal lines at the passivation layer interface. This in turn causes abnormal induced voltage and triggers electrical compensation bright lines (sense bright lines), significantly reducing panel yield.

[0034] In view of this, an embodiment of the present application proposes a display panel, which includes a display area and a non-display area arranged around the display area, and the non-display area includes a binding area, which is used to connect the internal circuit of the display panel and the external driving module. Figure 1 FIG. 1 shows a schematic structural diagram of a display panel in which a blocking structure is provided as a groove penetrating a passivation layer according to an embodiment of the present application. Figure 1As shown, the display panel includes: a substrate 11; a first conductive layer 13 disposed on one side of the substrate 11. The first conductive layer 13 includes a plurality of signal lines arranged at intervals. The signal lines include sense signal lines (Sense Line) and data lines (DATA Line). The sense signal lines are configured to monitor pixel voltage / current in real time for brightness uniformity compensation; the data lines are used to transmit display data voltage signals to control the gray scale value of pixels. The signal lines extend from the display area to the bonding area in the non-display area and are arranged at intervals in the bonding area. Among them, adjacent signal lines (such as between adjacent sense signal lines and data lines) need to be isolated from each other to prevent crosstalk.

[0035] Optionally, the first conductive layer 13 is a source-drain electrode layer, and the material of the first conductive layer 13 includes but is not limited to Al, Mo, Cr, Cu, Ti, etc.

[0036] In an embodiment of the present application, the display panel further includes: a passivation layer 14 disposed on the side of the first conductive layer 13 away from the substrate 11. Optionally, the material of the passivation layer 14 may be silicon oxide SiO2; an anode layer 15 disposed on the side of the passivation layer 14 away from the substrate 11. The anode layer 15 includes a plurality of anode patterns 151, and the anode patterns 151 are electrically connected to the corresponding signal lines of the first conductive layer 13 through conductive vias of the passivation layer 14.

[0037] In the embodiment of the present application, the passivation layer 14 is configured to prevent short - circuit and corrosion of the signal lines in the first conductive layer 13. Specifically, in order to block the path of water vapor diffusing from the side surface of the passivation layer 14 away from the substrate 11 to adjacent signal lines, in the gap region between adjacent signal lines, a blocking structure 142 is provided on the side surface of the passivation layer 14 facing away from the substrate 11. In the first direction, there is a height difference between the side surface of the blocking structure 142 facing away from the substrate 11 and the side surface of the anode pattern 151 close to the substrate 11, and the first direction is the arrangement direction of the substrate 11 and the first conductive layer 13. In the embodiment of the present application, by providing the blocking structure 142 located between adjacent signal lines, when water vapor invades the side surface of the passivation layer 14 away from the substrate 11, when the water vapor attempts to diffuse from the anode pattern 151 corresponding to any signal line on the side surface of the passivation layer 14 away from the substrate 11 to the anode pattern 151 corresponding to the adjacent signal line, due to the height difference between the blocking structure 142 and the side surface of the anode pattern 151 close to the substrate 11, the diffusion path of the water vapor is affected by the step difference between the blocking structure 142 and the region of the passivation layer 14 corresponding to the signal line, and cannot continue to invade the anode pattern 151 corresponding to the adjacent signal line. Thus, the leakage current between adjacent signal lines is effectively blocked, and further the induced voltage is not interfered, effectively improving the electrical compensation bright line phenomenon and significantly increasing the panel yield.

[0038] In some alternative embodiments, the passivation layer 14 further includes a plurality of passivation structures 141. The passivation structures 141 are used to protect the signal lines. The passivation structures 141 include the conductive vias, and the anode pattern 151 forms an electrical connection with the signal line through the conductive vias on the passivation structures 141. The orthographic projection of the passivation structures 141 on the substrate 11 at least covers the orthographic projection of the anode pattern 151 and the signal line on the substrate 11. Among them, in order to ensure a height difference between the side surface of the blocking structure 142 facing away from the substrate 11 and the side surface of the anode pattern 151 close to the substrate 11, the side surface of the passivation structure 141 facing away from the substrate 11 is flush with the side surface of the anode pattern 151 close to the substrate 11, and the blocking structure 142 is formed between adjacent passivation structures 141, and there is a height difference between the blocking structure 142 and the side surface of the passivation structure 141 close to the substrate 11.

[0039] In some alternative embodiments, such as Figure 1As shown, the blocking structure 142 is a groove 1421 formed by the surface of the passivation layer 14 away from the substrate 11 recessing towards the substrate 11. In the first direction, the distance from the bottom of the groove 1421 to the substrate 11 is less than the distance from the surface of the anode pattern 151 close to the substrate 11 to the substrate 11.

[0040] In some alternative embodiments, to ensure the effect of the passivation layer 14 in preventing short circuits between the signal lines, the passivation structure 141 covers at least the surface of the signal line away from the substrate 11 and the side surfaces close to adjacent signal lines. Therefore, the orthographic projection of the groove 1421 on the substrate 11 is located inside the gap region between the adjacent signal lines, so that the adjacent signal lines are separated by the passivation structure 141 and the blocking structure 142.

[0041] In some alternative embodiments, the display panel further includes a buffer layer 12 disposed between the substrate 11 and the first conductive layer 13. Figure 2 The schematic structural diagram shows a groove in which the blocking structure in a display panel proposed in an embodiment of the present application is partially penetrating the passivation layer, as Figure 2 shown, the groove 1421 partially penetrates the passivation layer 14. Exemplarily, the depth of the groove 1421 in the first direction is 30%-60% of the thickness of the passivation layer 14 in the first direction. To further enhance the blocking effect of the blocking structure 1421 on the lateral leakage current between adjacent signal lines, as Figure 1 shown, the groove 1421 can also completely penetrate the passivation layer 14, and the bottom of the groove 1421 is a partial surface of the buffer layer 12 away from the substrate 11.

[0042] Optionally, Figure 3 The schematic structural diagram shows a groove in which the blocking structure in a display panel proposed in an embodiment of the present application penetrates the passivation layer and the buffer layer, as Figure 3 shown, to further enhance the intrusion path of moisture between adjacent signal lines by the blocking structure 1421, the groove 1421 penetrates the passivation layer 13 and the buffer layer 12, and the buffer layer 12 is separated into a plurality of island patterns by the groove 1421. The orthographic projection of the island pattern on the substrate 11 coincides with the orthographic projection of the signal line on the substrate 11.

[0043] In some alternative embodiments, Figure 4 The schematic structural diagram shows a protrusion as the blocking structure in a display panel proposed in an embodiment of the present application, as Figure 4As shown, the blocking structure 142 is a protrusion 1422 that protrudes from a side surface of the passivation layer 14 away from the substrate 11 toward a direction away from the substrate 11. In the first direction, the distance between the side surface of the protrusion 1422 away from the substrate 11 and the substrate 11 is greater than the distance between the side surface of the anode pattern 151 close to the substrate 11 and the substrate 11.

[0044] Optionally, in order to enhance the blocking effect of the protrusion 1422, the distance from the side surface of the protrusion 1422 away from the substrate 11 to the substrate 11 is greater than the distance from the side surface of the anode pattern 151 away from the substrate 11 to the substrate 11, that is, in the first direction, the side surface of the protrusion away from the substrate 11 is arranged away from the substrate 11 relative to the anode pattern 151.

[0045] In some optional embodiments, there may be a gap between the protrusion 1422 and the passivation structure 141, and the orthographic projection of the protrusion 1422 on the substrate 11 is located inside the gap region between the adjacent signal lines; in order to enhance the blocking effect of the protrusion 1422 on the water vapor intrusion path between the adjacent signal lines, Figure 5 FIG. 1 shows a schematic diagram of another structure in which a blocking structure in a display panel is provided as a protrusion according to an embodiment of the present application. Figure 5 As shown, the protrusion 1422 is arranged in contact with the adjacent passivation structure 141 , and the orthographic projection of the protrusion 1422 on the substrate 11 coincides with the gap area between the adjacent signal lines.

[0046] Optionally, the width of the protrusion 1422 gradually decreases along the second direction, where the second direction is the arrangement direction of the signal line. Exemplarily, the cross-sectional shape of the protrusion 1422 along the plane perpendicular to the signal line is a trapezoid, and the width of the side surface of the protrusion 1422 away from the back plate 11 is smaller than the width of the plane where the protrusion 1422 is flush with the anode pattern 151.

[0047] In some alternative embodiments, the display panel further includes: an adhesive layer 16 disposed on a side of the anode layer 15 away from the substrate, where the adhesive layer 16 covers at least a surface of the anode pattern 151 away from the substrate 11 and a surface of the barrier structure 152 away from the substrate 11. Optionally, the adhesive layer 16 may be a bonding adhesive; a chip-on-film 17 disposed on a side of the adhesive layer 16 away from the substrate 11. In the embodiments of the present application, when the barrier structure 142 is the groove 1421, the adhesive layer 16 fills the inside of the groove 1421 to prevent moisture from diffusing along a surface of the passivation layer 14 away from the substrate 11 to an area of adjacent signal lines; when the barrier structure 142 is the protrusion 1422, the adhesive layer 16 covers at least the surface of the protrusion 1422 to prevent moisture from diffusing along a surface of the passivation layer 14 away from the substrate 11 to an area of adjacent signal lines.

[0048] In some alternative embodiments, the display panel further includes: an active layer disposed on a side of the buffer layer 12 away from the substrate 11; a gate insulating layer disposed on a side of the active layer away from the substrate 11; a gate layer disposed between the gate insulating layer and the first conductive layer 13; and an interlayer dielectric layer disposed between the first conductive layer 13 and the gate layer.

[0049] The present application provides a display panel and a display device. The display panel includes a display area and a non-display area, and the non-display area includes a bonding area. The display panel includes a substrate, a first conductive layer, a passivation layer, and an anode layer stacked in sequence. In the bonding area, the first conductive layer includes a plurality of signal lines arranged at intervals, and the anode layer includes a plurality of anode patterns. The anode patterns are electrically connected to corresponding signal lines through conductive vias of the passivation layer. In a gap area between adjacent signal lines, a barrier structure is provided on a surface of the passivation layer away from the substrate. In a first direction, there is a height difference between a surface of the barrier structure away from the substrate and a surface of the anode pattern close to the substrate. The first direction is the arrangement direction of the substrate and the first conductive layer. By providing a barrier structure located in the passivation layer in the gap area between adjacent signal lines, and there is a height difference between the barrier structure and the anode pattern, moisture is blocked by the barrier structure when diffusing along the surface of the passivation layer, thereby avoiding lateral leakage between signal lines, and further preventing the induced voltage from being interfered, effectively improving the electrical compensation bright line phenomenon, and significantly increasing the panel yield.

[0050] Based on the same inventive concept, an embodiment of the present application discloses a method for manufacturing a display panel, which is used to manufacture the display panel described in the embodiments of the present application. The manufacturing method includes the following steps: providing a substrate 11. Exemplarily, the substrate 11 includes but is not limited to glass, and the thickness of the substrate 11 is 50 - 1000 um; depositing metal on one side of the substrate 11, patterning through photolithography and wet etching, and stripping the photoresist on the metal surface to form a light-shielding layer; depositing the buffer layer 12 on the side of the light-shielding layer facing away from the substrate 11 by plasma-enhanced chemical vapor deposition (PECVD). Optionally, the buffer layer 12 includes at least one of the following: SiN x , SiO x or SiO x N y . The thickness of the buffer layer 12 is 150 - 500 nm; patterning through photolithography and dry etching, and stripping the photoresist on the surface of the buffer layer 12 to obtain CNT vias and grooves for Vdd and DATA traces.

[0051] In some alternative embodiments, after forming the buffer layer 12, an oxide is deposited on the buffer layer 12 as an active layer. Patterning through photolithography and wet etching, and stripping the photoresist on the metal surface. Optionally, the oxide can be an amorphous oxide such as IGZO, ZnON, ITZO, etc.; subsequently, a gate insulating layer is deposited on the side of the active layer facing away from the substrate 11 by chemical vapor deposition (CVD); a gate layer is deposited on the side of the gate insulating layer facing away from the substrate 11. The material of the gate layer includes but is not limited to Al, Mo, Cr, Cu, Ti, etc., and the thickness of the gate layer is 200 - 1000 nm; defining the gate pattern through photolithography and wet etching processes, and keeping the photoresist without stripping. Continuing to use the photoresist on the gate layer as a mask, dry-etching the pattern of the gate insulating layer.

[0052] After forming the gate layer, any one of the gases NH3, N2, and H2 is used to conduct the exposed active layer to reduce the ohmic contact resistance between the active layer and the first conductive layer 13 formed subsequently; a interlayer dielectric layer is deposited on the side of the gate layer away from the substrate 11 by plasma-enhanced chemical vapor deposition (PECVD), and the interlayer dielectric layer is etched through dry etching to obtain contact vias for realizing the contact between the first conductive layer 13 and the active layer.

[0053] A first conductive layer 13 is deposited on a side of the interlayer dielectric layer away from the substrate 11. The first conductive layer 13 serves as the source-drain electrode layer of the TFT in the display panel. Optionally, the material of the first conductive layer 13 includes, but is not limited to, Al, Mo, Cr, Cu, Ti, etc. The thickness of the first conductive layer 13 is 200 - 1000 nm. The pattern of the first conductive layer 13 is obtained through photolithography and wet etching processes. The pattern includes multiple signal lines. The passivation layer 14 is deposited on a side of the first conductive layer 13 facing away from the substrate 11 by a chemical vapor deposition (CVD) method. Optionally, the material of the passivation layer 14 is SiO2.

[0054] In the display area, a planarization material is deposited on the passivation layer 14. After pre-baking, exposure, and development, the pattern of the cured pixel area is exposed. After post-baking at 230 °C to remove water and organic solvents, a planar layer is obtained. The thickness of the planar layer is 2.0 - 3.5 um. The passivation layer 14 is etched through photolithography and dry etching processes to obtain the conductive vias. The conductive vias are used to connect the first conductive layer 13 of the driving TFT and the anode layer 15 of the OLED. At the same time, the area between adjacent signal lines in the bonding area is etched to form the blocking structure 142.

[0055] An anode layer 15 is deposited on a side of the passivation layer 14 away from the substrate 11. Optionally, the material of the anode layer 15 includes, but is not limited to: Cu / MoNb / ITO, Al / Mo / ITO, etc. The thickness of the anode layer 15 is 2000 - 6000 nm. The anode pattern 151 is obtained through photolithography and wet etching processes for the anode layer 15. In the display area, a pixel defining layer material is deposited on a side of the anode layer 15 facing away from the substrate 11. After pre-baking, exposure, and development, the pattern of the cured pixel area is exposed. After post-baking to remove water and organic solvents, the thickness of the pixel defining layer is 1.8 - 2.0 um. By an evaporation process, each layer of the OLED, the transparent cathode layer, is sequentially formed. Then, a packaging layer is deposited by a CVD process. The Array substrate and the CF cover plate are aligned to fabricate a top-emission OLED display. The CF cover plate is coated with a light-shielding layer BM (black matrix) material. Using a half-tone process, after pre-baking, exposure, and development, the pattern of the cured pixel area color film is exposed. After post-baking to remove water and organic solvents, the thickness of the light-shielding layer is 2.0 - 2.5 um. A blue color film material is coated. After pre-baking, exposure, and development, the pattern of the cured pixel area color film is exposed. After post-baking at 230 degrees to remove water and organic solvents, a color film layer is formed. The thickness of the color film layer is 2.0 - 3.5 um. The patterns of the green / red color films are formed in the same process. There is no RGB color film on the top-emission backplane.

[0056] In some alternative embodiments, within the bonding region, after forming the anode layer 15, an adhesive layer 16 is formed on the side of the anode layer 15 facing away from the substrate 11; the COF film 17 is attached to the side of the adhesive layer 16 facing away from the substrate 11.

[0057] Based on the same inventive concept, an embodiment of the present application discloses a display device, which includes the display panel described in the embodiments of the present application.

[0058] In some alternative embodiments, the display device is a product with an image display function. Optionally, the display device can be used to display static images, such as pictures, photos, etc.; the display device can also be used to display dynamic images, such as videos, game screens, etc.

[0059] In some alternative embodiments, the display device includes, but is not limited to, laptop computers, mobile phones, wireless devices, personal digital assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays, navigators, cockpit controllers and / or displays, displays for camera views, electronic photos, electronic billboards or signs, projectors, packaging, and aesthetic structures, etc.

[0060] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other.

[0061] In the description of this specification, it should be understood that the orientation or positional relationships indicated by terms such as "center", "thickness", "upper", "lower", "front", "rear", "horizontal", "top", "bottom", "inner", "outer", "axial", "radial", "circumferential", etc. are based on the orientation or positional relationships shown in the drawings. These are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present application.

[0062] In the present application, unless otherwise clearly defined and limited, terms such as "mounted", "connected", "coupled", "fixed", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection, an electrical connection, or a communication connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0063] In this application, unless otherwise clearly specified or limited, the first feature being "on" or "under" the second feature may include direct contact between the first and second features, or may include indirect contact between the first and second features through additional features therebetween. Moreover, the first feature being "above", "over" and "on top of" the second feature includes the first feature being directly above and obliquely above the second feature, or merely indicating that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly below and obliquely below the second feature, or merely indicating that the horizontal height of the first feature is lower than that of the second feature.

[0064] The above application provides many different embodiments or examples for implementing different structures of this application. To simplify this application, components and settings of specific examples are described above. Of course, they are merely examples and are not intended to limit this application. In addition, this application may repeat reference numerals and / or reference letters in different examples. This repetition is for the purpose of simplification and clarity, and does not in itself indicate the relationship between the various embodiments and / or settings discussed.

[0065] As used herein, the terms "an embodiment", "embodiment" or "one or more embodiments" mean that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of this application. In addition, please note that the examples of the phrase "in one embodiment" herein do not necessarily all refer to the same embodiment.

[0066] In the specification provided herein, a large number of specific details are set forth. However, it can be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures and technologies are not shown in detail so as not to obscure the understanding of this specification.

[0067] Finally, it should be noted that, in this document, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover a non-exclusive inclusion, such that a process, method, article or terminal device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or terminal device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or terminal device comprising the element.

[0068] The above has provided a detailed introduction to a display panel and a display device provided by the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those of ordinary skill in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A display panel, characterized in that, It includes a display area and a non-display area. The non-display area includes a bonding area. The display panel includes a substrate, a first conductive layer, a passivation layer, and an anode layer that are sequentially stacked. In the bonding area, the first conductive layer includes a plurality of signal lines arranged at intervals, and the anode layer includes a plurality of anode patterns. The anode patterns are electrically connected to the corresponding signal lines through conductive vias in the passivation layer. In the gap area between adjacent signal lines, a blocking structure is provided on the surface of the passivation layer facing away from the substrate. In a first direction, there is a height difference between the surface of the blocking structure facing away from the substrate and the surface of the anode pattern close to the substrate. The first direction is the arrangement direction of the substrate and the first conductive layer.

2. The display panel according to claim 1, wherein The blocking structure is a groove formed by the surface of the passivation layer away from the substrate recessing towards the substrate. In the first direction, the distance from the bottom of the groove to the substrate is less than the distance from the surface of the anode pattern close to the substrate to the substrate.

3. The display panel according to claim 1, wherein The orthographic projection of the groove on the substrate is located inside the gap area between adjacent signal lines.

4. The display panel according to claim 2, wherein, The groove at least partially penetrates the passivation layer.

5. The display panel according to claim 4, wherein The display panel further includes a buffer layer. The buffer layer is provided between the substrate and the first conductive layer, and the groove penetrates the passivation layer and the buffer layer.

6. The display panel according to claim 1, characterized in that, The blocking structure is a protrusion formed by the surface of the passivation layer away from the substrate protruding towards the direction away from the substrate. In the first direction, the distance from the surface of the protrusion away from the substrate to the substrate is greater than the distance from the surface of the anode pattern away from the substrate to the substrate.

7. The display panel according to claim 1, wherein The orthographic projection of the protrusion on the substrate is located inside the gap area between adjacent signal lines, or the orthographic projection of the protrusion on the substrate coincides with the gap area between adjacent signal lines.

8. The display panel according to claim 1, wherein The passivation layer further includes a plurality of passivation structures. The anode patterns are electrically connected to the signal lines through the conductive vias on the passivation structures. The orthographic projection of the passivation structures on the substrate at least covers the orthographic projections of the anode patterns and the signal lines on the substrate. The surface of the passivation structure facing away from the substrate is flush with the surface of the anode pattern close to the substrate, and the blocking structure is formed between adjacent passivation structures.

9. The display panel according to claim 1, wherein The display panel further includes: An adhesive layer. The adhesive layer is provided on the side of the anode layer facing away from the substrate, and the adhesive layer at least covers the surface of the anode pattern facing away from the substrate and the surface of the blocking structure facing away from the substrate. A chip-on-film. The chip-on-film is provided on the side of the adhesive layer away from the substrate.

10. A display device, characterized in that, The display device includes the display panel according to any one of claims 1 to 9.

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