Display device

Abstract

There is provided a display device including a display panel and an input sensing panel including a package substrate and a sensing circuit layer, where the sensing circuit layer includes first sensing electrodes, second sensing electrodes, first traces, second traces, and third traces respectively connected to first ends of the first sensing electrodes, each of the third traces includes a first conductive pattern, a second conductive pattern, and a bridge pattern extending from the sensing pattern and connected to the first conductive pattern and the second conductive pattern.

Description

[0001] This application claims the priority and benefit of Korean Patent Application No. 10-2024-0013317, filed with the Korean Intellectual Property Office on January 29, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The present disclosure relates herein to a display device including an input sensing panel having reduced dead space and reduced resistance. Background Art

[0003] A display device may include a display panel for displaying an image and an input sensing panel for sensing an external input. The input sensing panel may include sensing electrodes, traces, and sensing pads (also referred to as "pads"). As the number of sensing electrodes is increased to improve sensing sensitivity, the number of traces may also increase. As the number of traces increases, space is required for the peripheral area in which the traces will be located. Summary of the Invention

[0004] The present disclosure provides traces in a multilayer structure in an area where traces are densely located, thereby reducing the dead space of the input sensing panel and reducing the resistance of the traces.

[0005] The present disclosure provides a light-emitting element having modified surface characteristics by introducing a ligand that improves dispersibility to the surface of the host of the light-emitting element.

[0006] One or more embodiments of the present disclosure provide a display device including: a display panel including an active area and a peripheral area adjacent to the active area, with pixels located in the active area; and an input sensing panel including a sensing circuit layer and a package substrate above the display panel, wherein the sensing circuit layer includes: a first sensing insulating layer, a second sensing insulating layer, and a third sensing insulating layer sequentially stacked above the display panel; a first sensing electrode extending along a first direction and arranged along a second direction intersecting the first direction; a second sensing electrode including sensing patterns and connection patterns, the sensing patterns being arranged along the second direction, and the connection patterns extending along the second direction and arranged along the first direction respectively between adjacent sensing patterns among the sensing patterns; first traces respectively connected to first ends of the second sensing electrodes; second traces respectively connected to second ends of the second sensing electrodes; and third traces respectively connected to first ends of the first sensing electrodes and including a first conductive pattern, a second conductive pattern, and a bridging pattern, the second conductive pattern being stacked with the first conductive pattern and having a width smaller than the width of the first conductive pattern in the first direction, and the bridging pattern extending from one of the sensing patterns among the sensing patterns and connecting to the first conductive pattern and the second conductive pattern.

[0007] The first conductive pattern and the second conductive pattern may include molybdenum-based metals, wherein the bridging pattern includes a transparent conductive oxide.

[0008] The first conductive pattern may be above the encapsulation substrate and covered by a first sensing insulating layer, wherein the second conductive pattern is above the first sensing insulating layer and covered by a second sensing insulating layer, and wherein the bridging pattern is above the second sensing insulating layer and covered by a third sensing insulating layer.

[0009] In a plan view, a part of the upper surface of the first conductive pattern may be exposed from the second conductive pattern.

[0010] A first contact hole overlapping with the part of the first conductive pattern may be defined in the first sensing insulating layer and the second sensing insulating layer, wherein a second contact hole overlapping with the second conductive pattern is defined in the second sensing insulating layer, and wherein the bridging pattern is connected to the part of the first conductive pattern through the first contact hole and connected to the second conductive pattern through the second contact hole.

[0011] A contact hole overlapping with the part of the first conductive pattern and exposing a side surface and a part of the upper surface of the second conductive pattern may be defined in the first sensing insulating layer and the second sensing insulating layer, wherein the bridging pattern is connected to the part of the first conductive pattern and the side surface and the part of the second conductive pattern through the contact hole.

[0012] The connection pattern may be above the encapsulation substrate and may be covered by the first sensing insulating layer, wherein the sensing pattern and the first sensing electrode are above the second sensing insulating layer and covered by the third sensing insulating layer, and wherein the sensing pattern is connected to the connection pattern through a connection contact hole defined in the first sensing insulating layer and the second sensing insulating layer.

[0013] The bridging pattern may include an integral pattern extending from the sensing pattern.

[0014] The display device may further include: a bonding pattern adjacent to a first end of a first trace connected to the second sensing electrode, adjacent to a second end of a second trace connected to the second sensing electrode, and adjacent to a first end of a third trace connected to the first sensing electrode.

[0015] The bonding pattern may be above the encapsulation substrate and covered by the first sensing insulating layer, wherein the bridging pattern is connected to one of the bonding patterns in the bonding pattern through a first bonding contact hole defined in the first sensing insulating layer and the second sensing insulating layer.

[0016] The bonding pattern may be above the first sensing insulating layer and may be covered by the second sensing insulating layer, wherein the bridging pattern is connected to one of the bonding patterns in the bonding pattern through a second bonding contact hole defined in the second sensing insulating layer.

[0017] The portion of the third trace adjacent to the second end of the second sensing electrode may include a lower pattern above the encapsulation substrate, wherein the remaining portion of the third trace adjacent to the second end of the second sensing electrode includes an upper pattern that does not overlap with the lower pattern, and wherein, in a plan view, the end portions of the lower pattern are aligned with the end portions of the upper pattern respectively.

[0018] One of the lower patterns in the lower pattern may be integral with the first conductive pattern, wherein one of the upper patterns in the upper pattern is integral with the second conductive pattern.

[0019] The peripheral region may include an upper region adjacent to the upper end of the active region, a left region adjacent to the left side of the active region, a lower region adjacent to the lower end of the active region, and a right region adjacent to the right side of the active region, wherein the input sensing panel further includes sensing pads in the lower region.

[0020] In a plan view, the third trace may extend along the right region and the lower region and may be connected to the sensing pads.

[0021] In a plan view, the first trace may be connected to the first end of the second sensing electrode, may extend along the upper region, the left region and the lower region, and may be connected to the sensing pads, wherein the second trace extends along the lower region and is connected to the sensing pads.

[0022] The first trace may include a single layer above the encapsulation substrate.

[0023] The first sensing electrode and the second sensing electrode at the corners of the active region may be rounded.

[0024] The first sensing insulating layer, the second sensing insulating layer, and the third sensing insulating layer may include inorganic materials.

[0025] The encapsulation substrate may include glass, wherein the display device further includes a bonding member that overlaps with the peripheral region and is configured to bond the display panel and the encapsulation substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings are included to provide a further understanding of the present disclosure, and the drawings are incorporated into and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, are used to explain aspects of the present disclosure. In the drawings: Figure 1 is an assembled perspective view of a display device according to one or more embodiments of the present disclosure; Figure 2 is an exploded perspective view of a display device according to one or more embodiments of the present disclosure; Figure 3A is a cross-sectional view of a display device according to one or more embodiments of the present disclosure; Figure 3B is a cross-sectional view of a display device according to one or more embodiments of the present disclosure; Figure 4A is a plan view of a display panel according to one or more embodiments of the present disclosure; Figure 4B is an equivalent circuit diagram of a pixel according to one or more embodiments of the present disclosure; Figure 5 is a plan view of an input sensing panel according to one or more embodiments of the present disclosure; Figure 6 shows Figure 5 an enlarged plan view of the area AA'; Figure 7 is a cross-sectional view taken along the line I-I'; Figure 6 of Figure 8 is a plan view of an input sensing panel according to one or more embodiments of the present disclosure; Figure 9 is a cross-sectional view taken along the line II-II'; Figure 5 of Figure 10 is a cross-sectional view of a trace according to one or more embodiments of the present disclosure; Figure 11 is a cross-sectional view taken along the line III-III'; Figure 5 of Figure 12 is a cross-sectional view of a trace according to one or more embodiments of the present disclosure; Figure 13 is a cross-sectional view taken along the line IV-IV'; and Figure 5 of Figure 14 is a cross-sectional view of a trace according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0027] Aspects of some embodiments of the present disclosure and their implementation methods can be more easily understood by referring to the detailed description of the embodiments and the accompanying drawings. The described embodiments are provided as examples so that the disclosure will be thorough and complete, and will fully convey the aspects of the disclosure to those skilled in the art. Therefore, processes, elements, and techniques that are redundant, not relevant or unrelated to the description of the embodiments, or not necessary for those of ordinary skill in the art to fully understand the aspects of the disclosure may be omitted. Throughout the drawings and the written description, unless otherwise stated, the same reference numerals, characters, or combinations thereof indicate the same elements, and thus, their repeated description may be omitted.

[0028] The described embodiments may have various variations and may be implemented in different forms and should not be construed as limited to the embodiments shown herein. When describing the embodiments, the use of "may", "might", or "may not" corresponds to one or more embodiments of the present disclosure.

[0029] Those of ordinary skill in the art will understand that, considering the integrity of the present disclosure, the present disclosure covers all variations, equivalents, and replacements within the concept and technical scope of the present disclosure. Each of the features of the embodiments of the present disclosure can be partially or fully combined with each other, and various interlocks and operations are technically feasible, and unless otherwise stated or implied, each embodiment can be implemented independently of each other or can be implemented in association with each other.

[0030] In the drawings, for clarity and / or for the purpose of description, the relative dimensions of elements, layers, and regions may be exaggerated. In other words, since the dimensions and thicknesses of the elements are arbitrarily shown in the drawings for ease of description, the disclosure is not limited thereto. Additionally, the use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless stated, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, dimension, ratio, commonality between the elements shown, and / or any other characteristic, attribute, property, etc.

[0031] Various embodiments are described herein with reference to cross-sectional views that are schematic illustrations of embodiments and / or intermediate structures. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Additionally, for the purpose of describing embodiments in accordance with the concepts of the present disclosure, the specific structural or functional descriptions disclosed herein are merely illustrative. Therefore, the embodiments disclosed herein should not be construed as limited to the shapes shown for the elements, layers, or regions, but will include shape deviations caused by, for example, manufacturing.

[0032] For example, an implantation region shown as rectangular will typically have rounded or curved features and / or an implantation concentration gradient at its edges rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation can cause some implantation in the region between the buried region and the surface through which the implantation is performed.

[0033] For ease of explanation, spatial relative terms such as "below", "beneath", "lower", "bottom", "under", "above", "upper", "on", "higher", "top", "side" (e.g., as in "sidewall") may be used herein to describe the relationship of one element or feature to another element(s) or feature(s) as shown in the figures. It will be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below", "beneath", or "under" other elements or features will then be oriented "above" the other elements or features. Thus, the example terms "below" and "under" can encompass both an upper and a lower orientation. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Similarly, when a first portion is described as being disposed "on" a second portion, this indicates that the first portion is disposed on the upper or lower side of the second portion, and is not limited to the upper side based on the direction of gravity.

[0034] In addition, the phrase "in a plan view" means when the object portion is viewed from above, and the phrase "in a schematic cross-sectional view" means when a schematic cross-section taken by vertically cutting the object portion is viewed from the side. The terms "superposed" or "overlapped" mean that a first object can be above or below or at the side of a second object, and vice versa. In addition, the term "superposed" can include stacked, facing or oriented, extending over, covering or partially covering or any other suitable term as will be appreciated and understood by those of ordinary skill in the art. The expression "not superposed" can include meanings such as "separate from", "deviated from", or "offset from" and any other suitable equivalents as will be appreciated and understood by those of ordinary skill in the art. The terms "facing" and "oriented" can mean that a first object can be directly or indirectly opposite a second object. In a case where a third object is disposed between a first object and a second object, although the first object and the second object still face each other, the first object and the second object can be understood as being indirectly opposite each other.

[0035] It will be understood that when an element, layer, region or component is referred to as being "formed on", "on", "connected to" or "(operatively or communicatively) coupled to" another element, layer, region or component, it can be directly formed on, directly on, directly connected to or directly coupled to the other element, layer, region or component, or indirectly formed on, indirectly on, indirectly connected to or indirectly coupled to the other element, layer, region or component, such that there can be one or more intervening elements, intervening layers, intervening regions or intervening components. Further, this can be collectively referred to as direct or indirect coupling or direct or indirect connection and integral or non-integral coupling or integral or non-integral connection. For example, when a layer, region or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region or component, it can be directly electrically connected or directly electrically coupled to the other layer, region and / or component, or there can be one or more intervening layers, intervening regions or intervening components. One or more intervening components can include switches, resistors and / or capacitors, etc. When describing embodiments, unless explicitly described as a direct connection, the expression of connection indicates an electrical connection, and "direct connection / direct coupling" or "directly on" means that one component is directly connected or directly coupled to another component or directly on another component without an intermediate component.

[0036] In addition, in this specification, when a part of a layer, film, region or plate, etc. is formed on another part, the forming direction is not limited to the upward direction, but includes the case where the part is formed on a side surface or in a downward direction. Conversely, when a part of a layer, film, region or plate, etc. is formed "under" another part, this includes not only the case where the part is "directly under" the other part, but also the case where there is another part between the part and the other part. At the same time, other expressions describing the relationship between components, such as "between", "immediately between" or "adjacent to" and "directly adjacent to", can be similarly interpreted. It will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there can also be one or more intervening elements or intervening layers.

[0037] For the purposes of this disclosure, when expressions such as "at least one of...", "any one of...", or "one or more of..." follow a list of elements, they modify the entire list of elements and not individual elements within the list. For example, "at least one of X, Y, and Z" and "at least one of the group consisting of X, Y, and Z" can be interpreted to mean only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as XYZ, XYY, YZ, and ZZ for example), or any variation thereof. Similarly, the expression "at least one of A and B" can include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any combination and all combinations of one or more of the associated listed items. For example, the expression "A and / or B" can include A, B, or A and B. Similarly, when expressions such as "at least one of...", "a plurality of...", "one of...", and other prepositional phrases precede / follow a list of elements, they modify the entire list of elements and not individual elements within the list. When stating "C to D", unless otherwise specified, it means C or more and D or less.

[0038] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms do not correspond to a particular order, position, or priority and are only used to distinguish one element, member, component, region, zone, layer, section, or part from another element, member, component, region, zone, layer, section, or part. Thus, without departing from the spirit and scope of this disclosure, a first element, first component, first region, first layer, or first section described below may be referred to as a second element, second component, second region, second layer, or second section. Describing an element as a "first" element does not require or imply the existence of a second element or other elements. The terms "first", "second", etc. may also be used herein to distinguish different categories or sets of elements. For the sake of brevity, the terms "first", "second", etc. may respectively represent "first category (or first set)", "second category (or second set)", etc.

[0039] In an example, the DR1 axis, DR2 axis, and / or DR3 axis are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the DR1 axis, DR2 axis, and DR3 axis can be substantially perpendicular to each other, or can represent different directions that are not perpendicular to each other. This also applies to the first direction, second direction, and / or third direction.

[0040] The terms used herein are for the purpose of describing embodiments only and are not intended to limit the present disclosure. As used herein, unless the context clearly dictates otherwise, the singular forms "a", "an" and "the" are also intended to include the plural forms, and the plural forms are also intended to include the singular form. It will also be understood that when the terms "comprises", "comprising", "includes" and "including" are used in this specification, they specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0041] As used herein, the terms "substantially", "about", "approximately" and similar terms are used as approximate terms and not as terms of degree, and are intended to account for the inherent deviations of measured or calculated values that would be recognized by a person of ordinary skill in the art. For example, "substantially" may include a range of + / - 5% of the corresponding value. As used herein, "about" or "approximately" includes the stated value and represents an acceptable deviation from the particular value as determined by a person of ordinary skill in the art in view of the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations, or within + / - 30%, + / - 20%, + / - 10%, + / - 5% of the stated value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure".

[0042] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in a general dictionary, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0043] Figure 1 is an assembled perspective view of a display device according to one or more embodiments of the present disclosure. Figure 2 is an exploded perspective view of a display device according to one or more embodiments of the present disclosure.

[0044] Refer to Figure 1 and Figure 2, the display device EA can be activated in response to an electrical signal. The display device EA can include various embodiments. For example, the display device EA can be used in large electronic devices (such as televisions, monitors, or outdoor billboards) as well as small or medium-sized electronic devices (such as personal computers, laptop computers, personal digital assistants, automotive navigation units, gaming consoles, portable electronic devices, and cameras). However, these are presented only as examples, and thus, without departing from the scope of the present disclosure, the display device EA can also be used in other electronic devices. A smart phone is shown as an example of the display device EA.

[0045] The display device EA can display an image IM on a display surface FS in a third direction DR3, and the display surface FS is substantially parallel to each of a first direction DR1 and a second direction DR2. The image IM can include a still image and / or a moving image. Figure 1 A clock window and icons are shown as an example of the image IM. The display surface FS on which the image IM is displayed can correspond to the front surface of the display device EA and can correspond to the front surface of the window panel WP.

[0046] The front surface (or upper surface) and the rear surface (or lower surface) of each member are defined based on the direction along which the image IM is displayed. The front surface and the rear surface can be opposite to each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface can be substantially parallel to the third direction DR3. Meanwhile, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 can have relative concepts and can thus be changed to other directions. Hereinafter, the first direction, the second direction, and the third direction are the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3, respectively, and are represented by the same reference numerals or symbols. As used herein, the phrase "in a plan view" can mean viewing in the third direction DR3.

[0047] The display device EA can include a window panel WP, an anti-reflection panel RPP, a display module DM, and a housing HU. The window panel WP and the housing HU are coupled to each other to form the exterior of the display device EA.

[0048] The window panel WP can include an optically transparent insulating material. For example, the window panel WP can include glass or plastic. The window panel WP can have a multilayer structure or a single-layer structure. For example, the window panel WP can include a plurality of plastic films joined by an adhesive or a glass substrate and a plastic film joined by an adhesive.

[0049] As described above, the display surface FS of the window panel WP defines the front surface of the display device EA. The transmissive region TA can be an optically transparent region. For example, the transmissive region TA can be a region having a visible light transmittance of about 90% or more.

[0050] The border zone BZA can be a zone having a relatively low light transmittance as compared with the transmissive zone TA. The border zone BZA defines the shape of the transmissive zone TA. The border zone BZA can be adjacent to the transmissive zone TA and surround the transmissive zone TA.

[0051] The border zone BZA can have a certain color (e.g., a predetermined color). The border zone BZA can cover the peripheral area NAA of the display module DM, thereby reducing or preventing the visibility of components located in the peripheral area NAA. At the same time, this is shown by way of example, and in the window panel WP according to one or more embodiments of the present disclosure, the border zone BZA can be omitted.

[0052] The anti-reflection panel RPP can be positioned under the window panel WP. The anti-reflection panel RPP reduces the reflectance for external light incident from above the window panel WP. In one or more embodiments of the present disclosure, the anti-reflection panel RPP can be omitted and can be a component located in the display module DM.

[0053] The display module DM can display an image IM and can sense an external input. The display module DM includes a front surface IS having an active area AA and a peripheral area NAA. The active area AA can be an area activated in response to an electrical signal.

[0054] The active area AA can be an area in which pixels PX (see Figure 4A ) are located and the image IM is displayed, and is an area in which an external input is sensed at the same time. The transmissive zone TA at least overlaps with the active area AA. For example, the transmissive zone TA overlaps with the entire surface or at least a part of the active area AA. Thus, a user can view the image IM or provide an external input through the transmissive zone TA. However, this is shown by way of example, and in the active area AA, the area where the image IM is displayed and the area where an external input is sensed can be separated from each other, and one or more embodiments of the present disclosure are not limited thereto.

[0055] The peripheral area NAA can be an area covered by the border zone BZA. The peripheral area NAA is adjacent to the active area AA. The peripheral area NAA can (e.g., in a plan view) surround the active area AA. A driving circuit or driving lines for driving the active area AA can be located in the peripheral area NAA.

[0056] The display module DM includes a display panel DP, an input sensing panel ISL, and a driving circuit DC.

[0057] The display panel DP can be a component that substantially generates the image IM. A user views the image IM generated by the display panel DP from the outside through the transmissive zone TA.

[0058] The input sensing panel ISL senses an external input applied from the outside. As described above, the input sensing panel ISL can sense an external input provided to the window panel WP.

[0059] The driving circuit DC is electrically connected to the display panel DP and the input sensing panel ISL. The driving circuit DC includes a main circuit board MB, a first circuit board CF1, and a second circuit board CF2.

[0060] The first circuit board CF1 is electrically connected to the display panel DP. The first circuit board CF1 can connect the display panel DP and the main circuit board MB. The first circuit board CF1 is shown as a flexible circuit film. However, this is shown as an example, and the first circuit board CF1 may not be connected to the main circuit board MB, and the first circuit board CF1 may be a rigid board.

[0061] The first circuit board CF1 can be connected to a display pad PDD (see Figure 4A ) located in the peripheral area NAA of the display panel DP. The first circuit board CF1 provides an electrical signal for driving the display panel DP to the display panel DP. The electrical signal can be generated from the first circuit board CF1 or from the main circuit board MB.

[0062] The second circuit board CF2 is electrically connected to the input sensing panel ISL. The second circuit board CF2 can connect the input sensing panel ISL and the main circuit board MB. The second circuit board CF2 is shown as a flexible circuit film. However, this is shown as an example, and the second circuit board CF2 may not be connected to the main circuit board MB, and the second circuit board CF2 may be a rigid board.

[0063] The second circuit board CF2 can be connected to a sensing pad PDT (see Figure 5 ) located in the peripheral area NAA of the input sensing panel ISL. The second circuit board CF2 provides an electrical signal for driving the input sensing panel ISL to the input sensing panel ISL. The electrical signal can be generated from the second circuit board CF2 or from the main circuit board MB.

[0064] The main circuit board MB may include various driving circuits for driving the display module DM or connectors for supplying power, etc. Each of the first circuit board CF1 and the second circuit board CF2 can be connected to the main circuit board MB. According to the present disclosure, the display module DM can be easily controlled by one main circuit board MB. However, this is shown as an example, and in the display module DM according to one or more embodiments of the present disclosure, the display panel DP and the input sensing panel ISL may be connected to different main circuit boards, and either of the first circuit board CF1 and the second circuit board CF2 may not be connected to the main circuit board MB, but one or more embodiments of the present disclosure are not limited thereto.

[0065] The housing HU is coupled to the window panel WP. The housing HU is coupled to the window panel WP to provide an internal space (e.g., a predetermined internal space). The display module DM may be accommodated in the internal space.

[0066] The housing HU may include a material having relatively high rigidity. For example, the housing HU may include a plurality of frames and / or plates, the plurality of frames and / or plates including glass, plastic, or metal or being configured as a combination thereof. The housing HU may stably protect the components of the display device EA accommodated in the internal space from external impacts.

[0067] Figure 3A is a cross-sectional view of a display device according to one or more embodiments of the present disclosure. Figure 3B is a cross-sectional view of a display device according to one or more embodiments of the present disclosure.

[0068] Referring to Figure 3A , the display module DM may include a display panel DP, an input sensing panel ISL, and a coupling member SLM.

[0069] The display panel DP according to one or more embodiments of the present disclosure may be an emissive display panel and is not particularly limited. For example, the display panel DP may be an organic light-emitting display panel or a quantum dot light-emitting display panel.

[0070] The display panel DP may include a first substrate BS1, a display circuit layer ML-D, and an image display layer EML. The input sensing panel ISL may include a second substrate BS2 (encapsulation substrate) and a sensing circuit layer ML-T.

[0071] Each of the first substrate BS1 and the second substrate BS2 may be a stacked structure including a silicon substrate, a plastic substrate, a glass substrate, an insulating film, or a plurality of insulating layers.

[0072] The display circuit layer ML-D may be positioned on the first substrate BS1. The display circuit layer ML-D may include a plurality of insulating layers, a plurality of conductive layers, and a semiconductor layer. The plurality of conductive layers of the display circuit layer ML-D may constitute signal lines or control circuits of pixels.

[0073] The image display layer EML may be positioned on the display circuit layer ML-D. The image display layer EML may be a layer that generates light or controls light transmittance. For example, the image display layer EML of an organic light-emitting display panel may include an organic light-emitting material. The image display layer EML of a quantum dot light-emitting display panel may include at least one of a quantum dot and a quantum rod. The image display layer EML of a liquid crystal display panel may include a liquid crystal layer.

[0074] The second substrate BS2 may be positioned on the image display layer EML. A space (e.g., a predetermined space) may be defined between the second substrate BS2 and the image display layer EML. The space may be filled with air or an inert gas. Additionally, in one or more embodiments of the present disclosure, the space may also be filled with fillers such as silicone polymers, epoxy resins, or acrylic resins.

[0075] The sensing circuit layer ML-T may be positioned on the second substrate BS2. The sensing circuit layer ML-T may include a plurality of insulating layers and a plurality of conductive layers. The plurality of conductive layers may constitute sensing electrodes for sensing an external input, sensing lines connected to the sensing electrodes, and sensing pads connected to the sensing lines.

[0076] The bonding member SLM may be positioned between the first substrate BS1 and the second substrate BS2. The bonding member SLM may bond the first substrate BS1 and the second substrate BS2 to each other. The bonding member SLM may include an organic material (such as a photocurable resin or a photoplastic resin) or an inorganic material (such as a frit seal), and is not particularly limited.

[0077] Figure 3B is a cross-sectional view of a display device according to one or more embodiments of the present disclosure.

[0078] Referring to Figure 3B , the display module DM-1 may include a display panel DP-1 and an input sensing panel ISL-1. The input sensing panel ISL-1 may also be referred to as an input sensing layer.

[0079] The display panel DP-1 may include a first substrate BS1, a display circuit layer ML-D, an image display layer EML, and a thin film encapsulation layer ECL. The input sensing panel ISL-1 may include a substrate layer ECL and a sensing circuit layer ML-T. The thin film encapsulation layer ECL and the substrate layer ECL may be the same component.

[0080] According to one or more embodiments of the present disclosure, the display panel DP-1 and the input sensing panel ISL-1 may be formed by a continuous process. That is, the sensing circuit layer ML-T may be directly formed on the thin film encapsulation layer ECL without an additional adhesive layer.

[0081] Figure 4A is a plan view of a display panel according to one or more embodiments of the present disclosure. Figure 4B is an equivalent circuit diagram of a pixel according to one or more embodiments of the present disclosure.

[0082] Referring to Figure 4A , the display panel DP may include a plurality of pixels PX, a plurality of signal lines GL, DL, PL, and ECL, and a plurality of display pads PDD.

[0083] The active area AA of the display panel DP may be an area where an image is displayed, and the peripheral area NAA may be an area where a driving circuit or driving lines are located, etc. Figure 4A The active area AA and the peripheral area NAA of the display panel DP are shown. A plurality of pixels PX may be located in the active area AA.

[0084] A plurality of signal lines GL, DL, PL, and ECL are connected to the pixel PX and transmit an electrical signal to the pixel PX. Among the signal lines included in the display panel DP, the scan line GL, the data line DL, the power line PL, and the emission control line ECL are shown. However, this is shown as an example, and the signal lines GL, DL, PL, and ECL may further include an initialization voltage line and are not particularly limited.

[0085] Figure 4B An enlarged signal circuit diagram of one pixel PX among the plurality of pixels PX is shown. Figure 4B The pixel PX connected to the i-th scan line GLi and the i-th emission control line ECLi is shown.

[0086] The pixel PX may include a light-emitting element EE and a pixel circuit CC. The pixel circuit CC may include a plurality of transistors TR1 to TR7 and a capacitor CP. The plurality of transistors TR1 to TR7 may be formed by a low-temperature polysilicon (LTPS) process or a low-temperature polycrystalline oxide (LTPO) process.

[0087] The pixel circuit CC controls the amount of current flowing through the light-emitting element EE according to a data signal. The light-emitting element EE may emit light having a luminance (e.g., a predetermined luminance) according to the amount of current provided from the pixel circuit CC. To this end, the level of the first power ELVDD may be set to be higher than the level of the second power ELVSS. The light-emitting element EE may include an organic light-emitting element or a quantum dot light-emitting element.

[0088] Each of the plurality of transistors TR1 to TR7 may include an input electrode (or a source electrode, a first electrode), an output electrode (or a drain electrode, a second electrode), and a control electrode (or a gate electrode). In this specification, for convenience, either the input electrode or the output electrode may be referred to as the first electrode, and the other may be referred to as the second electrode.

[0089] The first electrode of the first transistor TR1 is connected to the first power ELVDD via the fifth transistor TR5, and the second electrode of the first transistor TR1 is connected to the anode electrode of the light-emitting element EE via the sixth transistor TR6. In this specification, the first transistor TR1 may be referred to as a driving transistor.

[0090] The first transistor TR1 controls the amount of current flowing through the light-emitting element EE according to the voltage applied to the control electrode of the first transistor TR1.

[0091] The second transistor TR2 is connected between the data line DL and the first electrode of the first transistor TR1. In addition, the control electrode of the second transistor TR2 is connected to the i-th scan line GLi. The second transistor TR2 is turned on when the i-th scan signal is supplied to the i-th scan line GLi, and electrically connects the data line DL and the first electrode of the first transistor TR1.

[0092] The third transistor TR3 is connected between the second electrode and the control electrode of the first transistor TR1. The control electrode of the third transistor TR3 is connected to the i-th scan line GLi. The third transistor TR3 is turned on when the i-th scan signal is supplied to the i-th scan line GLi, and electrically connects the second electrode and the control electrode of the first transistor TR1. Therefore, when the third transistor TR3 is turned on, the first transistor TR1 is diode-connected.

[0093] In one or more embodiments, the fourth transistor TR4 is connected between the node ND and the initialization power generator. In addition, the control electrode of the fourth transistor TR4 is connected to the (i - 1)-th scan line GLi-1. The fourth transistor TR4 is turned on when the (i - 1)-th scan signal is supplied to the (i - 1)-th scan line GLi-1, and supplies the initialization voltage Vint to the node ND.

[0094] The fifth transistor TR5 is connected between the power line PL and the first electrode of the first transistor TR1. The control electrode of the fifth transistor TR5 is connected to the i-th emission control line ECLi.

[0095] The sixth transistor TR6 is connected between the second electrode of the first transistor TR1 and the anode electrode of the light-emitting element EE. In addition, the control electrode of the sixth transistor TR6 is connected to the i-th emission control line ECLi.

[0096] In one or more embodiments, the seventh transistor TR7 is connected between the initialization power generator and the anode electrode of the light-emitting element EE. In addition, the control electrode of the seventh transistor TR7 is connected to the (i + 1)-th scan line GLi+1. Such a seventh transistor TR7 is turned on when the (i + 1)-th scan signal is supplied to the (i + 1)-th scan line GLi+1, and supplies the initialization voltage Vint to the anode electrode of the light-emitting element EE.

[0097] The seventh transistor TR7 can improve the black expression ability of the pixel PX. For example, in one or more embodiments, when the seventh transistor TR7 is turned on, the parasitic capacitor of the light-emitting element EE discharges. Then, when achieving black luminance, the light-emitting element EE does not emit light due to the leakage current from the first transistor TR1, thereby improving the black expression ability.

[0098] In addition, Figure 4B It is shown that the control electrode of the seventh transistor TR7 is connected to the (i + 1)-th scan line GLi+1, but one or more embodiments of the present disclosure are not limited thereto. In one or more other embodiments of the present disclosure, the control electrode of the seventh transistor TR7 may be connected to the i-th scan line GLi or the (i - 1)-th scan line GLi-1.

[0099] The capacitor CP is positioned between the power line PL and the node ND. The capacitor CP stores a voltage according to the data signal. According to the voltage stored in the capacitor CP, the amount of current flowing through the first transistor TR1 when the fifth transistor TR5 and the sixth transistor TR6 are turned on can be determined.

[0100] In the present disclosure, the equivalent circuit of the pixel PX is not limited to Figure 4B the equivalent circuit shown in. In one or more other embodiments of the present disclosure, the pixel PX may be implemented in various forms so that the light-emitting element EE emits light. Figure 4B The illustration of is based on PMOS, but one or more embodiments of the present disclosure are not limited thereto. In one or more other embodiments of the present disclosure, the pixel circuit CC may be configured as NMOS. In yet one or more other embodiments of the present disclosure, the pixel circuit CC may be configured as a combination of NMOS and PMOS.

[0101] Returning to Figure 4A , the power pattern VDD is positioned in the peripheral area NAA. The power pattern VDD is connected to a plurality of power lines PL. Therefore, since the display panel DP includes the power pattern VDD, the display panel DP can provide the same first power signal to multiple pixels PX.

[0102] The display pad PDD may include a first pad D1 and a second pad D2. The first pad D1 may be provided as a plurality of first pads D1 respectively connected to the data lines DL. The second pad D2 may be connected to the power pattern VDD and electrically connected to the power line PL. The display panel DP can provide an electrical signal provided from the outside to the pixel PX through the display pad PDD. Meanwhile, in addition to the first pad D1 and the second pad D2, the display pad PDD may further include pads for receiving other electrical signals and is not particularly limited.

[0103] Figure 5is a plan view of an input sensing panel according to one or more embodiments of the present disclosure. Figure 6 shows Figure 5 an enlarged plan view of region AA' of. Figure 7 is a cross-sectional view taken along line I-I' of. Figure 6 Hereinafter, the description will be made based on the input sensing panel ISL shown in, but the description made below can also be applied to the input sensing panel ISL-1 shown in. Figure 3A Hereinafter, the description will be made based on the input sensing panel ISL shown in, but the description made below can also be applied to the input sensing panel ISL-1 shown in. Figure 3B the input sensing panel ISL-1 shown in.

[0104] Referring to Figure 5 , the input sensing panel ISL includes a second substrate BS2, a first sensing electrode TE1, a second sensing electrode TE2, a first trace TL1, a second trace TL2, a third trace TL3, and a plurality of sensing pads PDT. The first sensing electrode TE1, the second sensing electrode TE2, the plurality of traces TL1, TL2, and TL3, and the plurality of sensing pads PDT may form a sensing circuit layer ML-T (see Figure 3A ).

[0105] An active area AA-I and a peripheral area NAA-I may be defined in the second substrate BS2. The peripheral area NAA-I may surround the active area AA-I (e.g., in a plan view).

[0106] The first sensing electrode TE1 and the second sensing electrode TE2 may be positioned in the active area AA-I. The input sensing panel ISL may obtain information about an external input through a change in capacitance between the first sensing electrode TE1 and the second sensing electrode TE2.

[0107] The first sensing electrode TE1 may extend along a first direction DR1 and may be arranged along a second direction DR2. The first sensing electrode TE1 may each include a first sensing pattern SP1 and a first connection pattern BP1 arranged along the first direction DR1. At least one first connection pattern BP1 may connect two first sensing patterns SP1 adjacent to each other along the first direction DR1. The first sensing pattern SP1 and the first connection pattern BP1 are substantially provided as an integral or single pattern, but will be divided for ease of description.

[0108] The second sensing electrode TE2 may extend along the second direction DR2 and may be arranged along the first direction DR1. The second sensing electrode TE2 may each include a second sensing pattern SP2 and a second connection pattern BP2 arranged along the second direction DR2. At least one second connection pattern BP2 may connect two second sensing patterns SP2 adjacent to each other along the second direction DR2. According to the present disclosure, the second sensing pattern SP2 and the second connection pattern BP2 may be positioned in different layers, respectively.

[0109] Reference Figure 6 and Figure 7 As shown in Figure 7 , the first sensing pattern SP1 and the first connection pattern BP1 positioned between the first sensing patterns SP1 may be substantially set as one pattern. The second sensing patterns SP2 may be spaced apart from each other along the second direction DR2. The first connection pattern BP1 may be positioned between the second sensing patterns SP2. The second sensing patterns SP2 spaced apart from each other may be connected to each other by the second connection pattern BP2. The second connection pattern BP2 and the second sensing pattern SP2 may be positioned in different layers, respectively, and the second sensing pattern SP2 may be connected to the second connection pattern BP2 through the connection contact hole CN-C.

[0110] As Figure 7 shown in Figure 7 , the input sensing panel ISL according to the present disclosure may include a first sensing insulating layer TIL1, a second sensing insulating layer TIL2, and a third sensing insulating layer TIL3 positioned on a second substrate BS2 (encapsulation substrate).

[0111] The first sensing pattern SP1, the first connection pattern BP1, and the second sensing pattern SP2 may be positioned on the second sensing insulating layer TIL2 and may be covered by the third sensing insulating layer TIL3. The second connection pattern BP2 may be positioned on the second substrate BS2 (encapsulation substrate) and may be covered by the first sensing insulating layer TIL1.

[0112] The second sensing pattern SP2 may be connected to the second connection pattern BP2 through the connection contact hole CN-C defined in the first sensing insulating layer TIL1 and the second sensing insulating layer TIL2.

[0113] According to the present disclosure, the first sensing insulating layer TIL1, the second sensing insulating layer TIL2, and the third sensing insulating layer TIL3 may each include a silicon-based inorganic material. The first sensing pattern SP1, the first connection pattern BP1, and the second sensing pattern SP2 positioned on the second sensing insulating layer TIL2 may be defined as being included in the third conductive layer, and the third conductive layer in the present disclosure may include a transparent conductive oxide. The second connection pattern BP2 positioned on the second substrate BS2 may be defined as the first conductive layer, and the first conductive layer may include a molybdenum-based metal. The second conductive layer positioned on the first sensing insulating layer TIL1 may be omitted in the first sensing electrode TE1 and the second sensing electrode TE2. The conductive patterns included in the second conductive layer may form a part of the traces TL1, TL2, and TL3, and their description will be provided later.

[0114] The traces TL1, TL2, and TL3 are positioned in the peripheral area NAA-I. The traces TL1, TL2, and TL3 may include a first trace TL1, a second trace TL2, and a third trace TL3.

[0115] According to the present disclosure, the peripheral region NAA-I can be divided into an upper region U-A adjacent to the upper side of the active region AA-I, a left region L-A adjacent to the left side of the active region AA-I, a right region R-A adjacent to the right side of the active region AA-I, and a lower region B-A adjacent to the lower side of the active region AA-I.

[0116] The first trace TL1 is connected to one end (e.g., the first end) of the second sensing electrode TE2. The said one end of the second sensing electrode TE2 can be adjacent to the boundary between the active region AA-I and the upper region U-A.

[0117] The first trace TL1 can be connected to one end of the second sensing electrode TE2 respectively, can extend along the upper region U-A, the left region L-A and the lower region B-A, and can be connected to the first sensing pad TP1.

[0118] The second trace TL2 is connected to the other end (e.g., the second end) of the second sensing electrode TE2. The said other end of the second sensing electrode TE2 can be adjacent to the boundary between the active region AA-I and the lower region B-A.

[0119] The second trace TL2 can be connected to the other end of the second sensing electrode TE2 respectively, can extend along the lower region B-A, and can be connected to the second sensing pad TP2.

[0120] The third trace TL3 is connected to one end (e.g., the first end) of the first sensing electrode TE1. One end of the first sensing electrode TE1 can be adjacent to the boundary between the active region AA-I and the right region R-A.

[0121] The third trace TL3 can be connected to one end of the first sensing electrode TE1, can extend along the right region R-A and the lower region B-A, and can be connected to the third sensing pad TP3.

[0122] According to the present disclosure, one second sensing electrode TE2 can be connected to two traces, namely the first trace TL1 and the second trace TL2. Therefore, the sensitivity of the region according to the second sensing electrode TE2 having a relatively large length compared to the first sensing electrode TE1 can be uniformly maintained. At the same time, this is shown as an example, and the first trace TL1 can be omitted and is not particularly limited.

[0123] The sensing pad PDT is positioned in the peripheral region NAA-I. The sensing pad PDT may include a first sensing pad TP1, a second sensing pad TP2, and a third sensing pad TP3. The first sensing pad TP1 is connected to a first trace TL1 and electrically connected to a second sensing electrode TE2. The second sensing pad TP2 is connected to a second trace TL2 and electrically connected to the second sensing electrode TE2. The third sensing pad TP3 is connected to a third trace TL3 and electrically connected to a first sensing electrode TE1.

[0124] The input sensing panel ISL according to one or more embodiments may further include a junction pattern JS. The junction pattern JS may be positioned in a region where the traces TL1, TL2, and TL3 are connected to the sensing electrodes TE1 and TE2 to each other. Accordingly, the junction pattern JS may be positioned along the boundaries between the upper region U-A and the active region AA-I, between the right region R-A and the active region AA-I, and between the lower region B-A and the active region AA-I. Figure 5 The junction pattern JS is shown positioned in the peripheral region NAA-I, but one or more embodiments of the present disclosure are not limited thereto, and the junction pattern JS may be positioned in the active region AA-I.

[0125] Figure 8 is a plan view of an input sensing panel according to one or more embodiments of the present disclosure. When described with reference to Figure 8 will describe the differences from Figure 5 .

[0126] Referring to Figure 8 , an active region AAa and a peripheral region NAAa may be defined in a second substrate BS2 of the input sensing panel ISLa. The peripheral region NAAa may surround the active region AAa.

[0127] Because the input sensing panel ISL described with reference to Figure 5 may have an active region AA-I having a quadrilateral shape, the boundary between the active region AA-I and the peripheral region NAA-I may be a straight line. Accordingly, the corners of the active region AA-I may all have a right angle shape. However, Figure 8 the active region AAa shown in

[0128] has a shape in which the lines adjacent to the vertices of the quadrilateral have curvature. Accordingly, a part of the boundary BDC between the active region AAa and the peripheral region NAAa may include a curved region.

[0129] The input sensing panel ISLa may include a normal bonding pattern JS-N and a bent bonding pattern JS-C. The bent bonding pattern JS-C may be adjacent to a sensing pattern positioned at a corner with curvature in the active area AAa, and the normal bonding pattern JS-N may be connected to other sensing patterns.

[0130] Figure 9 is a cross-sectional view taken along the Figure 5 line II-II'. Figure 10 is a cross-sectional view of a trace according to one or more embodiments of the present disclosure.

[0131] Figure 9 shows a cross-sectional view of a third trace TL3 described with reference to Figure 5 The following description of the third trace TL3 provided with reference to Figure 9 may be commonly applied to the third trace TL3 that is respectively connected to one end of the first sensing electrode TE1 and positioned in the Figure 5 right region R-A in the peripheral region NAA-I.

[0132] The third trace TL3 may include a first conductive pattern T1, a second conductive pattern T2, and a bridging pattern TB. The first conductive pattern T1 included in the first conductive layer and the second conductive pattern T2 included in the second conductive layer may include molybdenum-based metals, and the bridging pattern TB included in the third conductive layer may include a transparent conductive oxide.

[0133] The first conductive pattern T1 may be positioned on the second substrate BS2 (encapsulation substrate) and may be covered by the first sensing insulating layer TIL1.

[0134] The second conductive pattern T2 may be positioned on the first sensing insulating layer TIL1 and may be covered by the second sensing insulating layer TIL2. The second conductive pattern T2 may be stacked with the first conductive pattern T1. In the first direction DR1, a first width W1 of the first conductive pattern T1 may be greater than a second width W2 of the second conductive pattern T2. Thus, in a plan view, a part T-U of the upper surface of the first conductive pattern T1 may be exposed from the second conductive pattern T2.

[0135] The bridging pattern TB may be positioned on the second sensing insulating layer TIL2 and may be covered by the third sensing insulating layer TIL3. The bridging pattern TB may branch from the first sensing pattern SP1 to the right region R-A. Thus, the first sensing pattern SP1 and the bridging pattern TB may be patterned by the same process and may include the same material.

[0136] According to the present disclosure, the bridging pattern TB can be connected to the first conductive pattern T1 and the second conductive pattern T2. The bridging pattern TB can be connected to the portion T-U of the first conductive pattern T1 exposed from the second conductive pattern T2 through a first contact hole CN1 defined by the first sensing insulating layer TIL1 and the second sensing insulating layer TIL2. In addition, the bridging pattern TB can be connected to the second conductive pattern T2 through a second contact hole CN2 defined by the second sensing insulating layer TIL2.

[0137] According to one or more embodiments, the second conductive pattern T2 can be directly connected to the first conductive pattern T1 through a contact hole passing through the first sensing insulating layer TIL1.

[0138] According to the present disclosure, the third trace TL3 located in the right region R-A where traces are densely located can include metal layers stacked in two layers, and the resistance of the third trace TL3 can thus be reduced. In addition, since the second conductive pattern T2 can expose the portion T-U of the first conductive pattern T1, and the bridging pattern TB can be connected to the exposed portion T-U, the space for the peripheral region NAA-I (see Figure 5 ) in which the third trace TL3 is located can be reduced. Therefore, a display device EA including an input sensing panel ISL with reduced dead space can be provided (see Figure 2 ).

[0139] Referring to Figure 10 , the third trace TL3-1 can include the first conductive pattern T1, the second conductive pattern T2, and the bridging pattern TB-1.

[0140] The first conductive pattern T1 can be located on the second substrate BS2 (encapsulation substrate) and can be covered by the first sensing insulating layer TIL1.

[0141] The second conductive pattern T2 can be located on the first sensing insulating layer TIL1 and can be covered by the second sensing insulating layer TIL2. The second conductive pattern T2 can be stacked with the first conductive pattern T1. In a plan view, a part of the upper surface of the first conductive pattern T1 can be exposed from the second conductive pattern T2.

[0142] The bridging pattern TB-1 can be located on the second sensing insulating layer TIL2 and can be covered by the third sensing insulating layer TIL3. The bridging pattern TB-1 can branch from the first sensing pattern SP1 to the right region R-A. Therefore, the first sensing pattern SP1 and the bridging pattern TB-1 can be patterned by the same process and can include the same material.

[0143] According to the present disclosure, the bridging pattern TB-1 can be connected to the first conductive pattern T1 and the second conductive pattern T2. The bridging pattern TB-1 can be connected to the first conductive pattern T1 and the second conductive pattern T2 through a contact hole CN defined by the first sensing insulating layer TIL1 and the second sensing insulating layer TIL2.

[0144] The contact hole CN can expose a portion T-U of the first conductive pattern T1, a side surface T-S1 of the second conductive pattern T2, and an upper surface T-S2 of the second conductive pattern T2.

[0145] The bridging pattern TB-1 can be positioned in the contact hole CN and contact the portion T-U of the first conductive pattern T1, the side surface T-S1 of the second conductive pattern T2, and the upper surface T-S2 of the second conductive pattern T2. Thus, different from that shown in Figure 9 , the process of forming a second contact hole CN2 (see Figure 9 ) in the second sensing insulating layer TIL2 to separately connect the second conductive pattern T2 and the bridging pattern TB-1 can be skipped.

[0146] Figure 11 is a cross-sectional view taken along line III-III' of Figure 5 . Figure 12 is a cross-sectional view of a trace according to one or more embodiments of the present disclosure. Figure 11 shows the connection relationship between the third trace TL3 and the bonding pattern JS described with reference to Figure 5 .

[0147] With reference to Figure 11 , the third trace TL3 can include a first conductive pattern T1, a second conductive pattern T2, and a bridging pattern TB.

[0148] The first conductive pattern T1 can be positioned on the second substrate BS2 (package substrate) and can be covered by the first sensing insulating layer TIL1.

[0149] The second conductive pattern T2 can be positioned on the first sensing insulating layer TIL1 and can be covered by the second sensing insulating layer TIL2. The second conductive pattern T2 can be stacked with the first conductive pattern T1. In a plan view, a part of the upper surface of the first conductive pattern T1 can be exposed from the second conductive pattern T2.

[0150] The bridging pattern TB can be positioned on the second sensing insulating layer TIL2 and can be covered by the third sensing insulating layer TIL3. The bridging pattern TB can branch from the first sensing pattern SP1 to the right region R-A. Thus, the first sensing pattern SP1 and the bridging pattern TB can be patterned by the same process and can include the same material.

[0151] The bridging pattern TB can be connected to the first conductive pattern T1 and the second conductive pattern T2 through the first contact hole CN1 and the second contact hole CN2.

[0152] According to one or more embodiments, the bonding pattern JS can be included in the first conductive layer. Thus, the bonding pattern JS can be positioned on the second substrate BS2 (encapsulation substrate) and can be covered by the first sensing insulating layer TIL1. The bonding pattern JS can be spaced apart from the first conductive pattern T1 along the first direction DR1. Figure 11 It is shown that the bonding pattern JS is positioned in the right region R-A, but one or more embodiments of the present disclosure are not limited thereto. The bonding pattern JS can be positioned in the active region AA-I or can be positioned to overlap with the boundary between the active region AA-I and the right region R-A.

[0153] The bridging pattern TB can be connected to the bonding pattern JS. The bridging pattern TB can be connected to the bonding pattern JS through a bonding contact hole CN-J defined by the first sensing insulating layer TIL1 and the second sensing insulating layer TIL2.

[0154] Refer to Figure 12 The following description provided mainly focuses on the differences from Figure 11 According to one or more embodiments, the bonding pattern JS-1 can be included in the second conductive layer. Thus, the bonding pattern JS-1 can be positioned on the first sensing insulating layer TIL1 and can be covered by the second sensing insulating layer TIL2.

[0155] The bridging pattern TB can be connected to the bonding pattern JS-1. The bridging pattern TB can be connected to the bonding pattern JS-1 through a bonding contact hole CN-J defined by the second sensing insulating layer TIL2.

[0156] Figure 13 is a cross-sectional view taken along the line IV-IV' of Figure 5 The cross-sectional view is taken along the line IV-IV' of Figure 13 is related to the third trace TL3 positioned in the lower region B-A among the third traces TL3 described with reference to Figure 5 The cross-sectional view is related to the third trace TL3 positioned in the lower region B-A among the third traces TL3 described with reference to

[0157] The lower region B-A can be a region where the first trace TL1, the second trace TL2, and the third trace TL3 are densely positioned to be connected to the sensing pad PDT as described with reference to Figure 5 Thus, in order to reduce or prevent the possibility of short-circuit defects and an increase in dead space, the third trace TL3 positioned in the lower region B-A can include a single-layer metal layer.

[0158] The third trace TL3 related to Figure 5The portion adjacent to the other end of the described second sensing electrode TE2 (i.e., the third trace TL3 positioned in the lower region B-A) may include lower patterns TL-B1 and TL-B2, and the remaining portion of the third trace TL3 may include upper patterns TL-U1 and TL-U2. The number of each of the lower patterns TL-B1 and TL-B2 and the upper patterns TL-U1 and TL-U2 shown is two, but one or more embodiments of the present disclosure are not limited thereto.

[0159] The lower patterns TL-B1 and TL-B2 may be positioned on the second substrate BS2 (encapsulation substrate) and may be covered by the first sensing insulating layer TIL1. The lower patterns TL-B1 and TL-B2 may be spaced apart from each other along the first direction DR1. The upper patterns TL-U1 and TL-U2 may be positioned on the first sensing insulating layer TIL1 and may be covered by the second sensing insulating layer TIL2. The upper patterns TL-U1 and TL-U2 may be spaced apart from each other along the first direction DR1.

[0160] In a plan view, the lower patterns TL-B1 and TL-B2 and the upper patterns TL-U1 and TL-U2 may not overlap each other. Further, in a plan view, the lower patterns TL-B1 and TL-B2 and the upper patterns TL-U1 and TL-U2 may be alternately arranged along the first direction DR1. The ends of the lower patterns TL-B1 and TL-B2 may be aligned with the ends of the upper patterns TL-U1 and TL-U2 along the third direction DR3, respectively.

[0161] The lower patterns TL-B1 and TL-B2 and the upper patterns TL-U1 and TL-U2 may be connected to different third traces TL3, respectively. Accordingly, the lower patterns TL-B1 and TL-B2 and the upper patterns TL-U1 and TL-U2 may be connected to different sensing pads PDT (see Figure 5 )

[0162] The lower patterns TL-B1 and TL-B2 may branch from the first conductive pattern T1 of the third trace TL3 positioned in the right region R-A (see Figure 9 ), and the upper patterns TL-U1 and TL-U2 may branch from the second conductive pattern T2 of the third trace TL3 positioned in the right region R-A (see Figure 9 ).

[0163] The third traces TL3 positioned in the lower region B-A where traces are densely positioned may each include a single-layer metal layer, and the ends of the third traces TL3 may be aligned with each other and may not overlap each other, thereby reducing the dead space for the lower region B-A in which the traces are positioned.

[0164] Figure 14is a cross-sectional view of a trace according to one or more embodiments of the present disclosure. Figure 14 is related to the first trace TL1 positioned in the left region L-A among the first traces TL1 described with reference to Figure 5 For example, it is a cross-sectional view related to the first trace TL1. Figure 14 is a cross-sectional view taken along the line Figure 5 V-V'.

[0165] The first trace TL1 positioned in the left region L-A may include a single-layer metal layer. The first trace TL1 may be included in the first conductive layer, may be positioned on the second substrate BS2 (package substrate), and may be covered by the first sensing insulating layer TIL1. The description of the first trace TL1 positioned in the left region L-A may also be applied to the first trace TL1 positioned in the upper region U-A and the lower region B-A.

[0166] According to one or more embodiments of the present disclosure, in the input sensing panel, the area size of the peripheral region in which the traces are positioned may not be increased, thereby reducing the dead space. In addition, the traces may include a multi-layer conductive pattern, thereby providing a display device including an input sensing panel having a reduced trace resistance.

[0167] Although the present disclosure has been described with reference to the embodiments of the present disclosure, it is understood that the present disclosure should not be limited to these embodiments, but various changes and modifications can be made by those of ordinary skill in the art within the spirit and scope of the present disclosure as claimed. Therefore, the technical scope of the present disclosure is not limited to the content described in the detailed description of the specification, but should be determined by the appended claims and their functional equivalents included herein.

Claims

1. A display device, the display device comprising: A display panel including an active area and a peripheral area adjacent to the active area, pixels being located in the active area; And An input sensing panel including a sensing circuit layer and a package substrate above the display panel, Wherein, the sensing circuit layer includes: A first sensing insulating layer, a second sensing insulating layer, and a third sensing insulating layer, sequentially stacked above the display panel; A first sensing electrode extending along a first direction and arranged along a second direction intersecting the first direction; A second sensing electrode including a sensing pattern and a connection pattern, the sensing pattern being arranged along the second direction, the connection patterns respectively extending along the second direction and arranged along the first direction between adjacent sensing patterns in the sensing pattern; A first trace respectively connected to a first end of the second sensing electrode; A second trace respectively connected to a second end of the second sensing electrode; and A third trace respectively connected to a first end of the first sensing electrode and including: a first conductive pattern; a second conductive pattern stacked with the first conductive pattern and having a width smaller than that of the first conductive pattern in the first direction; and a bridging pattern extending from one of the sensing patterns in the sensing pattern and connected to the first conductive pattern and the second conductive pattern.

2. The display device according to claim 1, wherein The first conductive pattern and the second conductive pattern include molybdenum-based metals, and Wherein, the bridging pattern includes a transparent conductive oxide.

3. The display device according to claim 1, wherein, The first conductive pattern is above the package substrate and covered by the first sensing insulating layer, Wherein, the second conductive pattern is above the first sensing insulating layer and covered by the second sensing insulating layer, and Wherein, the bridging pattern is above the second sensing insulating layer and covered by the third sensing insulating layer.

4. The display device according to claim 3, wherein, In a plan view, a part of an upper surface of the first conductive pattern is exposed from the second conductive pattern.

5. The display device according to claim 4, wherein, A first contact hole overlapping with the part of the first conductive pattern is defined in the first sensing insulating layer and the second sensing insulating layer, Wherein, a second contact hole overlapping with the second conductive pattern is defined in the second sensing insulating layer, and Wherein, the bridging pattern is connected to the part of the first conductive pattern through the first contact hole and connected to the second conductive pattern through the second contact hole.

6. The display device according to claim 4, wherein, A contact hole overlapping with the part of the first conductive pattern and exposing a side surface and a part of an upper surface of the second conductive pattern is defined in the first sensing insulating layer and the second sensing insulating layer, and Wherein, the bridging pattern is connected to the part of the first conductive pattern through the contact hole and connected to the side surface and the part of the second conductive pattern.

7. The display device according to claim 3, wherein, The connection pattern is above the package substrate and covered by the first sensing insulating layer, Among them, the sensing pattern and the first sensing electrode are above the second sensing insulating layer and are covered by the third sensing insulating layer, and Among them, the sensing pattern is connected to the connection pattern through connection contact holes defined in the first sensing insulating layer and the second sensing insulating layer.

8. The display device according to claim 7, wherein, The bridging pattern includes an integral pattern extending from the sensing pattern.

9. The display device according to claim 1, wherein the display device further comprises: The bonding pattern is adjacent to the first end of the first trace connected to the second sensing electrode, adjacent to the second end of the second trace connected to the second sensing electrode, and adjacent to the first end of the third trace connected to the first sensing electrode.

10. The display device according to claim 9, wherein, The bonding pattern is above the encapsulation substrate and is covered by the first sensing insulating layer, and Among them, the bridging pattern is connected to one of the bonding patterns through a first bonding contact hole defined in the first sensing insulating layer and the second sensing insulating layer.

11. The display device according to claim 9, wherein, The bonding pattern is above the first sensing insulating layer and is covered by the second sensing insulating layer, and Among them, the bridging pattern is connected to one of the bonding patterns through a second bonding contact hole defined in the second sensing insulating layer.

12. The display device according to claim 1, wherein, The portion of the third trace adjacent to the second end of the second sensing electrode includes a lower pattern above the encapsulation substrate, Among them, the remaining portion of the third trace adjacent to the second end of the second sensing electrode includes an upper pattern that does not overlap with the lower pattern, and Among them, in a plan view, the end portions of the lower pattern are respectively aligned with the end portions of the upper pattern.

13. The display device according to claim 12, wherein, One of the lower patterns is integral with the first conductive pattern, and Among them, one of the upper patterns is integral with the second conductive pattern.

14. The display device according to claim 1, wherein, The peripheral region includes an upper region adjacent to the upper end of the active region, a left region adjacent to the left side of the active region, a lower region adjacent to the lower end of the active region, and a right region adjacent to the right side of the active region, and Among them, the input sensing panel further includes a sensing pad in the lower region.

15. The display device according to claim 14, wherein, In a plan view, the third trace extends along the right region and the lower region and is connected to the sensing pad.

16. The display device according to claim 15, wherein, In a plan view, the first trace is connected to the first end of the second sensing electrode, extends along the upper region, the left region, and the lower region, and is connected to the sensing pad, and Among them, the second trace extends along the lower region and is connected to the sensing pad.

17. The display device according to claim 16, wherein, The first trace includes a single layer above the encapsulation substrate.

18. The display device according to claim 1, wherein, The first sensing electrode and the second sensing electrode at the corners of the active region are rounded.

19. The display device according to claim 1, wherein, The first sensing insulating layer, the second sensing insulating layer, and the third sensing insulating layer include inorganic materials.

20. The display device according to claim 1, wherein, The encapsulation substrate includes glass, and Among them, the display device further includes a bonding member that overlaps with the peripheral region and is configured to bond the display panel and the encapsulation substrate.

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