Test circuit board, display panel and display device

Abstract

The invention discloses a test circuit board, a display panel and a display device. The test circuit board comprises a substrate and a test circuit located on one side of the substrate. The test circuit comprises a dummy circuit layer, a first insulating layer and a dummy light-emitting device layer which are sequentially stacked in the direction away from the substrate. The dummy circuit layer is electrically connected with the dummy light-emitting device layer; the dummy light-emitting device layer comprises a plurality of dummy light-emitting devices, each dummy light-emitting device comprises a first electrode, a first light-emitting function layer and a second electrode, and the first electrodes, the first light-emitting function layers and the second electrodes are sequentially stacked in the direction away from the substrate; a first isolation groove is formed in the first insulating layer and is configured to isolate the first light-emitting functional layer and / or the second electrode of the adjacent dummy light-emitting device; the test circuit further comprises a first test electrode and a second test electrode which are located on the periphery of orthographic projection of the multiple dummy light-emitting devices on the substrate, the first test electrode is electrically connected with the first light-emitting functional layer, and the second test electrode is electrically connected with the second electrode.

Description

Technical Field

[0001] The embodiments of the present disclosure belong to the field of display technology, and particularly relate to a test circuit board, a display panel, and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) displays have attracted widespread attention due to their advantages such as self-luminescence, low power consumption, lightness, flexibility, brilliant colors, high contrast, and fast response rate. Summary of the Invention

[0003] Embodiments of the present disclosure provide a test circuit board, a display panel, and a display device.

[0004] In a first aspect, an embodiment of the present disclosure provides a test circuit board, comprising: a substrate,

[0005] A test circuit is located on one side of the substrate;

[0006] The test circuit includes a dummy circuit layer, a first insulating layer and a dummy light-emitting device layer, which are stacked in sequence in a direction away from the substrate; the dummy circuit layer and the dummy light-emitting device layer are electrically connected;

[0007] The dummy light emitting device layer includes a plurality of dummy light emitting devices,

[0008] The dummy light emitting device comprises a first electrode, a first light emitting functional layer and a second electrode, which are stacked in sequence in a direction away from the substrate;

[0009] A first isolation groove is formed in the first insulating layer, and is configured to separate the first light-emitting functional layer and / or the second electrode of the adjacent dummy light-emitting device;

[0010] The test circuit further includes a first test electrode and a second test electrode, which are located outside the orthographic projection of the plurality of dummy light-emitting devices on the substrate. The first test electrode is electrically connected to the first light-emitting functional layer, and the second test electrode is electrically connected to the second electrode.

[0011] In some embodiments, the method comprises a first region and a second region, wherein the second region is located outside the first region;

[0012] The plurality of dummy light-emitting devices are arranged in an array and located in the first area;

[0013] The first region includes a plurality of first sub-regions,

[0014] The first test electrode includes a plurality of first sub-electrodes located in the second area, and each of the first sub-electrodes is electrically connected to a corresponding first light-emitting functional layer in the first sub-area;

[0015] The second test electrode includes a plurality of second sub-electrodes located in the second area, and each second sub-electrode is electrically connected to a corresponding second electrode in the first sub-area.

[0016] In some embodiments, the dummy light emitting device includes light emitting devices of multiple colors.

[0017] The first sub-electrode includes a plurality of first sub-portions, and each of the first sub-portions is electrically connected to the first light-emitting functional layer of a light-emitting device of one color in the first sub-region.

[0018] In some embodiments, the first light-emitting functional layer includes at least two organic stacked structures and at least one charge generation layer, the organic stacked structures and the charge generation layer are stacked, and the charge generation layer is located between any two adjacent organic stacked structures;

[0019] The first test electrode is electrically connected to the charge generation layer.

[0020] In some embodiments, the first light-emitting functional layer comprises an organic stacked structure.

[0021] The first test electrode is electrically connected to the organic stacked structure.

[0022] In some embodiments, the dummy circuit layer includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer, which are stacked in sequence in a direction away from the substrate, and a second insulating layer is provided between any two adjacent layers;

[0023] The first sub-electrode and the second sub-electrode have the same structure;

[0024] The first sub-electrode includes a first sub-layer, and the first sub-layer and the fifth conductive layer are arranged in the same layer;

[0025] The first insulating layer is provided with a first opening and a second opening, the first sub-electrode is exposed at the first opening; the second sub-electrode is exposed at the second opening;

[0026] The first sublayer extends to the junction of the second area and the first area to form a lead, the first light-emitting functional layer also extends to the second area and at least partially overlaps with the orthographic projection of the lead on the substrate, and the first light-emitting functional layer and the lead are electrically contacted in the overlapping area of their orthographic projections.

[0027] In some embodiments, the first sub-electrode further includes a second sub-layer located on a side of the first sub-layer facing away from the substrate.

[0028] The second sub-layer is disposed on the same layer as the first electrode;

[0029] The positive projections of the second sub-layer, the first sub-layer, and the first opening on the substrate at least partially overlap, and the second sub-layer and the first sub-layer are in electrical contact in the overlapping region of their positive projections;

[0030] The test circuit board further includes a pixel defining layer located on the side of the first electrode away from the substrate. A third opening is formed in the pixel defining layer, and the second sub-layer is exposed at the third opening.

[0031] In some embodiments, the first sub-electrode further includes a third sub-layer, a fourth sub-layer, a fifth sub-layer, and a sixth sub-layer, which are located between the first sub-layer and the substrate and are stacked in sequence along the direction away from the substrate.

[0032] The third sub-layer is disposed on the same layer as the first conductive layer;

[0033] The fourth sub-layer is disposed on the same layer as the second conductive layer;

[0034] The fifth sub-layer is disposed on the same layer as the third conductive layer;

[0035] The sixth sub-layer is disposed on the same layer as the fourth conductive layer;

[0036] The positive projections of the third sub-layer, the fourth sub-layer, the fifth sub-layer, the sixth sub-layer, and the first sub-layer on the substrate at least partially overlap. The second insulating layer is provided with a fourth opening in the region corresponding to the overlapping of the positive projections of the five layers. The third sub-layer, the fourth sub-layer, the fifth sub-layer, the sixth sub-layer, and the first sub-layer are in electrical contact with each other at the fourth opening.

[0037] In some embodiments, a touch layer is further included, which is located in the first region and on the side of the test circuit away from the substrate.

[0038] The first sub-electrode further includes a seventh sub-layer, which is located on the side of the second sub-layer away from the substrate and is disposed on the same layer as the touch layer;

[0039] A third insulating layer is further provided between the seventh sub-layer and the second sub-layer.

[0040] The positive projections of the seventh sub-layer and the second sub-layer on the substrate at least partially overlap. The third insulating layer is provided with a fifth opening in the region corresponding to the overlapping of the positive projections of the two layers. The seventh sub-layer and the second sub-layer are in electrical contact with each other at the fifth opening.

[0041] In some embodiments, a protective layer is further included, which is located on the side of the touch layer away from the substrate.

[0042] A sixth opening is formed in the protective layer, and the seventh sub-layer is exposed at the sixth opening.

[0043] In some embodiments, in a direction away from the substrate, for any two adjacent sub-layers of the first sub-electrode, the edge of the sub-layer farther from the substrate in the orthographic projection on the substrate falls within the orthographic projection on the substrate of the sub-layer closer to the substrate;

[0044] Alternatively, for any two adjacent sub-layers of the first sub-electrode, the edge of the sub-layer closer to the substrate in the orthographic projection on the substrate falls within the orthographic projection on the substrate of the sub-layer farther from the substrate.

[0045] In some embodiments, the plurality of first sub-electrodes are arranged in a straight line.

[0046] The plurality of second sub-electrodes are arranged in a straight line.

[0047] The shapes of the orthographic projections of the first sub-electrode and the second sub-electrode on the substrate include a rectangle, a circle, or a regular polygon;

[0048] The side length dimension or the radial dimension range of the orthographic projections of the first sub-electrode and the second sub-electrode on the substrate is 120-150 μm;

[0049] The center spacing range of adjacent first sub-electrodes is 160-190 μm;

[0050] The center spacing range of adjacent second sub-electrodes is 160-190 μm.

[0051] In some embodiments, it further includes a packaging layer located on a side of the dummy light-emitting device away from the substrate. The orthographic projection of the packaging layer on the substrate covers the orthographic projection of the dummy light-emitting device on the substrate, and the orthographic projections of the packaging layer and the lead on the substrate at least partially overlap;

[0052] The orthographic projections of the packaging layer and the first test electrode and the second test electrode on the substrate do not overlap;

[0053] It further includes a dam, and the orthographic projection on the substrate surrounds the four peripheral edges of the orthographic projection of the packaging layer on the substrate. The orthographic projections of the dam and the first test electrode and the second test electrode on the substrate do not overlap;

[0054] The orthographic projections of the dam and the lead on the substrate intersect with each other.

[0055] The line width of the lead at the position where it intersects with the orthographic projection of the dam is greater than 20 μm;

[0056] The dam includes an organic insulating layer in the second insulating layer, an organic insulating layer in the first insulating layer, and the pixel defining layer;

[0057] Regions on both sides of the dam include an inorganic insulating layer in the second insulating layer and an inorganic insulating layer in the first insulating layer.

[0058] In a second aspect, an embodiment of the present disclosure further provides a display panel having a display area and a non-display area, which includes the above-mentioned test circuit board located in the non-display area.

[0059] In some embodiments, it further includes a display circuit on the same side of the substrate as the test circuit in the test circuit board and located in the display area;

[0060] The display circuit includes a first circuit layer, the first insulating layer, and a first light-emitting device layer, which are sequentially stacked in a direction away from the substrate; the first circuit layer is electrically connected to the first light-emitting device layer;

[0061] The first circuit layer and the dummy circuit layer are provided on the same layer and have the same structure;

[0062] The first light-emitting device layer includes a plurality of first light-emitting devices,

[0063] The first light-emitting device includes a third electrode, a second light-emitting functional layer, and a fourth electrode, which are sequentially stacked in a direction away from the substrate;

[0064] The third electrode and the first electrode are provided on the same layer and have the same structure;

[0065] The fourth electrode and the second electrode are provided on the same layer and have the same structure;

[0066] The second light-emitting functional layer and the first light-emitting functional layer are provided on the same layer and have the same structure;

[0067] A second isolation groove is further formed in the first insulating layer and is configured to isolate the second light-emitting functional layer and / or the fourth electrode of adjacent first light-emitting devices;

[0068] The second isolation groove and the first isolation groove have the same structure.

[0069] In a third aspect, an embodiment of the present disclosure further provides a display device, which includes the above-mentioned display panel.

[0070] The test circuit board provided by the embodiments of the present disclosure can directly measure the contact resistance between the first light-emitting functional layer and the second electrode at the position of the first isolation groove by setting a test circuit. Therefore, the morphology of the first isolation groove can be improved according to the contact resistance between the first light-emitting functional layer and the second electrode at the position of the first isolation groove. Furthermore, the greenish smear defect of the display panel with the same structure as the test circuit at low gray levels can be improved, and the uniformity of the image quality of the display panel can be enhanced.

[0071] The display panel provided by the embodiments of the present disclosure can indirectly measure the contact resistance between the second light-emitting functional layer and the fourth electrode at the position of the second isolation groove by adopting the above-mentioned test circuit board. Therefore, the morphology of the second isolation groove can be improved according to the contact resistance between the second light-emitting functional layer and the fourth electrode at the position of the second isolation groove. Furthermore, the greenish smear defect of the display panel at low gray levels can be improved, and the uniformity of the image quality of the display panel can be enhanced.

[0072] The display device provided by the embodiments of the present disclosure can improve the greenish smear defect of the display device at low gray levels and enhance the uniformity of the image quality of the display device by adopting the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] The drawings are used to provide a further understanding of the embodiments of the present disclosure, and constitute a part of the specification. They are used together with the embodiments of the present disclosure to explain the present disclosure, and do not constitute a limitation to the present disclosure. By describing the detailed exemplary embodiments with reference to the drawings, the above and other features and advantages will become more obvious to those skilled in the art. In the drawings:

[0074] Figure 1a It is a schematic cross-sectional view of the structure of an OLED device with a traditional single light-emitting functional layer stack structure.

[0075] Figure 1b It is a schematic cross-sectional view of the structure of an OLED device with a multi-light-emitting functional layer stack structure.

[0076] Figure 1c It is a schematic cross-sectional view of the structure in which adjacent series OLED devices are separated by isolation grooves in the related art.

[0077] Figure 1d It is an electron microscope image of a series OLED device at the position of the isolation groove in the related art.

[0078] Figure 1e It is an equivalent circuit diagram of a series OLED device when it is lit in the related art.

[0079] Figure 2a It is a schematic top view of the structure of a test circuit board in the embodiments of the present disclosure.

[0080] Figure 2b is a schematic structural sectional view along Figure 2a the AA' cutting line in

[0081] Figure 3a This is a schematic top view of the structure of another test circuit board in the embodiment of the present disclosure.

[0082] Figure 3b is a schematic structural sectional view along Figure 3a the BB' cutting line in

[0083] Figure 3c is a schematic structural sectional view along Figure 3a the CC' cutting line in

[0084] Figure 4a This is a schematic top view of the structure of yet another test circuit board in the embodiment of the present disclosure.

[0085] Figure 4b is a schematic structural sectional view along Figure 4a the DD' cutting line in

[0086] Figure 4c is a schematic structural sectional view along Figure 4a the EE' cutting line in

[0087] Figure 4d is a schematic structural sectional view along Figure 4a the FF' cutting line in

[0088] Figure 4e is a schematic structural sectional view along Figure 4a the GG' cutting line in

[0089] Figure 5a is a schematic structural sectional view along Figure 3a a schematic structural sectional view along the HH' cutting line in

[0090] Figure 5b is a schematic structural sectional view along Figure 3a another schematic structural sectional view along the HH' cutting line in

[0091] Figure 6a This is a schematic structural sectional view of a first test electrode in the embodiment of the present disclosure.

[0092] Figure 6b This is a schematic structural sectional view of another first test electrode in the embodiment of the present disclosure.

[0093] Figure 6c This is a schematic structural sectional view of yet another first test electrode in the embodiment of the present disclosure.

[0094] Figure 6d This is a schematic structural sectional view of yet another first test electrode in the embodiment of the present disclosure.

[0095] Figure 7a This is a top view schematic diagram of the structure of a first test electrode in an embodiment of the present disclosure.

[0096] Figure 7b This is a top view schematic diagram of the structure of another first test electrode in an embodiment of the present disclosure.

[0097] Figure 8a is Figure 3a the enlarged top view of part I in Figure 4a and part J in

[0098] Figure 8b is a schematic cross-sectional view of the structure along the Figure 8a KK' cutting line in

[0099] Figure 9a This is a top view schematic diagram of the structure of a display panel in an embodiment of the present disclosure.

[0100] Figure 9b is a schematic cross-sectional view of the structure along the Figure 9a LL' cutting line in Detailed implementation manners

[0101] To enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the following further describes in detail a test circuit board, a display panel, and a display device provided by the embodiments of the present disclosure in conjunction with the accompanying drawings and specific implementation manners.

[0102] In the following, the embodiments of the present disclosure will be more fully described with reference to the accompanying drawings. However, the illustrated embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0103] The embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications to the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions, but are not intended to be restrictive.

[0104] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms such as "including" or "comprising" mean that the elements or items appearing before the term cover the elements or items listed after the term and their equivalents, without excluding other elements or items.

[0105] Features such as "parallel", "perpendicular", and "identical" used in at least one embodiment of the present disclosure include the strictly defined features of "parallel", "perpendicular", "identical", etc., as well as situations with certain errors such as "substantially parallel", "substantially perpendicular", "substantially identical", etc. Considering measurement and errors related to the measurement of specific quantities (e.g., limitations of the measurement system), it means within the acceptable deviation range for a specific value determined by those of ordinary skill in the art. For example, "substantially" can mean within one or more standard deviations, or within 10% or 5% of the value. When the quantity of a component is not specifically indicated in the following text of the embodiments of the present disclosure, it means that the component can be one or more, or can be understood as at least one. "At least one" means one or more, and "a plurality" means at least two. The so-called "formed on the same layer" in the disclosure refers to a structure formed by two (or more) structures through the same deposition process and patterned through the same lithography process, and their materials can be the same or different. The "integrally formed structure" in the present disclosure refers to a structure in which two (or more) structures are formed through the same deposition process and patterned through the same lithography process and are connected to each other, and their materials can be the same or different.

[0106] The trend of the continuous expansion of the application of AMOLED (Active Matrix / Organic Light Emitting Diode) display products from small-sized mobile phones, watches, etc. to the medium-sized field has become increasingly obvious. Especially in medium-sized applications such as tablets, notebooks, and in-vehicle displays, the demand has been growing rapidly. Medium-sized AMOLED display products will give rise to more new forms and new scenarios, and the requirements for service life and reliability are also getting higher and higher. Increasing product reliability is one of the most important ways to enhance product competitiveness. To improve the utilization efficiency of OLED current and reduce the luminous power consumption of the product, compared with the OLED device structure with a traditional single light-emitting functional layer stacked structure 9 (refer to Figure 1a )), the tandem OLED device structure in which multiple light-emitting functional layer stacked structures 9 are stacked and connected in series (refer to Figure 1b , that is, a high-efficiency OLED device formed by mutually connecting multiple light-emitting functional layer stacked structures 9 in series through a charge generation layer B2) has higher efficiency, lower current, and longer lifespan.

[0107] In the research, the inventors of the present application found that the light-emitting functional layer stack structure of a light-emitting element may include a plurality of light-emitting functional layer stack structures arranged in layers, such as a tandem device. The tandem device has the characteristics of low power consumption and long lifespan. However, a charge generation layer (B2) is provided between at least two of the plurality of light-emitting functional layer stack structures in the tandem device, and the charge generation layer has a relatively high conductivity. When the charge generation layer is a whole-film layer, the charge generation layers of adjacent two light-emitting elements are continuous film layers, and there is a phenomenon of lateral charge migration, resulting in chromaticity shift of the display substrate at low gray levels in a single color, such as crosstalk easily occurring between adjacent sub-pixels, leading to color deviation of the display substrate. For example, the charge generation layer easily causes crosstalk between sub-pixels of different colors at low brightness, resulting in color deviation at low gray levels.

[0108] In the related art, referring to Figure 1b , Figure 1c and Figure 1d , the tandem OLED device includes an anode 10, a first light-emitting functional layer stack structure 91, a charge generation layer B2, a second light-emitting functional layer stack structure 92, and a cathode 11 stacked in sequence. The first light-emitting functional layer stack structure 91, the charge generation layer B2, the second light-emitting functional layer stack structure 92, and the cathode 11 of adjacent OLED devices are separated by isolation grooves 12 provided in the insulating layer below the anode 10. Referring to Figure 1d and Figure 1e , since the upper and lower light-emitting functional layer stack structures of the tandem device each have a capacitance, and there is a difference in capacitance between the upper and lower light-emitting functional layer stack structures, the equivalent internal resistance of the upper and lower light-emitting functional layer stack structures is large at low brightness or low gray levels. The equivalent internal resistance of the upper and lower light-emitting functional layer stack structures at low brightness or low gray levels is close to the micro-short circuit resistance of the charge generation layer B2 and the cathode 11 at the position of the isolation groove 12. This causes the current to pass through both the normal light-emitting path ① of the tandem OLED device and the overlapping path ② of the charge generation layer B2 and the cathode 11 at the position of the isolation groove 12. The higher the proportion of the current shunted by the overlapping path ② at the position of the isolation groove 12, the higher the brightness of the OLED device; since the capacitance of the green OLED device is the largest among the red, green, and blue OLED devices, the overshoot current of the green OLED device is the largest and the brightness is the highest, resulting in a defective green trailing shadow when dragged at low gray levels.

[0109] In view of the problem of greenish smear at low gray levels in OLED displays, it is necessary to add a test circuit for real-time detection of the contact resistance between the charge generation layer and the cathode at the isolation trench position, so as to improve and optimize the greenish smear problem based on the test results of the contact resistance between the charge generation layer and the cathode at the isolation trench position. The improvement and optimization solutions are as follows: reducing the thickness of the cathode film layer so that the cathode film layer can be completely blocked at the isolation trench position, thereby increasing the contact resistance between the charge generation layer and the cathode at the isolation trench position, and further reducing the current in the contact path ② between the charge generation layer and the cathode at the isolation trench position, improving the greenish smear problem at low gray levels, and enhancing the uniformity of the OLED display image quality.

[0110] To solve the above problems in the related art, in a first aspect, referring to Figure 2a and Figure 2b , an embodiment of the present disclosure provides a test circuit board, including: a substrate 1, and a test circuit 2 located on one side of the substrate 1; the test circuit 2 includes a dummy circuit layer 21, a first insulating layer 22, and a dummy light-emitting device layer 23, which are stacked in sequence along a direction away from the substrate 1; the dummy circuit layer 21 and the dummy light-emitting device layer 23 are electrically connected; the dummy light-emitting device layer 23 includes a plurality of dummy light-emitting devices 230, and each dummy light-emitting device 230 includes a first electrode A, a first light-emitting functional layer B, and a second electrode C, which are stacked in sequence along a direction away from the substrate 1; a first isolation trench 220 is formed in the first insulating layer 22 and is configured to isolate the first light-emitting functional layer B and / or the second electrode C of adjacent dummy light-emitting devices 230; the test circuit 2 further includes a first test electrode 24 and a second test electrode 25, which are located outside the orthographic projection of the plurality of dummy light-emitting devices 230 on the substrate 1, the first test electrode 24 is electrically connected to the first light-emitting functional layer B, and the second test electrode 25 is electrically connected to the second electrode C.

[0111] Among them, the first electrode A serves as the anode of the dummy light-emitting device 230, and the second electrode C serves as the cathode of the dummy light-emitting device 230. The dummy circuit layer 21 can adopt any one of pixel driving circuits such as 7T (transistor) 1C (capacitor), 8T1C, 9T1C, or 9T2C. The first insulating layer 22 includes an organic insulating layer and an inorganic insulating layer stacked in sequence along a direction away from the substrate 1, and the notch edge of the organic insulating layer at the position of the first isolation trench 220 is recessed relative to the notch edge of the inorganic insulating layer at the position of the first isolation trench 220, so as to facilitate isolating the first light-emitting functional layer B and / or the second electrode C of adjacent dummy light-emitting devices 230.

[0112] In this embodiment, by providing the test circuit 2, the overlap resistance between the first light-emitting functional layer B and the second electrode C at the position of the first isolation groove 220 can be measured. Thus, the morphology of the first isolation groove 220 can be improved according to the overlap resistance between the first light-emitting functional layer B and the second electrode C at the position of the first isolation groove 220. Furthermore, the greenish smear defect at low gray levels of the display panel having the same structure as the test circuit 2 can be improved, and the uniformity of the display quality of the display panel can be enhanced.

[0113] In some embodiments, referring to Figure 3a , Figure 3b and Figure 3c , the test circuit board includes a first region 101a and a second region 101b, and the second region 101b is located outside the first region 101a; a plurality of dummy light-emitting devices 230 are arranged in an array and are located in the first region 101a; the first region 101a includes a plurality of first sub-regions G, and the first test electrode 24 includes a plurality of first sub-electrodes 240, which are located in the second region 101b, and each first sub-electrode 240 is correspondingly electrically connected to the first light-emitting functional layer B in a first sub-region G; the second test electrode 25 includes a plurality of second sub-electrodes 250, which are located in the second region 101b, and each second sub-electrode 250 is correspondingly electrically connected to the second electrode C in a first sub-region G.

[0114] In some embodiments, the first region 101a includes 12 first sub-regions G; correspondingly, the first test electrode 24 includes 12 first sub-electrodes 240, and the second test electrode 25 includes 12 second sub-electrodes 250. An external test device for testing the overlap resistance between the first light-emitting functional layer B and the second electrode C can simultaneously provide test signals to the 12 first sub-electrodes 240 and the 12 second sub-electrodes 250, and the test signals are such as voltage or current signals.

[0115] In some embodiments, referring to Figure 4a , Figure 4b , Figure 4c , Figure 4d and Figure 4e , on the basis of the solution in Figure 3a , the dummy light-emitting devices 230 include light-emitting devices of multiple colors, and the first sub-electrodes 240 include a plurality of first sub-parts H, and each first sub-part H is correspondingly electrically connected to the first light-emitting functional layer B of a light-emitting device of one color in a first sub-region G.

[0116] In some embodiments, referring to Figure 4a , Figure 4b , Figure 4c , Figure 4d and Figure 4e , the first region 101a includes 4 first sub-regions G; correspondingly, the first test electrode 24 includes 4 first sub-electrodes 240, and the second test electrode 25 includes 4 second sub-electrodes 250.

[0117] In some embodiments, referring to Figure 4a , Figure 4b , Figure 4c , Figure 4d and Figure 4e , the dummy light-emitting device 230 includes a red light-emitting device, a green light-emitting device, and a blue light-emitting device. The red light-emitting device, the green light-emitting device, and the blue light-emitting device are all distributed in each first sub-region G. Each first sub-electrode 240 corresponding to electrically connecting each first sub-region G includes 3 first sub-parts H. One first sub-part H is electrically connected to the first light-emitting functional layer B(R) of the red light-emitting device in the corresponding first sub-region G, another first sub-part H is electrically connected to the first light-emitting functional layer B(G) of the green light-emitting device in the corresponding first sub-region G, and yet another first sub-part H is electrically connected to the first light-emitting functional layer B(B) of the blue light-emitting device in the corresponding first sub-region G. An external test device for testing the contact resistance between the first light-emitting functional layer B and the second electrode C can simultaneously provide test signals to 12 first sub-parts H and 4 second sub-electrodes 250. The test signals are such as voltage or current signals.

[0118] In some embodiments, referring to Figure 5a , the first light-emitting functional layer B includes at least two organic stacked structures B1 and at least one charge generation layer B2. The organic stacked structures B1 and the charge generation layer B2 are stacked, and the charge generation layer B2 is located between any two adjacent organic stacked structures B1; the first test electrode 24 is electrically connected to the charge generation layer B2.

[0119] In some embodiments, referring to Figure 5b , the first light-emitting functional layer B includes one organic stacked structure B1, and the first test electrode 24 is electrically connected to the organic stacked structure B1.

[0120] In some embodiments, the organic stacked structure B1 includes a hole injection layer HIL, a hole transport layer HTL, a light-emitting layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL stacked in sequence in a direction away from the first electrode A.

[0121] In some embodiments, referring to Figure 6a, the dummy circuit layer 21 includes a first conductive layer 211, a second conductive layer 212, a third conductive layer 213, a fourth conductive layer 214, and a fifth conductive layer 215, which are stacked in sequence along the direction away from the substrate 1, and a second insulating layer 210 is provided between any two adjacent ones; the first sub-electrode 240 and the second sub-electrode 250 have the same structure; the first sub-electrode 240 includes a first sub-layer 2401, and the first sub-layer 2401 and the fifth conductive layer 215 are arranged on the same layer; a first opening 222 and a second opening 223 are formed in the first insulating layer 22, and the first sub-electrode 240 is exposed at the first opening 222; the second sub-electrode 250 is exposed at the second opening 223; refer to Figure 3a - Figure 3c and Figure 4a - Figure 4e , the first sub-layer 2401 extends towards the boundary position between the second region 101b and the first region 101a to form a lead 241, and the first light-emitting functional layer B also extends to the second region 101b and at least partially overlaps with the positive projection of the lead 241 on the substrate 1, and the first light-emitting functional layer B and the lead 241 are in electrical contact in the overlapping region of their positive projections.

[0122] Among them, the second sub-electrode 250 also includes the first sub-layer 2401. Refer to Figure 6a , the first sub-electrode 240 is composed only of the first sub-layer 2401 arranged on the same layer as the fifth conductive layer 215, that is, a film layer of the same layer and the same material as the first electrode A is avoided as a sub-layer of the first sub-electrode 240. Since the material of the first electrode A contains silver or platinum, it is possible to prevent silver or platinum generated during the wet etching of the first electrode A from overflowing into the display area, thereby avoiding defects such as dark spots or signal short circuits in the display area.

[0123] In some embodiments, the first conductive layer 211 can be used as a light-shielding layer, such as the first conductive layer 211 is used to shield the channel region of the transistor in the pixel driving circuit. The second conductive layer 212 can be used as the gate layer of the transistor in the pixel driving circuit. The third conductive layer 213 can be used as the source-drain layer of the transistor in the pixel driving circuit. The fourth conductive layer 214 can be used as the first transfer structure layer in the pixel driving circuit. The fifth conductive layer 215 can be used as the second transfer structure layer in the pixel driving circuit.

[0124] In some embodiments, refer to Figure 6b , in Figure 6aOn the basis of this, the first sub-electrode 240 further includes a second sub-layer 2402, and the second sub-electrode 250 also includes a second sub-layer 2402, which is located on the side of the first sub-layer 2401 away from the substrate 1. The second sub-layer 2402 and the first electrode A are arranged in the same layer; the positive projections of the second sub-layer 2402, the first sub-layer 2401, and the first opening 222 on the substrate 1 at least partially overlap, and the second sub-layer 2402 and the first sub-layer 2401 are in electrical contact in the overlapping area of their positive projections; the test circuit board further includes a pixel defining layer 4, which is located on the side of the first electrode A away from the substrate 1. A third opening 40 is formed in the pixel defining layer 4, and the second sub-layer 2402 is exposed at the third opening 40.

[0125] In some embodiments, on the basis of Figure 6a this, the second sub-layer 2402 also extends towards the junction position between the second region 101b and the first region 101a to form a sub-layer of the lead 241. At the position of the lead 241, the positive projections of the second sub-layer 2402 and the first sub-layer 2401 on the substrate 1 coincide.

[0126] In some embodiments, referring to Figure 6c this, on the basis of Figure 6b this, the first sub-electrode 240 further includes a third sub-layer 2403, a fourth sub-layer 2404, a fifth sub-layer 2405, and a sixth sub-layer 2406, which are located between the first sub-layer 2401 and the substrate 1 and are stacked in sequence along the direction away from the substrate 1. The third sub-layer 2403 and the first conductive layer 211 are arranged in the same layer; the fourth sub-layer 2404 and the second conductive layer 212 are arranged in the same layer; the fifth sub-layer 2405 and the third conductive layer 213 are arranged in the same layer; the sixth sub-layer 2406 and the fourth conductive layer 214 are arranged in the same layer; the positive projections of the third sub-layer 2403, the fourth sub-layer 2404, the fifth sub-layer 2405, the sixth sub-layer 2406, and the first sub-layer 2401 on the substrate 1 at least partially overlap, and the second insulating layer 210 is provided with a fourth opening 2100 in the area corresponding to the overlapping of the positive projections of the five layers. The third sub-layer 2403, the fourth sub-layer 2404, the fifth sub-layer 2405, the sixth sub-layer 2406, and the first sub-layer 2401 are in electrical contact with each other at the fourth opening 2100.

[0127] Among them, referring to Figure 6c, the first sub-electrode 240 is formed by sequentially stacking a third sub-layer 2403, a fourth sub-layer 2404, a fifth sub-layer 2405, a sixth sub-layer 2406, a first sub-layer 2401, and a second sub-layer 2402. In this way, after the second insulating layer 210 is etched away at the position of the fourth opening 2100, excessive collapse of the first sub-layer 2401 can be prevented, which affects the accuracy of the test of the first sub-electrode 240. By adding the third sub-layer 2403, the fourth sub-layer 2404, the fifth sub-layer 2405, and the sixth sub-layer 2406 on the side of the first sub-layer 2401 close to the substrate 1, the first sub-layer 2401 in the first sub-electrode 240 can be raised, thereby avoiding the collapse of the first sub-layer 2401.

[0128] In some embodiments, referring to Figure 6d , in Figure 6c , on the basis of this, the test circuit board further includes a touch layer, which is located in the first area 101a and on the side of the test circuit 2 away from the substrate 1. The first sub-electrode 240 further includes a seventh sub-layer 2407, which is located on the side of the second sub-layer 2402 away from the substrate 1 and is arranged on the same layer as the touch layer; a third insulating layer 5 is further arranged between the seventh sub-layer 2407 and the second sub-layer 2402. The positive projections of the seventh sub-layer 2407 and the second sub-layer 2402 on the substrate 1 at least partially overlap. The third insulating layer 5 is provided with a fifth opening 50 in the area corresponding to the overlapping positive projections of the two. The seventh sub-layer 2407 and the second sub-layer 2402 are in electrical contact with each other at the fifth opening 50.

[0129] In some embodiments, referring to Figure 6d , the test circuit board further includes a protective layer 6, which is located on the side of the touch layer away from the substrate 1. The protective layer 6 is provided with a sixth opening 60, and the seventh sub-layer 2407 is exposed at the sixth opening 60. The setting of the sixth opening 60 facilitates the contact between the external test device and the first sub-electrode 240.

[0130] In some embodiments, referring to Figure 7a , along the direction away from the substrate 1, the edge of the positive projection of any adjacent two sub-layers of the first sub-electrode 240 on the substrate 1 that is farther from the substrate 1 falls within the positive projection of the sub-layer that is closer to the substrate 1 on the substrate 1; or, referring to Figure 7b , the edge of the positive projection of any adjacent two sub-layers of the first sub-electrode 240 on the substrate 1 that is closer to the substrate 1 falls within the positive projection of the sub-layer that is farther from the substrate 1 on the substrate 1. With such a setting, the risk of peeling between adjacent two sub-layers in the exposed first sub-electrode 240 can be prevented.

[0131] In some embodiments, multiple first sub-electrodes 240 and multiple second sub-electrodes 250 are arranged along a straight line. The orthographic projections of the first and second sub-electrodes 240 and 250 on substrate 1 include rectangular, circular, or regular polygonal shapes. The side lengths or radial dimensions of the orthographic projections of the first and second sub-electrodes 240 and 250 on substrate 1 range from 120 to 150 μm. The center-to-center spacing between adjacent first sub-electrodes 240 and adjacent second sub-electrodes 250 ranges from 160 to 190 μm. This configuration can meet the testing requirements of external testing equipment for the first and second sub-electrodes 240 and 250.

[0132] In some embodiments, reference Figure 3a 、 Figure 4a 、 Figure 8a and Figure 8b The test circuit board further includes an encapsulation layer 7, which is located on the side of the dummy light-emitting device 230 away from the substrate 1. The orthographic projection of the encapsulation layer 7 on the substrate 1 covers the orthographic projection of the dummy light-emitting device 230 on the substrate 1. The orthographic projections of the encapsulation layer 7 and the lead 241 on the substrate 1 at least partially overlap; the orthographic projections of the encapsulation layer 7 and the first test electrode 24 and the second test electrode 25 on the substrate 1 do not overlap; and further includes a dam 8, the orthographic projection of the encapsulation layer 7 on the substrate 1 surrounds the four edges of the orthographic projection of the encapsulation layer 7 on the substrate 1, and the orthographic projections of the dam 8 and the first test electrode 24 and the second test electrode 25 on the substrate 1 No overlap; the orthographic projections of the dam 8 and the lead 241 on the substrate 1 intersect with each other, and the line width s of the lead 241 at the intersection with the orthographic projection of the dam 8 is greater than 20 μm; the dam 8 includes an organic insulating layer in the second insulating layer 210 (such as the first flat layer PLN1), an organic insulating layer in the first insulating layer 22 (such as the second flat layer PLN2), a pixel defining layer 4 and an organic support layer PS located on the side of the pixel defining layer 4 away from the substrate 1 (used to form a supporting spacer); the areas on both sides of the dam 8 include the inorganic insulating layer in the second insulating layer 210 and the inorganic insulating layer in the first insulating layer 22.

[0133] The line width s of the lead 241 at the intersection with the orthographic projection of the dam 8 is 100 μm. The line width s of the lead 241 at the intersection with the orthographic projection of the dam 8 can prevent the lead 241 from breaking when crossing the dam 8.

[0134] In this embodiment, the encapsulation layer 7 includes inorganic sublayers 71 and organic sublayers 72 alternately stacked in sequence. The provision of the dam 8 can prevent the organic sublayer 72 of the encapsulation layer 7 from overflowing outside the dam 8 .

[0135] The test circuit board provided in this embodiment can directly measure the contact resistance between the first light-emitting functional layer and the second electrode at the position of the first isolation groove by setting a test circuit. Thus, the morphology of the first isolation groove can be improved according to the contact resistance between the first light-emitting functional layer and the second electrode at the position of the first isolation groove. Furthermore, the green smear defect at low gray levels of the display panel having the same structure as the test circuit can be improved, and the uniformity of the image quality of the display panel can be enhanced.

[0136] In a second aspect, an embodiment of the present disclosure further provides a display panel. Referring to Figure 9a and Figure 9b , it has a display area 100 and a non-display area 101. Among them, it includes the test circuit board in the above embodiment, which is located in the non-display area 101.

[0137] In some embodiments, referring to Figure 9a and Figure 9b , the display panel further includes a display circuit 3, which is located on the same side of the substrate 1 as the test circuit 2 in the test circuit board and is located in the display area 100. The display circuit 3 includes a first circuit layer 31, a first insulating layer 22, and a first light-emitting device layer 32, which are stacked in sequence along a direction away from the substrate 1. The first circuit layer 31 and the first light-emitting device layer 32 are electrically connected. The first circuit layer 31 and the dummy circuit layer 21 are arranged on the same layer and have the same structure. The first light-emitting device layer 32 includes a plurality of first light-emitting devices 320. Each first light-emitting device 320 includes a third electrode D, a second light-emitting functional layer E, and a fourth electrode F, which are stacked in sequence along a direction away from the substrate 1. The third electrode D and the first electrode A are arranged on the same layer and have the same structure. The fourth electrode F and the second electrode C are arranged on the same layer and have the same structure. The second light-emitting functional layer E and the first light-emitting functional layer B are arranged on the same layer and have the same structure. The first insulating layer 22 is further provided with a second isolation groove 221, which is configured to isolate the second light-emitting functional layer E and / or the fourth electrode F of adjacent first light-emitting devices 320. The second isolation groove 221 and the first isolation groove 220 have the same structure.

[0138] Among them, the third electrode D serves as the anode of the first light-emitting device 320, and the fourth electrode F serves as the cathode of the first light-emitting device 320. The first circuit layer 31 can adopt any one of pixel driving circuits such as 7T (transistor) 1C (capacitor), 8T1C, 9T1C, or 9T2C. The first circuit layer 31 of the display circuit 3 in the display area 100 and the dummy circuit layer 21 of the test circuit 2 in the non-display area 101 can be prepared simultaneously through the same lithography process; the first insulating layer 22 of the display circuit 3 in the display area 100 and the second isolation groove 221 therein and the first insulating layer 22 of the test circuit 2 in the non-display area 101 and the first isolation groove 220 therein can be prepared simultaneously through the same lithography process; the first light-emitting device layer 32 of the display circuit 3 in the display area 100 and the dummy light-emitting device layer 23 of the test circuit 2 in the non-display area 101 can be prepared simultaneously through the same lithography process.

[0139] By making the structures of the display circuit 3 in the display area 100 and the test circuit 2 in the non-display area 101 exactly the same, the overlap resistance between the second light-emitting functional layer E and the fourth electrode F at the position of the second isolation groove 221 can be indirectly measured through the test circuit 2. Thus, the topography of the second isolation groove 221 can be improved according to the overlap resistance between the second light-emitting functional layer E and the fourth electrode F at the position of the second isolation groove 221, and further, the greenish smear defect at low gray levels of the display panel can be improved, and the uniformity of the image quality of the display panel can be enhanced.

[0140] In some embodiments, the first insulating layer 22 includes an organic insulating layer and an inorganic insulating layer stacked in sequence along the direction away from the substrate 1. The notch edge of the organic insulating layer at the position of the second isolation groove 221 is retracted relative to the notch edge of the inorganic insulating layer at the position of the second isolation groove 221, which is beneficial to isolating the second light-emitting functional layer E and / or the fourth electrode F of adjacent first light-emitting devices 320.

[0141] In some embodiments, the arrangement of the first light-emitting devices 320 in the first light-emitting device layer 32 is exactly the same as the arrangement of the dummy light-emitting devices 230 in the dummy light-emitting device layer 23. The stacked structure of the second light-emitting functional layer E in the first light-emitting device layer 32 and the first light-emitting functional layer B in the dummy light-emitting device layer 23 is exactly the same. The first light-emitting device 320 also includes a red light-emitting device, a green light-emitting device, and a blue light-emitting device.

[0142] In some embodiments, the display panel further includes a touch layer, which is located in the display area 100 and is arranged on the same layer as the touch layer in the non-display area 101. The protective layer in the test circuit board also extends to cover the touch layer in the display area 100.

[0143] In some embodiments, the display panel further includes a packaging layer on a side of the first light-emitting device 320 facing away from the substrate 1. The orthographic projection of the packaging layer on the substrate 1 also covers the entire display area 100, and the orthographic projection of the packaging layer on the substrate 1 covers the orthographic projection of the first light-emitting device 230 on the substrate 1.

[0144] By using the test circuit board in the above embodiments, the display panel provided by the embodiments of the present disclosure can indirectly measure the overlap resistance between the second light-emitting functional layer and the fourth electrode at the position of the second isolation groove. Therefore, the topography of the second isolation groove can be improved according to the overlap resistance between the second light-emitting functional layer and the fourth electrode at the position of the second isolation groove, and further, the greenish smear defect of the display panel at low gray levels can be improved, and the uniformity of the image quality of the display panel can be enhanced.

[0145] In a third aspect, the embodiments of the present disclosure further provide a display device including the display panel in the above embodiments.

[0146] By using the display panel in the above embodiments, the greenish smear defect of the display device at low gray levels can be improved, and the uniformity of the image quality of the display device can be enhanced.

[0147] The display device provided by the embodiments of the present disclosure can be any product or component with a display function, such as an OLED panel, an OLED TV, an OLED billboard, a display, a mobile phone, a navigator, etc.

[0148] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principles of the present disclosure. However, the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also considered within the protection scope of the present disclosure.

Claims

1. A test circuit board, comprising: base, A test circuit is located on one side of the substrate; The test circuit includes a dummy circuit layer, a first insulating layer and a dummy light-emitting device layer, which are stacked in sequence in a direction away from the substrate; the dummy circuit layer and the dummy light-emitting device layer are electrically connected; The dummy light emitting device layer includes a plurality of dummy light emitting devices, The dummy light emitting device comprises a first electrode, a first light emitting functional layer and a second electrode, which are stacked in sequence in a direction away from the substrate; A first isolation groove is formed in the first insulating layer, and is configured to separate the first light-emitting functional layer and / or the second electrode of the adjacent dummy light-emitting device; The test circuit further includes a first test electrode and a second test electrode, which are located outside the orthographic projection of the plurality of dummy light-emitting devices on the substrate. The first test electrode is electrically connected to the first light-emitting functional layer, and the second test electrode is electrically connected to the second electrode.

2. The test circuit board according to claim 1, wherein, comprising a first area and a second area, wherein the second area is located outside the first area; The plurality of dummy light-emitting devices are arranged in an array and located in the first area; The first region includes a plurality of first sub-regions, The first test electrode includes a plurality of first sub-electrodes located in the second area, and each of the first sub-electrodes is electrically connected to a corresponding first light-emitting functional layer in the first sub-area; The second test electrode includes a plurality of second sub-electrodes located in the second area, and each second sub-electrode is electrically connected to a corresponding second electrode in the first sub-area.

3. The test circuit board according to claim 2, wherein, The dummy light emitting devices include light emitting devices of multiple colors. The first sub-electrode includes a plurality of first sub-portions, and each of the first sub-portions is electrically connected to the first light-emitting functional layer of a light-emitting device of one color in the first sub-region.

4. The test circuit board according to claim 1, wherein, The first light-emitting functional layer includes at least two organic stacked structures and at least one charge generation layer, the organic stacked structures and the charge generation layer are stacked, and the charge generation layer is located between any two adjacent organic stacked structures; The first test electrode is electrically connected to the charge generation layer.

5. The test circuit board according to claim 1, wherein, The first light-emitting functional layer includes an organic stacked structure, The first test electrode is electrically connected to the organic stacked structure.

6. The test circuit board according to claim 3, wherein, The dummy circuit layer includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer, which are stacked in sequence in a direction away from the substrate, and a second insulating layer is provided between any two adjacent ones; The first sub-electrode and the second sub-electrode have the same structure; The first sub-electrode includes a first sub-layer, and the first sub-layer and the fifth conductive layer are arranged in the same layer; The first insulating layer is provided with a first opening and a second opening, the first sub-electrode is exposed at the first opening; the second sub-electrode is exposed at the second opening; The first sublayer extends to the junction of the second area and the first area to form a lead, the first light-emitting functional layer also extends to the second area and at least partially overlaps with the orthographic projection of the lead on the substrate, and the first light-emitting functional layer and the lead are electrically contacted in the overlapping area of their orthographic projections.

7. The test circuit board according to claim 6, wherein The first sub-electrode further includes a second sub-layer, which is located on the side of the first sub-layer away from the substrate. The second sub-layer and the first electrode are arranged in the same layer. The second sub-layer, the first sub-layer and the first opening have at least partial overlap in the orthographic projection on the substrate, and the second sub-layer and the first sub-layer are in electrical contact in the overlapping area of their orthographic projections. The test circuit board further includes a pixel defining layer, which is located on the side of the first electrode away from the substrate. A third opening is formed in the pixel defining layer, and the second sub-layer is exposed at the third opening.

8. The test circuit board according to claim 7, wherein, The first sub-electrode further includes a third sub-layer, a fourth sub-layer, a fifth sub-layer and a sixth sub-layer, which are located between the first sub-layer and the substrate and are stacked in sequence along the direction away from the substrate. The third sub-layer and the first conductive layer are arranged in the same layer. The fourth sub-layer and the second conductive layer are arranged in the same layer. The fifth sub-layer and the third conductive layer are arranged in the same layer. The sixth sub-layer and the fourth conductive layer are arranged in the same layer. The third sub-layer, the fourth sub-layer, the fifth sub-layer, the sixth sub-layer and the first sub-layer have at least partial overlap in the orthographic projection on the substrate. The second insulating layer is provided with a fourth opening in the area corresponding to the overlapping orthographic projections of the five layers, and the third sub-layer, the fourth sub-layer, the fifth sub-layer, the sixth sub-layer and the first sub-layer are in electrical contact with each other at the fourth opening.

9. The test circuit board according to claim 8, wherein, It further includes a touch layer, which is located in the first area and on the side of the test circuit away from the substrate. The first sub-electrode further includes a seventh sub-layer, which is located on the side of the second sub-layer away from the substrate and is arranged in the same layer as the touch layer. A third insulating layer is further provided between the seventh sub-layer and the second sub-layer. The seventh sub-layer and the second sub-layer have at least partial overlap in the orthographic projection on the substrate. The third insulating layer is provided with a fifth opening in the area corresponding to the overlapping orthographic projections of the two layers, and the seventh sub-layer and the second sub-layer are in electrical contact with each other at the fifth opening.

10. The test circuit board according to claim 9, wherein, It further includes a protective layer, which is located on the side of the touch layer away from the substrate. A sixth opening is formed in the protective layer, and the seventh sub-layer is exposed at the sixth opening.

11. The test circuit board according to claim 9, wherein, Along the direction away from the substrate, the edge of the orthographic projection of any adjacent two sub-layers of the first sub-electrode on the substrate that is farther from the substrate falls within the orthographic projection of the sub-layer that is closer to the substrate on the substrate. Alternatively, the edge of the orthographic projection of any adjacent two sub-layers of the first sub-electrode on the substrate that is closer to the substrate falls within the orthographic projection of the sub-layer that is farther from the substrate on the substrate.

12. The test circuit board according to claim 2, wherein The plurality of first sub-electrodes are arranged in a straight line. The plurality of second sub-electrodes are arranged in a straight line. The shapes of the orthographic projections of the first sub-electrode and the second sub-electrode on the substrate include rectangle, circle or regular polygon. The side length dimension or radial dimension range of the orthographic projections of the first sub-electrode and the second sub-electrode on the substrate is 120-150 μm. The center spacing range of adjacent first sub-electrodes is 160-190 μm. The center distance between adjacent second sub-electrodes ranges from 160 to 190 μm.

13. The test circuit board according to claim 6, wherein, It also includes an encapsulation layer, located on a side of the dummy light-emitting device facing away from the substrate, wherein the orthographic projection of the encapsulation layer on the substrate covers the orthographic projection of the dummy light-emitting device on the substrate, and the orthographic projections of the encapsulation layer and the leads on the substrate at least partially overlap; The orthographic projections of the encapsulation layer, the first test electrode, and the second test electrode on the substrate do not overlap; It also includes a dam, the orthographic projection of which on the substrate surrounds the edges of the orthographic projection of the encapsulation layer on the substrate, and the orthographic projection of the dam and the first test electrode and the second test electrode on the substrate do not overlap; The orthographic projections of the dam and the lead on the substrate intersect each other, The line width of the lead at the intersection with the orthographic projection of the dam is greater than 20 μm; The dam includes the organic insulating layer in the second insulating layer, the organic insulating layer in the first insulating layer and the pixel defining layer; The regions on both sides of the dam include the inorganic insulating layer in the second insulating layer and the inorganic insulating layer in the first insulating layer.

14. A display panel having a display area and a non-display area, wherein, The test circuit board comprises the test circuit board according to any one of claims 1 to 13, located in the non-display area.

15. The display panel according to claim 14, wherein, Also included is a display circuit, which is located on the same side of the substrate as the test circuit in the test circuit board and is located in the display area; The display circuit includes a first circuit layer, a first insulating layer and a first light-emitting device layer, which are stacked in sequence in a direction away from the substrate; the first circuit layer and the first light-emitting device layer are electrically connected; The first circuit layer and the dummy circuit layer are arranged on the same layer and have the same structure; The first light emitting device layer includes a plurality of first light emitting devices, The first light emitting device includes a third electrode, a second light emitting functional layer and a fourth electrode, which are stacked in sequence in a direction away from the substrate; The third electrode and the first electrode are provided in the same layer and have the same structure; The fourth electrode and the second electrode are provided in the same layer and have the same structure; The second light-emitting functional layer and the first light-emitting functional layer are provided on the same layer and have the same structure; A second isolation trench is further provided in the first insulating layer, configured to isolate the second light-emitting functional layer and / or the fourth electrode of the adjacent first light-emitting device; The second isolation trench has the same structure as the first isolation trench.

16. A display device, wherein, The display panel comprises any one of claims 14-15.

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