Thin film transistor, display substrate and display device

Abstract

The embodiment of the invention provides a thin film transistor, a display substrate and a display device. The thin film transistor includes: a substrate; the first insulating layer is located on one side of the substrate, and the first insulating layer is provided with a first concave part; the first active layer is located on the side, away from the substrate, of the first insulating layer, and the first active layer comprises a first part and a second part located on one side of the first part; the second part is positioned in the first concave part; the first metal layer and the first active layer are located on the same side of the substrate, the first metal layer comprises a first metal pattern, and the orthographic projection of the first part on the substrate and the orthographic projection of the first metal pattern on the substrate have an overlapping area.

Description

Thin film transistor, display substrate, and display device Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a thin film transistor, a display substrate, and a display device. Background Art

[0002] With the rise of the metaverse concept, virtual reality (VR) headsets are attracting significant attention as key devices. Currently, the most effective display products on the market are typically micro organic light-emitting display (OLED) devices with a PPI of 3000+. However, Micro OLED products are expensive and difficult to manufacture, making them difficult to popularize. Glass-based ultra-high-resolution (Pixels Per Inch, PPI) technology has the potential to produce products with PPIs of 2000-3000 at a cost of only one-tenth that of silicon-based OLED products, making it very attractive. Therefore, the development of ultra-high-PPI glass-based VR headsets has enormous market potential.

[0003] Summary of the Invention

[0004] The present disclosure provides a thin film transistor, a display substrate, and a display device. The thin film transistor includes:

[0005] substrate;

[0006] A first insulating layer is located on one side of the substrate, and the first insulating layer has a first recess;

[0007] a first active layer, located on a side of the first insulating layer facing away from the substrate, the first active layer comprising: a first portion, and a second portion located on one side of the first portion; the second portion is located in the first recess;

[0008] The first metal layer and the first active layer are located on the same side of the substrate. The first metal layer includes a first metal pattern. The orthographic projection of the first portion on the substrate has an overlapping area with the orthographic projection of the first metal pattern on the substrate.

[0009] In a possible implementation, the thin film transistor further includes: a second insulating layer located on a side of the first active layer facing away from the first insulating layer, and a first electrode located on a side of the second insulating layer facing away from the first active layer;

[0010] The second insulating layer has a first via hole, and the first electrode is electrically connected to the second portion through the first via hole.

[0011] In a possible implementation manner, the first active layer further includes: a first connecting portion located between the first portion and the second portion, wherein the first connecting portion covers a portion of a sidewall of the first recess;

[0012] The second insulating layer includes a first filling portion, an orthographic projection of the first filling portion on the substrate and an orthographic projection of the first recess on the substrate have an overlapping area, and the first filling portion covers the first connecting portion.

[0013] In a possible implementation manner, the first insulating layer further includes: a second recess;

[0014] The first active layer further includes: a third portion located on the other side of the first portion; at least a portion of the third portion is located in the second concave portion.

[0015] In a possible implementation manner, the first active layer further includes: a second connecting portion located between the first portion and the third portion, wherein the second connecting portion covers a portion of a sidewall of the second recess;

[0016] The second insulating layer includes a second filling portion, an orthographic projection of the second filling portion on the substrate and an orthographic projection of the second recess on the substrate have an overlapping area, and the second filling portion covers the second connecting portion.

[0017] In a possible implementation manner, the first active layer further includes: a fourth portion located between the first portion and the first connecting portion, and a fifth portion located between the first portion and the second connecting portion;

[0018] The orthographic projection of the fourth portion on the substrate does not overlap with the orthographic projection of the first metal pattern on the substrate, and the orthographic projection of the fifth portion on the substrate does not overlap with the orthographic projection of the first metal pattern on the substrate.

[0019] In a possible implementation manner, the first insulating layer further includes: a second recess;

[0020] At least a portion of the first portion is located in the second recess.

[0021] In a possible implementation, the thin film transistor further includes: a second metal layer located between the first insulating layer and the substrate; the second recess is a second via hole penetrating the first insulating layer;

[0022] The second metal layer includes a second metal pattern, at least a portion of the second metal pattern is located in the second via hole, and a portion of the third portion located in the second via hole is electrically connected to the second metal pattern.

[0023] In a possible implementation manner, the second via hole includes: a first sub-hole portion and a second sub-hole portion;

[0024] The orthographic projection of the first sub-hole portion on the substrate overlaps with the orthographic projection of the second metal pattern on the substrate, and the orthographic projection of the second sub-hole portion on the substrate is located on a side of the first sub-hole portion facing the first portion.

[0025] In a possible implementation manner, the second via hole includes: a first sub-hole portion and a second sub-hole portion;

[0026] The orthographic projection of the first sub-hole portion on the substrate overlaps with the orthographic projection of the second metal pattern on the substrate, and the orthographic projection of the second sub-hole portion on the substrate is located on a side of the orthographic projection of the first sub-hole portion on the substrate away from the orthographic projection of the first portion on the substrate.

[0027] In a possible implementation, the thin film transistor further includes: a second metal layer located between the first insulating layer and the substrate;

[0028] The second metal layer includes: a second metal pattern; the first active layer further includes: a third portion located on the other side of the first portion;

[0029] The first metal layer further includes: a first switching electrode; and the third portion is electrically connected to the second metal pattern through the first switching electrode.

[0030] In a possible implementation manner, an orthographic projection of the second metal pattern on the substrate at least partially overlaps with an orthographic projection of the first metal pattern on the substrate.

[0031] In a possible implementation, the thin film transistor further includes: a second metal layer located between the first insulating layer and the substrate, and a third metal layer located between the second metal layer and the substrate;

[0032] The first active layer further includes: a third portion located on the other side of the first portion;

[0033] The second metal layer includes a second metal pattern; the third metal layer includes a second switching electrode; and the third portion is electrically connected to the second metal pattern via the second switching electrode.

[0034] In a possible implementation manner, at least a portion of the orthographic projection of the second metal pattern on the substrate is located on a side of the orthographic projection of the second switching electrode on the substrate away from the first portion.

[0035] In a possible implementation manner, at least a portion of the orthographic projection of the second metal pattern on the substrate is located on a side of the orthographic projection of the second switching electrode on the substrate close to the first portion.

[0036] In a possible implementation, the first insulating layer further includes: a second recess; the thin film transistor further includes: a second metal layer located between the first insulating layer and the substrate; the second recess is a second via hole penetrating the first insulating layer;

[0037] The second metal layer includes: a second metal pattern, at least a portion of the second metal pattern is located in the second via hole;

[0038] At least a portion of the first portion is located in the second via hole, and a portion of the first portion located in the second via hole is electrically connected to the second metal pattern.

[0039] In a possible implementation, the second insulating layer includes: a first sub-insulating layer, and a second sub-insulating layer located on a side of the first sub-insulating layer away from the first active layer;

[0040] The first metal layer is located on a side of the first active layer facing away from the substrate.

[0041] In a possible implementation manner, the orthographic projection of the first sub-insulating layer on the substrate covers the orthographic projection of the first portion on the substrate; and the first sub-insulating layer includes the first filling portion.

[0042] In one possible embodiment, the orthographic projection of the first sub-insulating layer on the substrate covers at least part of the orthographic projection of the first part on the substrate, and the orthographic projection of the first sub-insulating layer on the substrate does not overlap with the orthographic projection of the second part on the substrate, and does not overlap with the orthographic projection of the third part on the substrate; the second sub-insulating layer includes the first filling part.

[0043] In a possible implementation, the first insulating layer includes: a first buffer layer; and a depth of the first recess in a direction perpendicular to the substrate is the same as a thickness of the first buffer layer in a direction perpendicular to the substrate.

[0044] In a possible implementation manner, a depth e1 of the first via hole in a direction perpendicular to the substrate satisfies the following relationship:

[0045] e2<e1≤e2+e3, e2 represents the thickness of the second insulating layer in the direction of the substrate, and e3 represents the thickness of the first edge layer in the direction of the substrate.

[0046] An embodiment of the present disclosure further provides a display substrate having a display area and a non-display area located outside the display area, wherein the display area includes: a first signal line, a second signal line, and at least one thin film transistor provided in the embodiment of the present disclosure.

[0047] In a possible implementation, the display substrate further includes: a fourth insulating layer located on a side of the second insulating layer facing away from the first active layer, and a pixel electrode located on a side of the fourth insulating layer facing away from the second insulating layer;

[0048] The fourth insulating layer has a third via hole, and the pixel electrode is electrically connected to the first electrode through the third via hole.

[0049] In a possible implementation manner, the third via hole is located at the center of the orthographic projection of the substrate and on a side of the center of the orthographic projection of the substrate of the first via hole away from the first portion;

[0050] The display substrate further includes: a bridge electrode located between the third insulating layer and the pixel electrode; the first electrode is electrically connected to the bridge electrode through the third via hole, and the bridge electrode is electrically connected to the pixel electrode.

[0051] In a possible implementation manner, the third via hole is located at a center of an orthographic projection of the substrate, and coincides with a center of an orthographic projection of the first via hole on the substrate;

[0052] The first electrode is electrically connected to the pixel electrode through the first via hole and the third via hole.

[0053] In a possible implementation manner, the first concave portion overlaps with the orthographic projection of the first via hole, and the overlapping portion is located on a side of the second portion away from the first signal line, and the distance from the first signal line is greater than 0.75 μm.

[0054] In one possible embodiment, the display substrate further includes a gate driving circuit located in the non-display area; the gate driving circuit board includes: a second active layer, a driving gate located on a side of the second active layer facing away from the substrate, and a driving source and drain located on a side of the driving gate facing away from the second active layer.

[0055] In a possible implementation manner, the driving source and drain are located in the second metal layer.

[0056] In a possible implementation manner, the driving gate is located in the third metal layer.

[0057] In a possible implementation, the driving source and drain are located in the first metal layer; and the driving gate is located in the second metal layer.

[0058] An embodiment of the present disclosure further provides a display device, which includes the display substrate provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] FIG1 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the present disclosure;

[0060] FIG2A is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure;

[0061] FIG2B is a schematic top view of a sub-pixel of a display substrate provided by an embodiment of the present disclosure;

[0062] FIG2C is a schematic diagram of the conductorization of the first active layer of the display substrate provided by an embodiment of the present disclosure;

[0063] FIG2D is a schematic diagram of a display substrate provided by an embodiment of the present disclosure when a first via hole is formed by etching;

[0064] FIG2E is a second schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure;

[0065] FIG2F is a third schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure;

[0066] FIG2G is a schematic top view of a display substrate according to an embodiment of the present disclosure;

[0067] FIG3A is a fourth schematic cross-sectional view of a display substrate provided by an embodiment of the present disclosure;

[0068] FIG3B is a second schematic top view of a sub-pixel of a display substrate provided by an embodiment of the present disclosure;

[0069] FIG4 is a fifth schematic cross-sectional view of a display substrate provided in an embodiment of the present disclosure;

[0070] FIG5 is a sixth schematic cross-sectional view of a display substrate provided by an embodiment of the present disclosure;

[0071] FIG6 is a seventh cross-sectional schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0072] FIG7A is an eighth schematic cross-sectional view of a display substrate provided by an embodiment of the present disclosure;

[0073] FIG7B is a schematic diagram of an embodiment of the present disclosure without providing a first recess;

[0074] FIG8 is a ninth cross-sectional view of a display substrate according to an embodiment of the present disclosure;

[0075] FIG9 is a tenth schematic cross-sectional view of a display substrate provided by an embodiment of the present disclosure;

[0076] FIG10A is an eleventh cross-sectional view of a display substrate provided by an embodiment of the present disclosure;

[0077] FIG10B is a schematic top view of a sub-pixel corresponding to FIG10A ;

[0078] FIG11 is a twelfth cross-sectional view of a display substrate provided by an embodiment of the present disclosure;

[0079] FIG12A is a schematic diagram of forming a second active layer on a display substrate provided by an embodiment of the present disclosure;

[0080] FIG12B is a schematic diagram of forming a driving gate on a display substrate according to an embodiment of the present disclosure;

[0081] FIG12C is a schematic diagram of forming a first insulating layer on a display substrate according to an embodiment of the present disclosure;

[0082] FIG12D is a schematic diagram of etching the first insulating layer on the display substrate according to an embodiment of the present disclosure;

[0083] FIG12E is a schematic top view corresponding to FIG12D ;

[0084] FIG12F is a schematic diagram of forming a first metal pattern on a display substrate according to an embodiment of the present disclosure;

[0085] FIG12G is a schematic top view corresponding to FIG12F;

[0086] FIG12H is a schematic diagram of forming a first electrode on a display substrate according to an embodiment of the present disclosure;

[0087] FIG12I is a schematic diagram of forming spacers on a display substrate according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0088] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other in any way.

[0089] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0090] In this specification, ordinal numbers such as "first", "second", and "third" are provided to avoid confusion among constituent elements, rather than to limit the quantity. The "plurality" in this disclosure may include two or more.

[0091] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0092] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0093] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with one or more functions.

[0094] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode (gate), a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0095] In this specification, in order to distinguish the two electrodes of a transistor other than the gate electrode, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode. The first electrode can be a source electrode or a drain electrode, and the second electrode can be a drain electrode or a source electrode. In addition, the gate electrode of a transistor can be referred to as a control electrode. In cases where transistors with opposite polarity are used or where the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged.

[0096] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus includes a state where the angle is greater than 85° and less than 95°.

[0097] In this specification, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0098] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0099] In this specification, "approximately" and "substantially" are used without strict limits and allow for process and measurement errors. In this specification, "substantially the same" may refer to values ​​that differ by less than 10%.

[0100] The current best option for ultra-high PPI is liquid crystal display (LCD) technology, because in the LCD display structure, the pixel area circuit has only one switching transistor (Thin Film Transistor, TFT), which is very conducive to achieving high PPI. However, the transmittance of LCD is relatively low, and it is necessary to develop a backplane process solution with a high aperture ratio. Especially when the PPI reaches above 2000, various line widths, line spacings and via sizes reach the limit capabilities of display manufacturing equipment, and the area of ​​the opening area is sharply compressed. This situation will greatly affect the performance of the thin film transistor, for example, it will cause the channel of the thin film transistor to be reduced and the threshold voltage to be negatively biased.

[0101] In view of this, an embodiment of the present disclosure provides a thin film transistor, as shown in FIG1 , comprising:

[0102] Substrate 1;

[0103] A first insulating layer 2 is located on one side of the substrate 1, and the first insulating layer 2 has a first recess 21;

[0104] The first active layer 3 is located on the side of the first insulating layer 2 facing away from the substrate 1. The first active layer 3 includes a first portion 31 and a second portion 32 located on one side of the first portion 31. The second portion 32 is located in the first recess 21.

[0105] The first metal layer 4 is located on the same side of the substrate 1 as the first active layer 3. The first metal layer 4 includes a first metal pattern 41. The orthographic projection of the first portion 31 on the substrate 1 overlaps with the orthographic projection of the first metal pattern 41 on the substrate 1. Specifically, the area of ​​the first active layer 3 that overlaps with the orthographic projection of the first metal pattern 41 on the substrate 1 can be defined as the first portion 31. Specifically, the orthographic projection of the second portion 32 on the substrate 1 can not overlap with the orthographic projection of the first metal pattern 41 on the substrate 1.

[0106] In the embodiment of the present disclosure, the first insulating layer 2 has a first recess 21, and the second portion 32 of the first active layer 3 is located in the first recess 21, so that the first portion 31 and the second portion 32 of the first active layer 3 can form a bent structure in a direction perpendicular to the substrate 1, so that the first portion 31 and the second portion 32 are layered, and a lateral climbing area is formed between the two. When the second portion 32 is conductorized through a conductorization process, the degree of diffusion of the conductorized ions to the first portion 31 can be reduced, thereby improving the problem that the conductorization process reduces the channel length due to ion diffusion, improving the characteristics of short-channel devices, and further improving the current problem that the performance of thin-film transistors is greatly affected by the increase in resolution and transmittance, resulting in a reduction in the channel of the thin-film transistor and a negative bias in the threshold voltage.

[0107] In one possible embodiment, the first recess 21 may be a recess from the surface of the first insulating layer 2 facing away from the substrate 1 toward the side of the substrate 1; in one possible embodiment, the depth of the recess may be less than the thickness of the first insulating layer 2 in a direction perpendicular to the substrate 1; in another possible embodiment, the depth of the recess may be equal to the thickness of the first insulating layer 2 in a direction perpendicular to the substrate 1, that is, the first recess 21 may be a via hole passing through the first insulating layer 2.

[0108] In one possible embodiment, the first metal layer 4 may be a gate metal layer, the first metal pattern 41 may be a gate, and the first portion 31 overlapping with the projection of the first metal pattern 41 may be a channel region; in one possible embodiment, the second portion 32 may be a drain region of a thin film transistor; in another possible embodiment, the second portion 32 may also be a source region of a thin film transistor.

[0109] In one possible implementation, the thin film transistor provided in the embodiment of the present disclosure may be a thin film transistor in a display panel. In another possible implementation, the thin film transistor provided in the embodiment of the present disclosure may also be a thin film transistor in a non-display panel, for example, a thin film transistor in a photosensitive structure, for example, a thin film transistor in a light detection component, or a thin film transistor in a photovoltaic component.

[0110] In a possible embodiment, referring to FIG. 2A and FIG. 2B , the display panel may include a display area AA and a non-display area BB located outside the display area AA. The thin film transistor may be a thin film transistor located in the display area AA, specifically a thin film transistor in a pixel circuit within the display area AA.

[0111] In a possible embodiment, referring to Figures 2A and 2B, the thin film transistor further includes: a second insulating layer 5 located on the side of the first active layer 3 away from the first insulating layer 2, and a first electrode 6 located on the side of the second insulating layer 5 away from the first active layer 3; the second insulating layer 5 has a first via hole K1, and the first electrode 6 is electrically connected to the second portion 32 through the first via hole K1.

[0112] In a possible implementation, as shown in FIG. 2A , the second portion 32 may only cover a portion of the first recess 21 , and the first electrode 6 may partially contact the second portion 32 and partially contact the bottom of the first recess 21 .

[0113] In a possible implementation, as shown in FIG. 2E , the second portion 32 may also cover the entire first recess 21 , and the first electrode 6 is in contact with the surface of the second portion 32 facing away from the substrate 1 .

[0114] In a possible embodiment, as shown in Figures 2A and 2B, the orthographic projection of the first via K1 on the substrate 1 needs to overlap with the orthographic projection of the first recess 21 on the substrate 1, and the overlapping area is not less than 25% of the orthographic projection area of ​​the first recess 21, so as to ensure the lap resistance.

[0115] In a possible implementation, as shown in FIG. 2A and FIG. 2B , the depth e1 of the first via hole in a direction perpendicular to the substrate satisfies the following relationship:

[0116] e2<e1≤e2+e3, where e2 represents the thickness of the second insulating layer 5 in the direction of the substrate, and e3 represents the thickness of the first insulating layer 2 in the direction of the substrate 1. That is, the first via K1 simultaneously etches the second sub-insulating layer 52, the first sub-insulating layer 51, and the first insulating layer 2. The orthographic projection area of ​​the first via K1 on the substrate 1 is larger than the orthographic projection area of ​​the first recess 21 on the substrate 1. However, it is necessary to ensure that the etching depth of the first via K1 is greater than the sum of the thicknesses of the second sub-insulating layer 52 and the first sub-insulating layer 51, and less than or equal to the sum of the thicknesses of the second sub-insulating layer 52, the first sub-insulating layer 51, and the first insulating layer 2, to avoid the problem of the first electrode 6 climbing up and breaking due to the formation of a step difference due to over-etching the third insulating layer 103.

[0117] In one possible embodiment, the first electrode 6 may be a drain electrode of a thin film transistor. In one possible embodiment, the material of the first electrode 6 may be a metal or a transparent metal oxide. The material of the first electrode 6 may include: indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), or similar conductive oxides.

[0118] In a possible embodiment, referring to Figures 2A and 2B, the first active layer 3 also includes: a first connecting portion 36 located between the first portion 31 and the second portion 32, the first connecting portion 36 covering part of the side wall of the first recess 21, specifically, the first connecting portion 36 covers the side wall of the first recess 21 facing the first portion 31; the second insulating layer 5 includes a first filling portion 501, the orthographic projection of the first filling portion 501 on the substrate 1 has an overlapping area with the orthographic projection of the first recess 21 on the substrate 1, and the first filling portion 501 covers the first connecting portion 36.

[0119] In the embodiment of the present disclosure, the first active layer 3 also includes a first connecting portion 36 covering a portion of the side wall of the first recess 21, and a first filling portion 501 covering the first connecting portion 36, wherein the first connecting portion 36 can constitute a lateral climbing area between the first portion 31 and the second portion 32. When the second portion 32 is conductorized through a conductorization process (as shown in FIG2C , where the thick arrow represents conductorization ion injection), the first connecting portion 36 can reduce the diffusion of conductorized ions into the first portion 31, improve the problem that the conductorization process will reduce the channel length, and enhance the characteristics of the short channel device; the first filling portion 501 covers the first connecting portion 36. When etching to form the first via K1, the first filling portion 501 can block the diffusion of dry etching by-products (as shown in FIG2D , the black balls represent dry etching products), which can further enhance the characteristics of the short channel device.

[0120] In a possible embodiment, in combination with FIG1 , FIG2A or FIG2B , the first insulating layer 2 further includes: a second recess 22 ; the first active layer 3 further includes: a third portion 33 located on the other side of the first portion 31 ; at least a portion of the third portion 33 is located in the second recess 22 .

[0121] In one possible embodiment, the second recess 22 may be recessed from the surface of the first insulating layer 2 facing away from the substrate 1 toward the side of the substrate 1; in one possible embodiment, the depth of the recess of the second recess 22 may be less than the thickness of the first insulating layer 2 in a direction perpendicular to the substrate 1; in another possible embodiment, the depth of the recess of the second recess 22 may be equal to the thickness of the first insulating layer 2 in a direction perpendicular to the substrate 1, that is, the second recess 22 may also be a via hole passing through the first insulating layer 2.

[0122] In one possible embodiment, the depth of the second recess 22 may be the same as the depth of the first recess 21, for example, both may be the same as the thickness of the first insulating layer 2 in a direction perpendicular to the substrate 1; in another possible embodiment, the depth of the second recess 22 may also be smaller than the depth of the first recess 21.

[0123] In one possible embodiment, when the second portion 32 is a drain region of a thin film transistor, the third portion 33 may be a source region of the thin film transistor; in another possible embodiment, the second portion 32 is a source region of a thin film transistor, and the third portion 33 may be a drain region of the thin film transistor.

[0124] In a possible embodiment, in combination with Figure 1, Figure 2A or Figure 2B, the first active layer 3 also includes: a second connecting portion 37 located between the first portion 31 and the third portion 33, the second connecting portion 37 covering part of the side wall of the second recess 22, specifically, the second connecting portion 37 covers the side wall of the second recess 22 facing the first portion 31; the second insulating layer 5 includes a second filling portion 502, the orthographic projection of the second filling portion 502 on the substrate 1 has an overlapping area with the orthographic projection of the second recess 22 on the substrate 1, and the second filling portion 502 covers the second connecting portion 37.

[0125] In a possible embodiment, in combination with Figure 1, Figure 2A or Figure 2B, the first active layer 3 further includes: a fourth portion 34 located between the first portion 31 and the first connecting portion 36, and a fifth portion 35 located between the first portion 31 and the second connecting portion 37; the orthographic projection of the fourth portion 34 on the substrate 1 does not overlap with the orthographic projection of the first metal pattern 41 on the substrate 1, and the orthographic projection of the fifth portion 35 on the substrate 1 does not overlap with the orthographic projection of the first metal pattern 41 on the substrate.

[0126] In a possible implementation, in the first active layer 3, the first part 31 can be a channel region, the second part 32 and the third part 33 can be conducting regions, and the fourth part 34, the fifth part 35, the first connection part 36, and the second connection part 37 can be transition regions and can be non-conducting regions; the fourth part 34, the fifth part 35, the first connection part 36, and the second connection part 37 can all be structures that block ion diffusion during the conducting process. In the embodiments of the present disclosure, the arrangement of the first connection part 36 and the second connection part 37 increases the length of the transition region compared to the conventional technology, reducing the impact of the conducting process on the channel.

[0127] In a possible implementation, as shown in FIG. 12G, the width b1 of the non-conducting region in the second direction Y and the width b2 of the first signal line 40 in the second direction Y satisfy: b2×30% < b1 < b2×75%, where b1 = a1 + a2. In this way, while improving the short-channel effect, the aperture ratio of the display panel can be increased.

[0128] In a possible implementation, as shown in FIGS. 1, 2A or 2B, the thin-film transistor further includes: a second metal layer 7 located between the first insulating layer 2 and the substrate 1; the second recess 22 is a second via hole K2 penetrating the first insulating layer 2; the second metal layer 7 includes: a second metal pattern 71, at least part of the second metal pattern 71 is located in the second via hole K2, and the part of the third part 33 located in the second via hole K2 is electrically connected to the second metal pattern 71. In the embodiments of the present disclosure, the second metal pattern 71 is located between the first insulating layer 2 and the substrate 1, and the second metal pattern 71 is electrically connected to the third part 33. Compared with the conventional technology where the number of dielectric layers between the second metal pattern 71 and the first electrode 6 is less, the embodiments of the present disclosure can increase the number of dielectric layers between the second metal pattern 71 and the first electrode 6, increase the distance between the second metal pattern 71 and the first electrode 6 in the direction perpendicular to the substrate 1, thereby reducing the parasitic capacitance between the second metal pattern 71 and the first electrode 6, and further reducing the signal crosstalk problem.

[0129] Compared with the conventional thin-film transistor, in the embodiments of the present disclosure, the second metal pattern 71 electrically connected to the third part 33 is placed below, and the two are connected through the second via hole K2; moreover, when forming the second via hole K2 connecting the two, the first recess 21 can be formed simultaneously in one patterning process through the same mask plate, realizing the formation of the second via hole K2 connecting the third part 33 and the second metal pattern 71 through one patterning process, and at the same time forming the first recess 21 that causes the second part 32 to sink, improving the short-channel problem and enhancing the characteristics of short-channel devices without adding new patterning processes.

[0130] In one possible implementation, the second metal pattern 71 may be a source of a thin film transistor. In one possible implementation, the material of the second metal pattern 71 may be metal.

[0131] In one possible embodiment, in combination with Figure 2B, the display panel may include a first signal line 40 (for example, a gate line) extending along a first direction X, and a second signal line 70 (for example, a data line) extending along a second direction Y; a portion of the first signal line 40 may serve as a first metal pattern 41; a portion of the second signal line 70 may serve as a second metal pattern 71.

[0132] In one possible embodiment, as shown in FIG1 or FIG2A , the second via K2 includes a first sub-hole portion K21 and a second sub-hole portion K22; the orthographic projection of the first sub-hole portion K21 on the substrate 1 overlaps the orthographic projection of the second metal pattern 71 on the substrate 1, and the orthographic projection of the second sub-hole portion K22 on the substrate 1 is located on the side of the orthographic projection of the first sub-hole portion K21 on the substrate 1 that faces the orthographic projection of the first portion 31 on the substrate 1. In the disclosed embodiment, the second via K2 partially overlaps the second metal pattern 71 and partially lies outside the second metal pattern 71, i.e., a semi-overlap design is employed. This reduces the size of the second via K2, thereby increasing the transmittance of the display panel.

[0133] In a possible embodiment, as shown in FIG2F , the second vias K2 may be entirely located in the area where the second metal pattern 71 is located, and the third portion 33 may be entirely in contact with the second metal pattern 71 , that is, the third portion 33 and the second metal pattern 71 may be connected in a fully overlapping manner.

[0134] As shown in Figures 2A and 2B, in a high-resolution display panel, the data line 70 reused as the second metal pattern 71 is relatively thin, and the size of the second via K2 in the first direction X, but when the third part 33 is formed in the second via K2, due to the existence of the automatic compensation mechanism, the third part 33 can be compensated into the shape of the second via K2 through the automatic compensation mechanism, ensuring that the third part 33 and the second metal pattern 71 have a larger overlap area, reducing the overlap resistance, and can accept larger process fluctuations.

[0135] In one possible embodiment, as shown in Figures 3A and 3B, the second via K2 includes a first sub-hole portion K21 and a second sub-hole portion K22; the orthographic projection of the first sub-hole portion K21 on the substrate 1 overlaps with the orthographic projection of the second metal pattern 71 on the substrate 1, and the orthographic projection of the second sub-hole portion K22 on the substrate 1 is located on a side of the orthographic projection of the first sub-hole portion K21 on the substrate 1 that is away from the orthographic projection of the first portion 31 on the substrate 1. In the disclosed embodiment, the overlapping position of the second via K2 and the second metal pattern 71 can be adjusted, that is, the side of the third portion 33 that is closer to the first portion 31 can overlap the second metal pattern 71, changing the contact position and contact area of ​​the overlap, thereby increasing the oblique length of the channel.

[0136] Specifically, the first active layer 3 and the second metal pattern 71 can be electrically connected in a variety of ways. For example, they can be electrically connected through the first transfer electrode of the first metal layer 4. Specifically, as shown in FIG4 , the thin film transistor further includes: a second metal layer 7 located between the first insulating layer 2 and the substrate 1;

[0137] The second metal layer 7 includes: a second metal pattern 71; the first active layer 3 also includes: a third portion 33 located on the other side of the first portion 31;

[0138] The first metal layer 4 further includes a first connecting electrode 42 ; the third portion 33 is electrically connected to the second metal pattern 71 via the first connecting electrode 42 .

[0139] In the embodiment of the present disclosure, the first metal layer 4 also includes: a first transfer electrode 42; the first transfer electrode 42 is electrically connected to the second metal pattern 71 through the first transfer electrode 42, which can avoid the third part 33 and the second metal pattern 71 from forming a lower overlap. Due to the use of an ion implantation scheme, the conductive layer is usually concentrated on the surface layer of the third part 33, and the contact resistance of the part where the third part 33 and the second metal pattern 71 overlap is large, which can easily lead to the problem of low on-state current.

[0140] Specifically, as shown in Figure 4, the second insulating layer 5 includes: a first sub-insulating layer 51, and a second sub-insulating layer 52 located on the side of the first sub-insulating layer 51 away from the first active layer 3; the thin film transistor also includes: a first transfer hole KZ1 that passes through the first sub-insulating layer 51 and the first insulating layer 2. The third part 33 can be specifically electrically connected to the second metal pattern 71 at the first transfer hole KZ1 through the first transfer electrode 42.

[0141] Specifically, as shown in Figure 4, the first transfer electrode 42 may include a portion located at the bottom of the first transfer hole KZ1, a portion covering the side wall of the first transfer hole KZ1, and a portion extending to the first sub-insulating layer 51 away from the surface of the first insulating layer; wherein, the first transfer electrode 42 located at the bottom of the first transfer hole KZ1 contacts the second metal pattern 71, and the first transfer electrode 42 covering the side wall of the first transfer hole KZ1 contacts the side wall of the third part 33, thereby realizing electrical connection between the third part 33 and the second metal pattern 71.

[0142] In a possible implementation, as shown in FIG. 4 , the orthographic projection of the second metal pattern 71 on the substrate 1 does not overlap with the orthographic projection of the first metal pattern 41 on the substrate 1 .

[0143] In one possible embodiment, as shown in FIG5 , the orthographic projection of the second metal pattern 71 on the substrate 1 at least partially overlaps the orthographic projection of the first metal pattern 41 on the substrate 1. This can shield the channel region of the thin film transistor from light, thereby increasing the light stability of the thin film transistor.

[0144] In a possible embodiment, the first active layer 3 and the second metal pattern 71 can also be electrically connected through the third metal layer's transition electrode. Specifically, as shown in FIG6 , the thin film transistor further includes: a second metal layer 7 located between the first insulating layer 2 and the substrate 1, and a third metal layer 8 located between the second metal layer 7 and the substrate 1;

[0145] The first active layer 3 further includes: a third portion 33 located on the other side of the first portion 31;

[0146] The second metal layer 7 includes a second metal pattern 71 ; the third metal layer 8 includes a second connecting electrode 82 ; and the third portion 33 is electrically connected to the second metal pattern 71 via the second connecting electrode 82 .

[0147] In the embodiment of the present disclosure, the thin film transistor also includes a second transfer electrode 82, and the third part 33 is electrically connected to the second metal pattern 71 through the second transfer electrode 82, which can avoid some problems caused by the lower overlap, such as large contact resistance. At the same time, the second transfer electrode 82 can be used to shield the via at this position (that is, the via through which the third part 33 is connected to the second metal pattern 71, such as the second transfer hole KZ2), which is beneficial to reduce light leakage from the second transfer hole KZ2 and improve contrast.

[0148] Specifically, a third insulating layer 103 may be provided between the first insulating layer 2 and the third metal layer 8. The thin film transistor includes: a second transfer hole KZ2 passing through the first insulating layer 2 and the third insulating layer 103. The third part 33 may be electrically connected to the second metal pattern 71 through the second transfer electrode 82 at the second transfer hole KZ2.

[0149] Specifically, as shown in Figure 6, the third part 33 may include a portion located at the bottom of the second transfer hole KZ2, and a portion extended to the surface of the second metal pattern 71 on the side away from the third insulating layer 103; wherein, the third portion 33 located at the bottom of the second transfer hole KZ2 is in contact with the second transfer electrode 82, and the third portion 33 extended to the surface of the second metal pattern 71 on the side away from the third insulating layer 103 is in contact with the second metal pattern 71, thereby realizing electrical connection between the third portion 33 and the second metal pattern 71.

[0150] In a possible implementation, as shown in FIG. 6 , at least a portion of the orthographic projection of the second metal pattern 71 on the substrate 1 is located on a side of the orthographic projection of the second switching electrode 82 on the substrate 1 away from the first portion 31 .

[0151] In one possible embodiment, as shown in FIG7A , at least a portion of the orthographic projection of the second metal pattern 71 on the substrate 1 is located on the side of the orthographic projection of the second transfer electrode 82 on the substrate 1 that is closer to the first portion 31. This avoids some problems caused by underlapping, such as high contact resistance. Furthermore, the second transfer electrode 82 can be used to shield the via at that location (i.e., the via connecting the third portion 33 to the second metal pattern 71, such as the second transfer hole KZ2), thereby reducing light leakage from the second transfer hole KZ2 and improving contrast.

[0152] In one possible embodiment, as shown in FIG7B , the first insulating layer 2 may not be provided with the first recess 21, and the second portion 32 and the first portion 31 may be substantially in the same plane. In this way, some problems caused by the lower overlap, such as high contact resistance, can be avoided. At the same time, the second transfer electrode 82 can be used to shield the via at this position (i.e., the via connecting the third portion 33 and the second metal pattern 71, such as the second transfer hole KZ2), which is beneficial for reducing light leakage from the second transfer hole KZ2 and improving contrast. At the same time, compared with FIG7A , in this embodiment, the first recess 21 and the second recess 22 can be omitted, which can reduce a mask patterning process.

[0153] In a possible embodiment, as shown in FIG8 , the first insulating layer 2 further includes: a second recess 22 ; the thin film transistor further includes: a second metal layer 7 located between the first insulating layer 2 and the substrate 1 ; the second recess 22 is a second via K2 penetrating the first insulating layer 2 ;

[0154] The second metal layer 7 includes: a second metal pattern 71 , at least a portion of the second metal pattern 71 is located in the second via hole K2 ;

[0155] At least a portion of the first portion 31 is located in the second recess 22 , and a portion of the first portion 31 located in the second via hole K2 is electrically connected to the second metal pattern 71 .

[0156] In the embodiment of the present disclosure, at least a portion of the second via K2 is located in the area where the orthographic projections of the second metal pattern 71 and the first metal pattern 41 overlap, forming a vertical channel structure, further reducing the size of the thin film transistor, reducing the area occupied by the thin film transistor in the display panel, and thereby improving the aperture ratio of the display panel.

[0157] In a possible embodiment, referring to FIG8 , the orthographic projection of the second via K2 on the substrate 1 has an overlapping area with the orthographic projection of the gate (such as the first metal pattern 41) on the substrate 1, and has an overlapping area with the orthographic projection of the source (such as the second metal pattern 71) on the substrate 1, and the orthographic projection of the gate (such as the first metal pattern 41) on the substrate 1 covers the orthographic projection of the second via K2 on the substrate 1, ensuring that the portion of the first active layer 3 within the second via K2 can be driven by the gate (such as the first metal pattern 41).

[0158] In one possible embodiment, as shown in Figures 1, 2A-2G, 3A-3B, 4, 5, 6, 7A-7B, and 8, the second insulating layer 5 includes: a first sub-insulating layer 51; a second sub-insulating layer 52 located on a side of the first sub-insulating layer 51 facing away from the first active layer 3; and a first metal layer 4 located on a side of the first active layer 3 facing away from the substrate 1. In the embodiment of the present disclosure, the thin film transistor is a top-gate thin film transistor. Compared to conventional dual-gate thin film transistors, the top-gate thin film transistor in the embodiment of the present disclosure can help improve the pixel aperture ratio.

[0159] In a possible embodiment, in combination with Figures 1, 2A-2G, 3A-3B, 4, 5, 6, 7A-7B and 8, the orthographic projection of the first sub-insulating layer 51 on the substrate covers the orthographic projection of the first part 31 on the substrate 1; the first sub-insulating layer 51 includes a first filling part 501.

[0160] In one possible embodiment, as shown in FIG9 , the orthographic projection of the first sub-insulating layer 51 on the substrate 1 covers at least a portion of the orthographic projection of the first portion 31 on the substrate 1, and the orthographic projection of the first sub-insulating layer 51 on the substrate 1 does not overlap with the orthographic projection of the second portion 32 on the substrate 1, nor does it overlap with the orthographic projection of the third portion 33 on the substrate 1; the second sub-insulating layer 52 includes a first filling portion 501. In the disclosed embodiment, the first sub-insulating layer 51 can be etched together with the first metal pattern 41, and the first active layer 3 is not conductively conductively formed by ion implantation, but rather by dry etching. That is, after etching the first sub-insulating layer 51, the surface of the second portion 32 is bombarded with Ar or He plasma, thereby converting the second portion 32 of the first active layer 3 from semiconductor properties to conductor properties. This has the advantage of reducing the need for a single ion implantation process and simplifying the thin film transistor fabrication process.

[0161] In one possible embodiment, as shown in conjunction with Figures 1, 2A-2G, 3A-3B, 4, 5, 6, 7A-7B, 8, and 9, first insulating layer 2 includes: a first buffer layer; and a first recess 21 having a depth perpendicular to substrate 1 that is the same as the thickness of the first buffer layer perpendicular to substrate 1. That is, first recess 21 is a via hole extending through first insulating layer 2.

[0162] Based on the same inventive concept, embodiments of the present disclosure further provide a display substrate. In one possible implementation, as shown in Figures 1, 2A-2G, 3A-3B, 4, 5, 6, 7A-7B, 8, and 9, the display substrate comprises a display area AA and a non-display area BB located peripherally to the display area AA. The display area AA includes a first signal line 40, a second signal line 70, and at least one thin film transistor as provided in embodiments of the present disclosure. Specifically, the first signal line 40 may be a gate line, and the second signal line 70 may be a data line.

[0163] In a possible embodiment, in combination with Figures 1, 2A-2G, 3A-3B, 4, 5, 6, 7A-7B, 8 and 9, the display substrate further includes: a fourth insulating layer 104 located on the side of the second insulating layer 5 away from the first active layer 3, and a pixel electrode 9 located on the side of the fourth insulating layer 104 away from the second insulating layer 5; the fourth insulating layer 104 has a third via hole K3, and the pixel electrode 9 is electrically connected to the first electrode 6 through the third via hole K3.

[0164] In one possible embodiment, as shown in conjunction with Figures 1, 2A-2G, 3A-3B, 4, 5, 6, 7A-7B, 8, and 9, the third via hole K3 is located at the center of the orthographic projection of the substrate 1, on the side of the center of the orthographic projection of the first via hole K1 on the substrate 1 away from the first portion 31. The display substrate further includes: a strapping electrode 90 located between the fourth insulating layer 104 and the pixel electrode 9. The first electrode 6 is electrically connected to the strapping electrode 90 via the third via hole K3, and the strapping electrode 90 is electrically connected to the pixel electrode 9. In the disclosed embodiment, the third via hole K3 is located at the center of the orthographic projection of the substrate 1, on the side of the center of the orthographic projection of the first via hole K1 on the substrate 1 away from the first portion 31. A two-step etching process is used to electrically connect the pixel electrode 9 to the first active layer 3. Compared to directly connecting the pixel electrode 9 to the first active layer 3 through a single via hole, which is more difficult to etch, the disclosed embodiment electrically connects the pixel electrode 9 to the first active layer 3 through two via holes, which is less difficult to manufacture and easier to implement.

[0165] Specifically, with reference to Figures 1, 2A-2G, 3A-3B, 4, 5, 6, 7A-7B, 8, and 9, the first via K1 overlaps at least a portion of the first recess 21; the first electrode 6 includes: a portion located at the bottom of the first recess 21, a portion covering the sidewall of the first recess 21 and the sidewall of the first via K1, and a portion extending to the surface of the second sub-insulating layer 52 away from the first sub-insulating layer 51; the bonding electrode 90 includes: a portion located at the bottom of the third via K3, a portion covering the sidewall of the third via K3, and an extension to the fourth insulating layer 1 04 is away from the part of the surface of the side of the second sub-insulating layer 52; the pixel electrode 9 covers at least the area where the third via hole K3 is located and the peripheral area of ​​the third via hole K3; wherein, the part of the overlapping electrode 90 located at the bottom K3 of the third hole overlaps with the part of the first electrode 6 that is extended to the surface of the second sub-insulating layer 52 on the side away from the first sub-insulating layer 51, thereby realizing the electrical connection between the overlapping electrode 90 and the first electrode 6; the overlapping electrode 90 is extended to the part of the surface of the fourth insulating layer 104 on the side away from the second sub-insulating layer 52, and overlaps with the pixel electrode 9, thereby realizing the electrical connection between the overlapping electrode 90 and the pixel electrode 9.

[0166] The specific pattern of the overlapping electrode 90 can be designed as needed, and its orthographic projection on the substrate 1 can be a triangle, quadrilateral, pentagon, hexagon, circle, ellipse, or other irregular shape. The specific pattern of the overlapping electrode 90 must meet the following requirements: on the one hand, it can achieve contact and overlap with the pixel electrode 9; on the other hand, after being stacked with the pixel electrode 9, the overall outer contour of the two covers the orthographic projections of the third via K3 and the first via K1 on the substrate 1.

[0167] Specifically, the orthographic projection of the pixel electrode 9 on the substrate 1 may cover the orthographic projection of the bonding electrode 90 on the substrate 1. Specifically, as shown in FIG2B or FIG10B , the orthographic projection of the pixel electrode 9 on the substrate 1 may be a rectangle.

[0168] In one possible embodiment, as shown in conjunction with Figures 1, 2A-2G, 3A-3B, 4, 5, 6, 7A-7B, 8, and 9, the display substrate further includes: a third filling portion 106 filling the third via hole K3. The step difference between the surface of the third filling portion 106 facing away from the substrate 11 and the surface of the fourth insulating layer 104 facing away from the substrate 1 is less than 0.2 μm. Specifically, the fourth insulating layer 104 may be a second planarizing layer PLN 2. In the disclosed embodiment, the display substrate further includes the third filling portion 106 filling the third via hole K3 to flatten the step around the third via hole K3. The step difference between the surface of the third filling portion 106 facing away from the substrate 11 and the surface of the fourth insulating layer 104 facing away from the substrate 1 is less than 0.2 μm. This prevents abnormal liquid crystal alignment during the cell alignment process if the step difference exceeds 0.2 μm, and avoids light leakage caused by excessive step difference around the third via hole K3.

[0169] Specifically, the fourth insulating layer 104 may be the first planar layer PLN1. Since this layer is typically thick, light leakage may occur when vias are provided. In conventional designs, the vias are provided at the locations where the light-shielding metal traces are located to block the light leakage. In the disclosed embodiment, the third via K3 of the fourth insulating layer 104 is located in the pixel opening area, which can increase the effective area of ​​the pixel electrode 9 and improve the liquid crystal efficiency. The third filling portion 106 also fills the area to ensure that there is no light leakage caused by the step difference.

[0170] In one possible embodiment, as shown in Figures 10A and 10B, the third via K3 is located at the center of the orthographic projection of the substrate 1, coinciding with the center of the orthographic projection of the first via K1 on the substrate 1. The first electrode is electrically connected to the pixel electrode through the first and third vias K1 and K3. In this public embodiment, the third via K3 is located at the center of the orthographic projection of the substrate 1, coinciding with the center of the orthographic projection of the first via K1 on the substrate 1. A deep trenching process is used in the pixel area, allowing the fourth insulating layer 104 and the second sub-insulating layer 52 to be etched in a single step. This eliminates two masking steps when patterning the second sub-insulating layer 52 and the bonding electrode 90. This also reduces the number of vias in the pixel opening area, thereby improving the contrast of the display panel.

[0171] In the embodiment of the present disclosure, the first via K1 and / or the third via K3 electrically connecting the pixel electrode 9 and the first active layer 3 are arranged in the pixel opening area. Compared with setting the first via K1 and / or the third via K3 electrically connecting the pixel electrode 9 and the first active layer 3 at the location of the wiring in the non-pixel opening area, part of the area in the pixel electrode is used for electrical connection with the first active layer, and part of the area is used for display, while the area for electrical connection is located outside the pixel opening area and cannot be used for display, so that the effective area of ​​the pixel electrode 9 is smaller. In the embodiment of the present disclosure, the first via K1 and / or the third via K3 electrically connecting the pixel electrode 9 and the first active layer 3 are located in the pixel opening area. While the pixel electrode 9 is electrically connected to the first active layer 3, it is also used for display, which increases the effective area of ​​the pixel electrode 9, improves the liquid crystal efficiency (the liquid crystal's ability to deflect linearly polarized light), and improves the light transmittance of the display substrate.

[0172] Specifically, the pixel opening region can be understood as the region of the display substrate where the sub-pixels are used for display. Specifically, the display panel can include a black matrix, which can include black matrix openings. The orthographic projection of the pixel opening region on substrate 1 can overlap with the orthographic projection of the black matrix opening on substrate 1.

[0173] In one possible embodiment, referring to Figures 1, 2A-2G, 3A-3B, 4, 5, 6, 7A-7B, 8, 9, 10A-10B, and 11, the orthographic projection of the pixel electrode 9 on the substrate covers the orthographic projection of the third via hole K3 and the first via hole K1 on the substrate 1. Since a lap electrode 90 is distributed in the third via hole K3 and a first electrode 6 is distributed in the first via hole K1, the lap electrode in the hole can form an electric field with the electrode layer above the pixel electrode 9 (e.g., the common electrode layer), which may interfere with the normal electric field formed by the pixel electrode 9 and the common electrode layer, thereby affecting the normal deflection of the liquid crystal. In the embodiment of the present disclosure, by covering the orthographic projections of the third via hole K3 and the first via hole K1 on the substrate 1 by the pixel electrode 9, the electric field in the hole can be shielded, thereby achieving a stable electric field effect.

[0174] In a possible embodiment, as shown in FIG2B , the first recess 21 and the orthographic projection of the first via K1 form an overlapping portion 210. The overlapping portion 210 is located on the side of the second portion 32 away from the first signal line 40, and the distance c from the first signal line 40 is greater than 0.75 μm, thereby preventing the first electrode 6 at the position of the first via K1 from short-circuiting with the first metal pattern 41 due to process fluctuations.

[0175] In a possible embodiment, in combination with Figures 2A-10B, the display substrate further includes a gate driving circuit located in the non-display area; the gate driving circuit board includes: a second active layer G1, a driving gate G2 located on the side of the second active layer G1 away from the substrate 1, and a driving source and drain G3 located on the side of the driving gate G2 away from the second active layer G1.

[0176] In one possible implementation, as shown in conjunction with Figures 2A to 10B , the driving source and drain electrodes G3 are located in the second metal layer 7. In the disclosed embodiment, the driving source and drain electrodes G3 are located in the second metal layer 7, and the driving source and drain electrodes G3 of the non-display area BB can be formed simultaneously with the formation of the second metal pattern 71 in the display area AA, thereby simplifying the manufacturing process of the display substrate.

[0177] In one possible implementation, as shown in FIG6 , the driving gate G2 is located in the third metal layer 8. In the disclosed embodiment, the driving gate G2 is located in the third metal layer 8. This allows the second transfer electrode 82 in the display area AA to be formed while the driving gate G2 in the non-display area BB is formed, thereby simplifying the manufacturing process of the display substrate.

[0178] In one possible implementation, as shown in Figure 11 , the driver source and drain G3 are located on the first metal layer 4, and the driver gate is located on the second metal layer. In the disclosed embodiment, the gate driver circuit of the non-display area BB and the metal layer of the display area AA are fully shared, reducing the number of masking operations.

[0179] In one possible embodiment, the material of the first active layer 3 includes rare earth element-doped indium zinc oxide or rare earth element-doped indium gallium zinc oxide. Rare earth element-doped indium zinc oxide or rare earth element-doped indium gallium zinc oxide is a light-resistant metal oxide. In the disclosed embodiment, the material of the first active layer 3 is rare earth element-doped indium zinc oxide or rare earth element-doped indium gallium zinc oxide. This allows the first active layer 3 to maintain stable performance even when exposed to light, eliminating the need for a light shielding layer in the pixel opening area, further improving the aperture ratio of the display substrate.

[0180] In one possible embodiment, the material of the second active layer G1 includes polysilicon. In the disclosed embodiment, the first active layer 3 of the display area thin-film transistor can be an oxide active layer, and the driving transistor in the non-display area can be a polysilicon active layer. Oxide thin-film transistors have advantages such as low leakage current, while low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging. By integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate to form a low-temperature polycrystalline oxide display panel, the advantages of both can be utilized to achieve high resolution (Pixel Per Inch, PPI) and low-frequency driving, which can reduce power consumption and improve display quality.

[0181] In a possible implementation, the material of the second active layer G1 includes rare earth element-doped indium zinc oxide, or rare earth element-doped indium gallium zinc oxide.

[0182] In a possible implementation, the second active layer G1 is made of a different material from the first active layer 3 .

[0183] In one possible embodiment, the first active layer 3 can be an oblique non-linear pattern. Specifically, as shown in Figure 2B, the second portion 32 and the third portion 33 both extend along the second direction Y, and the extension line of the second portion 32 does not coincide with the extension line of the third portion 33; the angle β formed by at least a portion of the third portion 33 and the first signal line 40 toward the electrically connected second signal line 70 is an acute angle.

[0184] In one possible embodiment, as shown in FIG2B , the region of the first active layer 3 for overlapping with the pixel electrode 9 may be used as the first portion 31, and the region for overlapping with the second signal line 70 may be used as the third portion 33. In one possible embodiment, as shown in FIG2B , the first portion 31 includes an obliquely extending portion, and the obliquely extending portion overlaps with the first signal line 40 to form a channel region.

[0185] In a possible embodiment, as shown in Figure 2G, the first active layer 3 can be an oblique pattern extending along the third direction Z, the second signal line 70 (data line) can be a bent structure in the second direction Y, and a pixel electrode is set in the area between two adjacent second signal lines 70 and two adjacent first signal lines 40 (gate lines); the area where the first active layer 3 overlaps with the first signal line 40 (gate line) serves as the first part 31, the part of the first active layer 3 electrically connected to the pixel electrode serves as the second part 32, and the part of the first active layer 3 electrically connected to the second signal line 70 (data line) serves as the third part 33.

[0186] In one possible embodiment, as shown in conjunction with Figures 2A to 11 , the display substrate further includes: a common electrode 107 located on the side of the pixel electrode 5 facing away from the substrate 1; the common electrode 107 includes: a first common electrode portion extending along a first direction X, and a second common electrode portion extending along a second direction Y; the orthographic projection of the first common electrode portion on the substrate 1 overlaps the orthographic projection of the first signal line 40 on the substrate 1, and the orthographic projection of the second common electrode portion on the substrate 1 overlaps the orthographic projection of the second signal line 70 on the substrate 1; the orthographic projection of the third via K3 on the substrate 1 is located within the orthographic projection of the intersection of the first common electrode portion and the second common electrode portion on the substrate 1. In one possible embodiment, the orthographic projection of the first via K1 on the substrate 1 is also located within the orthographic projection of the intersection of the first common electrode portion and the second common electrode portion on the substrate 1.

[0187] In a possible embodiment, in combination with Figures 2A to 11, the display substrate further includes: a first light-shielding layer 109 located on the side of the common electrode 107 away from the pixel electrode 9 and in direct contact with the common electrode 107, and a spacer 108 located on the side of the first light-shielding layer 109 away from the pixel electrode layer 6; the orthographic projection of the common electrode 107 on the substrate 1 covers the orthographic projection of the first light-shielding layer 109 on the substrate 1, and the line width of the first light-shielding layer 109 is smaller than the line width of the common electrode 107; the orthographic projection of the first light-shielding layer 109 on the substrate 1 covers the orthographic projection of the spacer 108 on the substrate 1, and the line width of the spacer 108 is smaller than the line width of the first light-shielding layer 109.

[0188] Specifically, the first light-shielding layer 109 can be made of a blackened metal material, and the spacer 108 can be made of molybdenum or aluminum (i.e., a material that can be wet-etched). The first light-shielding layer 109 and the spacer 108 can be formed by a mask process, using wet etching plus dry etching, and utilizing the difference in etching bias (bias) between the spacer 108 and the first light-shielding layer 109 to form the first light-shielding layer 109 and the spacer 108 into a step shape.

[0189] Specifically, the material of the first light-shielding layer 109 may also include: any one or more of titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), copper (Cu), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), or their compounds.

[0190] Specifically, the thickness of the first light shielding layer 109 can be 30 nm to 80 nm, and the thickness of the spacer 108 can be 0.4 μm to 1 μm. The first light shielding layer 109 can shield the first signal line 40 and the second signal line 70 and reduce the resistance of the common electrode 107 .

[0191] In one possible embodiment, the orthographic projection of the first shading layer 109 on the substrate 1 covers the orthographic projection of the second signal line 70 on the substrate 1, and covers the orthographic projection of the first signal line 40 on the substrate 1; the orthographic projection of the spacer 108 on the substrate 1 covers the orthographic projection of the second signal line 70 on the substrate 11, and covers the orthographic projection of the first signal line 40 on the substrate 1.

[0192] Specifically, the shapes of the first light-shielding layer 109 and the spacer 108 can be similar to the pattern shape of the common electrode 107, that is, the first light-shielding layer 109 can include a first light-shielding portion extending along the first direction X, and a second light-shielding portion extending along the second direction Y, and the first light-shielding portion and the second light-shielding portion intersect to form a mesh structure; the spacer 108 can include a first spacer portion extending along the first direction X, and a second spacer portion extending along the second direction Y, and the first spacer portion and the second spacer portion intersect to form a mesh structure. The spacer 108 with a mesh structure can be designed with a narrower line width, which is beneficial to improving the aperture ratio of the display substrate.

[0193] Specifically, as shown in FIG2A , the display substrate further includes at least one of the following:

[0194] a first buffer layer 101 located between the substrate 1 and the second active layer G1;

[0195] a first gate insulating layer 102 located between the second active layer G1 and the driving gate G2;

[0196] A passivation layer 105 is located between the pixel electrode 9 and the common electrode 107 .

[0197] Specifically, the first insulating layer 2 can be a second buffer layer; the first sub-insulating layer 51 can be a first gate insulating layer; the second sub-insulating layer 52 can be a second interlayer dielectric layer; the third insulating layer 103 can be a first interlayer dielectric layer; and the fourth insulating layer 104 can be a first planar layer.

[0198] In some examples, at least one of the first buffer layer, the second buffer layer, the first interlayer dielectric layer, the second interlayer dielectric layer, the first gate insulating layer, the second gate insulating layer, the first planarizing layer, and the second planarizing layer can be an inorganic insulating layer, and can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multilayer, or a composite layer. At least one of the first metal layer, the second metal layer, and the third metal layer can be made of a metal material, such as any one or more of aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), copper (Cu), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), or silver (Ag), or alloys of the foregoing metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single layer structure or a multilayer composite structure, such as Ti / Al / Ti.

[0199] In order to more clearly understand the display substrate provided by the embodiment of the present disclosure, the following is further detailed description with reference to FIG. 12A to FIG. 12I :

[0200] Step 1: Deposit a first buffer layer 101 on substrate 1. The material of the first buffer layer 101 may include SiN and / or SiO2 and / or aSi, and the thickness may be 200nm to 500nm. The first buffer layer 101 is crystallized into polycrystalline silicon (poly-Si) by excimer laser annealing (ELA), and then patterned, as shown in FIG12A below.

[0201] Step 2: Form a first gate insulating layer 102. The material of the first gate insulating layer 102 may include SiO2 and may have a thickness of 100 nm to 150 nm. Then, a driving gate G2 of a low-temperature polysilicon (LTPS) thin-film transistor is deposited. The material of the driving gate G2 may include Mo, Al, or other materials. Then, the shape of the driving gate G2 is formed by photolithography and etching, and the first interlayer dielectric layer 103 is completed, as shown in FIG12B below.

[0202] Step 3: Open holes in the first interlayer dielectric layer 103, deposit a second metal layer 7, and pattern it to form a driving source and drain G3 and a second metal pattern 71; the material of the second metal layer 7 is selected from metals such as Mo, Al, and Ti, and then patterned; then deposit a second buffer layer, that is, a first insulating layer 2. The material of the first insulating layer 2 includes: SiO2 or SiN / SiO2 stacked layers, as shown in Figure 12C below:

[0203] Step 4: Via holes are patterned and etched in the first insulating layer 2. One of the via holes (such as the second recess 22) overlaps the second metal pattern 71. The use of half-lapping can reduce the via size. At the same time, the metal oxide in the via hole will automatically compensate, increasing the overlap area and improving the overlap resistance problem. The other via hole (such as the first recess 21) is located in the pixel opening area, as shown in Figures 12D and 12E.

[0204] Step Five: Deposit a high-mobility metal oxide semiconductor layer HMOS. Materials such as rare-earth doped IGZO or ITZO are selected and patterned to serve as the first active layer 3. Then deposit the first sub-gate insulating layer 51, which is also the second gate insulating layer. The material of the first sub-gate insulating layer 51 includes SiO2. Then deposit the first metal layer 4 and pattern it to form the first metal pattern 41 (for example, the gate). The first active layer 3 straddles the second metal pattern 71, belonging to the lower lap joint. As shown in FIG. 2C, while the first metal pattern 41 is completed, an ion implantation and conductorization process is carried out. Since the regions of the first active layer 3 that need to be conductorized and the semiconductor regions are separated vertically, the semiconductor regions are less affected by the conductorization, and the lateral diffusion is reduced, which is beneficial to improving the deterioration of the short-channel characteristics. At the same time, the channel is obliquely designed in the direction parallel to the substrate 1 and bent in the direction perpendicular to the substrate 1, both of which increase the effective channel length to a certain extent and improve the device characteristics, as shown in FIGS. 12F and 12G. Specifically, the width b1 of the non-conductorized region in the second direction Y and the width b2 of the first signal line 40 in the second direction Y satisfy: b2×30% < b1 < b2×75%, where b1 = a1 + a2;

[0205] Step Six: Deposit the second sub-insulating layer 52 and etch to form the first via K1. The etching of the deep via K1 also affects the device characteristics. A straddling structure is adopted, and the dry etching by-products are isolated by the first filling portion 501 of the first sub-gate insulating layer 51, which can block the diffusion. And the lateral diffusion of the exposed part of the contact first active layer 3 needs to pass through the lateral transition region (i.e., the first connection portion 34). This structure is beneficial to improving the short-channel characteristics. And further form the pixel area transfer layer ITO, which is also the first electrode 6, as shown in FIG. 12H;

[0206] Step Seven: Continue to complete the subsequent process, as shown in FIG. 12I.

[0207] Based on the same inventive concept, the embodiments of the present disclosure also provide a display device, which includes a display substrate as provided in the embodiments of the present disclosure.

[0208] Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications once they know the basic creative concepts. Therefore, the appended claims are intended to be construed to include the preferred embodiments and all changes and modifications falling within the scope of the present invention.

[0209] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.

Claims

1. A thin film transistor, in, include: substrate; A first insulating layer, located on one side of the substrate, wherein the first insulating layer has a first concave portion; A first active layer is located on a side of the first insulating layer away from the substrate, the first active layer comprising: a first portion, and a second portion located on one side of the first portion; the second portion is located in the first concave portion; The first metal layer and the first active layer are located on the same side of the substrate, and the first metal layer includes a first metal pattern, wherein an orthographic projection of the first portion on the substrate has an overlapping area with an orthographic projection of the first metal pattern on the substrate.

2. The thin film transistor according to claim 1, in, The thin film transistor further includes: a second insulating layer located on a side of the first active layer away from the first insulating layer, and a first electrode located on a side of the second insulating layer away from the first active layer; The second insulating layer has a first via hole, and the first electrode is electrically connected to the second portion through the first via hole.

3. The thin film transistor according to claim 2, in, The first active layer further includes: a first connecting portion located between the first portion and the second portion, the first connecting portion covering a portion of a side wall of the first recess; The second insulating layer includes a first filling portion, an orthographic projection of the first filling portion on the substrate has an overlapping area with an orthographic projection of the first recessed portion on the substrate, and the first filling portion covers the first connecting portion.

4. The thin film transistor according to any one of claims 1 to 3, in, The first insulating layer further includes: a second recess; The first active layer further includes: a third portion located at the other side of the first portion; and at least a portion of the third portion is located in the second concave portion.

5. The thin film transistor according to claim 4, in, The first active layer further includes: a second connecting portion located between the first portion and the third portion, the second connecting portion covering a portion of a side wall of the second recess; The second insulating layer includes a second filling portion, an orthographic projection of the second filling portion on the substrate has an overlapping area with an orthographic projection of the second recessed portion on the substrate, and the second filling portion covers the second connecting portion.

6. The thin film transistor according to claim 5, in, The first active layer further includes: a fourth portion located between the first portion and the first connecting portion, and a fifth portion located between the first portion and the second connecting portion; The orthographic projection of the fourth portion on the substrate does not overlap with the orthographic projection of the first metal pattern on the substrate, and the orthographic projection of the fifth portion on the substrate does not overlap with the orthographic projection of the first metal pattern on the substrate.

7. The thin film transistor according to any one of claims 1 to 3, in, The first insulating layer further includes: a second recess; At least a portion of the first portion is located in the second recess.

8. The thin film transistor according to any one of claims 4 to 7, in, The thin film transistor further includes: a second metal layer located between the first insulating layer and the substrate; the second recess is a second via hole penetrating the first insulating layer; The second metal layer includes: a second metal pattern, at least a part of the second metal pattern is located in the second via hole, and a third part is electrically connected to the part of the second metal pattern located in the second via hole.

9. The thin film transistor according to claim 8, wherein, the second via hole includes: a first sub-via hole part, and a second sub-via hole part; a positive projection of the first sub-via hole part on the substrate overlaps a positive projection of the second metal pattern on the substrate, and a positive projection of the second sub-via hole part on the substrate is located on a side of the first sub-via hole part facing the first part.

10. The thin film transistor according to claim 8, wherein, the second via hole includes: a first sub-via hole part, and a second sub-via hole part; a positive projection of the first sub-via hole part on the substrate overlaps a positive projection of the second metal pattern on the substrate, and a positive projection of the second sub-via hole part on the substrate is located on a side of the positive projection of the first sub-via hole part on the substrate away from the positive projection of the first part on the substrate.

11. The thin film transistor according to any one of claims 1-3, wherein, the thin film transistor further includes: a second metal layer located between the first insulating layer and the substrate; the second metal layer includes: a second metal pattern; the first active layer further includes: a third part located on the other side of the first part; the first metal layer further includes: a first transfer electrode; the third part is electrically connected to the second metal pattern through the first transfer electrode.

12. The thin film transistor according to claim 11, wherein, at least a part of a positive projection of the second metal pattern on the substrate overlaps a positive projection of the first metal pattern on the substrate.

13. The thin film transistor according to any one of claims 1-3, wherein, the thin film transistor further includes: a second metal layer located between the first insulating layer and the substrate, and a third metal layer located between the second metal layer and the substrate; the first active layer further includes: a third part located on the other side of the first part; the second metal layer includes: a second metal pattern; the third metal layer includes: a second transfer electrode; the third part is electrically connected to the second metal pattern through the second transfer electrode.

14. The thin film transistor according to claim 13, wherein, at least a part of a positive projection of the second metal pattern on the substrate is located on a side of a positive projection of the second transfer electrode on the substrate away from the first part.

15. The thin film transistor according to claim 13, wherein, at least a part of a positive projection of the second metal pattern on the substrate is located on a side of a positive projection of the second transfer electrode on the substrate close to the first part.

16. The thin film transistor according to any one of claims 1-3, wherein, the first insulating layer further includes: a second recess; the thin film transistor further includes: a second metal layer located between the first insulating layer and the substrate; the second recess is a second via hole penetrating the first insulating layer; the second metal layer includes: a second metal pattern, at least a part of the second metal pattern is located in the second via hole; At least a part of the first portion is located in the second via hole, and the part of the first portion located in the second via hole is electrically connected to the second metal pattern.

17. The thin film transistor according to any one of claims 2-16, wherein, the second insulating layer includes: a first sub-insulating layer, and a second sub-insulating layer located on a side of the first sub-insulating layer away from the first active layer; the first metal layer is located on a side of the first active layer away from the substrate.

18. The thin film transistor according to claim 17, wherein, a positive projection of the first sub-insulating layer on the substrate covers a positive projection of the first portion on the substrate; the first sub-insulating layer includes the first filling portion.

19. The thin film transistor according to claim 17, wherein, a positive projection of the first sub-insulating layer on the substrate covers at least a part of a positive projection of the first portion on the substrate, and a positive projection of the first sub-insulating layer on the substrate does not overlap with a positive projection of the second portion on the substrate and does not overlap with a positive projection of the third portion on the substrate; the second sub-insulating layer includes the first filling portion.

20. The thin film transistor according to any one of claims 1-19, wherein, a depth of the first recess in a direction perpendicular to the substrate is the same as a thickness of the first insulating layer in a direction perpendicular to the substrate.

21. The thin film transistor according to any one of claims 2-20, wherein, a depth e1 of the first via hole in a direction perpendicular to the substrate satisfies the following relationship: e2 < e1 ≤ e2 + e3, where e2 represents a thickness of the second insulating layer in the substrate direction, and e3 represents a thickness of the first insulating layer in the substrate direction.

22. A display substrate having a display area and a non-display area located outside the display area, wherein, the display area includes: a first signal line, a second signal line, and at least one thin film transistor according to any one of claims 1-21.

23. The display substrate according to claim 22, wherein, the display substrate further includes: a fourth insulating layer located on a side of the second insulating layer away from the first active layer, and a pixel electrode located on a side of the fourth insulating layer away from the second insulating layer; the fourth insulating layer has a third via hole, and the pixel electrode is electrically connected to the first electrode through the third via hole.

24. The display substrate according to claim 23, wherein, a center of a positive projection of the third via hole on the substrate is located on a side of a center of a positive projection of the first via hole on the substrate away from the first portion; the display substrate further includes: an overlapping electrode located between the third insulating layer and the pixel electrode; the first electrode is electrically connected to the overlapping electrode through the third via hole, and the overlapping electrode is electrically connected to the pixel electrode.

25. The display substrate according to claim 24, wherein, a center of a positive projection of the third via hole on the substrate coincides with a center of a positive projection of the first via hole on the substrate; the first electrode is electrically connected to the pixel electrode through the first via hole and the third via hole.

26. The display substrate according to any one of claims 22-25, wherein, for the orthographic projection overlapping portion of the first recess and the first via hole, the overlapping portion is located on a side of the second portion away from the first signal line and is at a distance greater than 0.75 μm from the first signal line.

27. The display substrate according to any one of claims 22-26, wherein, the display substrate further includes a gate driving circuit located in the non-display area; the gate driving circuit board includes: a second active layer, a driving gate located on a side of the second active layer away from the substrate, and a driving source-drain located on a side of the driving gate away from the second active layer.

28. The display substrate according to claim 27, wherein, the driving source-drain is located in the second metal layer.

29. The display substrate according to claim 28, wherein, the driving gate is located in the third metal layer.

30. The display substrate according to claim 29, wherein, the driving source-drain is located in the first metal layer; the driving gate is located in the second metal layer.

31. A display device, wherein, it includes the display substrate according to any one of claims 22-30.

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