Display panel and display device

Abstract

A display panel comprises a substrate (10), a display structure layer and a touch control structure layer (15). The substrate (10) comprises a display area (AA), a second frame area (B2) located on one side of the display area (AA), and a first frame area (B1) located on the other side of the display area (AA). The display structure layer comprises at least one first crack detection line (311) and a plurality of data outgoing lines (323). The touch structure layer (15) comprises at least one second crack detection line (312). The first crack detection line (311) and the second crack detection line (312) are connected in series in the second frame region (B2) by a plurality of detection connection lines (321, 322a, 322b). The orthographic projection of the at least one detection connecting line (321) and the orthographic projection of the at least one data outgoing line (323) on the substrate (10) are overlapped, and at least two insulating layers are arranged between at least part of the line segment of the at least one detection connecting line (321) and the at least one data outgoing line (323).

Description

Display panel and display device Technical Field

[0001] This article relates to but is not limited to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, and extremely fast response times. With the continuous advancement of display technology, display devices using OLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present disclosure provide a display panel and a display device.

[0006] On the one hand, this embodiment provides a display panel comprising: a substrate, a display structure layer disposed on the substrate, and a touch structure layer. The substrate includes a display area and a frame area located around the display area. The frame area includes: a second frame area located on one side of the display area and a first frame area located on the remaining sides of the display area. The display structure layer includes: a plurality of sub-pixels and a plurality of data lines located in the display area, at least one first crack detection line located in the first frame area, and a plurality of data lead lines located in the second frame area. The plurality of data lines are connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels. The plurality of data lead lines are configured to provide data signals to the plurality of data lines. The touch structure layer is located on a side of the display structure layer away from the substrate. The touch structure layer includes at least one second crack detection line located in the first frame area. The at least one first crack detection line and the at least one second crack detection line are connected in series in the second frame area via a plurality of detection connection lines. The orthographic projection of at least one of the multiple detection connection lines on the substrate overlaps with the orthographic projection of at least one of the multiple data lead lines on the substrate, and at least two insulating layers are arranged between at least part of the line segment of the at least one detection connection line and the at least one data lead line.

[0007] In some exemplary embodiments, the at least two insulating layers may include at least one organic insulating layer and at least one inorganic insulating layer.

[0008] In some exemplary embodiments, a minimum thickness between at least a portion of the at least one detection connection line and the at least one data lead line is greater than 2.1 micrometers.

[0009] In some exemplary embodiments, the display panel further includes: at least one shielding electrode located in the second border region. In a direction perpendicular to the display panel, the shielding electrode is located between at least a portion of the at least one detection connection line and the at least one data lead line; and an orthographic projection of the shielding electrode on the substrate covers an overlapping portion of the orthographic projections of the at least one detection connection line and the at least one data lead line on the substrate.

[0010] In some exemplary embodiments, the display panel further includes: a plurality of first power lines located in the display area and a first power supply line located in the second border area, the plurality of first power lines being electrically connected to the plurality of sub-pixels, and the plurality of first power lines being connected to the first power supply line, and the at least one shielding electrode being connected to the first power supply line.

[0011] In some exemplary embodiments, the first power supply line includes: a first sub-power supply line and a second sub-power supply line connected to each other, the first sub-power supply line is located on a side of the second sub-power supply line close to the substrate; the at least one shielding electrode and the first sub-power supply line are an integrated structure connected to each other.

[0012] In some exemplary embodiments, at least a portion of the at least one detection connection line and the second sub-power supply line are in the same layer structure.

[0013] In some exemplary embodiments, the first power supply line includes: a first sub-power supply line and a second sub-power supply line connected to each other, the first sub-power supply line is located on a side of the second sub-power supply line close to the substrate; the at least one shielding electrode and the second sub-power supply line are an integrated structure connected to each other; at least a portion of the line segment of the at least one detection connection line is located on a side of the second sub-power supply line away from the substrate.

[0014] In some exemplary embodiments, the display structure layer includes at least: a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer disposed on the substrate; an interlayer insulating layer is disposed between the second gate metal layer and the first source / drain metal layer, and at least a first planarizing layer is disposed between the first source / drain metal layer and the second source / drain metal layer. At least a portion of the at least one detection connection line is located in the second source / drain metal layer, and the shielding electrode is located in the first source / drain metal layer. The insulating layer between at least a portion of the at least one detection connection line and the at least one data lead line includes at least an interlayer insulating layer and a first planarizing layer.

[0015] In some exemplary embodiments, the plurality of data lead lines include: a plurality of first data lead lines located in the first gate metal layer and a plurality of second data lead lines located in the second gate metal layer, and the plurality of first data lead lines and the plurality of second data lead lines are alternately arranged.

[0016] In some exemplary embodiments, the touch structure layer includes at least one touch conductive layer, and at least a portion of the at least one detection connection line is located in the touch conductive layer of the touch structure layer.

[0017] In some exemplary embodiments, the second border area includes a first signal access area, the first signal access area including: a plurality of data contact pads, at least one first detection contact pad, and at least one second detection contact pad, the at least one first detection contact pad and the at least one second detection contact pad being located on either side of the plurality of data contact pads along a first direction; the plurality of data contact pads being connected to the plurality of data lead lines. The plurality of detection connection lines include: two second detection connection lines and at least one first detection connection line; the first detection connection line is connected in series with the first crack detection line and the second crack detection line; one end of the series-connected first crack detection line and the second crack detection line is connected to the at least one first detection contact pad via a second detection connection line, and the other end is connected to the at least one second detection contact pad via another second detection connection line. A portion of the at least one first detection connection line overlaps with the at least one data lead line on the orthographic projection of the substrate.

[0018] In some exemplary embodiments, among the two second detection connection lines, the orthographic projection of one of the second detection connection lines on the substrate partially overlaps with the orthographic projection of the at least one data lead line on the substrate; and the distance between the orthographic projection of the other second detection connection line on the substrate and the orthographic projection of the multiple data lead lines on the substrate is greater than 0.

[0019] In some exemplary embodiments, a portion of the first detection connection line that overlaps with the orthographic projection of the at least one data lead line on the substrate, and a portion of the second detection connection line that overlaps with the orthographic projection of the at least one data lead line on the substrate are in the same layer structure.

[0020] In some exemplary embodiments, a distance between the orthographic projections of the two second detection connection lines on the substrate and the orthographic projections of the plurality of data lead lines on the substrate is greater than 0.

[0021] In some exemplary embodiments, the at least one first detection connection line includes: a first extension segment, a second extension segment, and a third extension segment connected in sequence, the extension direction of the second extension segment intersects with the extension directions of the first extension segment and the third extension segment, the second extension segment overlaps with the orthographic projection of the at least one data lead line on the substrate, and the distance between the orthographic projection of the first extension segment and the third extension segment on the substrate and the orthographic projection of the multiple data lead lines on the substrate is greater than 0.

[0022] In some exemplary embodiments, the second extending segment is located on a side of the first extending segment and the third extending segment away from the substrate, and the second extending segment is connected to the first extending segment or the third extending segment via a second connecting electrode.

[0023] In some exemplary embodiments, the first extension section, the second extension section, and the third extension section of the first detection connection line are interconnected as an integral structure.

[0024] In some exemplary embodiments, the display structure layer includes a plurality of first crack detection lines, the plurality of first crack detection lines being symmetrically arranged about a midline of the display panel in a first direction. The touch structure layer includes a plurality of second crack detection lines, the plurality of second crack detection lines being symmetrically arranged about a midline of the display panel in the first direction.

[0025] In some exemplary embodiments, each data lead line located in the second border area overlaps with the orthographic projection of the same number of detection connection lines on the substrate.

[0026] In some exemplary embodiments, the plurality of detection connection lines in the second border region are symmetrically arranged about a center line of the display panel in the first direction.

[0027] In some exemplary embodiments, the second border area further includes: a bending area, the bending area including: a plurality of detection bending lines, the plurality of detection connecting lines being connected to the at least one first crack detection line and the at least one second crack detection line through the plurality of detection bending lines; the plurality of detection bending lines being a same-layer structure.

[0028] On the other hand, this embodiment provides a display device including the display panel as described above.

[0029] On the other hand, this embodiment provides a display panel comprising: a substrate, a display structure layer disposed on the substrate, a touch structure layer, and at least one shielding electrode. The substrate comprises: a display area and a frame area located around the display area. The frame area comprises: a second frame area located on one side of the display area and a first frame area located on the remaining sides of the display area. The display structure layer comprises: a plurality of sub-pixels and a plurality of data lines located in the display area, at least one first crack detection line located in the first frame area, and a plurality of data lead lines located in the second frame area. The plurality of data lines are connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels. The plurality of data lead lines are configured to provide data signals to the plurality of data lines. The touch structure layer is located on a side of the display structure layer away from the substrate. The touch structure layer comprises: at least one second crack detection line located in the first frame area. The at least one first crack detection line and the at least one second crack detection line are connected in series in the second frame area via a plurality of detection connection lines. The orthographic projection of at least one of the plurality of detection connection lines on the substrate overlaps with the orthographic projection of at least one of the plurality of data lead lines on the substrate. The at least one shielding electrode is located in the second frame region. In a direction perpendicular to the display panel, the shielding electrode is located between at least a portion of the at least one detection connection line and the at least one data lead line, and the orthographic projection of the shielding electrode on the substrate at least partially overlaps with the orthographic projections of the at least one detection connection line and the at least one data lead line on the substrate.

[0030] In some exemplary embodiments, at least two insulating layers are provided between at least a portion of the at least one detection connection line and the at least one data lead line, and the at least two insulating layers include at least one organic insulating layer and at least one inorganic insulating layer.

[0031] In some exemplary embodiments, a minimum thickness between at least a portion of the at least one detection connection line and the at least one data lead line is greater than 2.1 micrometers.

[0032] In some exemplary embodiments, the display panel further includes: a plurality of first power lines located in the display area and a first power supply line located in the second border area, the plurality of first power lines being electrically connected to the plurality of sub-pixels, and the plurality of first power lines being connected to the first power supply line, and the at least one shielding electrode being connected to the first power supply line.

[0033] In some exemplary embodiments, the first power supply line includes: a first sub-power supply line and a second sub-power supply line connected to each other, the first sub-power supply line is located on a side of the second sub-power supply line close to the substrate; the at least one shielding electrode and the first sub-power supply line are an integrated structure connected to each other, or the at least one shielding electrode and the second sub-power supply line are an integrated structure connected to each other.

[0034] In some exemplary embodiments, the touch structure layer includes at least one touch conductive layer, and at least a portion of the at least one detection connection line is located in the touch conductive layer of the touch structure layer.

[0035] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0036] Summary of the Figures

[0037] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0038] FIG1 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0039] FIG2 is a partial cross-sectional schematic diagram of a display area of ​​a display panel according to at least one embodiment of the present disclosure;

[0040] FIG3 is a schematic diagram of crack detection of a display panel according to at least one embodiment of the present disclosure;

[0041] FIG4 is a partial schematic diagram of a second frame region of a display panel according to at least one embodiment of the present disclosure;

[0042] FIG5 is a schematic diagram of the wiring arrangement of the bending area of ​​the second frame area according to at least one embodiment of the present disclosure;

[0043] FIG6 is a partial enlarged schematic diagram of area C1 in FIG4 ;

[0044] FIG7A is a schematic partial cross-sectional view along the Q1-Q1' direction in FIG6;

[0045] FIG7B is another partial cross-sectional schematic diagram along the Q1-Q1' direction in FIG6;

[0046] FIG8 is a partial schematic diagram of a second frame area according to at least one embodiment of the present disclosure;

[0047] FIG9 is a partially enlarged schematic diagram of the first transfer area D1 in FIG8 ;

[0048] FIG10 is a schematic partial cross-sectional view along the Q2-Q2' direction in FIG9;

[0049] FIG11 is a partially enlarged schematic diagram of the second transfer area D2 in FIG8 ;

[0050] FIG12 is a schematic partial cross-sectional view along the Q3-Q3' direction in FIG11;

[0051] FIG13 is a partial enlarged schematic diagram of the third transfer area D3 in FIG8 ;

[0052] FIG14 is a schematic partial cross-sectional view along the Q4-Q4' direction in FIG13;

[0053] FIG15 is a partial schematic diagram of the second frame area according to at least one embodiment of the present disclosure;

[0054] FIG16 is a partial enlarged schematic diagram of area C2 in FIG15 ;

[0055] FIG17A is a schematic partial cross-sectional view along the Q5-Q5' direction in FIG16;

[0056] FIG17B is another partial cross-sectional schematic diagram along the Q5-Q5' direction in FIG16;

[0057] FIG17C is another partial cross-sectional schematic diagram along the Q5-Q5' direction in FIG16;

[0058] FIG18 is a partial enlarged schematic diagram of the eighth transfer area D8 in FIG15 ;

[0059] FIG19 is a schematic partial cross-sectional view along the Q6-Q6' direction in FIG18;

[0060] FIG20 is a partial enlarged schematic diagram of the tenth transfer area D10 in FIG15;

[0061] FIG21 is a schematic partial cross-sectional view along the Q7-Q7' direction in FIG20;

[0062] FIG22 is another partial schematic diagram of the second frame area according to at least one embodiment of the present disclosure;

[0063] FIG23 is a partial enlarged schematic diagram of area C3 in FIG22;

[0064] FIG. 24 is a schematic partial cross-sectional view along the Q8-Q8' direction in FIG. 23 .

[0065] FIG25 is another partial schematic diagram of the second frame area according to at least one embodiment of the present disclosure;

[0066] FIG26 is a partial enlarged schematic diagram of area C4 in FIG25 ;

[0067] FIG27 is a schematic partial cross-sectional view along the Q9-Q9' direction in FIG26.

[0068] FIG28 is another schematic diagram of crack detection of a display panel according to at least one embodiment of the present disclosure;

[0069] FIG29 is a partial enlarged schematic diagram of the second frame area in FIG28;

[0070] FIG30 is a schematic diagram of a partial film layer structure of area C5 in FIG29;

[0071] FIG31 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0072] Details

[0073] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0074] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0075] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. In this disclosure, "plurality" means two or more.

[0076] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0077] In this specification, unless otherwise expressly specified or limited, the terms "mounted," "connected," "connected," and "coupled" should be interpreted broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meanings of these terms in this disclosure based on the specific circumstances.

[0078] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0079] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this specification, the channel region refers to the region through which current primarily flows.

[0080] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. The functions of "source electrode" and "drain electrode" are sometimes interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged. Furthermore, the gate electrode can also be referred to as the control electrode.

[0081] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0082] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0083] In this disclosure, "approximately" and "substantially" are used without strict boundaries, allowing for process and measurement errors. In this disclosure, "same" includes both completely identical and substantially the same, and "substantially the same" means that the difference in value is within 10%.

[0084] In this specification, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. Throughout this specification, "A extends along direction B" means "the main portion of A extends along direction B."

[0085] As used herein, "A and B are of the same layer structure" or "A and B are arranged in the same layer" means that A and B are formed simultaneously through the same patterning process, or that the surfaces of A and B close to the substrate are at substantially the same distance from the substrate, or that the surfaces of A and B close to the substrate are in direct contact with the same film layer. "The same layer" does not always mean that the thickness or height of the layer is the same in a cross-sectional view. The "thickness" of a film layer is the dimension of the film layer in a direction perpendicular to the display substrate. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the range of the orthographic projection of A, or that the orthographic projection of A covers the orthographic projection of B.

[0086] In the display industry, with the continuous development of technology, the demand for display products (such as wearable display products) is increasing, and the requirements for screen image quality are becoming increasingly stringent. In particular, low grayscale image quality has become the main direction for improving image quality. For example, small display products such as wearable products are small in size, and the display data signal is easily interfered with by parasitic capacitance, which affects the display quality.

[0087] The present embodiment provides a display panel and a display device, which can reduce the interference of parasitic capacitance on a data signal, thereby improving the display quality of the display panel and reducing the risk of display defects of the display panel.

[0088] This embodiment provides a display panel, comprising: a substrate, a display structure layer and a touch structure layer disposed on the substrate. The substrate includes a display area and a frame area located around the display area. The frame area includes: a second frame area located on one side of the display area and a first frame area located on the other side of the display area. The display structure layer includes: a plurality of sub-pixels and a plurality of data lines located in the display area, at least one first crack detection line located in the first frame area, and a plurality of data lead lines located in the second frame area. The plurality of data lines are connected to the plurality of sub-pixels and are configured to provide data signals to the plurality of sub-pixels. The plurality of data lead lines are configured to provide data signals to the plurality of data lines. The touch structure layer is located on a side of the display structure layer away from the substrate. The touch structure layer includes at least one second crack detection line located in the first frame area. The at least one first crack detection line and the at least one second crack detection line are connected in series in the second frame area via a plurality of detection connection lines. The orthographic projection of at least one of the plurality of detection connection lines on the substrate overlaps with the orthographic projection of at least one of the plurality of data lead lines on the substrate, and at least two insulating layers are provided between at least a portion of the at least one detection connection line and the at least one data lead line. In some examples, the at least two insulating layers may include: at least one organic insulating layer and at least one inorganic insulating layer. For example, one organic insulating layer and two inorganic insulating layers may be provided between at least a portion of the at least one detection connection line and the at least one data lead line, or two organic insulating layers and three or more inorganic insulating layers may be provided.

[0089] The display panel provided in this embodiment can increase the distance between the detection connection line and the data lead line whose orthographic projection overlaps by setting at least two insulating layers between at least part of the line segment of the detection connection line and the data lead line whose orthographic projection overlaps, thereby reducing the coupling capacitance between the detection connection line and the data lead line, reducing the interference of the coupling capacitance on the data signal, thereby improving the display quality of the display panel and reducing the risk of poor display of the display panel.

[0090] In some exemplary embodiments, the minimum thickness between at least a portion of at least one detection connection line and at least one data lead line may be greater than 2.1 microns. By setting the distance between the detection connection line and the data lead line whose orthographic projections overlap, this example can reduce the coupling capacitance between the detection connection line and the data lead line, thereby reducing interference with the data signal caused by the coupling capacitance.

[0091] In some exemplary embodiments, the display panel may further include: at least one shielding electrode located in the second frame area. In a direction perpendicular to the display panel, the shielding electrode may be located between at least a portion of the line segment of the at least one detection connection line and the at least one data lead-out line. The orthographic projection of the shielding electrode on the substrate may cover the overlapping portion of the orthographic projection of at least one detection connection line and at least one data lead-out line on the substrate. In this example, by providing a shielding electrode in the second frame area, the shielding electrode can be used to separate the detection connection line and the data lead-out line, thereby reducing the coupling capacitance between the detection connection line and the data lead-out line, reducing the interference of the coupling capacitance on the data signal, thereby improving the display quality of the display panel, and reducing the risk of poor display of the display panel.

[0092] In some exemplary embodiments, the display panel may further include: a plurality of first power lines located in the display area and a first power supply line located in the second border area. The plurality of first power lines may be electrically connected to the plurality of sub-pixels, the plurality of first power lines may be connected to the first power supply line, and at least one shielding electrode may be connected to the first power supply line. In some examples, the first power line and the first power supply line may be configured to provide a high-level signal. In this example, by providing a shielding electrode connected to the first power supply line, a shielding effect of the shielding electrode may be achieved.

[0093] In some exemplary embodiments, the first power supply line may include: a first sub-power supply line and a second sub-power supply line that are interconnected, and the first sub-power supply line may be located on a side of the second sub-power supply line close to the substrate. At least one shielding electrode and the first sub-power supply line may be an integrated structure that is interconnected. In some examples, at least a portion of the line segments of at least one detection connection line may be a co-layer structure with the second sub-power supply line. In other examples, at least one shielding electrode and the second sub-power supply line may be an integrated structure that is interconnected; at least a portion of the line segments of at least one detection connection line may be located on a side of the second sub-power supply line that is away from the substrate. In this example, by setting the first power supply line to adopt a double-layer routing structure, it is beneficial to reduce the impedance of the first power supply line; and the shielding electrode and one of the layers of the first power supply line are an integrated structure that is interconnected, which can be beneficial to the arrangement of the shielding electrode and reduce the openings required for connecting the shielding electrode to the first power supply line.

[0094] In some exemplary embodiments, the display structure layer may include at least: a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer disposed on a substrate. An interlayer insulating layer is disposed between the second gate metal layer and the first source / drain metal layer, and at least a first planarizing layer is disposed between the first source / drain metal layer and the second source / drain metal layer. At least a portion of the at least one detection connection line is located in the second source / drain metal layer, and a shielding electrode is located in the first source / drain metal layer. The insulating layer between at least a portion of the at least one detection connection line and the at least one data lead line includes at least an interlayer insulating layer and a first planarizing layer. The inorganic insulating layer between at least a portion of the detection connection line and the data lead line may include an interlayer insulating layer, and the organic insulating layer may include a first planarizing layer. In this example, the interlayer insulating layer and the first planarizing layer are disposed between at least a portion of the detection connection line and the data lead line. This increases the distance between the detection connection line and the data lead line whose orthographic projection overlaps, thereby reducing the coupling capacitance between the detection connection line and the data lead line, and alleviating interference caused by the coupling capacitance on the data signal. However, this embodiment is not limited to this. In other examples, an interlayer insulating layer, a passivation layer, and a first planarizing layer may be provided between the first source-drain metal layer and the second source-drain metal layer, wherein the inorganic insulating layer between at least a portion of the detection connection line and the data lead line may include an interlayer insulating layer and a passivation layer, and the organic insulating layer may include a first planarizing layer.

[0095] In some exemplary embodiments, the touch structure layer may include at least one touch conductive layer, and at least a portion of at least one detection connection line may be located in the touch conductive layer of the touch structure layer. In this example, by locating the detection connection line in the touch conductive layer, the distance between the detection connection line and the data lead line whose orthographic projection overlaps can be increased, thereby reducing the coupling capacitance between the detection connection line and the data lead line, and alleviating interference with the coupling capacitance on the data signal.

[0096] In some exemplary embodiments, the display structure layer may include a plurality of first crack detection lines, and the plurality of first crack detection lines may be symmetrically arranged about the center line of the display panel in the first direction. The touch structure layer may include a plurality of second crack detection lines, and the plurality of second crack detection lines may be symmetrically arranged about the center line of the display panel in the first direction. In some examples, the plurality of detection connection lines in the second frame area may be symmetrically arranged about the center line of the display panel in the first direction. In some examples, each data lead line may overlap with the orthographic projection of the same number of detection connection lines on the substrate. In this example, by symmetrically arranging the crack detection lines and making each data lead line overlap with the same number of detection connection lines, the coupling capacitance between the plurality of data lead lines and the detection connection lines can be maintained consistent, thereby reducing the risk of display defects such as uneven brightness.

[0097] The solution of this embodiment is illustrated below through multiple examples.

[0098] Figure 1 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 1 , the display panel may include a display area AA and a border area surrounding the display area AA. The border area may include a second border area B2 located on one side of the display area AA and a first border area B1 located on the remaining sides of the display area AA. The first border area B1 and the second border area B2 may be connected. For example, the second border area B2 may be the lower border area of ​​the display panel.

[0099] In some examples, as shown in FIG1 , the display area AA may be a flat area including a plurality of sub-pixels PX constituting a pixel array, and the plurality of sub-pixels PX may be configured to display a dynamic image or a still image. The display area AA may be referred to as an active area. In some examples, the display area AA may be circular or elliptical. However, this embodiment is not limited thereto. For example, the display area may be a rectangular or other shape. In some examples, the display panel may be a flexible panel, and thus the display area may be deformable, such as being curled, bent, folded, or rolled up.

[0100] In some examples, as shown in FIG1 , the display panel may include a display structure layer and a touch structure layer sequentially arranged on a substrate. For example, the display panel may integrate a touch structure to form a touch structure on a thin film encapsulation (Touch on Thin Film Encapsulation, referred to as Touch on TFE). The Touch on TFE structure mainly includes a flexible multi-layer surface covering type (FMLOC, Flexible Multi-Layer On Cell) structure and a flexible single-layer surface covering type (FSLOC, Flexible Single-Layer On Cell) structure. The FMLOC structure is based on the working principle of mutual capacitance detection. Generally, two layers of metal are used to form the driving (Tx) electrode and the sensing (Rx) electrode. The driving chip (IC) realizes the touch action by detecting the mutual capacitance between the driving electrode and the sensing electrode. The FSLOC structure is based on the working principle of self-capacitance (or voltage) detection. Generally, a single layer of metal is used to form the touch electrode. The integrated circuit realizes the touch action by detecting the self-capacitance (or voltage) of the touch electrode.

[0101] In some examples, the display structure layer may include: a plurality of sub-pixels PX located in a display area AA, a plurality of gate lines GL, a plurality of data lines DL, and a plurality of first power lines VDD. The plurality of gate lines GL may be arranged along a second direction Y, each gate line GL may extend along a first direction X; the plurality of data lines DL may be arranged along the first direction X, each data line DL may extend along the second direction Y; and the plurality of first power lines VDD may be arranged along the first direction X, each first power line VDD may extend along the second direction Y. The orthographic projections of the plurality of gate lines GL and the plurality of data lines DL on the substrate may intersect to form a plurality of sub-pixel regions. A sub-pixel PX may be disposed within a sub-pixel region. The plurality of data lines DL may be electrically connected to the plurality of sub-pixels PX and may be configured to provide data signals to the plurality of sub-pixels PX. The plurality of gate lines GL may be electrically connected to the plurality of sub-pixels PX and may be configured to provide gate drive signals to the plurality of sub-pixels PX. For example, the gate drive signal may include a scan signal, or may include a scan signal and a light-emitting control signal, or may include a scan signal, a reset control signal, and a light-emitting control signal. A plurality of first power lines VDD may be electrically connected to the plurality of sub-pixels PX, and the plurality of first power lines VDD may be configured to provide a high-level signal to the plurality of sub-pixels PX.

[0102] In some examples, as shown in FIG1 , the first direction X may be an extending direction (e.g., a row direction) of the gate lines GL in the display area AA, and the second direction Y may be an extending direction (e.g., a column direction) of the data lines DL in the display area AA. The first direction X and the second direction Y may intersect each other, for example, may be perpendicular to each other.

[0103] In some examples, a pixel unit of the display area AA may include three sub-pixels, and the three sub-pixels may be a first sub-pixel emitting a first color light (e.g., red light), a second sub-pixel emitting a second color light (e.g., green light), and a third sub-pixel emitting a third color light (e.g., blue light). However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, and the four sub-pixels may be a sub-pixel emitting red light, a sub-pixel emitting green light, a sub-pixel emitting blue light, and a sub-pixel emitting white light. For another example, a pixel unit may include four sub-pixels, and the four sub-pixels may include a sub-pixel emitting red light, a sub-pixel emitting blue light, and two sub-pixels emitting green light.

[0104] In some examples, a sub-pixel may include: a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structure, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0105] In some examples, the multiple transistors in the pixel circuit can be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the difficulty of display panel manufacturing, and improve product yield. In other examples, the multiple transistors in the pixel circuit can include P-type transistors and N-type transistors.

[0106] In some examples, multiple transistors in the pixel circuit may use low-temperature polysilicon thin-film transistors, or may use oxide thin-film transistors, or may use low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor uses low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor uses oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display panel, that is, an LTPS+Oxide (LTPO for short) display panel, can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0107] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, which may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0108] In some examples, the shape of the light-emitting elements of a sub-pixel can be rectangular, rhombus, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern; when a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally, vertically, or in a square pattern. However, this embodiment is not limited to this.

[0109] FIG2 is a partial cross-sectional schematic diagram of the display area of ​​a display panel according to at least one embodiment of the present disclosure. FIG2 illustrates the structure of a sub-pixel in the display area as an example. In this example, the multiple transistors in the pixel circuit are of the same type. For example, the multiple transistors in the pixel circuit can all be low-temperature polysilicon thin-film transistors or oxide thin-film transistors.

[0110] In some examples, as shown in FIG2 , in a direction perpendicular to the display panel, the display area of ​​the display panel may include: a substrate 10, and a circuit structure layer 12, a light-emitting structure layer 13, an encapsulation structure layer 14, and a touch structure layer 15 sequentially disposed on the substrate 10. The display structure layer may include at least: a circuit structure layer 12 and a light-emitting structure layer 13. The circuit structure layer 12 may include at least: pixel circuits for multiple sub-pixels, each of which may include multiple transistors and at least one capacitor. The light-emitting structure layer 13 may include at least: light-emitting elements for multiple sub-pixels.

[0111] In some examples, FIG2 illustrates a thin film transistor 21 and a capacitor 22 included in a sub-pixel as an example. In some examples, the circuit structure layer 12 of the display area may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer disposed on the substrate 10. A first gate insulating layer 101 may be disposed between the semiconductor layer and the first gate metal layer, a second gate insulating layer 102 may be disposed between the first gate metal layer and the second gate metal layer, an interlayer insulating layer 103 may be disposed between the second gate metal layer and the first source-drain metal layer, a passivation layer 104 and a first planarizing layer 105 may be disposed between the first source-drain metal layer and the second source-drain metal layer, and a second planarizing layer 106 may be disposed on the side of the second source-drain metal layer away from the substrate 10. The first gate insulating layer 101, the second gate insulating layer 102, the interlayer insulating layer 103, and the passivation layer 104 may be inorganic insulating layers, and the first planarizing layer 105 and the second planarizing layer 106 may be organic insulating layers. However, this embodiment is not limited to this. In other examples, a buffer layer may be provided on the side of the semiconductor layer close to the substrate. The buffer layer can prevent harmful substances in the substrate from invading the interior of the display panel and can also increase the adhesion of the film layer in the display panel to the substrate. In other examples, only the first planarization layer 105 may be provided between the first source / drain metal layer and the second source / drain metal layer.

[0112] In some examples, as shown in FIG2 , the semiconductor layer in the display area may include at least an active layer 210 of a thin film transistor 21. The active layer 210 of the thin film transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least a gate electrode 213 of the thin film transistor 21 and a first electrode 221 of the capacitor 22. The orthographic projection of the gate electrode 213 of the thin film transistor 21 on the substrate 10 may overlap the orthographic projection of the channel region 2100 of the active layer 210 on the substrate 10. The second gate metal layer may include at least a second electrode 222 of the capacitor 22. The orthographic projections of the second electrode 222 and the first electrode 221 of the capacitor 22 on the substrate 10 may at least partially overlap, for example, they may coincide. The first source / drain metal layer may include at least a first electrode 211 and a second electrode 212 of the thin film transistor 21. The interlayer insulating layer 103 may have multiple vias (e.g., including a first pixel via and a second pixel via) in the display area. The interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the first pixel via can be removed, exposing at least a portion of the surface of the first region 2101 of the active layer 210. The interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the second pixel via can be removed, exposing at least a portion of the surface of the second region 2102 of the active layer 210. The first electrode 211 of the thin-film transistor 21 can be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the second electrode 212 can be electrically connected to the second region 2102 of the active layer 210 through the second pixel via. The second source-drain metal layer may include at least an anode connection electrode 23. The anode connection electrode 23 can be connected to the second electrode 212 of the thin-film transistor 21 through a via formed in the passivation layer 104 and the first planarization layer 105. In some examples, the gate lines of the display area may be located in the first gate metal layer, and the data lines and high-potential power lines of the display area may be located in the second source-drain metal layer. However, this embodiment is not limited to this. In other examples, a third planar layer and a third source-drain metal layer may be provided on the side of the second source-drain metal layer away from the substrate, and the data lines and high-potential power lines of the display area may be located in the third source-drain metal layer.

[0113] In some examples, as shown in FIG2 , the light-emitting structure layer 13 may include a pixel definition layer 134 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133. The first electrode 131 of the light-emitting element may be an anode. The first electrode 131 may be disposed on the second planar layer 106 and electrically connected to the anode connection electrode 23 through a pixel via provided in the second planar layer 106. The pixel definition layer 134 is disposed on the first electrode 131 and the second planar layer 106. The pixel definition layer 134 may have multiple pixel openings, each of which may expose at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 may be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 may be disposed on the organic light-emitting layer 132 and connected to the organic light-emitting layer 132. Driven by the first electrode 131 and the second electrode 133, the organic light-emitting layer 132 may emit light of a corresponding color.

[0114] In some examples, the organic light-emitting layer 132 of the light-emitting element may include an emitting layer (EML), and one or more of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Driven by the voltage of the first electrode 131 and the second electrode 133, the light-emitting properties of the organic material can be utilized to emit light according to the required grayscale.

[0115] In some examples, the light-emitting layers of light-emitting elements emitting light of different colors may be different. For example, a red light-emitting element may include a red light-emitting layer, a green light-emitting element may include a green light-emitting layer, and a blue light-emitting element may include a blue light-emitting layer. In order to reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may adopt a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may adopt a common layer. In some examples, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer can be made by a single process (a single evaporation process or a single inkjet printing process), and isolation is achieved by means of a surface step difference of the formed film layer or by surface treatment. For example, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer corresponding to adjacent sub-pixels may be isolated. In some examples, the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM) or an open mask (Open Mask), or by inkjet technology.

[0116] In some examples, as shown in FIG2 , the encapsulation structure layer 14 may include a stacked first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143. The first encapsulation layer 141 and the third encapsulation layer 143 may be made of an inorganic material, and the second encapsulation layer 142 may be made of an organic material. The second encapsulation layer 142 may be disposed between the first encapsulation layer 141 and the third encapsulation layer 143 to prevent external moisture from entering the light-emitting element. However, this embodiment is not limited to this. For example, the encapsulation structure layer may have a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0117] In some examples, the touch structure layer 15 may include multiple touch units. At least one touch unit may include at least one touch electrode. The orthographic projection of at least one touch electrode on the substrate may include the orthographic projections of multiple sub-pixels on the substrate. When the touch unit includes multiple touch electrodes, the multiple touch electrodes may be arranged at intervals, and adjacent touch electrodes may be connected to each other through connecting portions. The touch electrodes and the connecting portions may be in the same layer structure. In some examples, the touch electrode may have a rhombus shape, for example, a regular rhombus, a horizontally long rhombus, or a vertically long rhombus. However, this embodiment is not limited to this. In some examples, the touch electrode may have any one or more of a triangle, a square, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygons.

[0118] In some examples, taking the display panel as an FSLOC structure as an example, the touch structure layer 15 may include: a touch buffer layer, a first touch conductive layer, and a touch protection layer sequentially arranged on the packaging structure layer 14. The first touch conductive layer may include: a plurality of touch electrodes and a plurality of connection portions. In other examples, taking the display panel as an FMLOC structure as an example, the touch structure layer 15 may include: a touch buffer layer, a first touch conductive layer, a touch insulating layer, a second touch conductive layer, and a touch protection layer sequentially arranged on the packaging structure layer 14. For example, the first touch conductive layer may include a plurality of connection portions, and the second touch conductive layer may include a plurality of touch electrodes. However, this embodiment is not limited to this.

[0119] In some examples, as shown in FIG1 , the second border area B2 may include: a first fan-out area B21, a bending area B22, a second fan-out area B23, a first signal access area B24, and a second signal access area B25, which are sequentially arranged in a direction away from the display area AA. The first fan-out area B21 may be connected to the first border area B1 and located on one side of the display area AA. The first fan-out area B21 may be provided with a plurality of data fan-out lines and a first power transmission line. The plurality of data fan-out lines may be connected to the plurality of data lines DL of the display area AA, and the first power transmission line may be connected to the plurality of first power lines VDD of the display area AA.

[0120] In some examples, as shown in Figure 1, the bending region B22 can be connected to the first fan-out region B21 and the second fan-out region B23 and located on the side of the first fan-out region B21 away from the display area AA. The bending region B22 can bend the second fan-out region B23, the first signal access region B24, and the second signal access region B25 toward the back of the display area AA. The bending region B22 can include multiple curved connecting lines to connect the traces transmitting the same signal in the first fan-out region B21 and the second fan-out region B23.

[0121] In some examples, as shown in FIG1 , the second fan-out region B23 can be located on a side of the bending region B22 away from the display area AA. The second fan-out region B23 can be provided with multiple data lead lines 323 and a first power supply line 326. The multiple data lead lines 323 can be connected to the multiple data fan-out lines in the first fan-out region B21 via multiple data bending lines in the bending region B22 to provide data signals to the multiple data lines DL in the display area AA. The first power supply line 326 can be connected to the first power transmission line in the first fan-out region B21 via a first voltage bending line in the bending region B22 to connect to the multiple first power lines VDD in the display area AA.

[0122] In some examples, as shown in FIG1 , the first signal access area B24 may be located on a side of the second fan-out area B23 away from the display area AA. The first signal access area B24 may be configured to set a driver chip (IC). For example, the driver chip set in the first signal access area B24 may be a touch and display driver integrated chip (TDDI). The first signal access area B24 may also be referred to as a driver chip setting area. The driver chip may be configured to generate data signals required to drive sub-pixels, provide touch drive signals to the touch unit and receive touch signals generated by the touch unit, generate crack detection drive signals and receive crack detection signals.

[0123] In some examples, as shown in FIG1 , the second signal access area B25 can be located on a side of the first signal access area B24 away from the display area AA. The second signal access area B25 can be provided with multiple contact pads, which can be configured to bind a flexible printed circuit (FPC) so that multiple signal lines (e.g., power lines, control signal lines, etc.) are connected to an external control device through the multiple contact pads. The second signal access area B25 can also be referred to as a circuit binding area.

[0124] In some examples, the display panel may include a crack detection circuit (PCD, Panel Crack Detection), which may be configured to detect whether the display panel has cracks. For example, the crack detection circuit may include: at least one first crack detection line and at least one second crack detection line. The first crack detection line may be configured to detect whether there are cracks in the display structure layer, and the second crack detection line may be configured to detect whether there are cracks in the touch structure layer. The first crack detection line and the second crack detection line may use a resistance detection method to perform crack detection. The resistance detection method refers to: detecting the resistance of the crack detection line from both ends of the crack detection line to determine whether the crack detection line is broken, and then inferring whether the display panel is broken. In some examples, the first crack detection line and the second crack detection line may be connected to a driver IC, and the driver IC may control the crack detection process of the display panel.

[0125] FIG3 is a schematic diagram of crack detection for a display panel according to at least one embodiment of the present disclosure. In some examples, as shown in FIG3 , the display structure layer may include a first crack detection line 311 located at least in the first border region B1; the touch structure layer may include a second crack detection line 312 located at least in the first border region B1. This example is described using a first crack detection line 311 and a second crack detection line 312 as examples. Within the first border region B1, the first crack detection line 311 and the second crack detection line 312 may surround the periphery of the display region AA, and the first crack detection line 311 may be located on the side of the second crack detection line 312 away from the display region AA. In other words, within the first border region B1, the first crack detection line 311 may surround the periphery of the second crack detection line 312. However, this embodiment is not limited to this. In other examples, the orthographic projections of the first crack detection line and the second crack detection line on the substrate may overlap.

[0126] In some examples, the first crack detection line 311 may include a first end 3111 and a second end 3112. The first end 3111 and the second end 3112 may extend from the first border area B1 to the first fan-out area of ​​the second border area B2. The second crack detection line 312 may include a first end 3121 and a second end 3122. The first end 3121 and the second end 3122 of the second crack detection line 312 may extend from the first border area B1 to the first fan-out area of ​​the second border area B2. In the first direction X, the first end 3111 of the first crack detection line 311, the first end 3121 of the second crack detection line 312, the second end 3122 of the second crack detection line 312, and the second end 3112 of the first crack detection line 311 may be arranged in sequence.

[0127] In some examples, the bending area B22 of the second border area B2 may include at least: a plurality of detection bending lines (for example, including: first detection bending lines 331a and 331b, second detection bending lines 332a and 332b). The first detection bending lines 331a and 331b, and the second detection bending lines 332a and 332b may be arranged in sequence along the first direction X. The first detection bending line 331a may be connected to the first end 3111 of the first crack detection line 311, and the first detection bending line 331b may be connected to the first end 3121 of the second crack detection line 312. The second detection bending line 332a may be connected to the second end 3122 of the second crack detection line 312, and the second detection bending line 332b may be connected to the second end 3112 of the first crack detection line 311.

[0128] In some examples, the second fan-out area B23 of the second frame area B2 may include at least: a plurality of detection connection lines (for example, including: a first detection connection line 321, a second detection connection line 322a and a second detection connection line 322b). One end of the first detection connection line 321 may be connected to the first end 3111 of the first crack detection line 311 through a first detection bending line 331a, and the other end may be connected to the first end 3121 of the second crack detection line 312 through a first detection bending line 331b. The first detection connection line 321 may connect the first end 3111 of the first crack detection line 311 and the first end 3121 of the second crack detection line 312 in series. The second detection connection line 322a may be connected to the second end 3122 of the second crack detection line 312 through a second detection bending line 332a, and the second detection connection line 322b may be connected to the second end 3112 of the first crack detection line 311 through a second detection bending line 332b.

[0129] In some examples, the first signal access area B24 may include: at least two detection contact pads (for example, including at least one first detection contact pad 341 and at least one second detection contact pad 342). The first detection contact pad 341 and the second detection contact pad 342 may be arranged along a side of the first signal access area B24 close to the display area AA. The second detection connection line 322a may be connected to the first detection contact pad 341, and the second detection connection line 322b may be connected to the second detection contact pad 342. The second detection connection lines 322a and 322b can realize the connection between the first crack detection line 311 and the second crack detection line 312 connected in series and the detection contact pads.

[0130] In this example, the first end 3111 of the first crack detection line 311 can be connected to the first end 3121 of the second crack detection line 312 via the first detection bending line 331a, the first detection connecting line 321, and the first detection bending line 331b, respectively. The second end 3122 of the second crack detection line 312 can be connected to the first detection contact pad 341 via the second detection bending line 332a and the second detection connecting line 322a, respectively. The second end 3112 of the first crack detection line 311 can be connected to the second detection contact pad 342 via the second detection bending line 332b and the second detection connecting line 322b, respectively. In this way, the first crack detection line 311 and the second crack detection line 312 can be connected in series between the first detection contact pad 341 and the second detection contact pad 342. For example, the second detection contact pad 342 can transmit a crack detection drive signal generated by a driver IC, and the driver IC determines whether a crack has occurred in the display panel by detecting the crack detection signal received by the first detection contact pad 341.

[0131] Figure 4 is a partial schematic diagram of the second frame region of a display panel according to at least one embodiment of the present disclosure. Figure 5 is a schematic diagram of the wiring arrangement of the bending region of the second frame region according to at least one embodiment of the present disclosure.

[0132] In some examples, as shown in Figures 4 and 5, the first end 3111 and the second end 3112 of the first crack detection line 311 in the first border region, and the first end 3121 and the second end 3122 of the second crack detection line 312 can extend to the first fan-out region B21 of the second border region B2. The first fan-out region B21 of the second border region B2 can also include: multiple data fan-out lines, multiple drive fan-out lines, multiple touch fan-out lines, a first power transmission line 316, and second power transmission lines 317a and 317b.

[0133] In some examples, multiple data fan-out lines can be connected to multiple data lines of the display area AA. For example, the first border area B1 can be provided with multiple multiplexing circuits (MUX), and the multiple data fan-out lines and the multiple data lines can be connected to the multiple multiplexing circuits so as to transmit the data signal provided by each data fan-out line to the multiple data lines (for example, three, six or nine data lines). The multiple data fan-out lines may include: a first group of data fan-out lines 313a and a second group of data fan-out lines 313b. For example, the first group of data fan-out lines 313a can be connected to the multiple data lines in the left half of the display area AA, and the second group of data fan-out lines 313b can be connected to the multiple data lines in the right half of the display area AA.

[0134] In some examples, the plurality of data fan-out lines may include: a plurality of first data fan-out lines located in the first gate metal layer (such as the first data fan-out line 3131 shown in FIG8 ) and a plurality of second data fan-out lines located in the second gate metal layer (such as the second data fan-out line 3132 shown in FIG8 ). The plurality of first data fan-out lines and the plurality of second data fan-out lines may be arranged at intervals along the first direction X, and the orthographic projections of the first data fan-out lines and the second data fan-out lines on the substrate may not overlap. In this example, by alternately arranging the plurality of data fan-out lines in two conductive layers, it is beneficial to save gaps between adjacent traces, thereby saving arrangement space for the data fan-out lines.

[0135] In some examples, a plurality of drive fan-out lines can be configured to provide a drive signal (e.g., including a clock signal, a drive control signal, and a start signal) to at least one gate drive circuit provided in the first border area B1. The plurality of drive fan-out lines may include: a first group of drive fan-out lines 314a, a second group of drive fan-out lines 314b, and a third group of drive fan-out lines 314c. The third group of drive fan-out lines 314c may be located between the first group of drive fan-out lines 314a and the second group of drive fan-out lines 314b, the first group of drive fan-out lines 314a may be located on one side of the first group of data fan-out lines 313a in the opposite direction of the first direction X, the second group of drive fan-out lines 314b may be located on one side of the second group of data fan-out lines 313b in the first direction X, and the third group of drive fan-out lines 314c may be located between the first group of data fan-out lines 313a and the second group of data fan-out lines 313b. In some examples, the first and second drive fan-out lines 314a and 314b may be located in the second gate metal layer, and the third drive fan-out line 314c may be located in the first gate metal layer. However, this embodiment is not limited thereto.

[0136] In some examples, multiple touch fan-out lines can be configured to be connected to multiple touch connection lines set in the first frame area B1, and the multiple touch connection lines can be connected to multiple touch units in the display area AA to transmit touch signals. The multiple touch fan-out lines may include: a first group of touch fan-out lines 315a and a second group of touch fan-out lines 315b. The first group of touch fan-out lines 315a can be located between the first group of data fan-out lines 313a and the third group of drive fan-out lines 314c, and the second group of touch fan-out lines 315b can be located between the second group of data fan-out lines 313b and the third group of drive fan-out lines 314c. In some examples, the multiple touch fan-out lines of the first group of touch fan-out lines 315a and the second group of touch fan-out lines 315b can be located in the first touch conductive layer. However, this embodiment is not limited to this. In other examples, the multiple touch fan-out lines can be located in the second touch conductive layer.

[0137] In some examples, the first power transmission line 316 can be located in the second source / drain metal layer, or can be a dual-layer trace located in both the first source / drain metal layer and the second source / drain metal layer. The orthographic projection of the first power transmission line 316 on the substrate can partially overlap with the orthographic projections of the first group of touch fan-out lines 315a, the second group of touch fan-out lines 315b, and the third group of drive fan-out lines 314c on the substrate.

[0138] In some examples, the second power transmission line 317a can be located on a side of the first group of data fan-out lines 313a away from the first power transmission line 316, and the second power transmission line 317b can be located on a side of the second group of data fan-out lines 313b away from the first power line 316. The second power transmission line 317a and the second power transmission line 317b can be located in the second source-drain metal layer, or can be a double-layer trace located in the first source-drain metal layer and the second source-drain metal layer.

[0139] In some examples, the first end 3111 of the first crack detection line 311 can be located between the second power transmission line 317a and the first set of data fan-out lines 313a. The first end 3111 of the first crack detection line 311 can be located in the first gate metal layer. The second end 3112 of the first crack detection line 311 can be located between the second power transmission line 317b and the second set of data fan-out lines 313b. The second end 3112 of the first crack detection line 311 can be located in the first gate metal layer. The first crack detection line 311 can be located in the second gate metal layer in the first border region, or in the first source and drain metal layer, or can be arranged in a winding manner between the second gate metal layer and the first source and drain metal layer.

[0140] In some examples, the first end 3121 of the second crack detection line 312 can be located between the first group of data fan-out lines 313a and the first group of drive fan-out lines 315a. The second end 3122 of the second crack detection line 312 can be located between the second group of data fan-out lines 313b and the second group of drive fan-out lines 315b. The orthographic projections of the first end 3121 and the second end 3122 of the second crack detection line 312 on the substrate can partially overlap with the orthographic projections of the first power transmission line 316 on the substrate. The first end 3121 and the second end 3122 of the second crack detection line 312 can be located in the first touch conductive layer. The second crack detection line 312 can be located in the first touch conductive layer in the first border area B1. However, this embodiment is not limited to this. In other examples, the second crack detection line can be located in the second touch conductive layer.

[0141] In some examples, as shown in Figures 4 and 5, the bending region B22 may include multiple bending connection lines, for example, including first detection bending lines 331a and 331b, second detection bending lines 332a and 332b, multiple data bending lines (including a first group of data bending lines 333a and a second group of data bending lines 333b), multiple drive bending lines (including a first group of drive bending lines 334a, a second group of drive bending lines 334b, and a third group of drive bending lines 334c), multiple touch bending lines (including a first group of touch bending lines 335a and a second group of touch bending lines 335b), multiple first power bending lines (including first power bending lines 336a, 336b, 336c, and 336d), and multiple second power bending lines (including, for example, second power bending lines 337a and 337b). Figures 4 and 5 provide overall schematic diagrams of adjacent bending connection lines of the same type.

[0142] In some examples, within the bending area B22, the first group of drive bending lines 334a, the second power bending line 337a, the first detection bending line 331a, the first group of data bending lines 333a, the first power bending line 336a, the first detection bending line 331b, the first group of touch bending lines 335a, the first power bending line 336b, the third group of drive bending lines 334c, the first power bending line 336c, the second group of touch bending lines 335b, the second detection bending line 332a, the first power bending line 336d, the second group of data bending lines 333b, the second detection bending line 332b, the second power bending line 337b and the second group of drive bending lines 334b ​​can be arranged in sequence along the first direction X.

[0143] In some examples, the first group of drive bending lines 334a can be connected to the first group of drive fan-out lines 314a; the second group of drive bending lines 334b ​​can be connected to the second group of drive fan-out lines 314b; and the third group of drive bending lines 334c can be connected to the third group of drive fan-out lines 314c. The first group of data bending lines 333a can be connected to the first group of data fan-out lines 313a, and the second group of data bending lines 333b can be connected to the second group of data fan-out lines 313b. The first group of touch bending lines 335a can be connected to the first group of touch fan-out lines 315a, and the second group of touch bending lines 335b can be connected to the second group of touch fan-out lines 315b. The first power bending lines 336a, 336b, 336c, and 336d can be connected to the first power transmission line 316. The second power meandering line 337a may be connected to the second power transmission line 317a, and the second power meandering line 337b may be connected to the second power transmission line 317b.

[0144] In some examples, the first detection bending line 331a may be connected to the first end 3111 of the first crack detection line 311, and the first detection bending line 331b may be connected to the first end 3121 of the second crack detection line 312. The second detection bending line 332a may be connected to the second end 3122 of the second crack detection line 312, and the second detection bending line 332b may be connected to the second end 3112 of the first crack detection line 311.

[0145] In some examples, the multiple curved connection lines within the bending region B22 can be disposed in the same layer, for example, all located in the second source / drain metal layer. However, this embodiment is not limited to this. In other examples, the multiple curved connection lines in the bending region can be located in the first source / drain metal layer or the third source / drain metal layer.

[0146] In some examples, the second fan-out area B23 may include: a first detection connection line 321, a second detection connection line 322a and 322b, multiple data lead lines (for example, including a first group of data lead lines 323a and a second group of data lead lines 323b), multiple drive lead lines (for example, including a first group of drive lead lines 324a, a second group of drive lead lines 324b and a third group of drive lead lines 324c), multiple touch lead lines (for example, including a first group of touch lead lines 325a and a second group of touch lead lines 325b), a first power supply line 326, and second power supply lines 327a and 327b.

[0147] In some examples, the first signal access area B24 may include: multiple detection contact pads (for example, including at least one first detection contact pad 341 and at least one second detection contact pad 342), multiple data contact pads (for example, including a first group of data contact pads 343a and a second group of data contact pads 343b), multiple touch contact pads 344, and multiple transmission contact pads 345.

[0148] In some examples, the plurality of transmission contact pads 345 can be arranged along the first direction X and along a side of the first signal access area B24 away from the display area AA. The plurality of transmission contact pads 345 can be connected to the plurality of contact pads in the second signal access area B25 via a plurality of pin connection lines.

[0149] In some examples, multiple detection contact pads, multiple data contact pads, and multiple touch contact pads can be arranged along a side of the first signal access area B24 near the display area AA. Multiple data contact pads and multiple touch contact pads 344 can be located between the first detection contact pad 341 and the second detection contact pad 342. Multiple touch contact pads 344 can be located between the first group of data contact pads 343a and the second group of data contact pads 343b. The first detection contact pad 341 can be located on a side of the first group of data contact pads 343a away from the touch contact pads 344, and the second detection contact pad 342 can be located on a side of the second group of data contact pads 343b away from the touch contact pads 344.

[0150] In some examples, the first group of drive leads 324a can be connected to the first group of drive bending lines 334a, the second group of drive leads 324b can be connected to the second group of drive bending lines 334b, and the third group of drive leads 324c can be connected to the third group of drive bending lines 334c. The first group of drive leads 324a can extend generally along a third direction F3, which intersects both the first direction X and the second direction Y. The second group of drive leads 324b can extend generally along a fourth direction F4, which intersects both the first direction X and the second direction Y and intersects the third direction F3. For example, the third direction F3 and the fourth direction F4 can be generally symmetrical about the second direction Y. The third group of drive leads 324c can extend in the second direction Y, the first direction X, and the fourth direction F4 in sequence. The third group of drive leads 324c can be located in the middle of the plurality of drive leads of the second group of drive leads 324b.

[0151] In some examples, the first group of driving lead lines 324a, the second group of driving lead lines 324b, and the third group of driving lead lines 324c may be located in the second gate metal layer. However, this embodiment is not limited thereto.

[0152] In some examples, the first set of data lead lines 323a can be connected to the first set of data bending lines 333a; the second set of data lead lines 323b can be connected to the second set of data bending lines 333b. The first set of data lead lines 323a and the second set of data lead lines 323b can extend substantially along the second direction Y. The first set of data lead lines 323a can be connected to the first set of data contact pads 343a within the first signal access area B24, and the second set of data lead lines 323b can be connected to the second set of data contact pads 343b within the first signal access area B24.

[0153] In some examples, the plurality of data lead lines may include: a plurality of first data lead lines (as shown in FIG6 , first data lead lines 3231) located in the first gate metal layer and a plurality of second data lead lines (as shown in FIG6 , second data lead lines 3232) located in the second gate metal layer. The plurality of first data lead lines and the plurality of second data lead lines may be spaced apart along the first direction X, and the orthographic projections of the first data lead lines and the second data lead lines on the substrate may not overlap. In this example, by alternately arranging the plurality of data lead lines in two conductive layers, it is possible to save space between adjacent traces, thereby saving space for arranging the data lead lines.

[0154] In some examples, the first group of touch lead lines 325a can be connected to the first group of touch bending lines 335a, and the second group of touch lead lines 325b can be connected to the second group of touch bending lines 335b. The first group of touch lead lines 325a and the second group of touch lead lines 325b can extend substantially along the second direction Y and connect to the plurality of touch contact pads 344 within the first signal access area B24. The first group of touch lead lines 325a and the second group of touch lead lines 325b can be located between the first group of data lead lines 323a and the second group of data lead lines 323b.

[0155] In some examples, the plurality of touch lead lines of the first group of touch lead lines 325a and the second group of touch lead lines 325b may be located in the first touch conductive layer. However, this embodiment is not limited thereto. In other examples, the plurality of touch lead lines may be located in the second touch conductive layer.

[0156] In some examples, the second power supply line 327a can be connected to the second power meander line 337a, and the second power supply line 327b can be connected to the second power meander line 337b. The second power supply line 327a can extend substantially along the third direction F3 and be located between the first group of driving lead lines 324a and the first power supply line 326. The second power supply line 327b can extend substantially along the fourth direction F4 and be located between the second group of driving lead lines 324b and the first power supply line 326.

[0157] In some examples, the second power supply lines 327a and 327b may be located in the second source-drain metal layer, or may be double-layer lines located in the first source-drain metal layer and the second source-drain metal layer, which is not limited in this embodiment.

[0158] In some examples, the first power supply line 326 can be connected to the first power zigzag lines 336a, 336b, 336c, and 336d. The first power supply line 326 can include a first power extension section 3261, a second power extension section 3262, and a third power extension section 3263. The first power extension section 3261 can be connected between the second power extension section 3262 and the third power extension section 3263. The first power extension section 3261 can be generally strip-shaped, extending along the first direction X, the second power extension section 3262 can be generally strip-shaped, extending along the third direction F3, and the third power extension section 3263 can be generally strip-shaped, extending along the fourth direction F4. The first power extension section 3261 can be connected to the first power zigzag lines 336a, 336b, 336c, and 336d in a one-to-one correspondence via four protrusions.

[0159] In some examples, the first power supply line 326 may be a double-layered line located in the first source-drain metal layer and the second source-drain metal layer. However, this embodiment is not limited to this. In other examples, the first power supply line may be located in the second source-drain metal layer or the first source-drain metal layer.

[0160] In some examples, the first detection connection line 321 may include: a first extension section 3211, a second extension section 3212, and a third extension section 3213 connected in sequence. The first extension section 3211 and the third extension section 3213 may be roughly straight lines extending along the second direction Y, and the second extension section 3212 may be roughly straight lines extending along the first direction X. The second extension section 3212 is connected between the first extension section 3211 and the third extension section 3213. The first extension section 3211 may be connected to the first detection bend line 331a, and the third extension section 3213 may be connected to the first detection bend line 331b. In this example, the first end 3111 of the first crack detection line 311 and the first end 3121 of the second crack detection line 312 may be connected in series through the first detection connection line 321, the first detection bend lines 331a, and 331b.

[0161] In some examples, the first extension section 3211 of the first detection connection line 321 can be located between the second power supply line 327a and the first group of data lead lines 323a, and the third extension section 3213 can be located between the first group of data lead lines 323a and the first group of touch lead lines 325a. The second extension section 3212 spans the first group of data lead lines 323a to connect the first extension section 3211 and the third extension section 3213. The orthographic projection of the second extension section 3212 on the substrate overlaps with the orthographic projection of the first group of data lead lines 323a on the substrate.

[0162] In some examples, the second detection connection line 322a may include: a fourth extension section 3221, a fifth extension section 3222, and a sixth extension section 3223, which are connected in sequence. The fourth extension section 3221 may be roughly in the shape of a zigzag line extending along the second direction Y. The fifth extension section 3222 may be roughly in the shape of a zigzag line extending along the first direction X. The sixth extension section 3223 may be roughly in the shape of a zigzag line extending along the second direction Y. The fifth extension section 3222 may be connected between the fourth extension section 3221 and the sixth extension section 3223. The fourth extension section 3221 may be connected to the second detection bending line 332a, and the sixth extension section 3223 may be connected to the first detection contact pad 341 within the first signal access area B24. The fifth extension section 3222 may be located on the side of the first detection connection line 321 away from the bending area B22. For example, at least a portion of the fifth extending section 3222 and the second extending section 3212 of the first detection connection line 321 may be parallel to the first direction X and arranged sequentially in the second direction Y.

[0163] In some examples, the fourth extension segment 3221 of the second detection connection line 322a can be located between the second group of touch lead lines 325b and the second group of data lead lines 323b, and the sixth extension segment 3223 can be located between the first group of data lead lines 323a and the second power extension segment 3262 of the first power supply line 326. The fifth extension segment 3222 spans the first group of data lead lines 323a, the first group of touch lead lines 325a, and the second group of touch lead lines 325b to connect the fourth extension segment 3221 and the sixth extension segment 3223. The orthographic projection of the fifth extension segment 3222 on the substrate overlaps with the orthographic projection of the first group of data lead lines 323a on the substrate.

[0164] In some examples, the second detection connection line 322b can be roughly in the shape of a broken line extending along the second direction Y. One end of the second detection connection line 322b can be connected to the second bending detection line 332b, and the other end can be connected to the second detection contact pad 342 in the first signal access area B24. The second detection connection line 322b can be located between the second group of data lead lines 323b and the second power supply line 327b. A portion of the second detection connection line 322b can be located between the second power supply line 327b and the third power extension section 3263 of the first power supply line 326. The orthographic projection of the second detection connection line 322b on the substrate may not overlap with the orthographic projection of the data lead line on the substrate.

[0165] In some examples, by connecting the first crack detection line 311 and the second crack detection line 312 in series, multiple data lead lines (for example, including the first group of data lead lines 323a) and the detection connection line (for example, including the second extension section 3212 of the first detection connection line 321 and the fifth extension section 3222 of the second detection connection line 322a) in the second border area B2 overlap in the positive projection of the substrate, thereby forming an overlapping capacitance. The change of the crack detection signal transmitted by the detection connection line can easily cause the jump of the data signal, which will cause the data signal transmitted by the data lead line to be interfered by the parasitic capacitance, thereby causing uneven brightness and Mura-type display defects. In this example, the parasitic capacitance between the detection connection line and the data lead line can be shielded by setting a shielding electrode, or the overlapping capacitance between the detection signal and the data signal can be reduced by increasing the minimum thickness between the detection connection line and the data lead line, thereby reducing uneven brightness and Mura-type display defects.

[0166] Figure 6 is a partially enlarged schematic diagram of region C1 in Figure 4 . Figure 7A is a partially cross-sectional schematic diagram along the Q1-Q1' direction in Figure 6 . Figure 7B is another partially cross-sectional schematic diagram along the Q1-Q1' direction in Figure 6 . In some examples, as shown in Figures 4 and 6 , the first group of data lead lines 323a may include: a plurality of first data lead lines 3231 located in the first gate metal layer and a plurality of second data lead lines 3232 located in the second gate metal layer. The plurality of first data lead lines 3231 and the plurality of second data lead lines 3232 may be spaced apart along the first direction X, and the orthographic projections of the first data lead lines 3231 and the second data lead lines 3232 on the substrate may not overlap.

[0167] In some examples, the first power supply line 326 may include a first sub-power supply line 326-1 located in the first source / drain metal layer and a second sub-power supply line 326-2 located in the second source / drain metal layer. The second sub-power supply line 326-2 is connected to the first sub-power supply line 326-1. For example, the orthographic projection of the second sub-power supply line 326-2 on the substrate may overlap the orthographic projection of the first sub-power supply line 326-1 on the substrate. This embodiment is not limited to this.

[0168] In some examples, the second border region B2 may include a shielding electrode 351. The shielding electrode 351 may be located in the first source / drain metal layer. The orthographic projection of the shielding electrode 351 on the substrate may be substantially rectangular. The shielding electrode 351 may be located on a side of the first power extension 3261 of the first power supply line 326 away from the bending region B22. The shielding electrode 351 and the first sub-power supply line 326-1 of the first power supply line 326 may be interconnected and integrally formed.

[0169] In some examples, the second extension section 3212 of the first detection connection line 321 and the fifth extension section 3222 of the second detection connection line 322a can both be located in the second source-drain metal layer. The shielding electrode 351 can partially overlap with the second extension section 3212 of the first detection connection line 321 and the fifth extension section 3222 of the second detection connection line 322a in their orthographic projections on the substrate. The overlapping portion of the second extension section 3212 of the first detection connection line 321 and the multiple data lead lines (including the multiple first data lead lines 3231 and the second data lead lines 3232) in their orthographic projections on the substrate can be located within the orthographic projection range of the shielding electrode 351 in the substrate. The overlapping portion of the fifth extension section 3222 of the second detection connection line 322a and the multiple data lead lines (including the multiple first data lead lines 3231 and the second data lead lines 3232) in their orthographic projections on the substrate can be located within the orthographic projection range of the shielding electrode 351 in the substrate. In other words, the shielding electrode 351 can cover the overlapping portion of the first detection line 321 and the second detection line 322a with the orthographic projection of the first group of data lead lines on the substrate. In this example, by providing a shielding electrode connected to the first power supply line to cover the data lead lines that overlap with the orthographic projection of the detection connection line, it can help reduce the coupling capacitance between the data lead lines and the detection connection lines.

[0170] In some examples, as shown in FIG7A , a second gate insulating layer 102, an interlayer insulating layer 103, a shielding electrode 351, a passivation layer 104, and a first planarizing layer 105 may be disposed between the second extension 3212 of the first detection connection line 321 located in the second source / drain metal layer and the first data lead line 3231 located in the first gate metal layer. An interlayer insulating layer 103, a shielding electrode 351, a passivation layer 104, and a first planarizing layer 105 may also be disposed between the second extension 3212 of the first detection connection line 321 located in the second source / drain metal layer and the second data lead line 3232 located in the second gate metal layer. At least a shielding electrode 351 and three insulating layers (including the interlayer insulating layer 103, the passivation layer 104, and the first planarizing layer 105) are disposed between the data lead line and the second extension 3212 of the first detection connection line 321.

[0171] In some examples, the minimum thickness between the second extension section 3212 of the first detection connection line 321 and the data lead line can be the minimum distance between the surface of the second extension section 3212 close to the substrate 10 and the surface of the data lead line away from the substrate 10. For example, it can be the minimum distance between the surface of the second data lead line 3232 away from the substrate 10 and the surface of the second extension section 3212 close to the substrate 10. For example, the minimum thickness h1 can be greater than 2.1 microns. In this example, by increasing the minimum thickness between the second extension section 3212 of the first detection connection line 321 and the data lead line, the coupling capacitance between the first detection connection line and the data lead line can be reduced. Similarly, the minimum thickness between the fifth extension section 3222 of the second detection connection line 322a and the data lead line can be greater than 2.1 microns.

[0172] In some examples, the thickness of the passivation layer 104 can be 0.025 microns to 0.033 microns, such as approximately 0.03 microns; the thickness of the first planar layer 105 can be 1.35 microns to 1.65 microns, such as approximately 1.5 microns. In this example, the thickness of the film layer refers to the vertical distance between the surface of the film layer away from the substrate and the surface of the film layer close to the substrate.

[0173] In some examples, as shown in FIG7B , a second gate insulating layer 102, an interlayer insulating layer 103, a shielding electrode 351, and a first planarizing layer 105 may be disposed between the second extension 3212 of the first detection connection line 321 located in the second source / drain metal layer and the first data lead line 3231 located in the first gate metal layer. Interlayer insulating layer 103, a shielding electrode 351, and a first planarizing layer 105 may also be disposed between the second extension 3212 of the first detection connection line 321 located in the second source / drain metal layer and the second data lead line 3232 located in the second gate metal layer. At least a shielding electrode 351 and two insulating layers (including the interlayer insulating layer 103 and the first planarizing layer 105) are disposed between the data lead line and the second extension 3212 of the first detection connection line 321. The remaining description of this example can be referred to the description of the aforementioned embodiment, and therefore will not be repeated here.

[0174] Figure 8 is a partial schematic diagram of the second border area of ​​at least one embodiment of the present disclosure, illustrating the connection and positional relationship between the first set of data fan-out lines, the first set of data bending lines, the first set of data lead-out lines, the first detection connection lines, and some line segments of the second detection connection lines.

[0175] In some examples, as shown in FIG8 , the first group of data fan-out lines may include: a plurality of first data fan-out lines 3131 located in the first gate metal layer and a plurality of second data fan-out lines 3132 located in the second gate metal layer. The plurality of first data fan-out lines 3131 and the plurality of second data fan-out lines 3132 may be spaced apart along a first direction X, and the orthographic projections of the first data fan-out lines 3131 and the second data fan-out lines 3132 on the substrate may not overlap. In other words, the distance between the orthographic projections of adjacent first data fan-out lines 3131 and second data fan-out lines 3132 on the substrate is greater than zero. The first data fan-out lines 3131 and the second data fan-out lines 3132 may be respectively connected to the data fold lines 333 located in the second source / drain metal layer.

[0176] In some examples, the first set of data lead lines may include: a plurality of first data lead lines 3231 located in the first gate metal layer and a plurality of second data lead lines 3232 located in the second gate metal layer. The first data lead lines 3231 and the second data lead lines 3232 may be respectively connected to data fold lines 333 located in the second source / drain metal layer. The data fold lines 333 may connect corresponding data lead lines and data fan-out lines to implement data signal transmission.

[0177] In some examples, the first end 3111 of the first crack detection line 311 can be located in the first gate metal layer and connected to the first detection meander line 331a located in the second source / drain metal layer. The first detection meander line 331a can also be connected to the first extension section 3211 of the first detection connection line 321 located in the first gate metal layer. The first extension section 3211 can be connected to the second extension section 3212 located in the second source / drain metal layer. The second extension section 3212 can be connected to the third extension section 3213 located in the first gate metal layer. The third extension section 3213 can be connected to the first detection meander line 331b located in the second source / drain metal layer. The first detection meander line 331b can be connected to the first end 3121 of the second crack detection line 312 located in the first touch conductive layer.

[0178] In some examples, the touch fan-out lines 315 on the first touch conductive layer can be connected to the touch bending lines 335 on the second source / drain metal layer. The touch bending lines 335 can be connected to the touch lead-out lines 325 on the first touch conductive layer.

[0179] In some examples, the first power transmission line 316 located in the first source / drain metal layer can be connected to the first power meander line (e.g., first power meander line 336a) located in the second source / drain metal layer. The first power meander line 336a and the second sub-power supply line of the first power supply line 326 located in the second source / drain metal layer can be interconnected as an integrated structure. The shielding electrode 351 can be interconnected as an integrated structure with the first sub-power supply line of the first power supply line 326 located in the first source / drain metal layer.

[0180] In some examples, the first transition region D1 is the transition region between the first end 3121 of the second crack detection line 312 located in the first touch conductive layer and the first detection meandering line 331b located in the second source / drain metal layer. The second transition region D2 is the transition region between the first detection meandering line 331b located in the second source / drain metal layer and the third extension 3213 of the first detection connection line 321 located in the first gate metal layer. The third transition region D3 is the transition region between the third extension 3213 of the first detection connection line 321 located in the first gate metal layer and the second extension 3212 located in the second source / drain metal layer. The fourth transition region D4 is the transition region between the first extension 3211 of the first detection connection line 321 located in the first gate metal layer and the second extension 3212 located in the second source / drain metal layer. The fifth transition region D5 is the transition region between the first extension 3211 of the first detection connection line 321 located in the first gate metal layer and the first detection meandering line 331a located in the second source / drain metal layer. The sixth transition region D6 is the transition region between the first end 3111 of the first crack detection line 311 located in the first gate metal layer and the first detection zigzag line 331a located in the second source / drain metal layer. The seventh transition region D7 is the transition region between the portion of the fifth extension segment 3222 of the second detection connection line 322a located in the first gate metal layer and the portion located in the second source / drain metal layer.

[0181] Figure 9 is a partially enlarged schematic diagram of the first transition region D1 in Figure 8. Figure 10 is a schematic partial cross-sectional diagram along the Q2-Q2' direction in Figure 9. Figure 10 omits the film layers of the second source / drain metal layer close to the substrate. In some examples, at least portions of the first gate insulation layer 101, second gate insulation layer 102, interlayer insulation layer 103, passivation layer 104, and first planarization layer 105 in the bending region B22 can be removed to reduce the thickness of the bending region and facilitate bending.

[0182] In some examples, as shown in Figures 8 to 10 , the orthographic projections of the first end 3121 of the second crack detection line 312 and the first detection zigzag line 331b on the substrate may partially overlap. The first detection zigzag line 331b located in the second source / drain metal layer may be connected to the first end 3121 of the second crack detection line 312 located in the first touch conductive layer via a first via K1 defined in the second planar layer 106, a third via defined in the pixel definition layer 134, and a second via K2 defined in the touch buffer layer 151. The second planar layer 106, the pixel definition layer 314, and the touch buffer layer 151 may be arranged sequentially, away from the substrate.

[0183] Figure 11 is a partially enlarged schematic diagram of the second transfer area D2 in Figure 8. Figure 12 is a partial cross-sectional schematic diagram along the Q3-Q3' direction in Figure 11. In some examples, as shown in Figures 8, 11, and 12, the first detection bend line 331b located in the second source and drain metal layer can be connected to the first connection electrode 411 located in the first source and drain metal layer through the fourth via K4 opened in the first flat layer 105 and the passivation layer 104. The first connection electrode 411 can be connected to the third extension section 3213 of the first detection connection line 321 located in the first gate metal layer through a plurality of fifth vias K5 opened in the interlayer insulating layer 103 and the second gate insulating layer 102. The plurality of fifth vias K5 can be arranged in an array, for example, they can be arranged in six rows and three columns. The orthographic projection of the first connection electrode 411 on the substrate may partially overlap with the orthographic projections of the first detection bending line 331b and the third extension section 3213 on the substrate, and the orthographic projections of the first detection bending line 331b and the third extension section 3213 on the substrate may partially overlap.

[0184] Figure 13 is a partially enlarged schematic diagram of the third transfer region D3 in Figure 8 . Figure 14 is a partial cross-sectional schematic diagram along the Q4-Q4' direction in Figure 13 . In some examples, as shown in Figures 8 , 13 , and 14 , the second extension 3212 of the first detection connection line 321 located in the second source / drain metal layer can be connected to the second connection electrode 412 located in the first source / drain metal layer via multiple (e.g., three) sixth vias K6 defined in the first planarization layer 105 and the passivation layer 104 . The second connection electrode 412 can be connected to the third extension 3213 of the first detection connection line 321 located in the first gate metal layer via multiple (e.g., three) seventh vias K7 defined in the interlayer insulating layer 103 and the second gate insulating layer 102 . The orthographic projection of the first connection electrode 412 on the substrate may partially overlap with the orthographic projections of the second extension 3212 and the third extension 3213 on the substrate, while the orthographic projections of the second extension 3212 and the third extension 3213 on the substrate may not overlap. However, this embodiment is not limited thereto. In other examples, the orthographic projections of the second extension section and the third extension section on the substrate may partially overlap.

[0185] In some examples, the transfer method between the wiring located in the second source and drain metal layer and the wiring located in the first gate metal layer in the fourth transfer area D4, the fifth transfer area D5, the sixth transfer area D6 and the seventh transfer area D7 is similar to the transfer method of the third transfer area D3, so it is not repeated here.

[0186] In this example, by providing an interlayer insulating layer, a passivation layer, and a first flat layer (or providing an interlayer insulating layer and a first flat layer) between the detection connection line and the data lead line, the minimum thickness between the detection connection line and the data lead line whose orthographic projection overlaps can be increased, thereby reducing the coupling capacitance between the detection connection line and the data lead line. Moreover, by providing a shielding electrode between the detection connection line and the data lead line, and the shielding electrode and the first sub-power supply line of the first power supply line are interconnected as an integrated structure, the shielding electrode can be used to shield the data lead line whose orthographic projection overlaps with the detection connection line, thereby reducing the coupling capacitance between the detection connection line and the data lead line, thereby reducing the influence of the detection connection line on the data signal and reducing the risk of poor display of the display panel.

[0187] Figure 15 is a partial schematic diagram of the second border region of at least one embodiment of the present disclosure. Figure 15 also illustrates a partial structural schematic diagram of the bending region and the second fan-out region. Figure 16 is a partial enlarged schematic diagram of region C2 in Figure 15. Figure 17A is a partial cross-sectional schematic diagram along the Q5-Q5' direction in Figure 16. Figure 17B is another partial cross-sectional schematic diagram along the Q5-Q5' direction in Figure 16.

[0188] In some examples, as shown in Figures 15 to 17A, the first extension section 3211, the second extension section 3212, and the third extension section 3213 of the first detection connection line 321 can be an integrated structure connected to each other. The first detection connection line 321 and the multiple data lead lines (including the multiple first data lead lines 3231 located in the first gate metal layer and the first group of data lead lines of the multiple second data lead lines 3232 located in the second gate metal layer) can overlap in their orthographic projection on the substrate. The orthographic projection of the fifth extension section 3222 of the second detection connection line 322a on the substrate can overlap with the orthographic projection of the multiple data lead lines (including the first group of data lead lines) on the substrate. The first detection connection line 321 and the fifth extension section 3222 of the second detection connection line 322a can be located in the first touch conductive layer.

[0189] In some examples, as shown in FIG17A , an interlayer insulating layer 103, a passivation layer 104, a first planar layer 105, a second planar layer 106, and a touch buffer layer 151 may be disposed between the second extension 3212 of the first touch conductive layer and the data lead line 3232 located on the second gate metal layer. A second gate insulating layer 102, an interlayer insulating layer 103, a passivation layer 104, a first planar layer 105, a second planar layer 106, and a touch buffer layer 151 may be disposed between the second extension 3212 of the first touch conductive layer and the data lead line 3231 located on the first gate metal layer. At least five insulating layers are disposed between the data lead line and the second extension 3212 of the first detection connection line 321. Inorganic insulating layers may include the interlayer insulating layer 103, the passivation layer 104, and the touch buffer layer 151, and organic insulating layers may include the first planar layer 105 and the second planar layer 106. In some examples, the minimum thickness h2 between the second extension section 3212 of the first detection connection line 321 and the data lead line may include the sum of the thicknesses of the interlayer insulating layer 103, the passivation layer 104, the first planarizing layer 105, the second planarizing layer 106, and the touch buffer layer 151. However, this embodiment is not limited to this.

[0190] In other examples, as shown in FIG17B , an interlayer insulating layer 103, a first planar layer 105, a second planar layer 106, and a touch buffer layer 151 may be disposed between the second extension 3212 of the first touch conductive layer and the data lead line 3232 located on the second gate metal layer. A second gate insulating layer 102, an interlayer insulating layer 103, a first planar layer 105, a second planar layer 106, and a touch buffer layer 151 may be disposed between the second extension 3212 of the first touch conductive layer and the data lead line 3231 located on the first gate metal layer. At least four insulating layers are disposed between the data lead line and the second extension 3212 of the first detection connection line 321. Inorganic insulating layers may include the interlayer insulating layer 103 and the touch buffer layer 151, and organic insulating layers may include the first planar layer 105 and the second planar layer 106. However, this embodiment is not limited to this. In other examples, the first planarization layer can be omitted, provided that the minimum thickness between the data lead line and the first detection connection line is greater than 2.1 microns. In other examples, the display structure layer of the display panel may further include a third source / drain metal layer and a third planarization layer located on the side of the second source / drain metal layer away from the substrate. At least five insulating layers may be provided between the data lead line and the second extension 3212 of the first detection connection line 321 located on the first touch conductive layer. The inorganic insulating layer may include an interlayer insulating layer and a touch buffer layer, and the organic insulating layer may include a first planarization layer, a second planarization layer, and a third planarization layer.

[0191] In some examples, the first touch conductive layer can have a three-layer metal stack structure, such as a titanium-aluminum-titanium (Ti / Al / Ti) stack structure. The interlayer insulating layer 103 can have a thickness of 0.045 μm to 0.055 μm, for example, approximately 0.05 μm. The passivation layer 104 can have a thickness of 0.025 μm to 0.033 μm, for example, approximately 0.03 μm. The first planarization layer 105 can have a thickness of 1.35 μm to 1.65 μm, for example, approximately 1.5 μm. The second planarization layer 106 can have a thickness of 1.35 μm to 1.65 μm, for example, approximately 1.5 μm. The touch buffer layer 151 can have a thickness of 0.025 μm to 0.033 μm, for example, approximately 0.03 μm.

[0192] In some examples, the fifth extension section 3222 of the second detection connection line 322 a is similar to the film structure between the data lead lines, and therefore is not further described here.

[0193] In this example, by disposing the fifth extension segments of the first and second detection connection lines in the first touch conductive layer, the minimum thickness between the detection connection lines and the data lead lines whose orthographic projections overlap can be increased, thereby reducing the coupling capacitance between the detection connection lines and the data lead lines. Furthermore, since the number of insulating layers between the detection connection lines and the data lead lines whose orthographic projections overlap in this example is relatively large and the total thickness of these insulating layers is relatively high, shielding electrodes can be omitted. The coupling capacitance between the detection connection lines and the data lead lines can be reduced simply by increasing the distance between the detection connection lines and the data lead lines whose orthographic projections overlap.

[0194] Figure 17C is another partial cross-sectional schematic diagram along the Q5-Q5' direction in Figure 16. In some examples, as shown in Figure 17C, the fifth extension 3222 of the first detection connection line 321 and the second detection connection line 322a can be located in the second touch conductive layer. At least six insulating layers (including an interlayer insulating layer 103, a passivation layer 104, a first flat layer 105, a second flat layer 106, a touch buffer layer 151, and a touch insulating layer 152) are provided between the data lead line of this example and the second extension 3212 of the first detection connection line 321. In this example, by providing the fifth extension of the first detection connection line and the second detection connection line in the second touch conductive layer, the minimum thickness between the detection connection line and the data lead line where the orthographic projection overlaps can be increased, and the coupling capacitance between the detection connection line and the data lead line can be reduced. However, this embodiment is not limited to this. In other examples, the first detection connection line 321 and the fifth extension 3222 of the second detection connection line 322a can be located in different conductive layers. For example, the first detection connection line 321 can be located in the first touch conductive layer, and the fifth extension 3222 of the second detection connection line 322a can be located in the second touch conductive layer. Alternatively, the first detection connection line 321 can be located in the second touch conductive layer, and the fifth extension 3222 of the second detection connection line 322a can be located in the first touch conductive layer. The remaining structure of the display panel of this example can be referred to the description of the previous embodiment, and will not be repeated here.

[0195] Figure 18 is a partially enlarged schematic diagram of the eighth transition region D8 in Figure 15 . Figure 19 is a schematic partial cross-sectional diagram along the Q6-Q6' direction in Figure 18 . Figure 19 omits the film layers of the second source / drain metal layer close to the substrate. In some examples, at least portions of the first gate insulation layer 101, second gate insulation layer 102, interlayer insulation layer 103, passivation layer 104, and first planarization layer 105 in the bending region B22 can be removed to reduce the thickness of the bending region and facilitate bending.

[0196] In some examples, as shown in Figures 15, 18, and 19, the third extension 3213 of the first detection connection line 321 located in the first touch conductive layer can be connected to the first detection bending line 331b located in the second source / drain metal layer via the eighth via K8 provided in the second planar layer 106, the tenth via K9 provided in the pixel definition layer 134, and the ninth via K9 provided in the touch buffer layer 151. The second planar layer 106, the pixel definition layer 314, and the touch buffer layer 151 can be arranged sequentially in a direction away from the substrate.

[0197] In some examples, the connection method between the wiring located in the first touch conductive layer and the wiring located in the second source / drain metal layer in the ninth connection area D9 is similar to the connection method in the eighth connection area D8 , and therefore is not described again here.

[0198] Figure 20 is a partially enlarged schematic diagram of the tenth transition region D10 in Figure 15 . Figure 21 is a partial cross-sectional schematic diagram along the Q7-Q7' direction in Figure 20 . In some examples, as shown in Figures 15 , 20 , and 21 , the fifth extension segment 3222 of the second detection connection line 322a may include: a first line segment 3222-1 located in the first touch conductive layer and a second line segment 3222-2 located in the first gate metal layer. The first line segment 3222-1 and the second line segment 3222-2 are connected. The orthographic projection of the first line segment 3222-1 on the substrate overlaps with the orthographic projection of the first group of data lead lines on the substrate, while the orthographic projection of the second line segment 3222-2 on the substrate may not overlap with the orthographic projections of the multiple data lead lines on the substrate.

[0199] In some examples, the first line segment 3222-1 in the first touch conductive layer can be connected to the fourth connection electrode 414 in the second source / drain metal layer via the fifteenth via K15 in the touch buffer layer 151, the fourteenth via K14 in the pixel definition layer 134, and the thirteenth via K13 in the second planar layer 106. The fourth connection electrode 414 can be connected to the third connection electrode 413 in the first source / drain metal layer via the twelfth via K12 in the passivation layer 104 and the first planar layer 105. The third connection electrode 413 can be connected to the second line segment 3222-2 in the first gate metal layer via multiple eleventh vias K11 in the second gate insulation layer 102 and the interlayer insulation layer 103. The multiple eleventh vias K11 can be arranged in an array. The orthographic projections of the fourth connection electrode 414 and the third connection electrode 413 on the substrate can partially overlap. For example, the orthographic projection of the fourth connection electrode 414 on the substrate can cover the orthographic projection of the third connection electrode 413 on the substrate. The orthographic projections of the fourth connection electrode 414 and the third connection electrode 413 on the substrate may partially overlap with the orthographic projection of the second line segment 3222-2 on the substrate, and the orthographic projection of the fourth connection electrode 414 on the substrate may partially overlap with the orthographic projection of the first line segment 3222-1 on the substrate. The orthographic projections of the first line segment 3222-1 and the second line segment 3222-2 on the substrate may not overlap. This embodiment is not limited to this.

[0200] In this example, the electrical connection between the first line segment and the second line segment of the fifth extension section is achieved through the fourth connection electrode and the third connection electrode, which can ensure the effectiveness of the connection and avoid opening an overly deep via hole.

[0201] Figure 22 is another partial schematic diagram of the second border region of at least one embodiment of the present disclosure. Figure 22 illustrates a partial structural schematic diagram of the bending region and the second fan-out region. Figure 23 is a partial enlarged schematic diagram of region C3 in Figure 22. Figure 24 is a partial cross-sectional schematic diagram along the Q8-Q8' direction in Figure 23.

[0202] In some examples, as shown in Figures 22 to 24, the first extension segment 3211, the second extension segment 3212, and the third extension segment 3213 of the first detection connection line 321 can be interconnected as an integral structure. The first detection connection line 321 and the fifth extension segment 3222 of the second detection connection line 322a can be located in the first touch conductive layer. A shielding electrode 351 is provided where the second extension segment 3212 of the first detection connection line 321 and the fifth extension segment 3222 of the second detection connection line 322a cross the data lead line. The shielding electrode 351 can be located in the first source-drain metal layer and can be interconnected as an integral structure with the first sub-power supply line of the first power supply line 326. The orthographic projection of the shielding electrode 351 on the substrate can cover the overlapping portion of the orthographic projection of the second extension segment 3212 of the first detection connection line 321 and the fifth extension segment 3222 of the second detection connection line 322a and the data lead line on the substrate.

[0203] In some examples, as shown in Figure 24, the minimum thickness h3 between the second extension segment 3212 of the first detection connection line 321 and the data lead line may include the sum of the thicknesses of the interlayer insulating layer 103, the shielding electrode 351, the passivation layer 104, the first flat layer 105, the second flat layer 106 and the touch buffer layer 151.

[0204] In this example, by disposing the fifth extension segments of the first and second detection connection lines in the first touch conductive layer, the minimum thickness between the detection connection lines and the data lead lines whose orthographic projections overlap can be increased, thereby reducing the coupling capacitance between the detection connection lines and the data lead lines. Furthermore, by disposing a shielding electrode, which can be located in the first source / drain metal layer and separate the data lead lines from the detection connection lines, the coupling capacitance between the detection connection lines and the data lead lines can be further reduced.

[0205] In some examples, the transfer method between the wiring located in the second source and drain metal layer and the wiring located in the first touch conductive layer in the eleventh transfer area D11 and the twelfth transfer area D12 can refer to the transfer method of the eighth transfer area D8, and the transfer method between the wiring located in the first gate metal layer and the wiring located in the first touch conductive layer in the thirteenth transfer area D13 can refer to the transfer method of the tenth transfer area D10, so it will not be repeated here.

[0206] The remaining structures of the display panel of this example can be referred to the description of the aforementioned embodiment, and thus will not be described again here.

[0207] Figure 25 is another partial schematic diagram of the second border region of at least one embodiment of the present disclosure. Figure 25 illustrates a partial structural schematic diagram of the bending region and the second fan-out region. Figure 26 is a partial enlarged schematic diagram of region C4 in Figure 25. Figure 27 is a partial cross-sectional schematic diagram along the Q9-Q9' direction in Figure 26.

[0208] In some examples, as shown in Figures 25 to 27, the first extension segment 3211, the second extension segment 3212, and the third extension segment 3213 of the first detection connection line 321 can be interconnected as an integral structure. The first detection connection line 321 and the fifth extension segment 3222 of the second detection connection line 322a can be located in the first touch conductive layer. A shielding electrode 351 is provided where the second extension segment 3212 of the first detection connection line 321 and the fifth extension segment 3222 of the second detection connection line 322a cross the data lead line. The shielding electrode 351 can be located in the second source-drain metal layer and can be interconnected as an integral structure with the second sub-power supply line of the first power supply line 326. The orthographic projection of the shielding electrode 351 on the substrate can cover the overlapping portion of the orthographic projection of the second extension segment 3212 of the first detection connection line 321 and the fifth extension segment 3222 of the second detection connection line 322a and the data lead line on the substrate.

[0209] In some examples, as shown in Figure 26, the minimum thickness h3 between the second extension segment 3212 of the first detection connection line 321 and the data lead line may include the sum of the thicknesses of the interlayer insulating layer 103, the passivation layer 104, the first flat layer 105, the shielding electrode 351, the second flat layer 106 and the touch buffer layer 151.

[0210] In this example, by disposing the fifth extension segments of the first and second detection connection lines in the first touch conductive layer, the minimum thickness between the detection connection lines and the data lead lines, whose orthographic projections overlap, can be increased, thereby reducing the coupling capacitance between the detection connection lines and the data lead lines. Furthermore, by disposing a shielding electrode, which can be located in the second source / drain metal layer and separate the data lead lines from the detection connection lines, the coupling capacitance between the detection connection lines and the data lead lines can be further reduced.

[0211] The remaining structures of the display panel of this example can be referred to the description of the aforementioned embodiment, and thus will not be described again here.

[0212] In other examples, the second extension of the first detection connection line and the fifth extension of the second detection connection line may be located in different conductive layers. For example, the second extension of the first detection connection line may be located in the second source / drain metal layer, and the fifth extension of the second detection connection line may be located in the first touch conductive layer or the second touch conductive layer. The orthographic projection of the shielding electrode on the substrate may overlap with the second extension and not overlap with the fifth extension.

[0213] In other examples, the fifth extension segment of the second detection connection line can be located on a side of the second extension segment of the first detection connection line that is closer to the bend region, and the first extension segment, the third extension segment, and the fifth extension segment of the first detection connection line can be located on different conductive layers. The orthographic projection of the shielding electrode on the substrate can overlap with the orthographic projection of the fifth extension segment on the substrate, but not overlap with the orthographic projection of the second extension segment on the substrate.

[0214] Figure 28 is another schematic diagram of crack detection of a display panel according to at least one embodiment of the present disclosure. Figure 29 is a partially enlarged schematic diagram of the second frame region in Figure 28. Figure 30 is a schematic diagram of a partial film layer structure of region C5 in Figure 29.

[0215] In some examples, as shown in Figures 28 and 29, the display structure layer may include multiple first crack detection lines (for example, first crack detection lines 311a and 311b) located at least in the first border area B1; the touch structure layer may include multiple second crack detection lines (for example, second crack detection lines 312a and 312b) located at least in the first border area B1. The first crack detection line 311a and the second crack detection line 312a may be arranged along the left side of the display area AA, and the first crack detection line 311a may be located on the side of the second crack detection line 312a away from the display area AA. The first crack detection line 311b and the second crack detection line 312b may be arranged along the right side of the display area AA, and the first crack detection line 311b may be located on the side of the second crack detection line 312b away from the display area AA.

[0216] In some examples, the first crack detection lines 311a and 311b may be symmetrically arranged about the center line O1 of the display panel in the first direction X, and the second crack detection lines 312a and 312b may be symmetrically arranged about the center line O1 of the display panel in the first direction X. This example may adopt a mirrored design of the crack detection lines.

[0217] In some examples, the plurality of detection connection lines in the second border region may include: first detection connection lines 321a, 321b, and 321c, and second detection connection lines 322a and 322b. In this example, the first detection connection lines implement a series connection between the crack detection lines, and the second detection connection lines implement a series connection between the crack detection lines and the detection contact pads.

[0218] In some examples, one end of the second detection connection line 322a can be connected to the first end 3111a of the first crack detection line 311a via the detection bend line of the bend area B22, and the other end can be connected to the first detection contact pad 341 within the first signal access area B24. One end of the first detection connection line 321a can be connected to the second end 3112a of the first crack detection line 311a via the detection bend line of the bend area B22, and the other end can be connected to the first end 3121a of the second crack detection line 312a via the detection bend line of the bend area B22. One end of the first detection connection line 321b can be connected to the second end 3122a of the second crack detection line 312a via the detection bend line of the bend area B22, and the other end can be connected to the second end 3122b of the second crack detection line 312b via the detection bend line of the bend area B22. One end of the first detection connection line 321c can be connected to the first end 3121b of the second crack detection line 312b via the detection bending line in the bending area B22, and the other end can be connected to the second end 3112b of the first crack detection line 311b via the detection bending line in the bending area B22. One end of the second detection connection line 322b can be connected to the first end 3111b of the first crack detection line 311b via the detection bending line in the bending area B22, and the other end can be connected to the second detection contact pad 342 in the first signal access area B24.

[0219] In some examples, the second detection connection lines 322a and 322b can be arranged approximately symmetrically about the center line O1 of the display panel along the first direction X. The first detection connection lines 321a and 321c can be arranged approximately symmetrically about the center line O1 of the display panel along the first direction X. The first detection connection line 321b can be approximately symmetrical about the center line O1 of the display panel along the first direction X.

[0220] In some examples, as shown in Figure 30, the first detection connection line 321a may include: a first extension section 3211a, a second extension section 3212a and a third extension section 3213a connected in sequence. The orthographic projection of the second extension section 3212a on the substrate may overlap with the orthographic projection of the first group of data lead lines (including a plurality of first data lead lines 3231 located in the first gate metal layer and a plurality of second data lead lines 3232 located in the second gate metal layer) on the substrate. The first extension section 3211a and the third extension section 3213a may be located in the first gate metal layer, and the second extension section 3212a may be located in the second source and drain metal layer. A shielding electrode 351 may be provided at the position where the second extension section 3212a crosses the first group of data lead lines. The shielding electrode 351 may be located in the first source and drain metal layer and may be an integrated structure interconnected with the first sub-power supply line of the first power supply line. The orthographic projection of the shielding electrode 351 on the substrate may cover the overlapping portion of the orthographic projection of the second extension segment 3212a and the first set of data lead lines on the substrate. However, this embodiment is not limited to this. In other examples, the second extension segment 3212a of the first detection connection line 321a may be located in the first touch conductive layer or the second touch conductive layer, and a shielding electrode may not be provided. In other examples, the second extension segment 3212a of the first detection connection line 321a may be located in the first touch conductive layer or the second touch conductive layer, and a corresponding shielding electrode may be provided.

[0221] In some examples, the orthographic projection of the first detection connection line 321c on the substrate may overlap with the orthographic projection of the second group of data lead lines on the substrate. A shielding electrode may be provided between the first detection connection line 321c and the second group of data lead lines whose orthographic projections overlap, and the shielding electrode may be an integrated structure interconnected with the first sub-power supply line of the first power supply line. The structure of the first detection connection line 321c is similar to that of the first detection connection line 321a, so it will not be described here. However, this embodiment is not limited to this. In other examples, the extension section of the first detection connection line 321c that overlaps with the second group of data lead lines may be located in a different conductive layer from the second extension section 3212a of the first detection connection line 321a. For example, the extension section of the first detection connection line 321c that overlaps with the second group of data lead lines may be located in the first touch conductive layer or the second touch conductive layer, and the corresponding shielding electrode may be an integrated structure interconnected with the second sub-power supply line of the first power supply line.

[0222] In some examples, the first detection connection line 321b may be located between the first group of data lead lines and the second group of data lead lines, and may not overlap with the orthographic projections of the first group of data lead lines and the second group of data lead lines on the substrate. In other words, the distance between the first detection connection line 321b and the orthographic projections of the first group of data lead lines and the second group of data lead lines on the substrate is greater than zero. For example, the first detection connection line 321b may be located in the first gate metal layer. However, this embodiment is not limited to this.

[0223] In some examples, the second detection connection line 322a may be located on one side of the first group of data lead lines in the opposite direction of the first direction X, and the second detection connection line 322b may be located on one side of the second group of data lead lines in the first direction X. The second detection connection lines 322a and 322b may not overlap with the orthographic projections of the plurality of data lead lines on the substrate. In other words, the distance between the orthographic projections of the second detection connection lines 322a and 322b on the substrate and the orthographic projections of the plurality of data lead lines on the substrate is greater than 0.

[0224] In some examples, each data lead line overlaps with the same number of detection connection lines in their orthographic projections on the substrate. For example, as shown in FIG30 , each data lead line in the first group of data lead lines overlaps with the orthographic projection of the first detection connection line 321a on the substrate, and each data lead line in the second group of data lead lines overlaps with the orthographic projection of the first detection connection line 321c on the substrate. This example arrangement can maintain consistency in the coupling capacitance between multiple data lead lines and the detection connection lines, thereby reducing display defects such as uneven brightness and ensuring display quality.

[0225] The rest of the description about the display panel of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0226] This embodiment also provides a display panel, comprising: a substrate, a display structure layer disposed on the substrate, a touch structure layer, and at least one shielding electrode. The substrate comprises: a display area and a frame area located around the display area, the frame area comprising: a second frame area located on one side of the display area and a first frame area located on the remaining sides of the display area. The display structure layer comprises: a plurality of sub-pixels and a plurality of data lines located in the display area, at least one first crack detection line located in the first frame area, and a plurality of data lead lines located in the second frame area. The plurality of data lines are connected to the plurality of sub-pixels and are configured to provide data signals to the plurality of sub-pixels. The plurality of data lead lines are configured to provide data signals to the plurality of data lines. The touch structure layer is located on a side of the display structure layer away from the substrate, the touch structure layer comprising at least one second crack detection line located in the first frame area. The at least one first crack detection line and the at least one second crack detection line are connected in series in the second frame area via a plurality of detection connection lines. The orthographic projection of at least one of the multiple detection connection lines on the substrate overlaps with the orthographic projection of at least one of the multiple data lead lines on the substrate. At least one shielding electrode is located in the second frame area. In a direction perpendicular to the display panel, the shielding electrode is located between at least a portion of the line segment of the at least one detection connection line and the at least one data lead line. The orthographic projection of the shielding electrode on the substrate at least partially overlaps with the orthographic projections of the at least one detection connection line and the at least one data lead line on the substrate. For example, the orthographic projection of the shielding electrode on the substrate can cover the overlapping portion of the orthographic projections of the at least one detection connection line and the at least one data lead line on the substrate.

[0227] The display panel provided in this embodiment sets a shielding electrode in the second frame area, and uses the shielding electrode to separate the detection connection line and the data lead line, thereby reducing the coupling capacitance between the detection connection line and the data lead line, reducing the interference of the coupling capacitance on the data signal, thereby improving the display quality of the display panel and reducing the risk of poor display of the display panel.

[0228] In some exemplary embodiments, at least two insulating layers may be provided between at least a portion of at least one detection connection line and at least one data lead line. The at least two insulating layers include at least one organic insulating layer and at least one inorganic insulating layer. In this example, by providing at least two insulating layers between at least a portion of the detection connection line and the data lead line whose orthographic projection overlaps, the distance between the detection connection line and the data lead line whose orthographic projection overlaps can be increased, thereby reducing the coupling capacitance between the detection connection line and the data lead line, alleviating interference with the data signal caused by the coupling capacitance, thereby improving the display quality of the display panel and reducing the risk of display defects on the display panel.

[0229] In some exemplary embodiments, the minimum thickness between at least a portion of at least one detection connection line and at least one data lead line may be greater than 2.1 microns. By setting the distance between the detection connection line and the data lead line whose orthographic projections overlap, this example can reduce the coupling capacitance between the detection connection line and the data lead line, thereby reducing interference with the data signal caused by the coupling capacitance.

[0230] In some exemplary embodiments, the display panel may further include: a plurality of first power lines located in the display area and a first power supply line located in the second border area, the plurality of first power lines being electrically connected to the plurality of sub-pixels, the plurality of first power lines being connected to the first power supply line, and the at least one shielding electrode being connected to the first power supply line. In this example, by providing the shielding electrode with a connection to the first power supply line, a shielding effect of the shielding electrode can be achieved.

[0231] In some exemplary embodiments, the first power supply line includes: a first sub-power supply line and a second sub-power supply line that are interconnected, the first sub-power supply line being located on a side of the second sub-power supply line that is closer to the substrate; the at least one shielding electrode and the first sub-power supply line are interconnected as an integral structure, or the at least one shielding electrode and the second sub-power supply line are interconnected as an integral structure. In this example, the first power supply line utilizes a double-layer routing structure, which helps reduce the impedance of the first power supply line. Furthermore, the shielding electrode and one of the layers of the first power supply line are interconnected as an integral structure, which facilitates the layout of the shielding electrode and reduces the number of openings required to connect the shielding electrode to the first power supply line.

[0232] In some exemplary embodiments, the touch structure layer may include at least one touch conductive layer, and at least a portion of at least one detection connection line may be located in the touch conductive layer of the touch structure layer. In this example, by locating the detection connection line in the touch conductive layer, the distance between the detection connection line and the data lead line whose orthographic projection overlaps can be increased, thereby reducing the coupling capacitance between the detection connection line and the data lead line, and alleviating interference with the coupling capacitance on the data signal.

[0233] The rest of the description about the display panel of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0234] FIG31 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in FIG31 , this embodiment provides a display device 91 including a display panel 910 according to the aforementioned embodiment. In some examples, the display panel 910 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be a product having an image (including a static image or a dynamic image, wherein the dynamic image may be a video) display function. For example, the display device may be any of the following products: a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a painting screen, a personal digital assistant (PDA), a digital camera, a portable camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, an information query device (such as a business query device for e-government, a bank, a hospital, a power department, etc.), a monitor, etc. For another example, the display device may also be a microdisplay, a VR device or an AR device including a microdisplay, etc.

[0235] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures can refer to the general design. In the absence of conflict, the embodiments of the present disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments. It should be noted that the above-mentioned embodiments or implementation methods are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the contents shown and described in detail herein. Various modifications, replacements or omissions can be made to the form and details of the implementation without departing from the scope of this disclosure.

Claims

1. A display panel, comprising: a substrate including a display area and a border area surrounding the display area, the border area including a second border area on one side of the display area and a first border area on the remaining sides of the display area; a display structure layer disposed on the substrate, including a plurality of sub-pixels and a plurality of data lines located in the display area, at least one first crack detection line located in the first border area, and a plurality of data lead-out lines located in the second border area; the plurality of data lines are connected to the plurality of sub-pixels and are configured to provide data signals to the plurality of sub-pixels; the plurality of data lead-out lines are configured to provide data signals to the plurality of data lines; a touch structure layer located on a side of the display structure layer away from the substrate, including at least one second crack detection line located in the first border area; the at least one first crack detection line and the at least one second crack detection line are connected in series through a plurality of detection connection lines in the second border area; at least one of the plurality of detection connection lines has a positive projection on the substrate that overlaps with at least one of the plurality of data lead-out lines on the substrate, and at least two insulating layers are provided between at least a partial segment of the at least one detection connection line and the at least one data lead-out line.

2. The display panel according to claim 1, wherein, the at least two insulating layers include at least one organic insulating layer and at least one inorganic insulating layer.

3. The display panel according to claim 1, wherein, the minimum thickness between at least a partial segment of the at least one detection connection line and the at least one data lead-out line is greater than 2.1 micrometers.

4. The display panel according to any one of claims 1 to 3, further comprising: at least one shielding electrode located in the second border area; in a direction perpendicular to the display panel, the shielding electrode is located between at least a partial segment of the at least one detection connection line and the at least one data lead-out line; the positive projection of the shielding electrode on the substrate covers the overlapping portion of the positive projections of the at least one detection connection line and the at least one data lead-out line on the substrate.

5. The display panel according to claim 4, further comprising: a plurality of first power supply lines located in the display area and a first power supply line located in the second border area, the plurality of first power supply lines are electrically connected to the plurality of sub-pixels, and the plurality of first power supply lines are connected to the first power supply line, and the at least one shielding electrode is connected to the first power supply line.

6. The display panel according to claim 5, wherein, the first power supply line includes a first sub-power supply line and a second sub-power supply line connected to each other, the first sub-power supply line is located on a side of the second sub-power supply line close to the substrate; the at least one shielding electrode and the first sub-power supply line are an integrally connected structure.

7. The display panel according to claim 6, wherein, At least part of the at least one detection connection line and the second sub-power supply line are in the same layer structure.

8. The display panel according to claim 5, wherein, The first power supply line includes: a first sub-power supply line and a second sub-power supply line connected to each other, the first sub-power supply line is located on a side of the second sub-power supply line close to the substrate; the at least one shielding electrode and the second sub-power supply line are an integrally connected structure; at least part of the at least one detection connection line is located on a side of the second sub-power supply line away from the substrate.

9. The display panel according to claim 4, wherein, The display structure layer at least includes: a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer provided on the substrate; an interlayer insulating layer is provided between the second gate metal layer and the first source-drain metal layer, and at least a first planarization layer is provided between the first source-drain metal layer and the second source-drain metal layer; at least part of the at least one detection connection line is located in the second source-drain metal layer, and the shielding electrode is located in the first source-drain metal layer; the insulating layer between at least part of the at least one detection connection line and the at least one data lead-out line at least includes: the interlayer insulating layer and the first planarization layer.

10. The display panel according to claim 9, wherein, The multiple data lead-out lines include: multiple first data lead-out lines located in the first gate metal layer and multiple second data lead-out lines located in the second gate metal layer, and the multiple first data lead-out lines and the multiple second data lead-out lines are alternately arranged.

11. The display panel according to any one of claims 1 to 5, wherein, The touch structure layer includes at least one touch conductive layer, and at least part of the at least one detection connection line is located in the touch conductive layer of the touch structure layer.

12. The display panel according to claim 1, wherein, The second border area includes a first signal access area, and the first signal access area includes: a plurality of data contact pads, at least one first detection contact pad, and at least one second detection contact pad, the at least one first detection contact pad and the at least one second detection contact pad are located on both sides of the plurality of data contact pads along a first direction; the plurality of data contact pads are connected to the plurality of data lead-out lines; the plurality of detection connection lines include: two second detection connection lines and at least one first detection connection line; one end of the serially connected first crack detection line and second crack detection line is connected to the at least one first detection contact pad through one second detection connection line, and the other end is connected to the at least one second detection contact pad through the other second detection connection line; a partial segment of the at least one first detection connection line and a partial projection of the at least one data lead-out line on the substrate overlap.

13. The display panel according to claim 12, wherein, Among the two second detection connection lines, the positive projection of one of the second detection connection lines on the substrate overlaps with the positive projection of the at least one data lead-out line on the substrate; the distance between the positive projection of the other second detection connection line on the substrate and the positive projection of the multiple data lead-out lines on the substrate is greater than 0.

14. The display panel according to claim 13, wherein, The partial line segments of the first detection connection line that overlap with the positive projection of the at least one data lead-out line on the substrate, and the partial line segments of the second detection connection line that overlap with the positive projection of the at least one data lead-out line on the substrate are of the same layer structure.

15. The display panel according to claim 12, wherein, The distance between the positive projection of the two second detection connection lines on the substrate and the positive projection of the multiple data lead-out lines on the substrate is greater than 0.

16. The display panel according to claim 12, wherein, The at least one first detection connection line includes: a first extension segment, a second extension segment, and a third extension segment connected in sequence. The extension direction of the second extension segment intersects with the extension directions of the first extension segment and the third extension segment. The second extension segment overlaps with the positive projection of the at least one data lead-out line on the substrate, and the distance between the positive projection of the first extension segment and the third extension segment on the substrate and the positive projection of the multiple data lead-out lines on the substrate is greater than 0.

17. The display panel according to claim 16, wherein, The second extension segment is located on the side of the first extension segment and the third extension segment away from the substrate, and the second extension segment is connected to the first extension segment or the third extension segment through a second connection electrode.

18. The display panel according to claim 16, wherein, The first extension segment, the second extension segment, and the third extension segment of the first detection connection line are an integrally connected structure.

19. The display panel according to claim 1, wherein, The display structure layer includes multiple first crack detection lines, and the multiple first crack detection lines are symmetrically arranged with respect to the midline of the display panel in the first direction; the touch control structure layer includes multiple second crack detection lines, and the multiple second crack detection lines are symmetrically arranged with respect to the midline of the display panel in the first direction.

20. The display panel according to claim 19, wherein, Each data lead-out line located in the second border area overlaps with the positive projection of the same number of detection connection lines on the substrate.

21. The display panel according to claim 19, wherein, The multiple detection connection lines in the second border area are symmetrically arranged with respect to the midline of the display panel in the first direction.

22. The display panel according to claim 1, wherein, The second border area further includes: a bending area, and the bending area includes: multiple detection bending lines. The multiple detection connection lines are connected to the at least one first crack detection line and the at least one second crack detection line through the multiple detection bending lines; the multiple detection bending lines are of the same layer structure.

23. A display device, comprising a display panel as described in any one of claims 1 to 22.

24. A display panel, comprising: a substrate, comprising: a display area and a border area located around the display area, the border area comprising: a second border area located on one side of the display area and a first border area located on the remaining sides of the display area; a display structure layer disposed on the substrate, comprising: a plurality of sub-pixels and a plurality of data lines located in the display area, at least one first crack detection line located in the first border area, and a plurality of data lead-out lines located in the second border area; the plurality of data lines are connected to the plurality of sub-pixels and are configured to provide data signals to the plurality of sub-pixels; the plurality of data lead-out lines are configured to provide data signals to the plurality of data lines; a touch control structure layer located on a side of the display structure layer away from the substrate, comprising at least one second crack detection line located in the first border area; the at least one first crack detection line and the at least one second crack detection line are connected in series through a plurality of detection connection lines in the second border area; at least one of the plurality of detection connection lines has a positive projection on the substrate that overlaps with at least one of the plurality of data lead-out lines on the substrate; at least one shielding electrode located in the second border area, in a direction perpendicular to the display panel, the shielding electrode is located between at least a part of the at least one detection connection line and the at least one data lead-out line, and a positive projection of the shielding electrode on the substrate overlaps at least partially with positive projections of the at least one detection connection line and the at least one data lead-out line on the substrate.

25. The display panel according to claim 24, wherein, at least two insulating layers are provided between at least a part of the at least one detection connection line and the at least one data lead-out line, the at least two insulating layers comprising: at least one organic insulating layer and at least one inorganic insulating layer.

26. The display panel according to claim 24, wherein, a minimum thickness between at least a part of the at least one detection connection line and the at least one data lead-out line is greater than 2.1 micrometers.

27. The display panel according to claim 24, further comprising: a plurality of first power supply lines located in the display area and a first power supply line located in the second border area, the plurality of first power supply lines are electrically connected to the plurality of sub-pixels, and the plurality of first power supply lines are connected to the first power supply line, and the at least one shielding electrode is connected to the first power supply line.

28. The display panel according to claim 27, wherein, the first power supply line comprises: a first sub-power supply line and a second sub-power supply line connected to each other, the first sub-power supply line is located on a side of the second sub-power supply line close to the substrate; the at least one shielding electrode and the first sub-power supply line are an integrally connected structure, or the at least one shielding electrode and the second sub-power supply line are an integrally connected structure.

29. The display panel according to any one of claims 24 to 28, wherein, the touch structure layer includes at least one touch conductive layer, and at least a partial segment of the at least one detection connection line is located in the touch conductive layer of the touch structure layer.

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