Ultrasound coexistence in multi-transducer fetal monitoring system

Abstract

One or more systems, devices, computer-implemented methods, and / or computer program products for use provided herein relate to ultrasound coexistence in FMS. A system may include a memory that may store computer executable components. The system may further include a processor that may execute the computer executable component stored in the memory, where the computer executable component may include a frequency generating component, the frequency generating component may generate an electronic signal at one or more different frequencies in at least one fetal sensor device (FSD) of a fetal monitoring system (FMS) using a variable frequency generator circuit, wherein the electronic signal may cause a transducer of the at least one FSD to generate an ultrasound signal at the one or more different frequencies.

Description

Technical Field

[0001] The present subject matter generally relates to ultrasound technology and, more particularly, to ultrasound coexistence in a fetal monitoring system (FMS) that includes one or more fetal sensor devices (FSDs). Background Art

[0002] Doppler effect-based ultrasound sensors and transducers are used to detect fetal heart rate (FHR) and fetal movement, non-stress tests in outpatient clinics, and monitoring of other conditions such as fetal hypoxia or possible injury to the fetus prior to delivery. Typically, an ultrasound carrier signal with a specific amplitude is transmitted by an ultrasound transducer within a fixed time period Tx, and then the same transducer is used to receive the signal reflected from the fetus within a reception window Rx, where the reflected signal is Doppler-shifted due to the movement of cardiac tissue, fetal movement, etc. Using demodulation techniques, the ultrasound carrier signal can be removed, and the Doppler shift caused by the movement of cardiac tissue can be identified. Thereafter, correlation or peak detection algorithms are utilized to extract fetal heart rate, fetal movement parameters, etc. from the signal, and the signal is also distorted and driven to a speaker to generate a Doppler audio output. In a highly sensitive FSM (e.g., a multi-FSD ultrasound system) where multiple FSDs transmit pulses (ultrasound vibrations) into the same abdomen, interference may occur between the FSDs, which may lead to confusion between the hearts monitored by each FSD. Avoiding such interference may be crucial, especially for ensuring reliable and accurate fetal monitoring. If all FSDs operate at the same frequency, signal confusion may result between the FSDs (even for very small amplitudes). Frequency separation in an intelligent transducer system (e.g., an FMS) can help overcome small-signal confusion. However, due to Nyquist overlap between FSDs, inaccuracies in the frequencies used for pulse modulation / demodulation, and signal confusion due to aliasing and electronic interference, crosstalk may still occur. Crosstalk is a phenomenon where the signal transmitted by one FSD can interact with the signal transmitted by another FSD, resulting in an undesired effect in the system. Considering the high sensitivity of the transducer and the extremely high gain at the analog front end, harmonics typically creep in and result in repetitive waveforms that obscure the heart rate detection algorithm, which may lead to misinterpretation of the cardiotocogram (CTG).

[0003] Therefore, a system or technique for reliable ultrasound coexistence in an FMS may be desirable. Summary of the Invention

[0004] The following presents the invention content to provide a basic understanding of one or more embodiments described herein. This invention content is not intended to identify key or important elements, nor to depict the scope of a specific embodiment or the scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description presented later. In one or more embodiments described herein, systems, computer-implemented methods, devices, and / or computer program products that allow for coexistence of multiple FSDs in an FMS are discussed.

[0005] According to one embodiment, a system is provided. The system may include a memory that can store computer-executable components. The system may further include a processor that can execute the computer-executable components stored in the memory, wherein the computer-executable components may include a frequency generation component that can generate an electronic signal at one or more different frequencies in at least one FSD of an FMS using a variable frequency generator circuit, wherein at least one FSD can dynamically adjust the transmission voltage of at least one FSD to maintain a sound power value at one or more different frequencies, wherein at least one FSD may include a tunable inductor-capacitor (LC) energy storage circuit that includes a large-capacitance varactor that can tune the resonant frequency of the tunable LC energy storage circuit to the carrier frequency of at least one FSD, wherein tuning the resonant frequency of the tunable LC energy storage circuit to the carrier frequency of at least one FSD may include using a digital-to-analog converter (DAC) to adjust the bias voltage of a balanced varactor network, and wherein the carrier frequency may be a frequency selected from one or more different frequencies.

[0006] In aspects of the foregoing system, the electronic signal may cause a transducer of at least one FSD to generate an ultrasonic signal at one or more different frequencies, and adjusting the bias voltage of the balanced varactor network may dynamically change the capacitance value of the large-capacitance varactor.

[0007] In one or more embodiments of the foregoing system, the storage component may store DAC values corresponding to maximizing the gain of the tunable LC energy storage circuit at the carrier frequency of at least one FSD. In one or more embodiments of the foregoing system, the variable frequency generator circuit may use a damped offset frequency to automate the calibration process for the tunable LC energy storage circuit, and wherein at least one FSD may be calibrated to maximize the gain at the carrier frequency of at least one FSD. In one or more embodiments of the foregoing system, tuning the resonant frequency of the tunable LC energy storage circuit to the carrier frequency of at least one FSD may improve the receive sensitivity and gain of the tunable LC energy storage circuit at the carrier frequency, render at least one FSD insensitive to the corresponding carrier frequencies of additional FSDs in the FMS, and characterize and compensate for the behavior of the resonant frequency of the tunable LC energy storage circuit caused by temperature fluctuations experienced by at least one FSD such that the tunable LC energy storage circuit exhibits consistent performance despite temperature fluctuations.

[0008] In one or more embodiments of the foregoing system, the separation component may separate the corresponding carrier frequencies of multiple FSDs in the FMS such that the frequency difference between the carrier frequencies of any two FSDs is not a multiple of the pulse repetition rate (PRR) of either FSD, wherein separating the corresponding carrier frequencies of multiple FSDs may generate predictable harmonics during crosstalk in the FMS. In one or more embodiments of the foregoing system, the signal processing component may implement an automatic gain control (AGC) stage and filters to selectively eliminate the predictable harmonics to eliminate crosstalk in the FMS, wherein the automatic gain control stage may be implemented as software, hardware, or a combination of software and hardware.

[0009] In one or more embodiments of the foregoing system, the synchronization component may perform periodic PRR synchronization to synchronize the start of the transmission cycle of at least one FSD with the corresponding start of the transmission cycles of one or more additional FSDs in the FMS to prevent an ultrasonic signal generated by at least one FSD from being demodulated by the corresponding carrier frequency generated by one or more additional FSDs in the FMS. In one or more embodiments of the foregoing system, the periodic PRR synchronization may be performed by using a monitor that can signal the FSDs of the FMS in real time or by using a master FSD to signal additional FSDs in the FMS, and the periodic PRR synchronization may be performed wirelessly or through a wired connection.

[0010] In one or more embodiments of the foregoing system, the synchronization component may use a control system to perform pulse phase synchronization to prevent the signal transmitted by the first FSD of the FMS from entering the reception period of the second FSD of the FMS, where the second FSD is positioned directly across a distance from the first FSD, and the control system may measure the amount of harmonics generated by the first FSD at the second FSD and gradually offset the phase of the signal transmitted by the first FSD to align the signal transmitted by the first FSD with the signal transmitted by the second FSD in the FMS.

[0011] According to various embodiments, the foregoing system may be implemented as a computer-implemented method or a computer program product. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] One or more embodiments are described below in the "DETAILED DESCRIPTION" section with reference to the following drawings:

[0013] Figure 1 A block diagram illustrating an exemplary non-limiting system that allows multiple FSDs in an FMS to coexist, according to one or more embodiments described herein.

[0014] Figure 2 A diagram illustrating an exemplary non-limiting pulse repetition period, according to one or more embodiments described herein.

[0015] Figure 3 A block diagram illustrating an exemplary non-limiting clock generator that can generate one or more different frequencies in an FSD, according to one or more embodiments described herein.

[0016] Figure 4 A circuit diagram illustrating an exemplary non-limiting tunable LC energy storage circuit including a large capacitance varactor, according to one or more embodiments described herein.

[0017] Figure 5 A diagram illustrating an exemplary non-limiting graph of a finite element method (FEM) simulation, according to one or more embodiments described herein.

[0018] Figure 6 A diagram illustrating an exemplary non-limiting interference pattern representing crosstalk artifacts, according to one or more embodiments described herein.

[0019] Figure 7 A diagram illustrating an exemplary non-limiting scenario that can generate crosstalk in an FMS, according to one or more embodiments described herein.

[0020] Figure 8 A diagram illustrating an exemplary non-limiting interference pattern representing crosstalk artifacts, according to one or more embodiments described herein.

[0021] Figure 9 A diagram illustrating an exemplary non-limiting carrier according to one or more embodiments described herein.

[0022] Figure 10 Diagram illustrating an exemplary non-limiting scenario of three FSDs positioned on a pregnant woman for monitoring fetal parameters (heartbeats of triplets or whole body movement) according to one or more embodiments described herein.

[0023] Figure 11 Illustrated is a diagram showing an exemplary non-limiting scenario illustrating synchronization of pulse patterns generated by an FSD positioned on a pregnant woman for monitoring fetal parameters (heartbeats of triplets or whole body movement) in accordance with one or more embodiments described herein.

[0024] Figure 12 A diagram illustrating an exemplary non-limiting scenario showing a control system that can phase shift the start of a TX enabled period of an FSD to eliminate crosstalk artifact generation in an FMS according to one or more embodiments described herein is illustrated.

[0025] Figure 13 A flow chart illustrating an exemplary non-limiting method that may allow for the coexistence of multiple FSDs in an FMS according to one or more embodiments described herein.

[0026] Figure 14 A block diagram illustrating an exemplary non-limiting operating environment in which one or more embodiments described herein may be facilitated.

[0027] Figure 15 An exemplary networking environment is illustrated that is operable to perform various implementations described herein. DETAILED DESCRIPTION

[0028] The following detailed description is merely illustrative and is not intended to limit the application or use of the embodiments and / or the embodiments. In addition, it is not intended to be bound by any express or implied information set forth in the aforementioned "Background Technology" or "Summary of the Invention" section or "Detailed Description of the Invention" section.

[0029] One or more embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals are used throughout to represent like elements. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent that in various circumstances, one or more embodiments may be practiced without these specific details.

[0030] In a multi-FSD ultrasonic system where multiple FSDs can send pulses (ultrasound) to the highly sensitive mother's abdomen, interference may exist between the FSDs, leading to confusion related to the fetal heart monitored by each FSD. Avoiding interference ensures reliable and precise fetal monitoring. Although time-division multiplexing (TDM) can be implemented to ensure the coexistence of multiple FSDs, the FSDs can only operate continuously in TDM, where one FSD can send a signal and immediately receive the reflected signal in a pre-assigned time slot, then another FSD sends and receives the signal, and so on. That is, in TDM, the FSDs can send and receive pulses one by one and continuously. TDM can cause lower resolution during sampling, which may lead to a lower signal-to-noise ratio (SNR) and a reduction in the sensing range (depth). If all FSDs operate at the same frequency without TDM, signal confusion may occur between the FSDs (even for very small amplitudes of the received reflected signals). Using frequency-domain multiplexing / frequency-division multiplexing (FDM) to separate frequencies in an intelligent transducer system (e.g., FMS) can help overcome small-signal confusion. However, due to Nyquist overlap between FSDs, inaccuracies in one or more frequencies used for pulse modulation or demodulation, and signal confusion caused by aliasing and electronic interference, crosstalk may still occur. As mentioned before, crosstalk is a phenomenon where the signal sent by one FSD can interact with the signal sent by another FSD, resulting in an undesired effect generated in the system. Given the high sensitivity of a given FSD and the extremely high gain at the analog front end, harmonics usually creep in, which may lead to repetitive waveforms that can obscure the heart rate detection algorithm and result in misinterpretation of the CTG. In existing fetal monitoring technologies, all FSDs of the FMS operate at a single frequency. That is, existing FMSs do not include multiple FSDs operating at different frequencies. In addition, in existing FMSs, a single FSD cannot operate at multiple frequencies, and it is challenging for such existing systems to find a single sensor that can be configured for multiple frequencies. Therefore, reliable techniques for using a single FSD to generate multiple frequencies and for eliminating crosstalk in ultrasonic coexistence in FMS may be desirable.

[0031] Various embodiments of the present disclosure may provide solutions to one or more of the problems described above in connection with interference between multiple FSDs, where one FSD may detect a signal that is a reflected ultrasound signal of another FSD during fetal monitoring. In various embodiments, each FSD of the FMS may be tuned to a different resonant frequency of the LC network, and the corresponding DAC values may be stored in the FSD. An LC circuit (also referred to as an LC filter or LC network) may be defined as a circuit composed of passive circuit elements including an inductor (L) connected to a capacitor (C). An LC circuit may also be referred to as a resonant circuit, a storage circuit, or a tuning circuit. An LC circuit may be used to select or generate a signal at a specific frequency. Given the frequencies involved, the LC circuits herein may include large capacitance varactors / large impedance varactors. A varactor-based circuit may be used with a DAC to change the value of the capacitance (C) such that the LC may be tuned to different frequencies, depending on the frequency channel assigned to the FSD at a given moment. Multiple operating frequencies may be assigned to each FSD at different times. Tuning the FSDs may ensure that each FSD (e.g., each of three FSDs, etc.) may have a discrete frequency for modulation / demodulation, which may avoid crosstalk between the FSDs of the FMS. In various embodiments, a clock generation circuit may be used to generate a Doppler shift frequency, and driving a square wave (e.g., the LC storage may only allow the first harmonic sine wave to pass through) after attenuating the square wave into the receiving circuit may assist in automating the LC storage calibration process by changing the DAC voltage to maximize the amplitude of the offset sine wave seen at the input of the analog-to-digital converter (ADC). In various embodiments, the pulses or signals transmitted by the FSDs in the FMS may be phase-shifted until the artifacts of the FSDs may be reduced to zero. In this embodiment, the FSD with the largest amount of crosstalk components may act as the master FSD, and the other FSDs in the FMS may phase-shift the corresponding starts of their respective transmitted pulses relative to the master FSD until the crosstalk artifacts of the other FSDs may be reduced to zero. The phase shift may be performed until no crosstalk components remain in any FSD.

[0032] Various embodiments of the present disclosure ensure that each of multiple FSDs with discrete or differently tuned frequencies having an LC network can detect reflected ultrasonic waves at its own carrier frequency while minimizing crosstalk. Additionally, various embodiments of the present disclosure can perform periodic synchronization of the Tx enable and Rx enable pulse patterns of multiple FSDs via periodic pings from a monitoring system or by the master FSD to reduce crosstalk artifacts in the FMS. The embodiments discussed in the present disclosure can enable reliable monitoring of multiple fetal hearts, which can typically indicate a more complex delivery scenario. For example, the methods disclosed herein can reduce false fetal movement detections and unwanted Doppler audio noise. The reduction of the resulting false heart rates and confused situations related to the fetal heart across FSDs can ensure correct interpretation by the clinician and thus ensure timely action by the clinician. During fetal distress, the embodiments discussed herein can reduce the chance that an FSD presents an incorrect fetal heart rate and avoid otherwise catastrophic scenarios. The techniques disclosed in the present disclosure can use the same piezoelectric crystal to generate different frequencies and electronic tuning to create a universal FSD that can operate at multiple frequencies or FDM (with closer frequencies). Detection and elimination of crosstalk via suppression of known harmonics can additionally enable the clinician to reliably use FDM without any false FHR pickups.

[0033] The embodiments depicted in one or more of the figures described herein are for illustrative purposes only, and thus, the architecture of the embodiments is not limited to the systems, devices, and / or components depicted herein, nor to any particular order, connection, and / or coupling of the systems, devices, and / or components depicted herein. For example, in one or more embodiments, the non-limiting systems described herein (such as Figure 1 the non-limiting system 100 illustrated at [location]) and / or its systems can further include, be associated with, and / or be coupled to one or more computers and / or computing-based elements described herein with reference to an operating environment (such as Figure 14 the operating environment 1400 illustrated at [location]). For example, system 100 can be associated with (such as being able to access via) the computing environment 1400 described below with reference to Figure 14 such that aspects of the processing can be distributed between system 100 and the computing environment 1400. In one or more of the described embodiments, the computers and / or computing-based elements can be used in combination with the implementation Figure 1 and / or one or more of the systems, devices, components, and / or computer-implemented operations shown and described in the other figures described herein.

[0034] Figure 1 A block diagram of an exemplary non-limiting system 100 that allows coexistence of multiple FSDs in an FMS in accordance with one or more embodiments described herein is illustrated.

[0035] System 100 and / or components of system 100 can be used to solve problems that are highly technical in nature, not abstract, and cannot be performed as a set of mental acts of a human being (e.g., related to ultrasound technology, such as fetal monitoring, signal processing, etc.) using hardware and / or software. Additionally, some of the processes performed can be carried out by a dedicated computer for implementing defined tasks related to coexistence of ultrasound in FMS. System 100 and / or components of system 100 can be used to solve new problems arising from advancements such as those mentioned above. System 100 can provide technical improvements to FSM by generating lower noise in FSD, improving the sensitivity of FSD, and eliminating artifacts. System 100 can provide additional improvements by providing higher depth coverage in FDM compared to TDM.

[0036] The discussion simply turns to processor 102, memory 104, and bus 106 of system 100. For example, in one or more embodiments, system 100 can include a processor 102 (e.g., a computer processing unit, microprocessor, classical processor, and / or similar processor). In one or more embodiments, as described herein with reference to or without reference to one or more drawings of one or more embodiments, components associated with system 100 can include one or more computer and / or machine-readable, writable, and / or executable components and / or instructions that can be executed by processor 102 to permit execution of one or more processes defined by such components and / or instructions.

[0037] In one or more embodiments, system 100 can include a computer-readable memory (e.g., memory 104) that can be operably connected to processor 102. Memory 104 can store computer-executable instructions that, when executed by processor 102, can cause processor 102 and / or one or more other components of system 100 (e.g., frequency generation component 108, storage component 110, separation component 112, signal processing component 114, and / or synchronization component 116) to perform one or more actions. In one or more embodiments, memory 104 can store computer-executable components (e.g., frequency generation component 108, storage component 110, separation component 112, signal processing component 114, and / or synchronization component 116).

[0038] System 100 and / or its components as described herein may be communicatively, electrically, operationally, optically, and / or otherwise coupled to one another via bus 106. Bus 106 may include one or more of a memory bus, a memory controller, a peripheral bus, an external bus, a local bus, and / or another type of bus that may employ one or more bus architectures. One or more of these examples of bus 106 may be employed. In one or more embodiments, system 100 may be coupled (e.g., communicatively, electrically, operationally, optically, and / or similarly) to one or more external systems (e.g., an electrical output production system, one or more output targets, an output target controller, etc., not illustrated), sources, and / or devices (e.g., classical computing devices, communication devices, and / or similar devices) such as via a network. In one or more embodiments, one or more components of system 100 may reside in the cloud, and / or may reside locally in a local computing environment (e.g., at a specified location).

[0039] In addition to the above-described processor 102 and / or memory 104, system 100 may include one or more computer and / or machine-readable, writable, and / or executable components and / or instructions that, when executed by processor 102, may permit the performance of one or more operations defined by such components and / or instructions. For example, in various embodiments, frequency generation component 108 may generate an electronic signal at one or more different frequencies (e.g., frequency 118) in at least one FSD of the FMS using a variable frequency generator circuit (or variable frequency generation block), wherein at least one FSD may dynamically adjust the transmit voltage of at least one FSD to maintain an acoustic power value (i.e., the same acoustic power value) at one or more different frequencies, and wherein the electronic signal may cause a transducer of at least one FSD to generate an ultrasonic signal at one or more different frequencies. For example, various embodiments herein may implement FDM to simultaneously monitor multiple fetuses, wherein each sensor (i.e., each FSD) in the FMS may be configured by frequency generation component 108 to operate at different frequencies using a variable frequency generator circuit. Additionally, each sensor of the FMS may be fully reconfigurable, which may simplify the fetal monitoring task for a clinician or caregiver. For example, the FMS may include three sensors, sensor A, sensor B, and sensor C, wherein each of sensor A, sensor B, and sensor C may operate at any one of three frequencies F1, F2, and F3, depending on the connection order of sensors A, B, and C. For example, in one scenario, sensor A may be connected first, followed by sensors B and C to generate frequencies F1, F2, and F3. In a different scenario, sensor C may be connected first, followed by sensors B and A to generate frequencies F3, F2, and F1. For example, during a monitoring session, a sensor (e.g., sensor A, sensor B, or sensor C) may correspond to the frequency to which the sensor is locked. If the monitoring session ends and a new monitoring session begins, the first cable (associated with the sensor) that becomes connected may assume frequency F1. However, during a monitoring session with sensors A, B, and C, if a sensor is disconnected and reconnected, the sensor may resume generating frequencies F1, F2, and F3, respectively. The embodiments discussed herein may ensure good performance and efficiency of the FMS at all three frequencies using the same transducer. The FMS is also capable of being configured according to the number of FSDs, e.g., configured to include two FSDs for monitoring twin fetuses, three FSDs for monitoring triplets, and so on. Thus, dedicated FSDs may be utilized to monitor each fetus, and the dedicated FSD may emit a pulse (ultrasonic signal) and receive the pulse reflected from the fetus. It should be appreciated that a transducer refers to a piezoelectric element that can convert electrical energy into mechanical energy (i.e., the transducer is a piezoelectric crystal), and the transducer may be the passive part of the FSD / sensor.

[0040] In addition, the various embodiments herein ensure that the transducer of the FSD only receives signals having a frequency equal to the operating frequency / carrier frequency of the transducer to prevent signals from other FSDs having different carrier frequencies from being detected by the transducer. In other words, the various embodiments herein can isolate the FSDs to prevent the FSDs from detecting the heartbeat or fetal movement of a fetus not monitored by the FSDs, and thereby prevent confusion of the FSDs. Thus, the various embodiments herein enable the transducer to receive pulses at different frequencies based on the carrier frequency of the FSD. For example, in various embodiments, the FSD can include a tunable LC energy storage circuit that includes a large capacitance varactor that can tune the resonant frequency of the tunable LC energy storage circuit to the carrier frequency of at least one FSD, wherein tuning the resonant frequency of the tunable LC energy storage circuit to the carrier frequency of at least one FSD can include using a DAC to adjust the bias voltage of a balanced varactor network to dynamically change the capacitance value of the large capacitance varactor, and wherein the carrier frequency is a frequency selected from one or more different frequencies generated by the frequency generating component 108, which will be described in more detail below. In some embodiments, tuning the resonant frequency of the tunable LC energy storage circuit to the carrier frequency of at least one FSD can include using a voltage control mechanism different from the DAC, wherein the voltage control mechanism can be a resistor divider network, a DC regulator (which can generate a DC regulated voltage), or another type of voltage control mechanism. The tunable LC energy storage circuit can be a narrowband transducer, and since the resonant frequency of the tunable LC energy storage circuit is tuned to the carrier frequency of the FSD, the tunable LC energy storage can substantially suppress (i.e., suppress to a large extent) frequencies different from the carrier frequency of the FSD. The tunable LC energy storage circuit can provide narrowband amplification around the frequency of interest, thereby providing attenuation / partial suppression of small signals at other frequencies. In various embodiments, the tunable LC energy storage circuit can also act as an impedance matching circuit to minimize the phase difference between current and voltage from the transducer to the receiver circuit (by eliminating the imaginary component of the impedance).

[0041] In addition, a tunable LC energy storage circuit can assist in generating high gain and low noise amplification. For example, tuning the resonant frequency of the tunable LC energy storage circuit to the carrier frequency of the FSD can improve the receive sensitivity and gain of the tunable LC energy storage circuit at the carrier frequency. Tuning the resonant frequency of the tunable LC energy storage circuit to the carrier frequency of the FSD can also make the FSD insensitive to the corresponding carrier frequencies of additional FSDs. Additionally, tuning the resonant frequency of the tunable LC energy storage circuit to the carrier frequency of the FSD can characterize and compensate for the behavior of the resonant frequency of the tunable LC energy storage circuit caused by temperature fluctuations experienced by the FSD, such that the tunable LC energy storage circuit exhibits consistent performance despite temperature fluctuations. For example, the resonant frequency of the tunable LC energy storage circuit can be tuned once, but temperature fluctuations can shift the tuning frequency by biasing the tuning frequency. Various embodiments herein can characterize the temperature characteristics and maintain real-time changes to the tuning frequency value to maintain the performance of the tunable LC energy storage circuit. For example, in various embodiments, when the operating temperature of the FSD changes, the DAC value can also be changed to compensate for the thermal characteristics of the LC energy storage. In various embodiments, a variable frequency generator circuit can use an attenuated offset frequency to automate the calibration process for the tunable LC energy storage circuit. In some embodiments, the attenuated offset frequency can be a Doppler offset frequency. In other embodiments, the carrier can be biased with a smaller value that represents a value that can be seen in the Doppler shift caused by fetal heart tissue movement. Regarding the above discussion, hereinafter and with reference to Figure 3 , Figure 4 and Figure 5 the variable frequency generator circuit and the tunable LC energy storage circuit are described in more detail.

[0042] Clock generator :

[0043] A variable frequency generator circuit can be a clock generator (i.e., a tunable clock generator) that can generate odd frequencies (e.g., 1.151 megahertz (MHz), 1.162 MHz, etc.), and the clock generator can be programmed to generate a frequency based on the frequency assigned to the clock generator by a monitor or a master device. The clock generator can generate a frequency with high accuracy (e.g., as low as one part per million (ppm)) and extremely low jitter (e.g., 100 to 200 picoseconds (ps) or lower). The clock generator can assist in generating pulses to be transmitted, received pulses, and the switching required for actuation and pulses in combination with digital logic implemented prior to the clock generator to generate a variable clock. In various embodiments, each FSD of the FMS can include a clock generator, and the clock generator (e.g., by frequency generation component 108) can be used to generate a modulation (MOD) frequency for exciting a piezoelectric crystal, where the MOD frequency can refer to the carrier frequency of the FSD, such as, for example, 1.151 MHz, 1.162 MHz, etc. It should be recognized that the terms MOD frequency and carrier frequency have been used interchangeably throughout this specification. For example, the clock generator can excite a piezoelectric crystal (i.e., a transducer) for generating ultrasonic waves that can be directed at a fetus, reflected from the fetus, and returned to the piezoelectric crystal. To excite the piezoelectric crystal, the clock generator can generate a clock signal, where the clock signal is an electrical signal that can oscillate at a specific MOD frequency. The clock generator can provide a base frequency based on which waves can be shaped and driven by dedicated circuitry inside the FSD to drive the piezoelectric crystal. Thereafter, the piezoelectric crystal can convert the received reflected ultrasonic waves into electrical energy that can be processed during the signal processing stage. The clock generator can include a quartz crystal, such as the quartz crystals commonly used in electronic devices. It should be recognized that a quartz crystal and a piezoelectric crystal are different elements. As noted above, a piezoelectric crystal can be used to transmit and receive ultrasonic waves but not for generating the clocks used to generate different frequencies as discussed herein. The clock generator can further include a fractional multiplier, which can be a phase-locked loop (PLL) for multiplying the crystal frequency by a value X and further dividing the result to generate a desired MOD frequency (e.g., frequency 118). For example, the clock generator can generate a MOD frequency, a second frequency equal to 8× the MOD frequency, and a third frequency equal to the MOD frequency + 200 hertz (Hz). The MOD frequency can be used to drive and actuate the piezoelectric crystal in the FSD. The 8×MOD frequency can be a higher frequency generated by the clock generator and used to drive a processor, and the 8×MOD frequency can be sent to the processor to drive the digital logic inside the processor. The MOD frequency + 200 Hz frequency can be used to calibrate a tunable LC energy storage circuit. It should be recognized that the frequencies described herein are exemplary and not specific. Thus, a clock generator (e.g., by frequency generation component 108) can be employed to generate multiple MOD frequencies.

[0044] Tunable LC energy storage circuit :

[0045] The signal reflected from the fetus to the piezoelectric crystal in the FSD (i.e., the reflected signal) can be directly processed by the LC energy storage circuit. For example, the input of the tunable LC energy storage circuit can be an electrical signal received from the piezoelectric crystal and generated by the piezoelectric crystal by converting the ultrasonic wave reflected from the fetus into electrical energy. The tunable LC energy storage circuit can include an inductor and a capacitor, where the inductor can be a simple inductor, and the capacitor can be a simple capacitor. It is known that an inductor and a capacitor together can form a resonant circuit. As discussed above, the tunable LC energy storage circuit can further include a large-capacitance varactor, which can tune the resonant frequency of the tunable LC energy storage circuit to the carrier frequency of the FSD. A varactor is a diode-like component. However, a varactor can have a tunable capacitance, where the capacitance of the tunable varactor is based on the bias voltage. The capacitor of the tunable LC energy storage circuit can be divided into multiple sections for fine-tuning the precise capacitance value. For example, the capacitance of the tunable LC energy storage circuit can be divided into two parallel capacitances from two capacitors connected in parallel, followed by the capacitance from the varactor and some additional capacitance from the diode in the tunable LC energy storage circuit. The capacitance values from the two parallel capacitors and the diode can be fixed values, and the varactor can generate a variable capacitance. A varactor can be introduced into the tunable LC energy storage circuit to precisely tune the FSD by tuning the varactor to generate a precise capacitance representing the carrier frequency of the FSD. For example, when manufacturing the FSD, due to the presence of dust, the amount of solder, etc., the corresponding capacitance on the FSD board may vary from unit to unit. Due to manufacturing process variations, parasitic capacitance and inductance can also cancel out the rotation of the fixed capacitance. Therefore, it may be beneficial to tune the resonant frequency of the tunable LC energy storage circuit on each device (e.g., each FSD). The resonant frequency (f) of the FSD can be determined using Equation 1.

[0046] Equation 1:

[0047] As is evident from Equation 1, the capacitance value of the tunable LC energy storage circuit determines the frequency to which the tunable LC energy storage circuit can be tuned. In this regard, tuning the tunable LC energy storage circuit to the carrier frequency can result in better gain and sensitivity at the carrier frequency, as discussed in various embodiments herein. During operation, the reflected ultrasonic signal received and converted into electrical energy by the piezoelectric crystal can enter three capacitors, including two capacitors connected in parallel and the diode of the tunable LC energy storage circuit. Once the electrical signal is tuned, the electrical signal can oscillate back and forth between the inductor-capacitor and the midpoint of the tunable LC energy storage circuit, and the electrical signal can become amplified. Thereafter, the amplified signal can proceed to subsequent amplification sections. In this way, the tunable LC energy storage circuit can pre-amplify the electrical signal.

[0048] Various embodiments herein can also address the various crosstalk scenarios that can occur in an FMS. Generally, in the case of multiple FSDs, the FMS can be designed for microvolt (μV) and sub-microvolt (sub-μV) level signals, as the FSDs can be expected to receive only a small fraction of the signals in the form of reflected signals. However, in scenarios where two FSDs are placed directly opposite each other and direct ultrasonic pulses into each other, it can be expected that the FSDs will receive higher voltage (V) level signals. In such scenarios, the ultrasonic pulses received by the FSDs can also include strong reflected signals that correspond to signals transmitted by the other FSD based on the two FSDs feeding signals into each other. Such scenarios can generate crosstalk where the tunable LC energy storage circuits of the FSDs cannot fully attenuate and prevent unwanted signals from other FSDs from entering the FSDs. This is because the corresponding amplitudes of the signals from the transducers of the other FSDs can be very large, and signal attenuation does not assist in this regard. Due to crosstalk, several problems can occur, resulting in the generation of false heartbeats, which can be a serious problem in fetal monitoring.

[0049] In this regard, system 100 can generate predictable results from all crosstalk scenarios to selectively eliminate all artifacts. For example, in various embodiments, the separation component 112 can separate the respective carrier frequencies of multiple FSDs in the FMS such that the frequency difference between the carrier frequencies of any two FSDs is not a multiple of the PRR of either FSD. In other words, the separation component 112 can separate the MOD frequencies of the FSDs in the FMS such that the difference between the MOD frequencies of one FSD and another FSD cannot be a multiple of the PRR of the other FSD. The MOD frequency of an FSD is the internal higher carrier frequency transmitted by the FSD, and the difference between the MOD frequencies of two FSDs cannot be a multiple of the PRR of either FSD because such scenarios can lead to aliasing and signal confusion. Thus, isolating the MOD frequencies can prevent interference between two FSDs. The PRR of an FSD can be defined as a complete cycle of the transmitted signal and the received reflected signal. In other words, the PRR of an FSD can be defined as the rate at which a complete cycle can occur for the FSD, which complete cycle consists of the period of the transmission Tx and reception Rx of the pulse. Alternatively, the PRR refers to the number of ultrasonic pulses transmitted per defined time period, or more specifically, the repetition rate of the Tx and Rx periods. For example, an FSD can transmit ultrasonic pulses at a carrier frequency during a transmit (Tx) duration and receive the corresponding reflected pulses every 250 microseconds (μs), such that the PRR of the FSD is 4 kilohertz (kHz) according to Equation 1. In various embodiments, the separation component 112 can select odd frequencies (e.g., 1.152 MHz, 1.162 MHz, etc.) as the carrier frequencies of the FSDs in the FMS such that the difference between any two MOD frequencies is not a multiple of the PRR of the FSD to generate predictable harmonics that can be used to control crosstalk. Equation 2 (e.g., by the separation component 112) can be used to determine the difference (delta / Δ) between the MOD frequencies of the transducers for separating the MOD frequency of one transducer based on the MOD frequency of another transducer. That is, the MOD frequencies of two transducers can be separated by using Equation 2.

[0050] Equation 2: (p × (p - 1) - 1) kHz, where "p" represents the PRR of the FSD in kHz.

[0051] Separating the MOD frequencies using the above method makes crosstalk predictable and easier to eliminate, where crosstalk can otherwise remain unmanifested as crosstalk. For example, separating the MOD frequency / corresponding carrier frequency of a transducer can generate predictable harmonics during crosstalk in an FMS, where the predictable harmonics can be selectively eliminated during the signal processing stage of the sensor. For example, separating the corresponding carrier frequencies of (multiple) FSDs can cause the first carrier frequency of the first FSD among the multiple FSDs to be demodulated by the second carrier frequency of the second FSD among the multiple FSDs, which can generate predictable harmonics in the FMS. For example, for p = 4 in Equation 2, harmonics of 1 kHz, 2 kHz, and 3 kHz can be generated every 1 kHz from 1 kHz to (p - 1) kHz, and these harmonics can be eliminated to avoid crosstalk. Normally, fetal monitoring can involve frequencies at the sub-kHz level as opposed to specific frequencies (e.g., 1 kHz, 2 kHz, 3 kHz, etc.), and a clinician can look for fetal heart rate and variability of the heart rate during fetal monitoring. Harmonics and corresponding crosstalk effects can be eliminated by implementing a filter that can notch the harmonic frequencies and by implementing an AGC stage that can normalize the signal amplitude. For example, in various embodiments, the signal processing component 114 can implement the AGC stage and the filter to selectively eliminate the predictable harmonics to eliminate crosstalk in the FMS, where the automatic gain control stage can be implemented as software, hardware, or a combination of software and hardware. Normalizing the signal amplitude can remove the very low frequencies that result from crosstalk, and the notch filter can be implemented once every 1 kHz, where the notch filter can clear the harmonics. As previously stated, the AGC stage can be implemented as a firmware / signal processing software algorithm, and the filter can be implemented after the AGC stage to eliminate the 1 kHz, 2 kHz, and 3 kHz harmonics that can interfere with fetal heart rate detection. Both the 1 kHz filter and the algorithm for the AGC stage can be implemented in the signal processing core of a microcontroller. The AGC stage and the 1 kHz filter can be implemented much later in the signal chain than a tunable LC energy storage circuit. In one embodiment, the filter can be implemented without implementing the AGC stage; however, a performance tradeoff can be expected without the AGC stage.

[0052] Eliminating crosstalk by separating the MOD frequency of a transducer and generating predictable harmonics can depend on the accuracy of the MOD frequency generated by a clock generator. For example, the methods discussed above may require a highly accurate frequency to generate predictable harmonics because inaccuracies in the MOD frequency can generate significant noise other than harmonics. For example, inaccuracies in the MOD frequency can generate differences between frequencies where such differences are not multiples of the 1 kHz, 2 kHz, or 3 kHz harmonics. To ensure that an accurate MOD frequency is generated by the clock generator of the FSD, frequency calibration techniques can be implemented during the manufacture of the FSD. The frequency calibration techniques can compensate for inaccuracies in the MOD frequency by generating a frequency that can be biased based on an input clock. For example, if the clock generator generates a MOD frequency of 1.151 MHz + 5 Hz, the clock generator can be reconfigured (e.g., by frequency generation component 108) to generate 1.151 MHz to 5 Hz such that the total frequency generated by the clock generator can be 1.151 MHz. The design of the FSD can include provisions for calibrating the MOD frequency generated by the FSD to an accuracy of up to about 1 Hz or less. Calibration of the FSD can be performed by measuring in real time the frequency generated by the clock generator and compensating for the frequency generated by the clock generator. The calibration can be a digital calibration (e.g., by frequency generation component 108) performed via software.

[0053] In various embodiments, the synchronization component 116 may perform periodic PRR synchronization to synchronize the start of the transmission period of the FSD with the corresponding start of the transmission periods of one or more additional FSDs in the FMS to prevent the ultrasonic signals generated by the FSD from being demodulated by the corresponding carrier frequencies generated by one or more additional FSDs in the FMS, thereby preventing crosstalk in the FMS. It should be recognized that after the ultrasonic signal from the FSD is received by another FSD, converted into an electrical signal by the transducer (piezoelectric crystal) of another FSD, and processed by the tunable LC energy storage circuit of another FSD, the ultrasonic signal generated by the FSD may be demodulated by another FSD. The synchronization component 116 may synchronize the start of the transmission period of the FSD relative to another FSD and synchronize the corresponding PRRs of the FSDs in the FMS such that even in the case of a small bias in the MOD frequency generated by the corresponding clock generators of the transducers, the corresponding PRRs may remain synchronized. For example, due to the clock difference between transducers, one transducer may have a PRR of 3.9 kHz while another transducer may have a PRR of 4 kHz. In this case, the synchronization component 116 may perform periodic PRR synchronization to ensure that both transducers can transmit pulses at a PRR of 4 kHz. PRR synchronization may involve synchronizing the start of the transmit (Tx) pulse of the FSD with the start of the Tx pulse of another FSD. It should be noted that the 3.9 kHz PRR does not become fixed at 4 kHz after synchronization, i.e., PRR synchronization may prevent the corresponding transmit (Tx) and receive (Rx) pulses of the FSD from drifting across each other to substantially prevent any crosstalk via low-frequency harmonics without changing the PRR of the FSD. Thus, PRR synchronization may prevent the generation of lower-frequency noise during crosstalk. Generally speaking, the difference in PRRs may be on the order of a single-digit frequency (Hz) or much lower (e.g., on the order of millihertz (mHz)). Long before the Tx pulse of the FSD can overlap the entire pulse repetition period, the synchronization component 116 may synchronize (periodically, only once in a while) the start of the transmission period of the FSD relative to another FSD or a central hub to return the start of the transmission period to its initial position and cancel drift. The frequency at which synchronization is performed may be determined by the maximum possible frequency bias between any two sensors and may be much higher than the frequency difference from the ideal expected difference. For example, a 10 mHz difference in the PRRs of any two FSDs may mean that synchronization may be performed every 100 mHz such that the Tx pulse can be returned to its initial position before a 10% drift. That is, synchronization may be performed every 10 seconds. PRR synchronization may ensure that the corresponding Tx pulses of the FSDs can pulse simultaneously.

[0054] As stated above, periodic PRR synchronization can be performed by using a monitor to generate checks in real time or by using electrodes and a primary transducer to send signals to an additional transducer. In some embodiments, the signal sent by the primary transducer can be a high-frequency low-current signal. Periodic PRR synchronization can be performed wirelessly or via a wired connection, i.e., synchronization can also be performed in a wired FSD system. For example, the synchronization component 116 can synchronize the start of the transmission period of the FSD via a primary hub or monitor that can act as a primary device for controlling the transducer of the FMS or via an FSD that can control other transducers in the FMS. In some embodiments, after separating the respective MOD frequencies of the transducer to generate predictable harmonics, PRR synchronization can be achieved without implementing an AGC stage (i.e., by only using a filter). In other embodiments, the PRR synchronization technique can be implemented together with an AGC stage having a filter for eliminating crosstalk.

[0055] Enabling PRR synchronization of the FSD can remove lower-frequency noise generated in the FMS, but not harmonics (e.g., 1 kHz, 2 kHz, etc.). Additionally, since ultrasound can travel relatively slowly, PRR synchronization may be unhelpful in some scenarios. In a fetal monitoring scenario where two FSDs can be directly positioned opposite each other on a pregnant woman's abdomen, the signal sent from the first FSD of the two FSDs can enter the reception period of the second FSD. The reception period of the FSD can refer to the period after the FSD has sent a signal, during which the FSD can expect to receive a reflected signal. Thus, the second FSD can receive the signal sent by the first FSD as well as the reflected signal corresponding to the signal sent by the second FSD. Since the signal from the first FSD is direct, the intensity of the signal sent by the first FSD and received by the second FSD can be high, and such scenarios can generate harmonics such as 1 kHz, 2 kHz, 3 kHz, etc. At the same time, the first FSD can also receive the signal sent by the second FSD and the reflected signal corresponding to the signal sent by the first FSD.

[0056] In this regard, the various embodiments of the present disclosure may enable additional techniques to prevent crosstalk in the scenarios discussed herein. For example, in various embodiments, the synchronization component 116 may use a control system to perform pulse phase synchronization to prevent a signal transmitted by a first FSD from entering the reception period of a second FSD that is positioned a distance directly across from the first FSD, where the control system may measure the amount of harmonics generated by the first FSD at the second FSD and gradually offset the phase of the signal transmitted by the first FSD to align the signal transmitted by the first FSD with the signal transmitted by the second FSD in the FMS. For example, the first FSD may be operatively coupled to the control system without coupling the second FSD to the control system. The control system may measure the amount of harmonics generated by the first FSD at the second FSD (e.g., using the synchronization component 116) (since the second FSD may demodulate the transmitted pulse / signal of the first FSD), and the control system may gradually phase shift the signal transmitted by the first FSD, which may cause the signal transmitted by the first FSD to overlap with the signal transmitted by the second FSD and prevent the signal transmitted by the first FSD from entering the reception period of the second FSD.

[0057] Accordingly, the synchronization component 116 may offset the phase of a signal from one FSD to align the signal with another signal from another FSD, thereby preventing the signal from entering the reception period of the other FSD. This may be done by considering the travel time of the signal from the FSD. Such techniques may eliminate the need to remove crosstalk. Additionally, during crosstalk, the reflected signal received by the FSD (e.g., the signal reflected from the fetus) may sometimes be very weak, and in such cases, in addition to the reflected signal, the direct signal received by the FSD from another FSD may saturate the reflected signal. In this scenario, even if the crosstalk is eliminated, the reflected signal may become lost. Phase shifting the signal as described above may prevent saturation of the reflected signal and improve the reception sensitivity of the FSD. That is, aligning the corresponding signals transmitted by the FSDs may prevent any large signal from overwhelming the corresponding receive chain of either FSD during their corresponding reception periods. This may allow a greater amount of voltage to be available for the FSD to receive and amplify the reflected signal, e.g., compared to a scenario where the transducer may receive the reflected signal as well as the transmitted signal from another transducer.

[0058] More specifically, using predictable harmonics (1 kHz, 2 kHz, etc.), the control system can shift the transmitted signal / pulse (Tx) in time (i.e., change the phase of the pulse). In this embodiment, the PRR of the transmitted pulse can remain constant, and the control system can shift the Tx pulse to the right or left in time from the FSD and monitor the generated harmonics to determine when the harmonics disappear. The Tx pulses from the two FSDs can continue to be regularly transmitted with a constant time difference (e.g., 50 microseconds (μs), 60 μs, etc.). That is, the PRR of the Tx pulses can remain the same, but due to the phase shift, the positions of the Tx pulses can be different in time. Thus, when the Tx pulse from one FSD can reach the second FSD, the Tx pulse can violently enter the transmission of the second FSD during the reception period of the second FSD rather than intrude. Therefore, the phase shift can prevent crosstalk pulses from being received by the FSD, and crosstalk can be eliminated.

[0059] In various embodiments, by synchronizing the phases and PRRs of the respective transmitted pulses of the FSDs in the FMS, the implementation of an AGC stage with a filter can be avoided.

[0060] Figure 2 FIG. Exemplary non - limiting pulse repetition period 200 according to one or more embodiments described herein. Refer to Figure 2 One or more of the described embodiments can be implemented by one or more components of system 100. For the sake of brevity, the repeated description of similar elements and / or processes employed in the respective embodiments is omitted.

[0061] Generally speaking, compared with ultrasonic imaging that can use a relatively high acoustic power, FSD uses a relatively low acoustic power, which allows for a longer duration of fetal monitoring. The transducer operates based on the principle of Doppler shift, where pulses can be sent from a sensor at an object or location of interest, and the sensor can look for reflected signals. In the case of fetal monitoring, the reflected signal with a Doppler shift frequency can indicate that movement has been detected. A clinician can use FSD to detect regular movements that can be related to the fetal heartbeat and used to determine the fetal heart rate. FSD can also be used to detect lower frequency movements, such as those related to the fetus's breathing, rotation, or other movements within the mother's uterus, and different frequencies can be used to identify fetal movements and the fetal heart rate. Typically, the sensor can operate in TDM or FDM. Most sensors operate under TDM, where one sensor in the sensor system can send a pulse and receive the reflected pulse, followed by another sensor sending and receiving a pulse, as opposed to all sensors in the sensor system sending and receiving pulses at once or in an uncorrelated random sequence. Thus, in TDM, each sensor can complete one cycle of continuously sending and receiving pulses, and the TDM cycle can continue to alternate between sensors. TDM can prevent interference between the transducer and the sensor. However, due to less available sensing time, it may be challenging to monitor multiple fetuses (e.g., for triplets, quadruplets, etc.) using TDM. Additionally, the signal quality may be compromised under TDM. In this regard, the various embodiments discussed herein can allow multiple sensors to operate simultaneously using FDM.

[0062] According to the various embodiments discussed herein, the non-limiting pulse repetition period 200 (pulse repetition period 200) can represent the period during which FSD can send a signal (as illustrated by transmit signal 202) and receive a reflected signal corresponding to the transmit signal 202 (as illustrated by receive signal 204). According to Equation 3, the pulse repetition period of FSD can be related to the PRR of FSD.

[0063] Equation 3:

[0064] It is known that for FDM in an ultrasonic Doppler system, piezoelectric crystals with different center frequencies need to be used. However, as in Figure 5As seen in the FEM simulations presented herein, the range of frequencies at which maximum sensitivity can be achieved is large enough to accommodate multiple carrier frequencies that can be separated reasonably far from each other. In this regard, various embodiments of the present disclosure may enable a transducer to operate at multiple frequencies and ensure consistent performance of the transducer at each frequency. Doing so may enable FMSs to operate with a general-purpose FSD that can reconfigure themselves and be used interchangeably. Separating the frequencies of the same crystal may not be sufficient to fully avoid crosstalk unless the carrier frequencies can be appropriately selected in conjunction with additional artifact cancellation techniques. Accordingly, methods for achieving multiple frequencies using a single transducer and for selecting carrier frequencies using artifact cancellation techniques are disclosed with reference to the subsequent figures.

[0065] Figure 3 FIG. 300 is a block diagram of an exemplary non-limiting clock generator that can generate one or more different frequencies in an FSD in accordance with one or more embodiments described herein. Referring to Figure 3 the one or more embodiments described can be implemented by one or more components of system 100. For the sake of brevity, repeated descriptions of similar elements and / or processes employed in the corresponding embodiments are omitted.

[0066] As referred to Figure 1 to above, the frequency generation component 108 can generate multiple different desired frequencies in the FSD of the FMS using a variable frequency generator circuit (or variable frequency generation block), where the FSD can dynamically adjust the transmit voltage of the FSD to maintain the same acoustic power value at one or more different frequencies. The range of frequencies at which the FSD can achieve maximum sensitivity can be large enough to accommodate multiple carrier frequencies that can be separated to be reasonably far from each other. Accordingly, the embodiments disclosed herein for artifact cancellation can ensure that the multiple carrier frequencies can be far enough apart (e.g., although in the vicinity) to separate signals. In combination with the crosstalk cancellation techniques discussed in one or more embodiments, the range of frequencies can be sufficient to handle any artifacts. For receive sensitivity, the FSD can utilize a tunable LC energy storage circuit having a large capacitance varactor as Figure 4 illustrated. Using a DAC (or other voltage control mechanism), the bias voltage of the balanced varactor network can be adjusted to tune the resonant frequency of the LC energy storage to the corresponding FDM frequency (i.e., the carrier frequency of the FSD). It should be recognized that the terms "tunable LC energy storage circuit," "tunable LC energy storage circuit system," "LC energy storage," and "LC circuit" can be used interchangeably throughout this specification. An LC circuit (also referred to as an LC filter or LC network) can be defined as a circuit composed of passive circuit elements including an inductor and a capacitor connected together. An LC circuit can also be referred to as a resonant circuit, an energy storage circuit, or a tuning circuit. An LC circuit can be used to selectively pick out or generate a signal at a specific frequency.

[0067] The purpose of LC energy storage can be threefold. For example, LC energy storage can provide noiseless amplification of the received signal, act as a filter and provide narrowband amplification of only each specific frequency, thereby providing some isolation from other FDM frequencies in a multi-transducer system (e.g., FMS), and optimizing the loop gain of the system. The open-loop gain can be proportional to the conversion efficiency of the transducer and the cosine of the phase difference between the current and voltage from the transducer to the receiver circuit. The LC network can act as an impedance matching circuit to minimize the phase difference, thereby maximizing the cosine value to improve the open-loop gain.

[0068] In various embodiments, a variable frequency generator circuit can generate a decaying offset frequency (which simulates a Doppler-shifted reflected signal) to automate the calibration process for a tunable LC energy storage circuit. The variable frequency generator circuit can be a clock generator (e.g., clock generator 302) that can generate odd frequencies (e.g., 1.151 MHz, 1.162 MHz, etc.), and the clock generator 302 can be programmed to generate a frequency based on the frequency assigned to the clock generator 302 by a monitor or master device. The clock generator can assist in generating the pulses to be transmitted, received pulses, and the switching required for actuation and pulses in combination with the digital logic implemented prior to the clock generator to generate a variable clock. In various embodiments, each FSD of an FMS can include a clock generator (e.g., clock generator 302), and the clock generator can be used to generate a MOD frequency for exciting a piezoelectric crystal (i.e., a transducer), where the MOD frequency can refer to different operating frequencies of the FSD, such as, for example, 1.151 MHz, 1.162 MHz, etc. For example, the clock generator can excite the piezoelectric crystal to generate ultrasonic waves (or pulses / signals) that can be directed at a fetus, reflected from the fetus, and returned to the piezoelectric crystal. To excite the piezoelectric crystal, the clock generator can generate a clock signal, where the clock signal is an electrical signal that can oscillate at a specific MOD frequency. The clock generator can provide a base frequency based on which the wave can be shaped and driven by dedicated circuitry inside the FSD to drive the piezoelectric crystal. Thereafter, the piezoelectric crystal can convert the reflected ultrasonic waves into electrical energy that can be processed during the signal processing stage.

[0069] The clock generator 302 may include a crystal 304, where the crystal 304 may be a quartz crystal. It should be recognized that a quartz crystal and a piezoelectric crystal are different components. As pointed out above, a piezoelectric crystal can be used to transmit and receive ultrasonic waves, but not for generating the clocks of different frequencies used by the clock generator 302 as discussed herein. The clock generator 302 may further include a PLL A (fractional multiplier) 306, and the fractional multiplier may be a PLL for multiplying the crystal frequency by a value X and further dividing the result to generate a desired MOD frequency. The clock generator 302 may generate a MOD frequency (illustrated at 310), a second frequency equal to 8×MOD frequency (illustrated at 308), and a third frequency equal to MOD frequency + 200 Hz (illustrated at 312). The MOD frequency may be used to drive and actuate the piezoelectric crystal in the FSD. The 8×MOD frequency may be the higher frequency generated by the clock generator and used to drive the processor, and the 8×MOD frequency may be sent to the processor to drive the digital logic inside the processor. The MOD frequency + 200 Hz frequency may be used to calibrate the tunable LC energy storage circuit. It should be recognized that the frequencies and configurations described herein are exemplary rather than specific. For example, the second frequency (illustrated at 308) may be Z×MOD frequency, where Z may be 8 or another value, and the third frequency (illustrated at 312) may be MOD frequency + Y Hz, where Y may be 200 or another value. Similarly, the MOD frequency may be a multiple of the MOD frequency (illustrated at 310). Therefore, the MOD frequency can be used as a carrier, the 8×MOD frequency can be used as a source for the digital section, and the MOD frequency + 200 Hz frequency can allow automatic calibration of the LC energy storage. Thus, a clock generator (e.g., by the frequency generation component 108) may be employed to generate multiple MOD frequencies.

[0070] Figure 4 A circuit diagram of an exemplary non - restrictive tunable LC energy storage circuit 400 including a large - capacitance varactor is illustrated in accordance with one or more embodiments described herein. Refer to Figure 4 One or more of the described embodiments may be implemented by one or more components of the system 100. For the sake of brevity, the repeated description of similar elements and / or processes employed in the corresponding embodiments is omitted.

[0071] Continue to refer to Figure 1 and Figure 3, various embodiments of the present disclosure disclose a method in which the FSD can be calibrated to maximize the gain at each frequency (thus ensuring tuning to the resonant frequency of the LC network). The corresponding DAC values can be stored in the FSD. For example, a variable frequency generator circuit can use a damped offset frequency to automate the calibration process for the tunable LC energy storage circuit, and in which the FSD can be calibrated to maximize the gain at the carrier frequency of the FSD, where the carrier frequency can be a frequency selected from one or more different frequencies generated by a clock generator (variable frequency generator circuit). The storage component 110 can store the DAC values corresponding to maximizing the gain of the tunable LC energy storage circuit at the carrier frequency of the FSD. In various embodiments, the storage component 110 can store multiple DAC values (or multiple values corresponding to another voltage control mechanism) on a single FSD, because each frequency generated by the variable frequency generator circuit can have a corresponding DAC value. Thus, after the calibration process, all DAC values corresponding to each of the one or more carrier frequencies generated in the FSD can be stored in the FSD. When the FSD is turned on, the FSD can be selected or signaled (e.g., by the frequency generation component 108, monitor) to select an operating channel and configure the non-limiting tunable LC energy storage circuit 400 (tunable LC energy storage circuit 400) to the DAC value corresponding to the FDM frequency. The clock generator 302 (e.g., clock generation circuit) can generate the same discrete frequencies for modulation / demodulation.

[0072] As stated elsewhere herein, the clock generator 302 (e.g., by the frequency generation component 108) can also be used to generate an offset frequency (e.g., Doppler offset frequency), and driving the square wave after attenuating it into the receiving circuit (the tunable LC energy storage circuit 400 may only allow the first harmonic sine wave to pass through, while the higher order harmonics undergo significant attenuation) can help automate the calibration process for the tunable LC energy storage circuit 400 by changing the DAC voltage to maximize the amplitude of the offset signal of interest at the ADC. Additionally, the resonant frequency of the tunable LC energy storage circuit 400 can drift with temperature due to changes in the winding inductance and capacitance added by the varactor. The behavior of the resonant frequency can be characterized and compensated to ensure consistent performance of the tunable LC energy storage circuit 400 across various operating conditions. For example, in various embodiments, when the operating temperature of the FSD changes, the DAC value can also change to compensate for the thermal characteristics of the LC energy storage.

[0073] The input of the tunable LC energy storage circuit 400 can be an electrical signal received from a piezoelectric crystal and generated by the piezoelectric crystal by converting ultrasonic waves reflected by a fetus into electrical energy, as illustrated by input 410. The tunable LC energy storage circuit 400 can include an inductor (LA) and a capacitor, where the inductor can be a simple inductor and the capacitor can be a simple capacitor. The tunable LC energy storage circuit 400 can further include large-capacitance varactors DA, DB, DC, and DD, which can tune the resonant frequency of the tunable LC energy storage circuit 400 to the carrier frequency of the FSD. Given the lower operating frequency of the FSD described herein compared to the high-frequency applications of varactors, various embodiments herein can employ large-capacitance varactors. A varactor is a diode-like element. However, a varactor can have a tunable capacitance, where the capacitance of the tunable varactor is based on the bias voltage. More specifically, given the fluctuations in the bias voltage due to the input signal in the tunable LC energy storage circuit 400, the varactor network illustrated in the tunable LC energy storage circuit 400 can be used to balance the capacitance in the tunable LC energy storage circuit 400. In circuit 400, DA, DB, DC, and DD form a balancing network / varactor network. In the tunable LC energy storage circuit 400, the entire circuit below the horizontal line connecting the inductor to the midpoint (LNA_FRONTEND_OUT) can be considered a single capacitor. The capacitor of the tunable LC energy storage circuit 400 can be divided into multiple segments for fine-tuning the exact capacitance value. For example, the capacitance of the tunable LC energy storage circuit 400 can be divided into two parallel capacitances from two capacitors connected in parallel (capacitor CA illustrated at 402 and capacitor CB illustrated at 404), followed by the capacitance from the varactors and some additional capacitance from the diodes of the tunable LC energy storage circuit 400 located after the varactors. Capacitors CA and CB can be used as fixed capacitors to obtain a tuned LC voltage while accommodating the swing that can be delivered by the varactor network. Capacitors CC and CD can be used to isolate the bias voltage from the main signal line. The capacitance value of the varactors can be dynamically changed using a reverse bias generated / regulated by a DAC, such that the tunable LC energy storage circuit 400 can be tuned to the carrier frequency being used by the FSD. It should be recognized that, Figure 4 The configuration of the tunable LC energy storage circuit 400 illustrated therein is exemplary, and the LC circuits discussed in one or more embodiments can have different configurations.

[0074] The capacitance values from two parallel capacitors (i.e., CA and CB) and a diode (illustrated at 414) can be fixed values, and a varactor can generate a variable capacitance. The use of the diode in the tunable LC energy storage circuit can allow (by clamping) control of the gain of large-level signals such as transmit pulses of the same transducer or crosstalk transmit signals from different transducers. The diode can also add a fixed capacitance in parallel with the signal line. The fixed-value capacitor can be used to provide a base value, and the varactor can add capacitance based on this base value to adjust the total value of all parallel capacitors. In various embodiments, C0G capacitors can be selected to maximize the stability of the capacitance value, and lower-resistance inductors / lower-leakage-current diodes can be used to minimize losses. A varactor can be introduced into the tunable LC energy storage circuit 400 to precisely tune the FSD by tuning the varactor to generate an exact capacitance representing the carrier frequency of the FSD. For example, when manufacturing the FSD, due to the presence of dust, the amount of solder, etc., the corresponding capacitance on the FSD board may vary from unit to unit. The varactor can also account for variations in the inductance of the inductor. The resonant frequency of the FSD / the resonant frequency (f) can be determined using Equation 1.

[0075] The input 410 can enter three capacitors, including two capacitors connected in parallel and the diode of the tunable LC energy storage circuit 400. Once the electrical signal represented by the input 410 is tuned, the electrical signal can oscillate back and forth between the inductor-capacitor and the midpoint of the tunable LC energy storage circuit 400 (LNA_FRONTEND_OUT illustrated at 412), and the electrical signal can become amplified. Thereafter, the amplified signal can continue to the subsequent amplification section. In this way, the tunable LC energy storage circuit 400 can pre-amplify the electrical signal. Therefore, the midpoint (LNA_FRONTEND_OUT) can continue to the subsequent amplification section, such that when the signal leaves the tunable LC energy storage circuit 400, unwanted signals outside the frequency band of the tuned LC circuit can become attenuated.

[0076] Figure 5 An exemplary non-limiting graph 500 of an FEM simulation in accordance with one or more embodiments described herein is illustrated. Refer Figure 5 One or more of the described embodiments can be implemented by one or more components of the system 100. For the sake of brevity, the repeated description of similar elements and / or processes employed in the corresponding embodiments is omitted.

[0077] Continuing to refer Figure 1 、 Figure 3 and Figure 4, the non-limiting graph 500 (graph 500) illustrates a FEM simulation of the piezoelectric efficiency of a device, showing multiple options for FDM while ensuring maximum sensitivity. In various embodiments, the piezoelectric crystal (transducer) can be a narrowband crystal. Various embodiments herein can employ narrowband transducers to achieve the conversion efficiency in FMS. Narrowband transducers can operate with high efficiency at specific frequencies. For FDM, the MOD frequency of FSD may require similar sensitivity. In graph 500, curve 502 can represent the acoustic efficiency of FSD, and curve 506 can represent the electrical efficiency of FSD. Curve 504 can be generated by combining curve 502 and curve 506, and curve 504 can show the degree to which FSD can be sensitive to different frequencies. For example, the highlighted points on curve 504 can indicate the MOD frequencies (e.g., between 1.16 MHz and 1.2 MHz) to which FSD can be sensitive. Each line of curve 502 can represent the characteristics of FSD. Herein, all FSDs can have the same family of piezoelectric crystals, and variations in the characteristics of individual FSDs can be caused by manufacturing process defects and crystal tolerances. Curve 504 can indicate the overall efficiency of FSD, directly indicating the sensitivity performance of FSD. Curve 506 can represent the electrical efficiency of different transducers. For example, curve 506 illustrates five samples of electrical efficiency plotted at different frequencies. It is evident from graph 500 that there can be multiple frequencies that provide similar efficiency, as indicated by the highlighted points on curve 504. There can be various possibilities for the MOD frequency, and all extreme cases can be considered.

[0078] Figure 6 A figure illustrating an exemplary non-limiting interference pattern 600 representing crosstalk artifacts according to one or more embodiments described herein. Refer to Figure 6 One or more embodiments described can be implemented by one or more components of system 100. For the sake of brevity, the repeated description of similar elements and / or processes employed in the corresponding embodiments is omitted.

[0079] Continuing to refer to Figure 1, various embodiments of the present disclosure can generate predictable results from all crosstalk scenarios to selectively eliminate all artifacts and ensure the reliability of the FMS. This can be achieved by selecting specific excitation and reception schemes to avoid signal aliasing and generate noise that is always modulated to a predictable 1 kHz harmonic, which can be used to identify and eliminate crosstalk effects in the system. When a signal transmitted by one FSD is directly received by another FSD, artifacts and interference may be generated. For the scenario of using n asynchronous FSDs on a single mother, the corresponding carrier frequencies of the FSDs need to be separated to prevent the frequency difference between any two FSDs from being a multiple of the PRR of either FSD to avoid crosstalk and interference in the FMS. It should be recognized that for the coexistence of n FSDs using FDM on a single mother, the PRR p should be at least n kHz. Since the receive front-end of the FSD can be designed for very small signals (with high amplification), inaccurate clocks in two systems (e.g., FSDs) can generate tiny harmonics, which can become amplified and creep into the receive signal chain of the FSD. This can further result in the generation of predictable interference harmonics far outside the band of interest (15 Hz to 300 Hz), i.e., for every 1 kHz from 1 kHz to (p - 1) kHz. The noise generated due to inaccuracies in the PRR and MOD frequencies can become modulated (frequency modulation (FM)) to these relatively high-frequency interference harmonics. Therefore, by finding and eliminating the 1 kHz repeating harmonics in the signal, the effects of frequency inaccuracies can be detected and controlled.

[0080] In various embodiments, the separation component 112 may separate the MOD frequencies of the FSDs in the FMS such that the difference between the MOD frequencies of the FSD and another FSD is not a multiple of the PRR of the other FSD. The separation component 112 may separate the corresponding carrier frequencies by (p×(p - 1)-1) kHz (Equation 2), where p represents the PRR of the FSD in kHz. The harmonic and corresponding crosstalk effects may be eliminated by implementing a filter that can notch the harmonic frequencies and by implementing an AGC stage that can normalize the signal amplitude. For example, in various embodiments, the signal processing component 114 may implement the AGC stage and the filter to selectively eliminate predictable harmonics to eliminate crosstalk in the FMS, and the AGC stage may be implemented as software, hardware, or a combination of software and hardware. Normalizing the signal amplitude may remove the very low frequencies generated due to crosstalk, and the notch filter may be implemented once every 1 kHz, where the notch filter may remove the harmonics. The AGC may be implemented (e.g., by the signal processing component 114) as firmware / signal processing software / algorithm (significantly after the tunable LC energy storage circuit), and the filter may be implemented after the AGC (e.g., by the signal processing component 114) to remove the 1 kHz, 2 kHz, and 3 kHz harmonics that may interfere with fetal heart rate detection. Both the filter and the algorithm for the AGC may be implemented in the signal processing core in the microcontroller. The AGC may also be implemented as a hardware block.

[0081] In one example, in a triplet monitoring scenario with a PRR of 4 kHz, where the corresponding frequencies of three FSDs (each FSD monitors one of the three fetuses) may be separated by 11 kHz, crosstalk may cause the generation of 1 kHz and 2 kHz artifacts. The noise introduced by the PRR error and the inaccurate carrier frequencies may be frequency modulated onto the 1 kHz and 2 kHz signals. Thereafter, the AGC stage may be implemented to normalize the amplitude for signal detection, and further filtering of the 1 kHz and 2 kHz signals may completely attenuate all the noise generated due to crosstalk. The non-limiting interference pattern 600 (Interference Pattern 600) may illustrate an example of crosstalk. The interference pattern 600 may illustrate the core fundamental frequency of a 1 kHz sine wave. When the AGC is implemented, the interference pattern 600 may look like a flat band of the 1 kHz sine wave, contrary to the shape illustrated by the interference pattern 600. More specifically, the interference pattern 600 may illustrate an example of crosstalk artifacts composed of lower frequencies riding on the 1 kHz sine wave. The interference illustrated by the interference pattern 600 may occur between two FSDs operating at 1.151 MHz and 1.162 MHz with a PRR of 4 kHz. The interference pattern 600 may occur due to frequency inaccuracies in the carrier and the MOD frequencies of the FSDs. Applying the AGC stage and filtering the 1 kHz harmonics may result in an almost zero signal amplitude for FHR or FMD detection, which may not be sufficient to generate any audible noise or artifacts in the monitored fetal parameters.

[0082] The crosstalk effect in FMS can be reduced by reducing the frequency inaccuracy of the clock source used by the transducer. Using a high-precision clock source for commercial high-cost-effective FSD is not always economical. The embodiments disclosed herein can use frequency calibration techniques during the manufacture of the transducer, where the effect of a given temperature deviation on the quartz crystal can be performed in a temperature-controlled environment. For each carrier frequency, the calibration process can determine the inaccuracy in the input crystal, which can be utilized to tune (e.g., by frequency generation component 108) the frequency generation circuit to generate an accurate frequency output based on the inaccurate input clock or crystal. As stated elsewhere herein, the calibration can be digital calibration performed (e.g., by frequency generation component 108) via software.

[0083] Figure 7 A diagram illustrating an exemplary non-limiting scenario 700 that can generate crosstalk in FMS according to one or more embodiments described herein. Refer Figure 7 One or more embodiments described can be implemented by one or more components of system 100. For the sake of brevity, the repeated description of similar elements and / or processes employed in the corresponding embodiments is omitted.

[0084] Non-limiting scenario 700 (scenario 700) can be an example of a scenario in which one or more embodiments discussed herein can be implemented to address frequency interaction and crosstalk in FMS.

[0085] The positioning of the FSD for fetal monitoring can be performed by a clinician. For a clinician, it may be an impractical task to view whether the signal beam from the FSD is within sight. An example of the placement of the FSD for fetal monitoring is illustrated at 702, and such placement can generate crosstalk. An example of how the placement of the FSD illustrated at 702 can generate crosstalk is illustrated at 710. At 710, the left portion of the figure can illustrate the transmit cycle (TX) and receive cycle (RX) of FSD T1, and the right portion of the figure can illustrate the transmit cycle (TX) and receive cycle (RX) of FSD T2. In this scenario, the signal transmitted from sensor T1 can be received by T2 during the receive cycle of T2 and can become demodulated, as illustrated by the dashed arrow from T1 to T2. Similarly, the signal transmitted from sensor T2 can be received by T1 during the receive cycle of T1 and can become demodulated, as illustrated by the dashed arrow from T2 to T1. In this regard, a diagram of an experimental setup performed for monitoring crosstalk using FSD T1 and T2 is illustrated at 720. The experiment was performed on a Phantom and refers Figure 8 to the described results.

[0086] Figure 8A diagram illustrating exemplary non - limiting interference patterns 800 and 810 representative of crosstalk artifacts in accordance with one or more embodiments described herein. Referring to Figure 8 One or more embodiments described may be implemented by one or more components of system 100. For the sake of brevity, repeated descriptions of similar elements and / or processes employed in the corresponding embodiments are omitted.

[0087] Continuing to refer at least to Figure 7 , Figure 8 Illustrates the results corresponding to the experimental setup exemplified at 720 in Figure 7 , where FSD T1 and T2 are placed directly across from each other, and the processed signal at the input of the ADC at either FSD is observed. In one scenario, both T1 and T2 have a pulse repetition period of approximately 250 μs, T1 has a MOD frequency of 1.15097613 MHz and a PRR of 3.999917 kHz, and T2 has a MOD frequency of 1.16197836 MHz and a PRR of 3.9992551 kHz. Thus, the interference pattern exemplified at 800 corresponds to the frequency difference generated based on Equation 4. The interference pattern at 800 may show a sine wave repeating at the third harmonic of 2.3 Hz. The bar indicated at 802 on the interference pattern exemplified at 800 may be magnified to show the interference pattern at 804. Similarly, the interference pattern exemplified at 810 corresponds to the frequency difference generated based on Equation 5. The interference pattern at 810 may show a slowly moving pattern repeating every 8 mHz.

[0088] Equation 4: ΔF = ||MOD T1 - MOD T2 | - 11KHz| = ∼2.3Hz, where MOD T1 represents the MOD frequency of T1 (1.15097613 MHz in this experimental scenario), and MOD T2 represents the MOD frequency of T2 (1.16197836 MHz in this experimental scenario).

[0089] Equation 5: |PRR T1 - PRR T2 | = ∼8mHz, where PRR T1 represents the PRR of T1 (3.999917 kHz in this experimental scenario), and PRR T2 represents the PRR of T2 (3.9992551 kHz in this experimental scenario).

[0090] Based on the above discussion, it can be observed that each frequency involved in pulse formation can produce a crosstalk effect. Separating (e.g., by separation component 112) the MOD frequency of the FSD to generate predictable harmonics and applying an AGC and a filter (e.g., by signal processing component 114) to eliminate the predictable harmonics can eliminate crosstalk in the FMS.

[0091] Figure 9 A diagram of an exemplary non - restrictive carrier 900 in accordance with one or more embodiments described herein is illustrated. Refer Figure 9 One or more embodiments described can be implemented by one or more components of system 100. For the sake of brevity, the repeated description of similar elements and / or processes employed in the corresponding embodiments is omitted.

[0092] Continuing to refer at least Figures 6 to 8 , Figure 9 The ultrasonic (ULS) aliasing and demodulation of signals in the FMS are described. The non - restrictive carrier 900 (carrier 900) illustrates the pulse repetition period for the FSD. At 902, the carrier 900 can indicate the reception period (RX allowed) for the FSD, and the reception period can have a duration of 90 μs. The transmission period (TX) for the FSD can be indicated by the flat portion of the carrier 900, and the transmission period can have a duration of 160 μs. The FSD can operate by looking for Doppler shifts and demodulating. For example, the FSD can have a carrier frequency of 1.140 MHz (the cable operates at 1.140000 MHz), and the FSD can experience crosstalk from a first sensor (FSD) operating at 1.151 MHz and a second sensor (FSD) operating at 1.162 MHz. Due to crosstalk, within the RX allowed period of the FSD, the 1.151 MHz signal from the first sensor and the 1.162 MHz signal from the second sensor can be demodulated at 1.140 MHz. Demodulation can refer to subtraction. Thus, demodulation can result in a 11 kHz difference between the FSD and the first sensor and a 22 kHz difference between the FSD and the second sensor.

[0093] The 11 kHz and 22 kHz frequencies can be received by the FSD within the Rx enable period (90 μs) after demodulation. Since, according to Equation 3, the FSD considered in this document has a pulse repetition period of 250 μs (90 μs + 160 μs), the PRR of the FSD can be 4 kHz. In other words, the FSD can sample the signal at 4 kHz. In this scenario, an 11 kHz signal sampled at 4 kHz can generate an output of 1 kHz. That is, within the RX enable period, there can be an 11 kHz signal that can appear only once every 250 μs (i.e., only during the reception period of the FSD). In fact, demodulation itself represents sampling at 4 kHz. Therefore, an 11 kHz signal sampled at 4 kHz can mean that the 11 kHz signal is sampled at a sampling rate of 4 kHz, and this signal can generate an output of 1 kHz (harmonic) that can be used to cancel crosstalk. Similarly, a 22 kHz signal sampled at 4 kHz can generate an output of 2 kHz (harmonic) because, based on the Nyquist theory, the minimum achievable frequency is half of the sampling frequency. Therefore, for a sampling rate (PRR) of 4 kHz, the Nyquist frequency is 2 kHz, and for a sampling rate of 2 kHz, the Nyquist frequency is 1 kHz. Since the generated outputs can be 1 kHz and 2 kHz, the observed 100 Hz to 300 Hz offset can be added / subtracted to this output to ensure that the signal never enters the 0 Hz to 300 Hz frequency band of interest for fetal heart rate monitoring.

[0094] Generally speaking, signals of interest for fetal monitoring (fetal heart rate monitoring or fetal movement monitoring or the like) typically range from 15 Hz to 300 Hz. Thus, for a Doppler shift system, the bandwidth of the signal can be about 600 Hz (i.e., 300 Hz in either direction from the nominal carrier frequency). Given this bandwidth of the signal of interest, the PRR and carrier frequency of the FSD are preferably integer multiples of 1 kHz, because using fractional multiples may result in interference and false pick-up. For example, consider two FSDs, namely T1 and T2, both operating at a PRR of 3 kHz, where T2 can operate at a carrier frequency 3.5 kHz higher than T1. Any positive Doppler shift on the T1 signal can be picked up by T2, and any negative Doppler shift on T2 can be picked up by T1. In the case where T2 picks up the T1 signal, the spacing between the signal (with a 200 Hz Doppler shift) and the T2 frequency can be 3.3 kHz (3.5 kHz - 200 Hz). Since the PRR is 3 kHz, according to the Nyquist theory, T2 can perceive the signal as a 300 Hz shift (3.3 kHz = 3 kHz + 300 Hz), thus bringing the signal into the band of interest. If the difference is 4 kHz, the T2 frequency can be 3.8 kHz (4 kHz - 200 Hz). With a PRR of 3 kHz, according to the Nyquist theory, T2 can perceive the signal as an 800 Hz shift (3.8 kHz = 3 kHz + 800 Hz), which is outside the band of interest.

[0095] The following example can further emphasize how the various embodiments disclosed herein can handle strong reflected signals with Doppler shift. It should be noted that the embodiment can be implemented to handle only large signals, since the tunable LC energy storage circuit can account for smaller signals. In an FMS, sensors other than the FSD that transmits the signal can also receive the signal transmitted by the FSD and the corresponding signal reflected from the fetus monitored by the FSD. The various embodiments herein can prevent direct and reflected signals from one or more FSDs received by the FSD from entering the signal chain of the FSD. For example, consider a 200 Hz Doppler shift signal on a 1.151 MHz carrier signal from a first sensor and a 1.162 MHz carrier signal from a second sensor. In this scenario, the reflected signal from the first sensor can have a frequency of 1.151200 MHz (positive (+) 200 Hz shift), and the reflected signal from the second signal can have a frequency of 1.162200 MHz (positive (+) 200 Hz shift). In other words, the first sensor can transmit a signal at 1.151 MHz, which can be reflected by the fetus and Doppler shifted by 200 Hz, where due to the Doppler shift, the frequency of the reflected signal can be 1.151200 MHz.

[0096] Using the same logic, the 1.162 MHz signal from the second sensor can be Doppler shifted by 200 Hz, resulting in a reflected signal of 1.162200 MHz. The reflected signals of 1.151200 MHz and 1.162200 MHz can enter the receive cycle of the FSD operating at 1.140 MHz (in addition to entering the first and second sensors respectively), resulting in corresponding demodulated signals of 11200 Hz and 22200 Hz. According to the Nyquist theory, the 11200 Hz signal can produce an output of 800 Hz, and the 22200 Hz signal can produce an output of 1800 Hz. The 800 Hz output and the 1800 Hz output can be outside the frequency band of interest and can be eliminated (e.g., by the signal processing component 114), and the Doppler shift artifacts can also be eliminated (e.g., by the signal processing component 114). In this scenario, the reflected signal is already small, and the tunable LC energy storage circuit can account for most of the reflected signal. Similarly, the reflected signal of 1.150800 MHz from the FSD (negative (-) 200 Hz shift) entering the FSD operating at 1.140 MHz can be demodulated to generate a frequency difference of 10800 Hz and an output of 1200 Hz, and the reflected signal of 1.161800 MHz from the FSD (negative (-) 200 Hz shift) entering the FSD operating at 1.140 MHz can be demodulated to generate a frequency difference of 21800 Hz and an output of 1800 Hz. As before, the 1200 Hz and 1800 Hz outputs can be outside the 0 Hz to 300 Hz frequency band of the frequency of interest, and the FSD operating at 1.140 MHz can avoid detecting the Doppler shift from different FSDs.

[0097] The following discussion describes how the sampling rate can cause aliasing. If the FSD with a carrier frequency of 1.140 kHz has a PRR / sampling rate of 2 kHz, then according to the Nyquist theory, a frequency of 1.151 MHz without Doppler shift demodulated at 1.140 MHz can result in a frequency difference of 11 kHz and an output of 1 kHz. Similarly, according to the Nyquist theory, a frequency of 1.162 MHz without Doppler shift demodulated at 1.140 MHz can result in a frequency difference of 22 kHz and an output of 0 kHz. Additionally, for a PRR of 2 kHz, a Doppler shift frequency of 1.151200 MHz (positive Doppler shift) demodulated at 1.140 MHz can generate a frequency difference of 11200 Hz and an output of 800 Hz, a Doppler shift frequency of 1.150800 MHz (negative Doppler shift) demodulated at 1.140 MHz can generate a frequency difference of 10800 Hz and an output of 800 Hz, a Doppler shift frequency of 1.162200 MHz (positive Doppler shift) demodulated at 1.140 MHz can generate a frequency difference of 22200 Hz and an output of 200 Hz, and a Doppler shift frequency of 1.161800 MHz (negative Doppler shift) demodulated at 1.140 MHz can generate a frequency difference of 21800 Hz and an output of 200 Hz. In the four scenarios presented, the 200 Hz frequency can be detected within the FHR band / band of interest and can be amplified by the main filter, resulting in crosstalk. Table 1 lists different frequencies sampled at 4 kHz and 2 kHz sampling rates and the corresponding outputs.

[0098] Table 1 :

[0099] Input signal frequency Sampling rate Output 0 kHz 2 kHz 0 Hz 1 kHz 2 kHz 1 kHz 2 kHz 2 kHz 0 Hz 3 kHz 2 kHz 1 kHz 4 kHz 2 kHz 0 Hz 5 kHz 2 kHz 1 kHz 11200 Hz 2 kHz 800 Hz 21800 Hz 2 kHz 200 Hz

[0100] Figure 10 FIG. Exemplary non - limiting scenario 1000 of three FSDs positioned on a pregnant woman for monitoring fetal parameters (heartbeat of triplets or movement of the whole body) in accordance with one or more embodiments described herein. Refer to Figure 10 One or more embodiments described can be implemented by one or more components of system 100. For the sake of brevity, repeated descriptions of similar elements and / or processes employed in the corresponding embodiments are omitted.

[0101] Various embodiments of the present disclosure may allow for PRR synchronization to ensure that the large-signal transmission pulses of one FSD in the FMS are not demodulated by another FSD, thereby eliminating all artifacts in the FSD. Independent FSDs with respective free-running clocks may indicate a high likelihood that the respective free-running clocks determining the pulse timing for the FSDs may be slightly asynchronous relative to each other. Such a situation may indicate that the respective PRRs of the FSDs may be asynchronous, and in a crosstalk scenario, the transmitted and received pulses may be shifted relative to each other on either FSD. For example, the transmitted pulse may reach the receiving section of another FSD. The relative offset / shifting of the pulse patterns generated by the FSDs may result in crosstalk components (at the difference of their PRR frequencies) and corresponding harmonics. MOD frequency errors may also cause crosstalk, especially in extremely large signals. This may occur mainly due to the harmonics generated when the difference in frequencies is not a perfect value (e.g., Δ(frequency difference) is ± a few Hertz (Hz) instead of 11 kHz, 22 kHz, etc.), which may be displayed at high-amplitude inputs when sampled at 4 kHz.

[0102] Continuing reference Figure 1, the synchronization component 116 can perform periodic PRR synchronization to prevent the ultrasonic signals generated by the FSD from being demodulated by the corresponding carrier frequencies generated by additional FSDs in the FMS, thereby preventing crosstalk in the FMS. It should be recognized that the demodulation of the ultrasonic signals generated by the FSD can occur after the ultrasonic signals from the FSD are received by another FSD, converted into electrical signals by the transducer (piezoelectric crystal) of another FSD, and processed by the tunable LC energy storage circuit of another FSD. The non-limiting scenario 1000 can illustrate an FMS of three FSDs (i.e., T1, T2, and T3) positioned on a surface 1002 (i.e., the abdomen of a pregnant woman). FSD T1 can be used to monitor the fetal heartbeat 1004, FSD T2 can be used to monitor the fetal heartbeat 1006, and FSD T3 can be used to monitor the fetal heartbeat 1008. Due to the clock differences between the FSDs, each of the three FSDs can have a different PRR. For example, with respect to the transmit pulse 1010 of FSD T1, when observed with reference to the vertical dashed line, the transmit pulses 1012 and 1014 of FSD T2 and FSD T3 can appear to be shifted due to different PRRs, respectively. In this case, the synchronization component 116 can perform periodic PRR synchronization to ensure that the three FSDs can transmit pulses with the same PRR, which can prevent the generation of a lower frequency noise during crosstalk. The synchronization component 116 can synchronize the corresponding PRRs of FSDs T1, T2, and T3 in the FMS such that the corresponding PRRs of FSDs T1, T2, and T3 can remain synchronized even in the case of a slight bias in the MOD frequencies generated by the corresponding clock generators of the three FSDs. In one embodiment, the synchronization component 116 can synchronize the transmit (Tx) pulses of FSDs T1, T2, and T3 regardless of any differences in the corresponding PRRs of the FSDs.

[0103] More specifically, the synchronization component 116 may perform periodic synchronization of the pulse patterns of FSDs T1, T2, and T3. For example, a monitoring system or a predetermined master FSD may send a slow but very low-jitter periodic check to the FSDs to synchronize the pulse patterns and PRRs of the three FSDs to reduce artifacts, as discussed above. The periodic synchronization may be performed at a rate much lower than the rate of the PRR but at least greater than the frequency difference between the PRRs. Doing so may reset the transmission before the entire cycle of window overlap is completed. That is, long before the Tx pulses of the FSDs can overlap the entire pulse repetition period, the synchronization component 116 may synchronize (periodically, only once in a while) the start of the transmission period of an FSD relative to another FSD or a central hub to bring the start of the transmission period back to its initial position and cancel drift. The frequency at which the synchronization is performed may be determined by the maximum possible frequency offset between any two sensors, and this frequency may be much higher than the frequency difference from the ideal expected difference. PRR synchronization may keep the corresponding transmit pulses (Tx) and receive pulses (Rx) of the FSDs from drifting across each other to substantially prevent any crosstalk via low-frequency harmonics without changing the PRR of the FSDs. PRR synchronization may prevent the generation of lower-frequency noise during crosstalk. Generally speaking, the difference in PRRs may be on the order of a single-digit frequency (Hz) or much lower (e.g., on the order of mHz). By synchronizing the corresponding PRRs, one of the sources of noise caused by crosstalk may be avoided. The ability of the system (e.g., FMS) to synchronize in the case of wireless FSDs may also allow for the possibility of TDM implementation. In other embodiments, the PRR synchronization technique may be implemented together with an AGC stage having a filter for canceling crosstalk.

[0104] Figure 11 FIGURES 1100 and 1120 are exemplary non-limiting scenarios illustrating the synchronization of pulse patterns generated by FSDs positioned on a pregnant woman for monitoring fetal parameters (heartbeats of triplets or movement of the entire body), in accordance with one or more embodiments described herein. Refer to Figure 11 One or more embodiments described herein may be implemented by one or more components of system 100. For the sake of brevity, repeated descriptions of similar elements and / or processes employed in the corresponding embodiments are omitted.

[0105] Continuing to refer to Figure 10, Periodic PRR synchronization can be performed by using a monitor to generate checks in real time or by using electrodes and a master FSD to send to additional FSDs. For example, the monitor can signal multiple FSDs of the FMS, or the FSDs can operate peer-to-peer to synchronize. For example, in one embodiment, the synchronization component 116 can synchronize the respective PRRs of three FSDs by using a master hub or monitor, which can act as a master device for controlling the FSDs of the FMS and can send wireless signals to the FSDs in real time. In another embodiment, the synchronization component 116 can synchronize the respective PRRs of three FSDs by using a master FSD / sensor, which can wirelessly control other FSDs in the FMS and can send signals (e.g., high-frequency low-current signals) to additional FSDs in the FMS. Synchronization of the PRR can be performed wirelessly or through a wired connection (e.g., a wire).

[0106] Non-limiting scenario 1100 (Scenario 1100) illustrates the PRR synchronization of FSDs T1, T2, and T3 performed by hub 1102 by generating and sending wireless checks to the three FSDs in real time, where hub 1102 can be a master hub that can control FSDs T1, T2, and T3. The real-time wireless check can be used as an interruption to realign the transmission cycles of the three FSDs. The transmission cycles can also be realigned by using the human body as an antenna technology to reduce power requirements. Non-limiting scenario 1120 (Scenario 1120) illustrates the wireless PRR synchronization of FSDs T1, T2, and T3 performed by: using electrodes and FSD 1122 (e.g., FSDT1) to send a signal across surface 1002 such that the same signal can be picked up by other FSDs (e.g., T2 and T3) on surface 1002 and used as an interruption to realign the pulses transmitted by the three FSDs. In various embodiments, the signal sent by FSD 1122 can be a high-frequency low-current signal. Scenarios 1100 and 1120 illustrate the wireless synchronization of the pulse patterns (and thus the PRRs) for FSDs T1, T2, and T3, as shown by the synchronized transmission pulses 1010, 1012, and 1014. In various embodiments, PRR synchronization can be wired or wireless.

[0107] In some embodiments, after separating the respective MOD frequencies of FSDs T1, T2, and T3 to generate predictable harmonics, PRR synchronization can be achieved without implementing an AGC stage (i.e., by using only filters). In other embodiments, the PRR synchronization technique can be implemented together with an AGC stage having a filter for canceling crosstalk.

[0108] Figure 12A diagram illustrating exemplary non - limiting scenarios 1200 and 1220 of a control system that can phase - shift the start of the TX enable period of a transducer to eliminate crosstalk artifacts generated in an FMS, in accordance with one or more embodiments described herein. Refer to Figure 12 One or more of the described embodiments may be implemented by one or more components of system 100. For the sake of brevity, repeated descriptions of similar elements and / or processes employed in the corresponding embodiments are omitted.

[0109] Various embodiments herein may allow PRR synchronization to ensure that the large - signal transmit pulses of one FSD in an FMS are not demodulated by another FSD, thereby eliminating all artifacts in the FSD. In various embodiments herein, by attacking the cause of crosstalk, crosstalk can be completely avoided in the FMS. For example, if the transmit pulses of FSDs (i.e., the signals transmitted by transducers) can overlap or can be prevented from entering each other's receive periods, the possibility of signals becoming demodulated can be avoided, which can further eliminate the chance of any harmonics creeping in the FMS. Such cases may also result in minor acoustic interference in small signals. The travel time of an ultrasonic signal through abdominal tissue can be high enough such that it is necessary to account for / consider the distance traveled by the transmit pulse, which can directly affect whether the pulse falls into the receive period (fully or partially). However, tracking the exact travel time of the pulse down to microseconds may be difficult to accomplish and may depend on the relative position of the FSD on the abdomen.

[0110] Non - limiting scenario 1200 (Scenario 1200) illustrates a fetal monitoring scenario where FSD 1 can be directly positioned on the abdomen of a pregnant woman opposite FSD 2. In Figure 12 it, transmission 1206 (solid line) may represent the signal transmitted (TX1) by FSD 1, and reception 1208 (dashed line) may represent the signal received (TX2) by FSD 1. Similarly, transmission 1210 (dashed line) may represent the signal transmitted (TX2) by FSD2, and reception 1212 (solid line) may represent the signal received (TX1) by FSD 2. The signal transmitted from FSD 2 can enter the receive period of FSD 1 and vice versa. The receive period of an FSD may refer to the period during which an FSD can expect to receive a reflected signal after the transducer of the FSD has transmitted a signal. Thus, TX2 may represent the signal transmitted by FSD 2 and received by FSD 1 during the receive period of FSD 1, and TX1 may represent the signal transmitted by FSD 1 and received by FSD 2 during the receive period of FSD 2. In scenario 1200, FSD 1 may receive TX2 as well as the reflected signal corresponding to the signal transmitted (TX1) by FSD 1 ( Figure 12(not illustrated in the figure). Since the signal from FSD 2 is directly received by FSD 1, the intensity of TX2 may be high, and the scenario 1200 may generate harmonics such as 1 kHz, 2 kHz, 3 kHz, etc. Meanwhile, FSD 2 may receive TX1 and the reflected signal corresponding to the signal transmitted (TX2) by FSD 2. Figure 12 (not illustrated in the figure).

[0111] In various embodiments, the synchronization component 116 may perform pulse phase synchronization to offset the phase of the TX2 signal to prevent the TX2 signal from entering the reception period of FSD 1 directly opposite FSD 2. The synchronization component 116 may perform pulse phase synchronization via the control system 1202. For example, FSD 2 may be operatively coupled to the control system 1202, and FSD 1 may operate without being coupled to the control system 1202. The control system 1202 may measure the amount of harmonics generated by FSD 2 at FSD1, and the control system 1202 may gradually phase-shift the TX2 signal transmitted by FSD 2, which may cause the TX2 signal to overlap with the TX1 signal. Thus, TX1 may become aligned with TX2, and prevent TX2 from entering the reception period of FSD 1.

[0112] More specifically, the synchronization component 116 may detect the generated harmonics (every 1 kHz from ((p - 1) kHz to 1 kHz)) by using the control system 1202 and phase-shift the already synchronized PRR of the FSDs (e.g., FSD 1 and 2) to eliminate crosstalk artifacts generated in the FDM system. In this embodiment, the FSD with the largest amount of crosstalk components may act as the master FSD in the FMS, and the other FSDs may phase-shift the corresponding start of the corresponding TX enable periods of the other FSDs relative to the master FSD. The phase shift may be performed until no more crosstalk components remain in any FSD. Thus, for FSDs (e.g., FSD 1 and 2) that send signals to each other across the mother's abdomen, the transmission pulses of the FSDs (e.g., TX1 and TX2) may be offset in time to prevent the transmission pulse of one FSD from entering the reception period / reception window of the other FSD, thereby completely avoiding all possible crosstalk in the FMS. Implementing the embodiments discussed herein may indirectly consider the travel time of the ultrasonic transmission pulses from FSD 1 and FSD 2 across the abdominal tissue and the resulting overlapping positions.

[0113] Accordingly, the control system 1202 may offset the phase of the signal from FSD 2 to align the TX2 signal with the TX1 signal to prevent the TX2 signal from entering the receive cycle of FSD 1. Aligning TX2 with TX1 also prevents the TX1 signal from entering the receive cycle of FSD 2. Such techniques may eliminate the need to remove crosstalk. Additionally, during crosstalk, the reflected signal received by the transducer (e.g., the signal reflected from the fetus) may sometimes be very weak, and in such cases, in addition to the reflected signal, the direct signal received by the transducer from another transducer (e.g., TX1 or TX2) may saturate the reflected signal. For example, in scenario 1200, even if crosstalk is eliminated (e.g., through signal processing as described elsewhere herein), the reflected signal corresponding to TX1 may become lost. Phase shifting the signals as described above may prevent saturation of the reflected signal and improve the receive sensitivity of the FSD. That is, aligning the corresponding signals transmitted by the FSDs may prevent any large signal from overwhelming the corresponding receive chain of either FSD during their respective receive cycles. This may allow a greater voltage range to be available for the transducer to receive and amplify the reflected signal, e.g., compared to a scenario where the transducer may receive both the reflected signal and the transmitted signal from another transducer. The non-limiting scenario 1220 (scenario 1220) may illustrate that the TX2 signal is phase shifted until the artifacts at either FSD have dropped to zero. This may indicate that transmitting TX1 and TX2 may overlap, and the respective travel times of the TX1 and TX2 waves across the abdomen of the pregnant woman may be compensated.

[0114] Figure 13 A flowchart of an exemplary non-limiting method 1300 that permits coexistence of multiple FSDs in an FMS in accordance with one or more embodiments described herein is illustrated. Refer to Figure 13 One or more of the described embodiments may be implemented by one or more components of system 100. For the sake of brevity, repeated descriptions of similar elements and / or processes employed in the corresponding embodiments are omitted.

[0115] At 1302, the non - limiting method 1300 may include generating, by a device operatively coupled to a processor using a variable frequency generator circuit (e.g., by frequency generation component 108), an electronic signal at one or more different frequencies in at least one FSD of an FMS, wherein at least one FSD may dynamically adjust the transmit voltage of the at least one FSD to maintain an acoustic power value at the one or more different frequencies. At 1302, the non - limiting method 1300 may further include tuning, by the device, the resonant frequency of a tunable LC energy storage circuit included in the at least one FSD to the carrier frequency of the at least one FSD, wherein the carrier frequency may be a frequency selected from the one or more different frequencies, wherein the tunable LC energy storage circuit may include a large - capacitance varactor that performs the tuning, and wherein tuning the resonant frequency of the tunable LC energy storage circuit to the carrier frequency of the at least one FSD may include adjusting, by the device using a DAC, the bias voltage of a balanced varactor network to dynamically change the capacitance value of the large - capacitance varactor. In some embodiments, tuning the resonant frequency of the tunable LC energy storage circuit to the carrier frequency of the at least one FSD may include using a voltage - control mechanism different from a DAC, wherein the voltage - control mechanism may be a resistor divider network, a DC regulator (which may generate a DC regulated voltage), or another type of voltage - control mechanism.

[0116] At 1304, the non - limiting method 1300 may include separating, by the device (e.g., by separation component 112), the respective carrier frequencies of multiple FSDs in an FMS such that the frequency difference between the carrier frequencies of any two FSDs is not a multiple of the PRR of either FSD, wherein separating the respective carrier frequencies of the multiple FSDs may generate predictable harmonics during crosstalk in the FMS.

[0117] At 1306, the non - limiting method 1300 may include implementing, by the device (e.g., by signal processing component 114), an AGC stage and a filter to selectively eliminate the predictable harmonics to eliminate crosstalk in the FMS, wherein the automatic gain control stage may be implemented as software, hardware, or a combination of software and hardware.

[0118] At 1308, the non - limiting method 1300 may include performing, by the device (e.g., by synchronization component 116), periodic PRR synchronization to synchronize the start of the transmit period of at least one FSD with the respective starts of the transmit periods of one or more additional FSDs in the FMS to prevent an ultrasonic signal generated by the at least one FSD from being demodulated by the respective carrier frequencies generated by one or more additional FSDs in the FMS.

[0119] At 1310, the non-limiting method 1300 may include performing (e.g., by the synchronization component 116) pulse phase synchronization by the device using a control system to prevent a signal transmitted by a first FSD of the FMS from entering the reception period of a second FSD of the FMS, the second FSD being positioned a distance directly across from the first FSD, wherein the control system may measure the amount of harmonics generated by the first FSD at the second FSD and gradually offset the phase of the signal transmitted by the first FSD to align the signal transmitted by the first FSD with the signal transmitted by the second FSD in the FMS.

[0120] At 1312, the non-limiting method 1300 may determine (e.g., using the synchronization component 116) whether the signal transmitted by the first FSD has been phase-shifted to align with the signal transmitted by the second FSD by detecting the interaction frequency and minimizing the interaction frequency, by identifying the presence or absence of harmonics such as 1 kHz, 2 kHz, etc.

[0121] If so, then at 1314, the non-limiting method 1300 may stop offsetting the phase of the signal transmitted by the first FSD.

[0122] If not, then at 1316, the non-limiting method 1300 may continue to offset the phase of the signal transmitted by the first FSD.

[0123] As stated elsewhere herein, crosstalk may be a common problem in fetal monitors that do not use TDM. Various embodiments herein may employ the same piezoelectric crystal to electronically generate multiple carrier frequencies for a transducer operating in an FDM mode. Various embodiments herein may also employ a specific frequency separation and use a known interaction frequency to eliminate crosstalk in the FMS. Additionally, the embodiments discussed herein may perform PRR synchronization and phase shifting to eliminate crosstalk between transducers by detecting the interaction frequency and minimizing the interaction frequency.

[0124] For simplicity of explanation, the computer-implemented and non-computer-implemented methods provided herein are depicted and / or described as a series of acts. It should be understood that the claimed invention is not limited by the acts and / or the order of acts illustrated, e.g., acts may occur in one or more orders and / or simultaneously and have other acts not presented and described herein. Additionally, not all of the illustrated acts may be utilized to implement the computer-implemented and non-computer-implemented methods in accordance with the described subject matter. Further, the computer-implemented methods described hereinafter and throughout this specification are capable of being stored on a manufacture such that the computer-implemented methods can be transmitted and transferred to a computer. As used herein, the term "manufacture" is intended to cover a computer program accessible from any computer-readable device or storage medium.

[0125] The present document has (and / or will further) described systems and / or devices with respect to interactions between one or more components. Such systems and components may include those components or sub-components specified herein, one or more specified components or sub-components, and / or additional components. A sub-component may also be implemented as a component that is communicatively coupled to other components in addition to the components included within a parent component. One or more components and / or sub-components may be combined into a single component that provides aggregated functionality. A component may interact with one or more other components that are not specifically described herein for the sake of brevity but are known to those skilled in the art.

[0126] One or more embodiments described herein may employ hardware and / or software to solve highly technical, non-abstract problems that cannot be performed as a set of mental acts of a human being. For example, a human or even thousands of humans cannot efficiently, accurately, and / or effectively generate multiple different frequencies in a transducer of an FMS because one or more embodiments described herein can implement this process. Also, neither the human mind nor a human with a pen and paper can implement the pulse scheme and artifact cancellation techniques for eliminating crosstalk of ultrasonic coexistence in an FMS as performed by one or more embodiments described herein.

[0127] To provide additional context to the various embodiments described herein, Figure 14 and the following discussion is intended to provide a brief general description of a suitable computing environment 1400 in which the various embodiments described herein may be implemented. While the embodiments have been described above in the general context of computer-executable instructions that may run on one or more computers, those skilled in the art will recognize that these embodiments may also be implemented in conjunction with other program modules or as a combination of hardware and software.

[0128] Generally, program modules include routines, programs, components, data structures, etc. that perform particular tasks or implement particular abstract data types. In addition, those skilled in the art will understand that the methods of the present invention may be practiced with other computer system configurations, including single-processor or multi-processor computer systems, minicomputers, mainframe computers, Internet of Things (IoT) devices, distributed computing systems, and personal computers, handheld computing devices, microprocessor-based or programmable consumer electronics, etc., each of which may be operably coupled to one or more associated devices.

[0129] The illustrated embodiments of the present document may also be practiced in a distributed computing environment where particular tasks are performed by remote processing devices linked through a communication network. In a distributed computing environment, program modules may be located in local and remote memory storage devices.

[0130] Computing devices generally include various media, which may include computer-readable storage media, machine-readable storage media, or communication media, where the use of these two terms is different from each other herein, as described below. Computer-readable storage media or machine-readable storage media can be any available storage media accessible by a computer, and include volatile and non-volatile media, removable and non-removable media. By way of example and not limitation, computer-readable storage media or machine-readable storage media can be implemented in conjunction with any method or technology for storing information such as computer-readable or machine-readable instructions, program modules, structured data, or unstructured data.

[0131] Computer-readable storage media can include, but are not limited to, random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD), Blu-ray disc (BD) or other optical disc storage devices, magnetic tape cartridges, tapes, magnetic disk storage devices or other magnetic storage devices, solid state drives or other solid state storage devices, or other tangible or non-transitory media that can be used to store the desired information. In this regard, the terms "tangible" or "non-transitory" as applied to storage devices, memory, or computer-readable media herein should be understood to exclude only propagating transitory signals themselves as a modifier, and do not relinquish the right to all standard storage devices, memory, or computer-readable media that are not only propagating transitory signals themselves.

[0132] Computer-readable storage media can be accessed by one or more local or remote computing devices, for example, via access requests, queries, or other data retrieval protocols, to perform various operations with respect to the information stored by the media.

[0133] Communication media typically contain computer-readable instructions, data structures, program modules, or other structured or unstructured data in a data signal, which can be, for example, a modulated data signal such as a carrier wave or other transmission mechanism, and include any information delivery or transmission medium. The term "modulated data signal" or "signal" refers to a signal that sets or changes one or more of its characteristics to encode information in one or more signals. By way of example and not limitation, communication media include wired media (such as a wired network or a direct wired connection) and wireless media (such as acoustic, RF, infrared, and other wireless media).

[0134] Refer again to Figure 14, An exemplary environment 1400 for various implementations for realizing the aspects described herein includes a computer 1402, which includes a processing unit 1404, a system memory 1406, and a system bus 1408. The system bus 1408 couples system components including, but not limited to, the system memory 1406 to the processing unit 1404. The processing unit 1404 can be any of a variety of commercially available processors. Dual microprocessors and other multiprocessor architectures can also be used as the processing unit 1404.

[0135] The system bus 1408 can be any of several types of bus structures that can be further interconnected to a memory bus (with or without a memory controller), a peripheral bus, and a local bus using any of a variety of commercially available bus architectures. The system memory 1406 includes a ROM 1410 and a RAM 1412. The basic input / output system (BIOS) can be stored in non-volatile memory (such as ROM, erasable programmable read-only memory (EPROM), EEPROM), where the BIOS contains basic routines that help transfer information between elements within the computer 1402, such as during startup. The RAM 1412 can also include high-speed RAM, such as static RAM for caching data.

[0136] The computer 1302 further includes an internal hard disk drive (HDD) 1414 (e.g., EIDE, SATA), one or more external storage devices 1416 (e.g., a magnetic floppy disk drive (FDD) 1416, a memory stick or flash drive reader, a memory card reader, etc.), and a drive 1420 (e.g., such as a solid-state drive, an optical disc drive) that can read from or write to a disk 1422 (such as a CD-ROM disc, a DVD, a BD, etc.). Alternatively, in the case of a solid-state drive, the disk 1422 will not be included unless separated. Although the internal HDD 1414 is illustrated as being within the computer 1402, the internal HDD 1414 can also be configured for use external to a suitable infrastructure (not shown). Additionally, although not shown in the environment 1400, a solid-state drive (SSD) can be used as a supplement or alternative to the HDD 1414. The HDD 1414, the external storage device 1416, and the drive 1420 can be connected to the system bus 1408 through an HDD interface 1424, an external storage interface 1426, and a drive interface 1428, respectively. The interface 1424 for the external drive implementation can include at least one or both of the universal serial bus (USB) and the Institute of Electrical and Electronics Engineers (IEEE) 1394 interface technologies. Other external drive connection technologies are within the scope of the embodiments described herein.

[0137] The drive and its associated computer-readable storage medium provide non-volatile storage of data, data structures, computer-executable instructions, and the like. For computer 1402, the drive and storage medium are adapted to store any data in a suitable digital format. Although the above description of computer-readable storage media refers to corresponding types of storage devices, those skilled in the art should understand that other types of storage media that are computer-readable (whether currently existing or developed in the future) can also be used in the exemplary operating environment, and furthermore, any such storage media may contain computer-executable instructions for performing the methods described herein.

[0138] Multiple program modules may be stored in the drive and RAM 1412, including operating system 1430, one or more application programs 1332, other program modules 1434, and program data 1436. All or part of the operating system, application programs, modules, or data may also be cached in RAM 1412. The systems and methods described herein may be implemented using various commercially available operating systems or combinations of operating systems.

[0139] Computer 1402 may optionally include emulation technology. For example, a hypervisor (not shown) or other intermediary may emulate the hardware environment for operating system 1430, and the emulated hardware may optionally be different from Figure 14 that illustrated in. In such an implementation, operating system 1430 may include one VM among multiple virtual machines (VMs) hosted at computer 1402. Additionally, operating system 1430 may provide a runtime environment to application 1432, such as a Java runtime environment or a.NET framework. The runtime environment is a consistent execution environment that allows application 1432 to run on any operating system that includes the runtime environment. Similarly, operating system 1430 may support containers, and application 1432 may be in the form of containers that are lightweight, independent, executable software packages that include, for example, the code of the application, the runtime, system tools, system libraries, and settings.

[0140] Furthermore, computer 1402 may be enabled using a security module, such as a Trusted Platform Module (TPM). For example, in the case of a TPM, the boot component is hashed in the next boot component and waits for the result to match a security value before loading the next boot component. This process may occur at any layer in the code execution stack of computer 1402, such as applied to the application execution level or the OS kernel level, thereby achieving security at any code execution level.

[0141] A user can input commands and information into computer 1402 through one or more wired / wireless input devices (e.g., keyboard 1438, touch screen 1440, and pointing devices such as mouse 1442). Other input devices (not shown) may include a microphone, an infrared (IR) remote control, a radio frequency (RF) remote control or other remote controls, a joystick, a virtual reality controller or virtual reality headset, a gamepad, a stylus, an image input device (e.g., a camera), a gesture sensor input device, a vision motion sensor input device, an emotion or face detection device, a biometric input device (e.g., a fingerprint or iris scanner), etc. These input devices and other input devices are often connected to processing unit 1404 through an input device interface 1444 coupled to system bus 1408, but can be connected through other interfaces (such as a parallel port, an IEEE 1394 serial port, a game port, a USB port, an IR interface, interfaces, etc.).

[0142] Monitor 1446 or other types of display devices can also be connected to system bus 1308 via an interface (such as video adapter 1448). In addition to monitor 1446, a computer typically also includes other peripheral output devices (not shown), such as speakers, printers, etc.

[0143] Computer 1402 can operate in a networked environment using a logical connection to one or more remote computers (such as remote computer 1450) via wired or wireless communication. Remote computer 1450 can be a workstation, a server computer, a router, a personal computer, a portable computer, a microprocessor-based entertainment appliance, a peer device, or other common network nodes, and generally includes many or all of the elements described with respect to computer 1402, but for simplicity, only memory / storage device 1452 is illustrated. The depicted logical connection includes a wired / wireless connection to a local area network (LAN) 1454 or a larger network (e.g., a wide area network (WAN) 1456). Such LAN and WAN networking environments are common in offices and companies and facilitate enterprise-wide computer networks (such as intranets), all of which can be connected to a global communication network (e.g., the Internet).

[0144] When used in a LAN networking environment, computer 1402 can be connected to local network 1454 through a wired or wireless communication network interface or adapter 1458. Adapter 1458 can facilitate wired or wireless communication with LAN 1454, which may also include a wireless access point (AP) set thereon for communicating with adapter 1458 in wireless mode.

[0145] When used in a WAN networking environment, computer 1402 may include a modem 1460 or may be connected to a communication server on WAN 1456 via other components for establishing communications over the WAN 1456 (such as over the Internet). The modem 1460, which can be an internal or external device and a wired or wireless device, may be connected to the system bus 1408 via the input device interface 1444. In a networking environment, program modules depicted relative to computer 1402 or portions thereof may be stored in the remote memory / storage device 1452. It should be understood that the network connections shown are examples and other components may be used to establish a communications link between computers.

[0146] When used in a LAN or WAN networking environment, in addition to or in place of the external storage device 1416 as described above, computer 1402 may access a cloud storage system or other network-based storage systems, such as but not limited to network virtual machines that provide one or more aspects of information storage or processing. Generally, the connection between computer 1402 and the cloud storage system may be established, for example, by adapter 1458 or modem 1460 over LAN 1454 or WAN 1456, respectively. When connecting computer 1402 to an associated cloud storage system, the external storage interface 1426 may manage the storage provided by the cloud storage system with the help of adapter 1458 or modem 1460, just as with other types of external storage devices. For example, the external storage interface 1426 may be configured to provide access to cloud storage sources as if those cloud storage sources were physically connected to computer 1402.

[0147] Computer 1402 may be capable of operating to communicate with any wireless device or entity operating in a wireless communication manner, such as a printer, scanner, desktop or portable computer, portable data assistant, communication satellite, any equipment or location associated with a wirelessly detectable tag (such as a kiosk, newsstand, store shelf, etc.), and a telephone. This may include Wi-Fi and wireless technologies. Thus, the communication may be a predefined structure like a conventional network or simply an ad hoc communication between at least two devices.

[0148] Figure 15is a schematic block diagram of an example computing environment 1500 with which the disclosed subject matter may interact. The example computing environment 1500 includes one or more clients 1510. The clients 1510 can be hardware or software (e.g., threads, processes, computing devices). The example computing environment 1500 also includes one or more servers 1530. The servers 1530 can also be hardware or software (e.g., threads, processes, computing devices). For example, the servers 1530 can house threads to perform transformations by adopting one or more embodiments as described herein. A possible communication between the clients 1510 and the servers 1530 can be in the form of data packets suitable for being sent between two or more computer processes. The example computing environment 1500 includes a communication framework 1550 that can be used to facilitate communication between the clients 1510 and the servers 1530. The clients 1510 are operatively connected to one or more client data repositories 1520, which can be used to store information local to the clients 1510. Similarly, the servers 1530 are operatively connected to one or more server data repositories 1540, which can be used to store information local to the servers 1530.

[0149] The various embodiments can be a system, a method, an apparatus, or a computer program product at any possible technical detail integration level. The computer program product can include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to implement aspects of the various embodiments. The computer-readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer-readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer-readable storage medium can also include the following: a portable computer floppy disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as a punch card or raised structures in grooves recorded with instructions, and any suitable combination of the foregoing items. As used herein, the computer-readable storage medium should not be construed to be a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse passing through an optical fiber cable), or an electrical signal transmitted through a wire.

[0150] The computer-readable program instructions described herein can be downloaded to a corresponding computing / processing device from a computer-readable storage medium or downloaded to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, or a wireless network). The network may include copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers, or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within the corresponding computing / processing device. The computer-readable program instructions for carrying out operations of the various implementations may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuits, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk, C++, etc., and procedural programming languages such as the "C" programming language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may establish a connection with an external computer (e.g., through the Internet using an Internet service provider). In some implementations, an electronic circuit, including, for example, a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA), can execute the computer-readable program instructions by utilizing the state information of the computer-readable program instructions to personalize the electronic circuit for various aspects.

[0151] Aspects described herein are illustrated by flowchart illustrations or block diagrams of methods, apparatus (systems), and computer program products according to various embodiments. It should be understood that each block of the flowchart illustrations or block diagrams, and combinations of blocks in the flowchart illustrations or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions executed via the processor of the computer or other programmable data processing apparatus create means for implementing the functions / acts specified in one or more blocks of the flowchart or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, or other device to function in a particular manner, such that the computer-readable storage medium having instructions stored therein comprises an article of manufacture including instructions for implementing aspects of the functions / acts specified in one or more blocks of the flowchart or block diagram. The computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, such that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / acts specified in one or more blocks of the flowchart or block diagram.

[0152] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments. In this regard, each block in the flowchart illustrations or block diagrams may represent a module, segment, or portion of instructions, which includes one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustrations, and combinations of blocks in the block diagrams or flowchart illustrations, can be implemented by a system based on dedicated hardware that performs the specified functions or acts, or combinations of dedicated hardware and computer instructions.

[0153] Although the subject matter has been described above in the general context of computer-executable instructions of a computer program product that runs on one or more computers, those skilled in the art will recognize that the present disclosure may also be implemented, or implemented in combination with, other program modules. Generally, program modules include routines, programs, components, data structures, etc. that perform particular tasks or implement particular abstract data types. In addition, those skilled in the art should recognize that various aspects may be practiced with other computer system configurations, including single-processor or multi-processor computer systems, small computing devices, mainframe computers, and computers, handheld computing devices (e.g., PDAs, telephones), microprocessor-based or programmable consumer or industrial electronic products, etc. The illustrated aspects may also be practiced in a distributed computing environment where tasks are performed by remote processing devices linked through a communications network. However, some, if not all, aspects of the present disclosure may be practiced on a stand-alone computer. In a distributed computing environment, program modules may be located in local and remote memory storage devices.

[0154] As used in this application, the terms "component", "system", "platform", "interface", etc. may refer to, or may include, a computer-related entity or an entity related to an operating machine having one or more specific functionalities. Entities disclosed herein may be hardware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a program running on a processor, a processor, an object, an executable file, an execution thread, a program, or a computer. By way of illustration, both an application running on a server and the server can be components. One or more components may reside within a process or execution thread, and a component may be located on one computer or distributed between two or more computers. As another example, a corresponding component may execute according to various computer-readable media on which various data structures are stored. Components may communicate via local or remote processes, such as according to a signal having one or more data packets (e.g., data from one component that interacts with another component in a local system, a distributed system, or a network, such as the Internet, with other systems) via the signal. As another example, a component may be a device having specific functionality provided by mechanical parts operated by an electrical or electronic circuit, and the electrical or electronic circuit is operated by a software or firmware application executed by a processor. In such cases, the processor may be inside or outside the device and may execute at least a portion of the software or firmware application. As yet another example, a component may be a device that provides specific functionality through electronic components rather than mechanical parts, where the electronic components may include a processor or other components for executing software or firmware that at least partially imparts functionality to the electronic components. In one aspect, a component may, for example, emulate an electronic component via a virtual machine within a cloud computing system.

[0155] In addition, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X employs A or B" is intended to mean any natural inclusive permutation. That is, if X employs A; X employs B; or X employs both A and B, then "X employs A or B" is satisfied in any of the foregoing instances. As used herein, the term "and / or" is intended to have the same meaning as "or". Further, unless otherwise specified or clear from the context as being directed to the singular form, the articles "a" and "an" used in this specification and the drawings are generally to be construed to mean "one or more". As used herein, the terms "example" or "exemplary" are used to mean serving as an example, instance, or illustration. To avoid doubt, the subject matter disclosed herein is not limited by such examples. Additionally, any aspect or design described herein as "example" or "exemplary" should not necessarily be construed as more preferred or advantageous than other aspects or designs, nor does it mean excluding equivalent exemplary structures and techniques known to those of ordinary skill in the art.

[0156] The disclosure herein describes non - limiting examples. For ease of description or explanation, when discussing various examples, each part of the disclosure herein uses the terms "each", "every", or "all". Such uses of the terms "each", "every", or "all" are non - limiting. In other words, when the disclosure herein provides a description of "each", "every", or "all" of some particular objects or components applied to some particular objects or components, it should be understood that this is a non - limiting example, and it should also be understood that in various examples, there may be cases where such a description applies to less than "each", "every", or "all" of the particular objects or components.

[0157] As used in this specification, the term "processor" can generally refer to any computing processing unit or device, including but not limited to a single-core processor; a single-processor with software multithreading execution capabilities; a multi-core processor; a multi-core processor with software multithreading execution capabilities; a multi-core processor with hardware multithreading technology; a parallel platform; and a parallel platform with distributed shared memory. Additionally, a processor can refer to an integrated circuit, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field-programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Further, a processor can utilize nanoscale architectures (such as but not limited to molecule- and quantum-dot-based transistors, switches, and gates) in order to optimize space usage or enhance the performance of user equipment. A processor can also be implemented as a combination of computing processing units. In the present disclosure, terms such as "repository", "storage device", "data repository", "data storage device", "database", and substantially any other information storage component related to the operation and functionality of a component are used to refer to "memory components", entities embodied in "memory", or components that include memory. It should be understood that the memory or memory components described herein can be volatile memory or non-volatile memory, or can include both volatile memory and non-volatile memory. By way of illustration and not limitation, non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). For example, volatile memory can include RAM that can act as an external cache memory. By way of illustration and not limitation, RAM can be provided in various forms, such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). Additionally, the disclosed memory components of the systems or computer-implemented methods herein are intended to include but not limited to including these and any other suitable types of memory.

[0158] The foregoing description only includes examples of systems and computer-implemented methods. Of course, it is not possible to describe every conceivable combination of components or computer-implemented methods for the purposes of describing the present disclosure, but many other combinations and permutations of the present disclosure are possible. Additionally, to the extent that the terms "including", "having", "owning", etc. are used in the detailed description, claims, appendices, and drawings, such terms are intended to be inclusive in a manner similar to the term "comprising", as "comprising" is interpreted when used as a transitional word in a claim.

[0159] The descriptions of the various embodiments have been given for purposes of illustration, but these descriptions are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent without departing from the scope and spirit of the described embodiments. The terms used herein are chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable other ordinary skilled artisans in the art to understand the embodiments disclosed herein.

Claims

1. A system, the system comprising: a memory that stores computer-executable components; and a processor that executes the computer-executable components stored in the memory, wherein the computer-executable components include: a frequency generation component that generates an electronic signal at one or more different frequencies in at least one fetal sensor device (FSD) of a fetal monitoring system (FMS) using a variable frequency generator circuit, wherein the at least one FSD dynamically adjusts a transmit voltage of the at least one FSD to maintain an acoustic power value at the one or more different frequencies, wherein the at least one FSD includes a tunable inductor-capacitor (LC) energy storage circuit, the tunable LC energy storage circuit including a large capacitance varactor that tunes a resonant frequency of the tunable LC energy storage circuit to a carrier frequency of the at least one FSD, wherein tuning the resonant frequency of the tunable LC energy storage circuit to the carrier frequency of the at least one FSD includes using a digital-to-analog converter (DAC) to adjust a bias voltage of a balanced varactor network, and wherein the carrier frequency is a frequency selected from the one or more different frequencies.

2. The system of claim 1, wherein the electronic signal causes a transducer of the at least one FSD to generate an ultrasonic signal at the one or more different frequencies, and wherein adjusting the bias voltage of the balanced varactor network dynamically changes a capacitance value of the large capacitance varactor.

3. The system of claim 1, the system further comprising: a storage component that stores a DAC value corresponding to maximizing a gain of the tunable LC energy storage circuit at the carrier frequency of the at least one FSD.

4. The system of claim 1, wherein the variable frequency generator circuit uses a decaying offset frequency to automate a calibration process for the tunable LC energy storage circuit, and wherein the at least one FSD is calibrated to maximize a gain at the carrier frequency of the at least one FSD.

5. The system of claim 1, wherein tuning the resonant frequency of the tunable LC energy storage circuit to the carrier frequency of the at least one FSD improves a receive sensitivity and a gain of the tunable LC energy storage circuit at the carrier frequency, makes the at least one FSD insensitive to a corresponding carrier frequency of an additional FSD in the FMS, and characterizes and compensates for a behavior of the resonant frequency of the tunable LC energy storage circuit caused by temperature fluctuations experienced by the at least one FSD such that the tunable LC energy storage circuit exhibits consistent performance despite the temperature fluctuations.

6. The system of claim 1, wherein the FMS includes a plurality of FSDs, and wherein the computer-executable components further include: A separating component that separates the respective carrier frequencies of the plurality of FSDs in the FMS such that the frequency difference between the carrier frequencies of any two FSDs is not a multiple of the pulse repetition rate (PRR) of any FSD, wherein separating the respective carrier frequencies of the plurality of FSDs generates predictable harmonics during crosstalk in the FMS.

7. The system according to claim 6, the system further comprising: A signal processing component that implements an automatic gain control stage and a filter to selectively eliminate the predictable harmonics to eliminate crosstalk in the FMS, wherein the automatic gain control stage is implemented as software, hardware, or a combination of software and hardware.

8. The system according to claim 1, the system further comprising: A synchronization component that performs periodic PRR synchronization to synchronize the start of the transmission cycle of the at least one FSD with the corresponding start of the transmission cycles of one or more additional FSDs in the FMS to prevent an ultrasonic signal generated by the at least one FSD from being demodulated by the corresponding carrier frequency generated by the one or more additional FSDs in the FMS.

9. The system according to claim 8, wherein the periodic PRR synchronization is performed by using a monitor that signals the FSDs of the FMS in real time or by using a master FSD to transmit to the additional FSDs in the FMS, and wherein the periodic PRR synchronization is performed wirelessly or through a wired connection.

10. The system according to claim 8, wherein the synchronization component uses a control system to perform pulse phase synchronization to prevent a signal transmitted by a first FSD of the FMS from entering the reception cycle of a second FSD of the FMS, the second FSD being positioned a distance directly across from the first FSD, wherein the control system measures the amount of harmonics generated by the first FSD at the second FSD and gradually offsets the phase of the signal transmitted by the first FSD to align the signal transmitted by the first FSD with the signal transmitted by the second FSD in the FMS.

11. A computer-implemented method, the computer-implemented method comprising: Using a variable frequency generator circuit by a device operably coupled to a processor to generate an electronic signal at one or more different frequencies in at least one FSD of an FMS, wherein the at least one FSD dynamically adjusts the transmission voltage of the at least one FSD to maintain an acoustic power value at the one or more different frequencies; And Tuning the resonant frequency of a tunable LC energy storage circuit included in the at least one FSD to the carrier frequency of the at least one FSD, wherein the carrier frequency is a frequency selected from the one or more different frequencies, wherein the tunable LC energy storage circuit includes a large capacitance varactor that performs the tuning, and wherein tuning the resonant frequency of the tunable LC energy storage circuit to the carrier frequency of the at least one FSD includes: The device uses a DAC to adjust the bias voltage of the balanced varactor network to dynamically change the capacitance value of the large capacitance varactor.

12. The computer-implemented method according to claim 11, wherein the electronic signal causes the transducer of the at least one FSD to generate an ultrasonic signal at the one or more different frequencies.

13. The computer-implemented method according to claim 11, the computer-implemented method further comprising: The device stores the DAC value corresponding to maximizing the gain of the tunable LC energy storage circuit at the carrier frequency of the at least one FSD.

14. The computer-implemented method according to claim 11, the computer-implemented method further comprising: The device uses a decaying offset frequency to automate the calibration process for the tunable LC energy storage circuit; and The device calibrates the at least one FSD to maximize the gain at the carrier frequency of the at least one FSD.

15. The computer-implemented method according to claim 11, wherein tuning the resonant frequency of the tunable LC energy storage circuit to the carrier frequency of the at least one FSD improves the receiving sensitivity and gain of the tunable LC energy storage circuit at the carrier frequency, makes the at least one FSD insensitive to the corresponding carrier frequencies of additional FSDs in the FMS, and characterizes and compensates for the behavior of the resonant frequency of the tunable LC energy storage circuit caused by temperature fluctuations experienced by the at least one FSD, such that the tunable LC energy storage circuit exhibits consistent performance despite the temperature fluctuations.

16. The computer-implemented method according to claim 11, wherein the FMS includes a plurality of FSDs, and wherein the computer-implemented method further comprises: The device separates the corresponding carrier frequencies of the plurality of FSDs in the FMS such that the frequency difference between the carrier frequencies of any two FSDs is not a multiple of the PRR of either FSD, wherein separating the corresponding carrier frequencies of the plurality of FSDs generates predictable harmonics during crosstalk in the FMS; and The device implements an automatic gain control stage and a filter to selectively eliminate the predictable harmonics to eliminate crosstalk in the FMS, wherein the automatic gain control stage is implemented as software, hardware, or a combination of software and hardware.

17. The computer-implemented method according to claim 11, the computer-implemented method further comprising: The device performs periodic PRR synchronization to synchronize the start of the transmission period of the at least one FSD with the corresponding start of the transmission periods of one or more additional FSDs in the FMS to prevent the ultrasonic signal generated by the at least one FSD from being demodulated by the corresponding carrier frequencies generated by the one or more additional FSDs in the FMS.

18. The computer-implemented method according to claim 17, wherein the periodic PRR synchronization is performed by using a monitor that signals the FSD of the FMS in real time or by using a master FSD to signal an additional FSD in the FMS, and wherein the periodic PRR synchronization is performed wirelessly or via a wired connection.

19. The computer-implemented method according to claim 11, the computer-implemented method further comprising: performing pulse phase synchronization by the device using a control system to prevent a signal transmitted by a first FSD of the FMS from entering a reception period of a second FSD of the FMS, the second FSD being positioned a distance directly across from the first FSD, wherein the control system measures an amount of harmonics generated by the first FSD at the second FSD and gradually offsets a phase of the signal transmitted by the first FSD to align the signal transmitted by the first FSD with a signal transmitted by the second FSD in the FMS.

20. A computer program product for ultrasonic coexistence in an FMS, the computer program product comprising a non-transitory computer-readable memory having program instructions embodied therewith, the program instructions being executable by a processor to cause the processor to implement the method according to any one of claims 11 to 19.

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