A motorcycle voltage regulator chip drive circuit with zero-crossing detection function

Abstract

The present invention belongs to the technical field of motorcycle voltage regulator chip circuits, and particularly relates to a motorcycle voltage regulator chip driver circuit with a zero-crossing detection function. The circuit comprises a zero-crossing detection module, which inputs three-phase electrical signals PH1-PH3 and determines whether these signals cross zero positively or negatively. The module outputs a low-level signal when the signals PH1-PH3 are greater than zero, and a high-level signal when the signals PH1-PH3 are less than zero. A digital signal processing module processes the signals VOD1-VOD3 output by the zero-crossing detection module and outputs signals DL_A and DL_B. A driver module inputs the signals DL_A and DL_B and outputs signals DRV1-DRV3 to an off-chip switching transistor. This invention effectively addresses the issue of high thermal load during high-power output, improving voltage regulation accuracy and stability.

Description

Technical Field

[0001] The present invention belongs to the technical field of motorcycle voltage regulator chip circuits, and in particular relates to a motorcycle voltage regulator chip drive circuit with a zero-crossing detection function. Background Art

[0002] In a motorcycle's electrical system, the performance of the voltage regulator chip circuit plays a key role in the stable operation of the entire vehicle. With the continuous innovation of motorcycle technology, especially the development trend of intelligentization and high performance, the requirements for voltage regulator chip circuits are becoming increasingly stringent. Accurate zero-crossing detection has become a core element to improve system performance.

[0003] At present, the common motorcycle voltage regulators on the market have exposed a series of technical defects that need to be solved when dealing with complex working conditions. The traditional thyristor short-circuit voltage regulator adopts a parallel voltage regulation mode. When the motorcycle is running at high speed and the engine is running at high speed, causing the output power of the magneto to increase significantly, the thermal load of the voltage regulator will rise sharply. In order to prevent the voltage regulator from being damaged by overheating, the existing means have to increase a large amount of heat dissipation area. This not only makes the voltage regulator bulky and significantly increases the cost, but also severely limits its application in the compact space layout of motorcycles. In particular, its applicability in high-power voltage regulation scenarios is greatly reduced. The existing voltage regulator chip circuit lacks an effective zero-crossing detection method and cannot adjust the working state in a timely and accurate manner according to the phase change of voltage and current. This causes the chip to operate at high load for a long time, accelerating the aging process of the chip and greatly shortening its service life.

[0004] Existing technologies also have significant shortcomings in terms of the stability and accuracy of voltage regulation. For example, thyristor open-circuit voltage regulators use a series voltage regulation method. When the output end is under heavy load, the thermal load problem will be further exacerbated, making it only suitable for low-power voltage regulation scenarios. Furthermore, when the engine is running at high speeds, due to the constraints of the thyristor's dv / dt parameters, long conduction is very likely to occur, which can lead to loss of control of the voltage regulator. When the motorcycle is in a state of drastic changes in engine operating conditions, such as acceleration and climbing, voltage fluctuations become extremely obvious. At this time, the existing voltage regulator chip circuit cannot accurately capture the voltage zero crossing point, making it difficult to accurately regulate the voltage. For example, in the electronic control unit of a motorcycle's electronic fuel injection system, which requires extremely high voltage stability, voltage instability can cause deviations in fuel injection control, seriously affecting engine performance and even damaging the equipment.

[0005] Furthermore, when the motorcycle's load changes, the response speed of existing voltage regulator chip circuits lags significantly. When the load switches instantly from a low-power indicator light to a high-power headlight, or when additional electronic equipment is connected, the load current changes dramatically and instantaneously. At this point, the conventional voltage regulator chip circuit cannot quickly detect the voltage zero crossing and adjust the output in a timely manner. This causes large fluctuations in the output voltage, preventing it from quickly stabilizing within the appropriate range, thus affecting the normal operation of electrical equipment. In devices such as motorcycle anti-theft alarm systems that require a stable and real-time power supply, these voltage fluctuations can cause false alarms and other adverse conditions.

[0006] In summary, existing motorcycle voltage regulator chip circuits have significant technical deficiencies in thermal load management, voltage regulation accuracy, and load response. These issues are largely due to the lack of an accurate and effective zero-crossing detection function. Therefore, developing a motorcycle voltage regulator chip circuit with zero-crossing detection is of great practical significance for improving the overall performance, reliability, and stability of motorcycle electrical systems. Summary of the Invention

[0007] The purpose of the present invention is to provide a motorcycle voltage regulator circuit with a zero-crossing detection function. The present invention can effectively solve a series of key problems, including eliminating the shortcomings of existing voltage regulators such as large thermal load at high power output, improving voltage regulation accuracy and stability, and accelerating load change response speed.

[0008] To solve the above technical problems, the present invention provides a motorcycle voltage regulator chip driving circuit with a zero-crossing detection function, comprising:

[0009] A zero-crossing detection module is configured to input three-phase electrical signals PH1-PH3 and determine whether the three-phase electrical signals PH1-PH3 have crossed zero positively or negatively, output a low-level signal when the three-phase electrical signals PH1-PH3 are greater than zero, and output a high-level signal when the three-phase electrical signals PH1-PH3 are less than zero; the zero-crossing detection module comprises a zero-crossing comparison level generating circuit, a level detection circuit, and a comparison circuit; wherein the zero-crossing comparison level generating circuit is configured to generate a low-level signal VCOMP after resistive voltage division by controlling a constant current source through a switch tube; the level detection circuit is configured to detect whether the three-phase electrical signals PH1-PH3 have crossed zero, and output signals VC1-VC3 respectively; the comparison circuit is configured to compare the low-level signal VCOMP with the signals VC1-VC3 respectively, and output signals VOD1-VOD3 respectively;

[0010] a digital signal processing module, which processes the signals VOD1 to VOD3 output by the zero-crossing detection module and outputs signals DL_A and DL_B;

[0011] The driver module is used to input signals DL_A and DL_B and output signals DRV1 to DRV3 to the off-chip switch tube to control the on and off of the off-chip switch tube.

[0012] Preferably, the zero-crossing comparison level generating circuit includes: current sources Ia~Id, PMOS transistors P1~P4, resistors R1~R2 and control signals F1~F4; one end of the current sources Ia~Id is connected to the power supply VCC1, and the other end is respectively connected to the source of the PMOS transistors P4~P1, the gates of the PMOS transistors P1~P4 are respectively connected to the control signals F1~F4, the drain of the PMOS transistor P1 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to one end of the resistor R2 and the drains of the PMOS transistors P2~P4 and outputs a low-level signal VCOMP, and the other end of the resistor R2 is grounded.

[0013] Preferably, the relationship between the current sources Ia~Id is: current source Ia=I, current source Ib=2I, current source Ic=Id=4I.

[0014] Preferably, the level detection circuit includes: NMOS transistors N1~N4, resistors R3~R4, capacitor C1 and bias voltage VB1; the three-phase electrical signals PH1~PH3 are respectively connected to one end of the resistor R3, the other end of the resistor R3 is connected to the drain of the NMOS transistor N1, the gate of the NMOS transistor N1 is connected to the bias voltage VB1, the source of the NMOS transistor N1 is connected to the drain and gate of the NMOS transistor N2 and one end of the resistor R4, the source of the NMOS transistor N2 is connected to the drain and gate of the NMOS transistor N3, the source of the NMOS transistor N3 is connected to the drain and gate of the NMOS transistor N4, the source of the NMOS transistor N4 is grounded, the other end of the resistor R4 is connected to one end of the capacitor C1 and outputs signals VC1~VC3 respectively, and the other end of the capacitor C1 is grounded.

[0015] Preferably, the comparison circuit includes: PMOS transistors P5~P10, NMOS transistors N5~N6, a resistor R5, current sources Ie~Ig and bias voltages VB2~VB5; the source of the PMOS transistor P5 is connected to the power supply VCC1, the drain of the PMOS transistor P5 is connected to the source of the PMOS transistor P6, the drain of the PMOS transistor P6 is connected to the gate of the PMOS transistor P5 and the drain of the NMOS transistor N5 and is connected to the bias voltage VB2, the gate of the PMOS transistor P6 is connected to the bias voltage VB3, the gate of the NMOS transistor N5 is connected to the bias voltage VB4, the source of the NMOS transistor N5 is connected to the drain of the PMOS transistor P9 and one end of the current source If, ​​the other end of the current source If is grounded, the gate of the PMOS transistor P9 is connected to the low-level signal VCOMP, and the source of the PMOS transistor P9 is connected to The resistor R5 and one end of the current source Ie are connected to the power supply VCC1. The other end of the current source Ie is connected to the source of the PMOS transistor P10. The gate of the PMOS transistor P10 is connected to signals VC1 to VC3 respectively. The drain of the PMOS transistor P10 is connected to the source of the NMOS transistor N6 and one end of the current source Ig. The other end of the current source Ig is grounded. The gate of the NMOS transistor N6 is connected to the bias voltage VB5. The drain of the NMOS transistor N6 is connected to the drain of the PMOS transistor P8 and outputs signals VOD1 to VOD3. The gate of the PMOS transistor P8 is connected to the bias voltage VB3. The source of the PMOS transistor P8 is connected to the drain of the PMOS transistor P7. The gate of the PMOS transistor P7 is connected to the bias voltage VB2. The source of the PMOS transistor P7 is connected to the power supply VCC1.

[0016] Preferably, the driving module includes: a digital logic circuit and a level conversion circuit; the digital logic circuit is used to input signals DL_A and DL_B; the signal DL_A indicates whether the three-phase electrical signals PH1~PH3 are zero-crossing, and the DL_B indicates whether the digital signal processing module is working. The two signals DL_A and DL_B are processed by the digital logic circuit to output the signal DL_YN, and the signal DL_YN is processed by the level conversion circuit to output the signals DRV1~DRV3 to drive the off-chip switching tube.

[0017] Preferably, the level conversion circuit includes: PMOS transistors P11 to P18, NMOS transistors N7 to N11, resistors R6 to R11, capacitors C2 to C3, and a diode D1; the sources of the PMOS transistors P11, PMOS transistors P14, and PMOS transistors P17, and one end of the resistors R6 to R7 are connected to the power supply VCC2, the gate and drain of the PMOS transistor P11 are connected to the source of the PMOS transistor P12, the gate and drain of the PMOS transistor P12 are connected to the source of the PMOS transistor P13, the gate and drain of the PMOS transistor P13 are connected to the gate of the PMOS transistor P18, the drains of the NMOS transistors N7 to N8, and the other end of the resistor R6, and the sources of the NMOS transistors N7 to N8 are interconnected. The drain of the PMOS transistor P18 is connected to the drains of the NMOS transistors N9 and N10, the gate and drain of the PMOS transistor P16, the gate of the PMOS transistor P17, and the other end of the resistor R7. The gates of the NMOS transistors N9 and N10 are interconnected, and the sources of the NMOS transistors N9 and N10 are interconnected. The drain of the PMOS transistor P17 is connected to one end of the diode D1, and the other end of the diode D1 is connected to one end of the resistor R10 and the drain of the NMOS transistor N11. The gate of the NMOS transistor N11 is connected to the signal DL_YN. The source of the NMOS transistor N11 is connected to one end of the resistor R11 and is grounded. The other end of the resistor R11 is connected to the other end of the resistor R10 and outputs signals DRV1 to DRV3.

[0018] Preferably, two filter circuits are further included, one end of the two filter circuits are respectively connected to the source of the NMOS tubes N7~N8 and the source of the NMOS tubes N9~N10, and the other ends are respectively grounded; wherein the two filter circuits are respectively composed of a capacitor C2 and a resistor R8 in parallel, and a capacitor C3 and a resistor R9 in parallel.

[0019] Preferably, the circuit further includes a fuse trimming circuit 1 and a fuse trimming circuit 2, wherein the fuse trimming circuit 1 includes: PMOS transistors P20-P21, NMOS transistors N13-N14, a resistor R13, and a fuse FUSE1; the sources of the PMOS transistors P20-P21 are connected to the power supply VCC1, the gate of the PMOS transistor P20 is connected to the bias voltage VB6, the drain of the PMOS transistor P20 is connected to the gate of the PMOS transistor P21 and the drain of the NMOS transistor N13, the gate of the NMOS transistor N13 is connected to the bias voltage VB7, the source is connected to one end of the resistor R13, the other end of the resistor R13 is connected to one end of the fuse FUSE1 and inputs the off-chip fuse write signal FUSE_WR1 signal, the other end of the fuse FUSE1 is grounded, the drain of the PMOS transistor P21 is connected to the drain of the NMOS transistor N14 and outputs the control signal F2, the gate of the NMOS transistor N14 is connected to the bias voltage VB8, and the source is grounded;

[0020] The second fuse trimming circuit includes: a PMOS transistor P19, an NMOS transistor N12, a resistor R12, and a fuse FUSE2; the source of the PMOS transistor P19 is connected to the power supply VCC1, the gate is connected to the bias voltage VB6, the drain is connected to the drain of the NMOS transistor N12 and outputs control signals F3~F4, the gate of the NMOS transistor N12 is connected to the bias voltage VB7, the source is connected to one end of the resistor R12, the other end of the resistor R12 is connected to one end of the fuse FUSE2 and inputs off-chip fuse write signals FUSE_WR2~FUSE_WR3, and the other end of the fuse FUSE2 is grounded.

[0021] Preferably, when the voltage of the three-phase electrical signals PH1~PH3 is greater than 0V but less than 2.1V, the signals VC1~VC3 change with the three-phase electrical signals PH1~PH3; when the voltage of the three-phase electrical signals PH1~PH3 is greater than 2.1V, the three-phase electrical signals PH1~PH3 are clamped by the three diode-connected NMOS transistors N2~N4, and the output signals VC1~VC3 are 2.1V; when the voltage of the three-phase electrical signals PH1~PH3 is lower than -0.8V, the diodes of the NMOS transistors N2~N4 protecting the three-phase electrical signals PH1~PH3 are turned on, so that the output signals VC1~VC3 are -0.8V.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] 1. This invention addresses the problem of excessive thermal load: Existing voltage regulators experience high thermal loads at high power output. However, this invention utilizes zero-crossing detection to accurately determine the moment when the voltage and current cross zero, and promptly adjusts the voltage regulator's operating state based on the motorcycle's engine operating conditions and magneto output. This prevents the chip from operating at high loads for extended periods, reduces unnecessary power loss and heat generation, and thus lowers thermal load and extends the voltage regulator's service life. This eliminates the need for extensive heat sinks, saving space and cost.

[0024] 2. The present invention improves voltage regulation accuracy and stability: Traditional voltage regulators have poor voltage regulation when operating conditions change. The present invention uses zero-crossing detection to accurately capture the voltage zero-crossing point, and combines the real-time detected voltage and current signals to quickly and accurately adjust the output voltage.

[0025] 3. The present invention accelerates the response speed to load changes: In the face of sudden changes in motorcycle load, traditional voltage regulators respond slowly. The present invention uses a drive circuit with a zero-crossing detection function to enable the voltage regulator to quickly adjust the output to meet the power requirements of different loads. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is the overall structural block diagram of the motorcycle voltage regulator chip drive circuit provided by the present invention.

[0027] Figure 2 It is a circuit diagram of the zero-crossing comparison level generating circuit provided by the present invention.

[0028] Figure 3 It is a circuit diagram of a level detection circuit provided by the present invention.

[0029] Figure 4 1 is a circuit diagram of a comparison circuit provided by the present invention.

[0030] Figure 5 It is a principle diagram of the digital signal processing module provided by the present invention.

[0031] Figure 6 It is a principle diagram of the digital logic circuit provided by the present invention.

[0032] Figure 7 It is a circuit diagram of the level conversion circuit provided by the present invention.

[0033] Figure 8 1 and 2 are circuit diagrams of fuse trimming circuits provided by the present invention; (a) is a circuit diagram of fuse trimming circuit 1; and (b) is a circuit diagram of fuse trimming circuit 2. DETAILED DESCRIPTION

[0034] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present invention.

[0035] like Figure 1 and Figure 5 As shown, the embodiment of the present invention specifically provides a motorcycle voltage regulator chip driving circuit with a zero-crossing detection function, comprising:

[0036] A zero-crossing detection module is configured to input three-phase electrical signals PH1-PH3 and determine whether the three-phase electrical signals PH1-PH3 have crossed zero positively or negatively, output a low-level signal when the three-phase electrical signals PH1-PH3 are greater than zero, and output a high-level signal when the three-phase electrical signals PH1-PH3 are less than zero; the zero-crossing detection module comprises a zero-crossing comparison level generating circuit, a level detection circuit, and a comparison circuit; wherein the zero-crossing comparison level generating circuit is configured to generate a low-level signal VCOMP after resistive voltage division by controlling a constant current source through a switch tube; the level detection circuit is configured to detect whether the three-phase electrical signals PH1-PH3 have crossed zero, and output signals VC1-VC3 respectively; the comparison circuit is configured to compare the low-level signal VCOMP with the signals VC1-VC3 respectively, and output signals VOD1-VOD3 respectively;

[0037] a digital signal processing module, which processes the signals VOD1 to VOD3 output by the zero-crossing detection module and outputs signals DL_A and DL_B;

[0038] The driver module is used to input signals DL_A and DL_B, and output signals DRV1~DRV3 to the off-chip switch tube to control the on and off of the off-chip switch tube to start and stop charging the battery.

[0039] like Figure 2 As shown, the zero-crossing comparison level generating circuit includes: current sources Ia-Id, PMOS transistors P1-P4, resistors R1-R2, and control signals F1-F4; one end of the current sources Ia-Id is connected to the power supply VCC1, and the other end is respectively connected to the source of the PMOS transistors P4-P1, the gates of the PMOS transistors P1-P4 are respectively connected to the control signals F1-F4, the drain of the PMOS transistor P1 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to one end of the resistor R2 and the drains of the PMOS transistors P2-P4 and outputs a low-level signal VCOMP, and the other end of the resistor R2 is grounded.

[0040] Preferably, the relationship between the current sources Ia~Id is: current source Ia=I, current source Ib=2I, current source Ic=Id=4I.

[0041] like Figure 8 As shown, it also includes a fuse trimming circuit 1 and a fuse trimming circuit 2. The fuse trimming circuit 1 includes: PMOS transistors P20-P21, NMOS transistors N13-N14, a resistor R13 and a fuse FUSE1; the sources of the PMOS transistors P20-P21 are connected to the power supply VCC1, the gate of the PMOS transistor P20 is connected to the bias voltage VB6, the drain of the PMOS transistor P20 is connected to the gate of the PMOS transistor P21 and the drain of the NMOS transistor N13, the gate of the NMOS transistor N13 is connected to the bias voltage VB7, the source is connected to one end of the resistor R13, the other end of the resistor R13 is connected to one end of the fuse FUSE1 and inputs the off-chip fuse write signal FUSE_WR1 signal, the other end of the fuse FUSE1 is grounded, the drain of the PMOS transistor P21 is connected to the drain of the NMOS transistor N14 and outputs the control signal F2, the gate of the NMOS transistor N14 is connected to the bias voltage VB8, and the source is grounded;

[0042] The second fuse trimming circuit includes: a PMOS transistor P19, an NMOS transistor N12, a resistor R12, and a fuse FUSE2; the source of the PMOS transistor P19 is connected to the power supply VCC1, the gate is connected to the bias voltage VB6, the drain is connected to the drain of the NMOS transistor N12 and outputs control signals F3~F4, the gate of the NMOS transistor N12 is connected to the bias voltage VB7, the source is connected to one end of the resistor R12, the other end of the resistor R12 is connected to one end of the fuse FUSE2 and inputs off-chip fuse write signals FUSE_WR2~FUSE_WR3, and the other end of the fuse FUSE2 is grounded.

[0043] When the external fuse write signals FUSE_WRn (n=1, 2, 3) are input, the corresponding output signals are Fi (i=2, 3, 4). For fuse FUSE1, when FUSE1 is not blown, output signal F2 is high. When fuse FUSE1 needs to be blown, the external write signal FUSE_WR1 is high, blowing FUSE1, and the circuit output signal F2 is low. For fuse FUSE2, when fuse FUSE2 is not blown, output signals F3 and F4 are low. When fuse FUSE2 needs to be blown, the write signals FUSE_WR2 and FUSE_WR3 are high, and the circuit output signals F3 and F4 are high, respectively.

[0044] like Figure 3 As shown, the level detection circuit includes: NMOS transistors N1-N4, resistors R3-R4, capacitor C1, and bias voltage VB1; the three-phase electrical signals PH1-PH3 are respectively connected to one end of the resistor R3, the other end of the resistor R3 is connected to the drain of the NMOS transistor N1, the gate of the NMOS transistor N1 is connected to the bias voltage VB1, the source of the NMOS transistor N1 is connected to the drain and gate of the NMOS transistor N2 and one end of the resistor R4, the source of the NMOS transistor N2 is connected to the drain and gate of the NMOS transistor N3, the source of the NMOS transistor N3 is connected to the drain and gate of the NMOS transistor N4, the source of the NMOS transistor N4 is grounded, the other end of the resistor R4 is connected to one end of the capacitor C1 and outputs signals VC1-VC3 respectively, and the other end of the capacitor C1 is grounded.

[0045] like Figure 4As shown, the comparison circuit includes: PMOS transistors P5~P10, NMOS transistors N5~N6, a resistor R5, current sources Ie~Ig and bias voltages VB2~VB5; the source of the PMOS transistor P5 is connected to the power supply VCC1, the drain of the PMOS transistor P5 is connected to the source of the PMOS transistor P6, the drain of the PMOS transistor P6 is connected to the gate of the PMOS transistor P5 and the drain of the NMOS transistor N5 and is connected to the bias voltage VB2, the gate of the PMOS transistor P6 is connected to the bias voltage VB3, the gate of the NMOS transistor N5 is connected to the bias voltage VB4, the source of the NMOS transistor N5 is connected to the drain of the PMOS transistor P9 and one end of the current source If, ​​the other end of the current source If is grounded, the gate of the PMOS transistor P9 is connected to the low-level signal VCOMP, and the source of the PMOS transistor P9 is connected to The resistor R5 and one end of the current source Ie are connected to the power supply VCC1. The other end of the current source Ie is connected to the source of the PMOS transistor P10. The gate of the PMOS transistor P10 is connected to signals VC1 to VC3 respectively. The drain of the PMOS transistor P10 is connected to the source of the NMOS transistor N6 and one end of the current source Ig. The other end of the current source Ig is grounded. The gate of the NMOS transistor N6 is connected to the bias voltage VB5. The drain of the NMOS transistor N6 is connected to the drain of the PMOS transistor P8 and outputs signals VOD1 to VOD3. The gate of the PMOS transistor P8 is connected to the bias voltage VB3. The source of the PMOS transistor P8 is connected to the drain of the PMOS transistor P7. The gate of the PMOS transistor P7 is connected to the bias voltage VB2. The source of the PMOS transistor P7 is connected to the power supply VCC1.

[0046] like Figure 6 and Figure 7 As shown, the driver module includes a digital logic circuit and a level shifter circuit. The digital logic circuit is used to input signals DL_A and DL_B. The signal DL_A indicates whether the three-phase electrical signals PH1-PH3 have crossed zero, and the signal DL_B is the output signal of the digital signal processing module, indicating whether the digital signal processing module is operating. The two signals DL_A and DL_B are processed by the digital logic circuit to output the signal DL_YN. The signal DL_YN is processed by the level shifter circuit to output the signals DRV1-DRV3 to drive the off-chip switching transistors. When X1_YN and X2_YN are constantly high, X1_YN and X2_YN serve as the gate signals for transistors N7 and N8, and for transistors N9 and N10, respectively. This causes transistors P17 and P18 to be in a conductive state when the level shifter circuit is operating.

[0047] like Figure 7As shown, the level conversion circuit includes: PMOS transistors P11 to P18, NMOS transistors N7 to N11, resistors R6 to R11, capacitors C2 to C3, and a diode D1; the sources of the PMOS transistors P11, PMOS transistors P14, and PMOS transistors P17, and one end of the resistors R6 to R7 are connected to the power supply VCC2, the gate and drain of the PMOS transistor P11 are connected to the source of the PMOS transistor P12, the gate and drain of the PMOS transistor P12 are connected to the source of the PMOS transistor P13, the gate and drain of the PMOS transistor P13 are connected to the gate of the PMOS transistor P18, the drains of the NMOS transistors N7 to N8, and the other end of the resistor R6, and the sources of the NMOS transistors N7 to N8 are interconnected. The drain of the PMOS transistor P18 is connected to the drains of the NMOS transistors N9 and N10, the gate and drain of the PMOS transistor P16, the gate of the PMOS transistor P17, and the other end of the resistor R7. The gates of the NMOS transistors N9 and N10 are interconnected, and the sources of the NMOS transistors N9 and N10 are interconnected. The drain of the PMOS transistor P17 is connected to one end of the diode D1. The other end of the diode D1 is connected to one end of the resistor R10 and the drain of the NMOS transistor N11. The gate of the NMOS transistor N11 is connected to the signal DL_YN. The source of the NMOS transistor N11 is connected to one end of the resistor R11 and is grounded. The other end of the resistor R11 is connected to the other end of the resistor R10 and outputs signals DRV1 to DRV3.

[0048] When this level shifter circuit is operating, DL_YN is the output signal after the DL_A and DL_B signals pass through the digital logic circuit. Since X1_YN and X2_YN are constantly high, transistors N7, N8, N9, and N10 are constantly on, and the gate of transistor P17 is low. When DL_YN is low, transistor N11 is off, and outputs DRV1 through DRV3 are high (the high level is the on-chip high-voltage operating power supply VCC2). When DL_YN is high (the high level of DL_YN is the on-chip low-voltage operating power supply VCC1, that is, VCC1 is less than VCC2), transistor N11 is on, and outputs DRV1 through DRV3 are low.

[0049] like Figure 7 As shown, two filter circuits are also included, one end of the two filter circuits is respectively connected to the source of the NMOS transistors N7~N8 and the source of the NMOS transistors N9~N10, and the other end is respectively grounded; wherein the two filter circuits are respectively composed of a capacitor C2 and a resistor R8 in parallel, and a capacitor C3 and a resistor R9 in parallel.

[0050] When the zero-crossing detection module is working, its main function is to determine whether the voltage of the three-phase electrical signals PH1, PH2, and PH3 crosses zero. When the three-phase voltage is greater than zero, the circuit outputs a low-level signal to the digital signal processing module at the next level, notifying the digital signal processing module that the phase power can charge the battery. When the three-phase voltage is lower than zero, the circuit outputs a high level, and the digital signal processing module turns off the NMOS switch tube corresponding to the phase power, stopping charging the battery. When the three-phase voltage is greater than 0 but less than 2.1V, VC1, VC2, and VC3 follow the changes of PH1, PH2, and PH3. When the phase voltage exceeds 2.1V, the three-phase signals are clamped by the three diode-connected MOS transistors (NMOS transistors N2-N4), outputting a voltage of approximately 2.1V (approximately three times the threshold voltage VTH of N2-N4). When the phase voltage falls below -0.8V, the diodes in the ESD protection circuits for PH1, PH2, and PH3 conduct, outputting a voltage of approximately -0.8V (VC1, VC2, and VC3) to one end of the comparator circuit. F1, F2, F3, and F4 are the constant current source control signals. They generate a very low-level signal (VCOMP) through resistors. This signal is compared with the generated signals VC1, VC2, and VC3, respectively, to produce outputs VOD1, VOD2, and VOD3.

[0051] Initially, the constant current source control signal F1 is low, while F2 is high, F3, and F4 are low, resulting in VCOMP = 7IR (where R is the resistance of resistor R2). When the digital signal processing module detects a zero-crossing, it flips F1 high, and VCOMP becomes 4IR, making the comparator circuit function similarly to a Schmitt trigger. Furthermore, due to the presence of resistor R5, VC1, VC2, and VC3 must be at a voltage lower than VCOMP to trigger VOD1, VOD2, and VOD3, thereby reducing the flip voltage from VCOMP by I × 1 / 2R5. To adjust the positive and negative zero-crossing flip voltages, the VCOMP voltage value is adjusted using fuses in steps of IR. After flipping, F1 remains constant high, while F2-F4 are adjusted using off-chip fuse trim circuits 1 and 2. To overcome zero-crossing errors caused by process variations, when the positive and negative zero-crossing flip voltages need to be adjusted, fuse trim circuits 1 and 2 are used to control signals F2 through F4 to change the VCOMP voltage value, with an adjustment step size of IR.

[0052] When the input phase voltage signal rises from negative voltage to 5mV, it is judged that the output current of the corresponding phase of the magnetic motor crosses zero from negative to positive, and the phase drive circuit outputs a low level, the off-chip NMOS switch tube is turned off, and the voltage regulator charges the battery; similarly, when the input phase voltage signal drops from positive voltage to -5mV, it is judged that the output current of the corresponding phase of the magnetic motor crosses zero from positive to negative, and the phase drive circuit outputs a high level, the off-chip NMOS switch tube is turned on, and the voltage regulator stops charging the battery.

[0053] In summary, the present invention, through the zero-crossing detection function, can accurately grasp the moment when the voltage and current cross zero, adjust the working state of the voltage regulator in real time, and quickly and accurately adjust the output voltage in combination with the voltage and current signals detected in real time. The structure is simple and the cost is low. The drive module of the present invention can quickly sense and respond by virtue of the zero-crossing detection function. It can timely adjust the drive signal at the moment of sudden load change, reduce the fluctuation of the output voltage, and quickly stabilize the voltage within an appropriate range to meet the power demand of different loads, avoid malfunction or damage of electrical equipment due to unstable voltage, and enhance the system's adaptability to complex working conditions.

[0054] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A motorcycle voltage regulator chip drive circuit with zero-crossing detection function, characterized in that: include: A zero-crossing detection module is configured to input the three-phase electrical signals PH1-PH3 and determine whether the three-phase electrical signals PH1-PH3 have positive and negative zero crossings. When the three-phase electrical signals PH1-PH3 are greater than zero, a low-level signal is output; and when the three-phase electrical signals PH1-PH3 are less than zero, a high-level signal is output. The zero-crossing detection module includes a zero-crossing comparison level generating circuit, a level detection circuit, and a comparison circuit. The zero-crossing comparison level generating circuit is used to generate a low-level signal VCOMP by controlling a constant current source through a switch tube to perform resistor voltage division; the level detection circuit is used to detect whether the three-phase electrical signals PH1 to PH3 cross zero and output signals VC1 to VC3 respectively; the comparison circuit is used to compare the low-level signal VCOMP with the signals VC1 to VC3 respectively and output signals VOD1 to VOD3 respectively; a digital signal processing module, which processes the signals VOD1 to VOD3 output by the zero-crossing detection module and outputs signals DL_A and DL_B; The driver module is used to input signals DL_A and DL_B and output signals DRV1 to DRV3 to the off-chip switch tube to control the on and off of the off-chip switch tube; The zero-crossing comparison level generating circuit includes: current sources Ia-Id, PMOS transistors P1-P4, resistors R1-R2, and control signals F1-F4; one end of the current sources Ia-Id is connected to a power supply VCC1, and the other end is connected to the source of the PMOS transistors P4-P1, respectively; the gates of the PMOS transistors P1-P4 are connected to the control signals F1-F4, respectively; the drain of the PMOS transistor P1 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to one end of the resistor R2 and the drains of the PMOS transistors P2-P4 and outputs a low-level signal VCOMP; the other end of the resistor R2 is grounded; The comparison circuit includes: PMOS transistors P5-P10, NMOS transistors N5-N6, a resistor R5, current sources Ie-Ig and bias voltages VB2-VB5; the source of the PMOS transistor P5 is connected to the power supply VCC1, the drain of the PMOS transistor P5 is connected to the source of the PMOS transistor P6, the drain of the PMOS transistor P6 is connected to the gate of the PMOS transistor P5 and the drain of the NMOS transistor N5 and is connected to the bias voltage VB2, the gate of the PMOS transistor P6 is connected to the bias voltage VB3, the gate of the NMOS transistor N5 is connected to the bias voltage VB4, the source of the NMOS transistor N5 is connected to the drain of the PMOS transistor P9 and one end of the current source If, ​​the other end of the current source If is grounded, the gate of the PMOS transistor P9 is connected to the low-level signal VCOMP, and the source of the PMOS transistor P9 is connected to the resistor R5 is connected to one end of the current source Ie. The other end of the current source Ie is connected to the power supply VCC1. The other end of the resistor R5 is connected to the source of the PMOS transistor P10. The gate of the PMOS transistor P10 is connected to signals VC1 to VC3 respectively. The drain of the PMOS transistor P10 is connected to the source of the NMOS transistor N6 and one end of the current source Ig. The other end of the current source Ig is grounded. The gate of the NMOS transistor N6 is connected to the bias voltage VB5. The drain of the NMOS transistor N6 is connected to the drain of the PMOS transistor P8 and outputs signals VOD1 to VOD3. The gate of the PMOS transistor P8 is connected to the bias voltage VB3. The source of the PMOS transistor P8 is connected to the drain of the PMOS transistor P7. The gate of the PMOS transistor P7 is connected to the bias voltage VB2. The source of the PMOS transistor P7 is connected to the power supply VCC1.

2. A motorcycle voltage regulator chip drive circuit with zero-crossing detection function as claimed in claim 1, characterized in that: The relationship between the current sources Ia~Id is: current source Ia=I, current source Ib=2I, current source Ic=Id=4I.

3. The motorcycle voltage regulator chip driving circuit with zero-crossing detection function as claimed in claim 1, characterized in that: The level detection circuit includes: NMOS transistors N1-N4, resistors R3-R4, capacitor C1, and bias voltage VB1; the three-phase electrical signals PH1-PH3 are respectively connected to one end of resistor R3, the other end of resistor R3 is connected to the drain of NMOS transistor N1, the gate of NMOS transistor N1 is connected to bias voltage VB1, the source of NMOS transistor N1 is connected to the drain and gate of NMOS transistor N2 and one end of resistor R4, the source of NMOS transistor N2 is connected to the drain and gate of NMOS transistor N3, the source of NMOS transistor N3 is connected to the drain and gate of NMOS transistor N4, the source of NMOS transistor N4 is grounded, the other end of resistor R4 is connected to one end of capacitor C1 and outputs signals VC1-VC3 respectively, and the other end of capacitor C1 is grounded.

4. The motorcycle voltage regulator chip driving circuit with zero-crossing detection function as claimed in claim 1, characterized in that: The driving module includes: a digital logic circuit and a level conversion circuit; the digital logic circuit is used to input signals DL_A and DL_B; the signal DL_A indicates whether the three-phase electrical signals PH1~PH3 are zero-crossing, and the DL_B indicates whether the digital signal processing module is working. After the two signals DL_A and DL_B are processed by the digital logic circuit, the output signal DL_YN is output. After the signal DL_YN is processed by the level conversion circuit, the output signal DRV1~DRV3 is output to drive the off-chip switch tube.

5. A motorcycle voltage regulator chip driving circuit with zero-crossing detection function as claimed in claim 4, characterized in that: The level conversion circuit includes: PMOS transistors P11-P18, NMOS transistors N7-N11, resistors R6-R11, capacitors C2-C3 and a diode D1; the sources of the PMOS transistors P11, PMOS transistors P14 and PMOS transistors P17, and one end of the resistors R6-R7 are connected to the power supply VCC2, the gate and drain of the PMOS transistor P11 are connected to the source of the PMOS transistor P12, the gate and drain of the PMOS transistor P12 are connected to the source of the PMOS transistor P13, the gate and drain of the PMOS transistor P13 are connected to the gate of the PMOS transistor P18, the drains of the NMOS transistors N7-N8 and the other end of the resistor R6, the sources of the NMOS transistors N7-N8 are interconnected, and the The drain of the PMOS transistor P18 is connected to the drains of the NMOS transistors N9 and N10, the gate and drain of the PMOS transistor P16, the gate of the PMOS transistor P17, and the other end of the resistor R7. The gates of the NMOS transistors N9 and N10 are interconnected, and the sources of the NMOS transistors N9 and N10 are interconnected. The drain of the PMOS transistor P17 is connected to one end of the diode D1. The other end of the diode D1 is connected to one end of the resistor R10 and the drain of the NMOS transistor N11. The gate of the NMOS transistor N11 is connected to the signal DL_YN. The source of the NMOS transistor N11 is connected to one end of the resistor R11 and is grounded. The other end of the resistor R11 is connected to the other end of the resistor R10 and outputs signals DRV1 to DRV3.

6. A motorcycle voltage regulator chip drive circuit with zero-crossing detection function as claimed in claim 5, characterized in that: It also includes two filter circuits, one end of the two filter circuits is respectively connected to the source of the NMOS transistors N7~N8 and the source of the NMOS transistors N9~N10, and the other end is respectively grounded; wherein the two filter circuits are respectively composed of a capacitor C2 and a resistor R8 in parallel, and a capacitor C3 and a resistor R9 in parallel.

7. The motorcycle voltage regulator chip driving circuit with zero-crossing detection function as claimed in claim 1, characterized in that: The circuit also includes a fuse trimming circuit 1 and a fuse trimming circuit 2. The fuse trimming circuit 1 includes: PMOS transistors P20-P21, NMOS transistors N13-N14, a resistor R13, and a fuse FUSE1. The sources of the PMOS transistors P20-P21 are connected to a power supply VCC1, the gate of the PMOS transistor P20 is connected to a bias voltage VB6, the drain of the PMOS transistor P20 is connected to the gate of the PMOS transistor P21 and the drain of the NMOS transistor N13, the gate of the NMOS transistor N13 is connected to a bias voltage VB7, the source is connected to one end of the resistor R13, the other end of the resistor R13 is connected to one end of the fuse FUSE1 and inputs an off-chip fuse write signal FUSE_WR1, the other end of the fuse FUSE1 is grounded, the drain of the PMOS transistor P21 is connected to the drain of the NMOS transistor N14 and outputs a control signal F2, the gate of the NMOS transistor N14 is connected to a bias voltage VB8, and the source is grounded. The second fuse trimming circuit includes: a PMOS transistor P19, an NMOS transistor N12, a resistor R12, and a fuse FUSE2; the source of the PMOS transistor P19 is connected to the power supply VCC1, the gate is connected to the bias voltage VB6, the drain is connected to the drain of the NMOS transistor N12 and outputs control signals F3~F4, the gate of the NMOS transistor N12 is connected to the bias voltage VB7, the source is connected to one end of the resistor R12, the other end of the resistor R12 is connected to one end of the fuse FUSE2 and inputs off-chip fuse write signals FUSE_WR2~FUSE_WR3, and the other end of the fuse FUSE2 is grounded.

8. A motorcycle voltage regulator chip drive circuit with a zero-crossing detection function according to any one of claims 1 to 7, characterized in that: When the voltage of the three-phase electrical signals PH1-PH3 is greater than 0V but less than 2.1V, the signals VC1-VC3 change in accordance with the three-phase electrical signals PH1-PH3. When the voltage of the three-phase electrical signals PH1-PH3 is greater than 2.1V, the three-phase electrical signals PH1-PH3 are clamped by the three diode-connected NMOS transistors N2-N4, and the output signals VC1-VC3 are 2.1V. When the voltage of the three-phase electrical signals PH1-PH3 is less than -0.8V, the diodes of the NMOS transistors N2-N4 protecting the three-phase electrical signals PH1-PH3 are turned on, and the output signals VC1-VC3 are -0.8V.

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