Data access method and storage device

Abstract

The invention provides a data access method and a storage device. The method comprises the steps that in response to a data access event, first verification information is generated at a first verification position in the storage device according to target data and first logic unit information, and the data access event indicates that the target data is stored in a memory module or read from the memory module; according to the target data and the second logic unit information, second verification information is generated at a second verification position in the storage device, and the second verification position is different from the first verification position; executing a verification operation according to the first verification information and the second verification information to obtain a verification result; and executing an operation corresponding to the data access event according to the verification result. Therefore, the accuracy of data transmission can be ensured, and the operation stability of the storage device is further improved.

Description

Technical Field

[0001] The present invention relates to the field of storage technologies, and more particularly to a data access method and a storage device. Background Art

[0002] With the development of technology, the application of storage devices including non-volatile memory modules (such as flash memory modules) has become increasingly popular. Generally, a host system uses operation instructions in combination with logical addresses (such as logical block addresses) to instruct the storage device to read, store, or delete user data stored at this logical address. Most storage devices support error correction (such as decoding) for user data to avoid accessing incorrect user data.

[0003] However, storage devices generally lack an integrity verification mechanism for logical addresses. Therefore, when there are integrity problems with logical addresses, accessing the memory module based on this logical address will result in access errors, thereby reducing the operational stability of the storage device. Summary of the Invention

[0004] The present invention provides a data access method and a storage device, which can improve the above problems and further enhance the operational stability of the storage device.

[0005] An embodiment of the present invention provides a data access method for a storage device, where the storage device is connected to a host system, the storage device includes a memory module, and the data access method includes: in response to a data access event, generating first check information at a first verification location inside the storage device according to target data and first logical unit information corresponding to the target data, where the data access event indicates storing the target data into the memory module or reading the target data from the memory module; generating second check information at a second verification location inside the storage device according to the target data and second logical unit information corresponding to the target data, where the second verification location is different from the first verification location; performing a verification operation according to the first check information and the second check information to obtain a verification result; and performing an operation corresponding to the data access event according to the verification result.

[0006] An embodiment of the present invention further provides a storage device, which includes a connection interface, a memory module, and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory controller is configured to: in response to a data access event, generate first check information at a first verification location inside the storage device according to target data and first logical unit information corresponding to the target data, where the data access event indicates storing the target data into the memory module or reading the target data from the memory module; generate second check information at a second verification location inside the storage device according to the target data and second logical unit information corresponding to the target data, where the second verification location is different from the first verification location; perform a verification operation according to the first check information and the second check information to obtain a verification result; and perform an operation corresponding to the data access event according to the verification result. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic diagram of a data storage system shown according to an embodiment of the present invention;

[0008] Figure 2 is a schematic diagram of a memory controller shown according to an embodiment of the present invention;

[0009] Figure 3 is a schematic diagram of a managed memory module shown according to an embodiment of the present invention;

[0010] Figure 4 is a schematic diagram of a memory control circuit including a first controller and a second controller shown according to an embodiment of the present invention;

[0011] Figure 5 AND Figure 6 is a schematic diagram of an operation scenario for a data write event shown according to an embodiment of the present invention;

[0012] Figures 7 to 9 is a schematic diagram of an operation scenario for a data read event shown according to an embodiment of the present invention;

[0013] Figure 10 is a flowchart of a data access method shown according to an embodiment of the present invention. DETAILED DESCRIPTION

[0014] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0015] Figure 1It is a schematic diagram of a data storage system shown according to an embodiment of the present invention. Please refer to Figure 1 , the data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and is used to store data from the host system 11. For example, the host system 11 can be a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game console, a server, or a computer system disposed in a specific carrier (such as a vehicle, an aircraft, or a ship), and the type of the host system 11 is not limited thereto. In addition, the storage device 12 can include a solid state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0016] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 can support an embedded Multi-Media Card (eMMC), a Universal Flash Storage (UFS), a Peripheral Component Interconnect Express (PCIExpress), a Non-Volatile Memory Express (NVM express), a Serial Advanced Technology Attachment (SATA), a Universal Serial Bus (USB), or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 (such as exchanging signals, instructions, and / or data) via the connection interface 121.

[0017] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more arrays of memory cells. The memory cells in the memory cell array store data in the form of a voltage (also referred to as a threshold voltage). For example, the memory module 122 may include a single-level cell (SLC) NAND flash memory module, a multi-level cell (MLC) NAND flash memory module, a triple-level cell (TLC) NAND flash memory module, a quad-level cell (QLC) NAND flash memory module, and / or other memory modules with the same or similar characteristics.

[0018] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be regarded as the control core of the storage device 12 and is used to control the storage device 12. For example, the memory controller 123 can be used to control or manage the overall or partial operation of the storage device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar devices or combinations of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0019] The memory controller 123 can send a sequence of instructions to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a sequence of write instructions to the memory module 122 to instruct the memory module 122 to store data in a specific storage unit. For example, the memory controller 123 can send a sequence of read instructions to the memory module 122 to instruct the memory module 122 to read data from a specific storage unit. For example, the memory controller 123 can send a sequence of erase instructions to the memory module 122 to instruct the memory module 122 to erase the data stored in a specific storage unit. In addition, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited in the present invention. The memory module 122 can receive the instruction sequence from the memory controller 123 and access the storage units inside the memory module 122 according to this instruction sequence.

[0020] Figure 2 is a schematic diagram of a memory controller shown according to an embodiment of the present invention. Please refer to Figure 1 and Figure 2 , the memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0021] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 can be used to control or manage the overall or partial operation of the memory controller 123. For example, the memory control circuit 23 can communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 can include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0022] In an embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and is used to cache data. For example, the buffer memory 24 can be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0023] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure the correctness of the data. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), Exclusive OR (XOR) code, etc. In one embodiment, the memory controller 123 may further include various other types of circuit modules (such as a power management circuit, etc.), which are not limited in the present invention.

[0024] Figure 3 is a schematic diagram of managing a memory module shown according to an embodiment of the present invention. Please refer to Figures 1 to 3 , the memory module 122 includes a plurality of physical units 301(1) to 301(B). Each physical unit includes a plurality of memory cells and is used to store data non-volatilely.

[0025] In one embodiment, a physical unit may include one or more physical programming units. In one embodiment, a physical erasing unit may include one or more physical programming units.

[0026] In one embodiment, a physical programming unit may include a plurality of physical sectors. For example, the data capacity of a physical sector may be 512 bytes (B), and a physical programming unit may include 32 physical sectors. However, both the data capacity of a physical sector and / or the total number of physical sectors included in a physical programming unit can be adjusted according to practical requirements, which are not limited in the present invention. In one embodiment, a physical programming unit can be regarded as a physical page. For example, the storage capacity of a physical programming unit may be 16 kilobytes, and the present invention is not limited thereto.

[0027] In one embodiment, a physical programming unit is the minimum unit for synchronously writing data in the memory module 122. For example, when performing a programming operation (also referred to as a writing operation) on a physical programming unit to write data into this physical programming unit, multiple memory cells in this physical programming unit can be synchronously programmed to store the corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to this physical programming unit to change the threshold voltage of at least some of the memory cells in this physical programming unit. For example, the threshold voltage of a memory cell can reflect the bit data stored in this memory cell.

[0028] In one embodiment, multiple entity programming units in an entity erasure unit can be synchronously erased. For example, when an erasure operation is performed on an entity erasure unit, an erasure voltage can be applied to the multiple entity programming units in this entity erasure unit to change the threshold voltages of at least some of the storage units in these entity programming units. By performing an erasure operation on an entity erasure unit, the data stored in this entity erasure unit can be cleared. In one embodiment, an entity erasure unit can be regarded as an entity block.

[0029] In one embodiment, the memory control circuit 23 can logically associate the entity units 301(1) to 301(A) and 301(A + 1) to 301(B) with the data area 31 and the idle area 32 respectively. The entity units 301(1) to 301(A) in the data area 31 all store data (also known as user data) from the host system 11. For example, any one of the entity units in the data area 31 can store valid data and / or invalid data. In addition, the entity units 301(A + 1) - 301(B) in the idle area 32 do not store data (such as valid data).

[0030] In one embodiment, if a certain entity unit does not store valid data, this entity unit can be associated with the idle area 32. In addition, the entity units in the idle area 32 can be erased to clear the data in these entity units. In one embodiment, the entity units in the idle area 32 are also called idle entity units. In one embodiment, the idle area 32 is also called a free pool.

[0031] In one embodiment, when data is to be stored, the memory control circuit 23 can select one or more entity units from the idle area 32 and instruct the memory module 122 to store the data in the selected entity units. After storing the data in this entity unit, this entity unit can be associated with the data area 31. In other words, one or more entity units can be alternately used between the data area 31 and the idle area 32.

[0032] In one embodiment, the memory control circuit 23 can configure multiple logic units 302(1) to 302(C) to map the entity units (i.e., entity units 301(1) to 301(A)) in the data area 31. For example, one logic unit can correspond to one logical block address (LBA) or other logical management units. One logic unit can be mapped to one or more entity units.

[0033] In one embodiment, if a certain physical unit is currently mapped by any logical unit, the memory control circuit 23 may determine that the data currently stored in this physical unit includes valid data. Conversely, if a certain physical unit is not currently mapped by any logical unit, the memory control circuit 23 may determine that this physical unit does not currently store any valid data.

[0034] In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical unit and the physical unit in at least one management table (also referred to as the logical-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing, or erasing according to the information in this management table (i.e., the logical-to-physical mapping table).

[0035] In one embodiment, the memory control circuit 23 may detect a data access event. The data access event indicates accessing specific data (also referred to as target data). For example, the data access event can be used to indicate storing the target data into the memory module 122, or reading the target data from the memory module 122.

[0036] In one embodiment, if the data access event is a data write event for the target data, then the data access event can be used to indicate storing the target data into the memory module 122. Or, in one embodiment, if the data access event is a data read event for the target data, then the data access event can be used to indicate reading the target data from the memory module 122.

[0037] In one embodiment, in response to the data access event, the memory control circuit 23 may dynamically generate check information (also referred to as first check information) at a certain verification location (also referred to as the first verification location) inside the storage device 12 according to the target data and the logical unit information corresponding to the target data (also referred to as the first logical unit information). For example, the first logical unit information may reflect the logical unit to which the target data belongs (such as Figure 3 at least one of the logical units 302(1)~302(C)).

[0038] In one embodiment, at the first verification location, the memory control circuit 23 may perform a logical operation (also referred to as the first logical operation) on the target data and the first logical unit information to obtain the first check information. Or, from another perspective, the first check information may reflect the operation result (also referred to as the first operation result) of performing the first logical operation on the target data and the first logical unit information.

[0039] In one embodiment, the first check information includes a Cyclic Redundancy Check (CRC) code. For example, in the first logical operation, the memory control circuit 23 may input the target data and the first logical unit information into the generation algorithm of the cyclic redundancy check code to dynamically generate the first check information.

[0040] Subsequently, the first check information can be used to verify the integrity of at least one of the target data and the logical unit information corresponding to the target data (such as the first logical unit information). In one embodiment, the first check information may further include other types of check information, as long as it conforms to the relevant descriptions of the embodiments of the present invention.

[0041] In one embodiment, in response to the data access event, the memory control circuit 23 may also dynamically generate another check information (also referred to as the second check information) at another verification location (also referred to as the second verification location) inside the storage device 12 according to the target data and another logical unit information corresponding to the target data (also known as the second logical unit information). It should be noted that the second verification location must be different from the first verification location.

[0042] In one embodiment, at the second verification location, the memory control circuit 23 may perform a logical operation (also referred to as the second logical operation) on the target data and the second logical unit information to obtain the second check information. Or, from another perspective, the second check information may reflect the operation result (also referred to as the second operation result) of performing the second logical operation on the target data and the second logical unit information.

[0043] In one embodiment, the second check information also includes a Cyclic Redundancy Check (CRC) code. For example, in the second logical operation, the memory control circuit 23 may input the target data and the second logical unit information into the generation algorithm of the cyclic redundancy check code to dynamically generate the second check information. Subsequently, the second check information can be used to verify the integrity of at least one of the target data and the logical unit information corresponding to the target data (such as the second logical unit information). It should be noted that in one embodiment, the second check information may further include other types of check information, as long as it conforms to the relevant descriptions of the embodiments of the present invention.

[0044] In one embodiment, the storage device 12 may include multiple controllers. For example, the storage device 12 may include a first controller and a second controller. The first controller can be used to communicate with the host system 11.

[0045] For example, the first controller can be used to parse instructions or signals from the host system 11 and can be used to transmit data to the host system 11. The second controller can be used to control the memory module 122. For example, the second controller can be used to control the access operation of the storage device 12 to the memory module 122. For example, the access operation includes a read operation, a write operation, an erase operation, or other operations, which are not limited in the present invention.

[0046] In one embodiment, the first verification location is located in the first controller, and the second verification location is located in the second controller. That is, the first check information is dynamically generated by the first controller according to the target data and the first logical unit information. In addition, the second check information is dynamically generated by the second controller according to the target data and the second logical unit information.

[0047] In one embodiment, the first controller and the second controller can be synchronously included in Figure 2 the memory control circuit 23. In one embodiment, the first controller is also referred to as the host controller, and / or the second controller is also referred to as the storage controller. In one embodiment, at least one of the first controller and the second controller can also be independent of Figure 2 the memory control circuit 23.

[0048] In one embodiment, after obtaining the first check information and the second check information, the memory control circuit 23 can perform a verification operation according to the first check information and the second check information to obtain a verification result. For example, this verification result can reflect the operation result of the verification operation. Then, the memory control circuit 23 can perform an operation corresponding to the foregoing data access event according to the verification result.

[0049] In one embodiment, the verification operation is used to confirm whether the first check information is the same as the second check information. For example, the memory control circuit 23 can compare the first check information and the second check information to obtain the verification result. For example, the verification result can reflect whether the first check information is the same as the second check information.

[0050] In one embodiment, if the verification result is that the first check information is the same as the second check information, the memory control circuit 23 can determine that the verification result is a specific result (also referred to as the first result). In other words, the first result can reflect that the first check information is the same as the second check information.

[0051] In one embodiment, if the verification result is that the first check information is different from the second check information, the memory control circuit 23 can determine that the verification result is another result (also referred to as the second result). In other words, the second result can reflect that the first check information is different from the second check information.

[0052] In one embodiment, the first verification information being the same as the second verification information may mean that the cyclic redundancy check (CRC) code in the first verification information is the same as the cyclic redundancy check (CRC) code in the second verification information. In one embodiment, the first verification information being different from the second verification information may mean that the cyclic redundancy check (CRC) code in the first verification information is different from the cyclic redundancy check (CRC) code in the second verification information.

[0053] In one embodiment, the verification operation can also be used to confirm whether the first verification information and the second verification information meet specific conditions. For example, in one embodiment, if the first verification information and the second verification information meet specific conditions, the memory control circuit 23 may determine that the verification result is the first result. Or, in one embodiment, if the first verification information and the second verification information do not meet specific conditions, the memory control circuit 23 may determine that the verification result is the second result.

[0054] In one embodiment, the first verification information and the second verification information meeting specific conditions may mean that after substituting the first verification information and the second verification information into a specific algorithm, the output of this specific algorithm meets the expectation. In one embodiment, the first verification information and the second verification information not meeting specific conditions may mean that after substituting the first verification information and the second verification information into a specific algorithm, the output of this specific algorithm does not meet the expectation.

[0055] In one embodiment, according to the verification result, the memory control circuit 23 may perform a preset operation corresponding to the data access event, or perform error handling corresponding to the foregoing data access event.

[0056] In one embodiment, if the data access event is a data write event for target data and the verification result is the first result, the memory control circuit 23 may write the target data and the second logical unit information into the memory module 122 to respond to the write instruction from the host system 11.

[0057] Or, if the data access event is a data write event for target data and the verification result is the second result, the memory control circuit 23 may perform error handling corresponding to the write instruction. For example, in the error handling corresponding to the write instruction, the memory control circuit 23 may send an error message to the host system 11 to notify the host system 11 that the write of the target data has failed.

[0058] In one embodiment, if the data access event is a data read event for target data and the verification result is the first result, the memory control circuit 23 may transmit the target data read from the memory module 122 to the host system 11 to respond to the read instruction from the host system 11.

[0059] Alternatively, if the data access event is a data read event for target data and the verification result is the second result, the memory control circuit 23 may perform error handling corresponding to the read instruction. For example, in the error handling corresponding to the read instruction, the memory control circuit 23 may send an error message to the host system 11 to notify the host system 11 that the read of the target data has failed. In addition, the implementation details of the foregoing error handling can all be adjusted according to practical requirements.

[0060] The following will use multiple embodiments to separately describe the operation behaviors respectively performed by the first controller and the second controller in the memory control circuit 23 when the data access event is a data write event or a data read event for target data.

[0061] Figure 4 is a schematic diagram of a memory control circuit including a first controller and a second controller shown according to an embodiment of the present invention. Please refer to Figure 4 , assuming that the memory control circuit 23 includes a controller 41 (i.e., the first controller or also called the host controller) and a controller 42 (i.e., the second controller or also called the storage controller). The controller 41 can be used to communicate with the host system 11. The controller 42 can be used to control the memory module 122. In addition, both the controller 41 and 42 can access the buffer memory 24. For example, both the controller 41 and 42 can cache data into the buffer memory 24 or read data from the buffer memory 24.

[0062] In one embodiment, the first verification location is in the controller 41, and the second verification location is in the controller 42. In this case, the first check information is dynamically generated by the controller 41 according to the target data and the first logical unit information. In addition, the second check information is dynamically generated by the controller 42 according to the target data and the second logical unit information.

[0063] Thus, through the method provided by the above embodiment: the first check information and the second check information are calculated based on the target data and the first logical unit information / second logical unit information, and the first check information and the second check information are used for security verification. While ensuring the accuracy of the target data transmission and improving the reliability of the data transmission, it can also ensure the correctness of the logical address and ensure the correspondence between the target data written into the storage device and the logical address.

[0064] In one embodiment, the first verification location is in the controller 42, and the second verification location is in the controller 41. In this case, the first check information is dynamically generated by the controller 42 according to the target data and the first logical unit information. In addition, the second check information is dynamically generated by the controller 41 according to the target data and the second logical unit information.

[0065] Figure 5 With Figure 6 is a schematic diagram of an operation scenario for a data write event shown according to an embodiment of the present invention. Please refer to Figure 5 , after obtaining the write instruction 51 corresponding to the data write event from the host system 11, the controller 41 can obtain the data 52 (i.e., the target data) and the logical unit information 53 (i.e., the first logical unit information) from the write instruction 51. For example, assuming that the logical unit information 53 reflects logical unit A, the write instruction 51 can be used to indicate storing the data 52 belonging to logical unit A.

[0066] After obtaining the data 52 and the logical unit information 53, the controller 41 can perform a logical operation 54 (i.e., the first logical operation) on the data 52 and the logical unit information 53 to dynamically generate the check information 55 (i.e., the first check information). The controller 41 can store the data 52 and the dynamically generated check information 55 in the buffer memory 24. In addition, the controller 41 can transmit the logical unit information 53 to the controller 42 as Figure 6 the logical unit information 61 (i.e., the second logical unit information) in

[0067] Please refer to Figure 6 , continuing with the embodiment in Figure 5 , the controller 42 can obtain the logical unit information 61 according to the logical unit information 53 from the controller 41. In particular, the information content of the logical unit information 61 can be the same as or different from the information content of the logical unit information 53.

[0068] For example, in an ideal situation, the information content of the logical unit information 61 would be the same as the information content of the logical unit information 53. However, in a real situation, affected by channel noise, the information content of the logical unit information 61 may be different from the information content of the logical unit information 53. If the information content of the logical unit information 61 is different from the information content of the logical unit information 53, subsequent access behaviors (such as the write operation 66) performed on the memory module 122 based on the logical unit information 61 may result in a failed execution or incorrect data being stored.

[0069] In an embodiment, the controller 42 can read the data 52 and the check information 55 from the buffer memory 24. The controller 42 can perform a logical operation 62 (i.e., the second logical operation) on the logical unit information 61 and the data 52 to dynamically generate the check information 63 (i.e., the second check information). After generating the check information 63, the controller 42 can perform a verification operation 64 according to the check information 55 and the check information 63 to obtain the verification result 65.

[0070] In one embodiment, if the verification result 65 is the first result (e.g., the check information 55 is the same as the check information 63), the controller 42 may perform a write operation 66 in response to the write instruction 51. For example, in the write operation 66, the controller 42 may write the data 52 and the logical unit information 61 to the memory module 122.

[0071] However, in one embodiment, if the verification result 65 is the second result (e.g., the check information 55 is different from the check information 63), the controller 41 may perform an error handling 67 corresponding to the write instruction 51. For example, in the error handling 67, the controller 41 may send an error message to the host system 11 to notify the host system 11 that the write of the data 52 fails. Thus, it can be ensured that the data (e.g., the data 52) finally written to the memory module 122 is indeed the data required by the write instruction 51, thereby effectively improving the operation stability of the storage device 12.

[0072] Figures 7 to 9 is a schematic diagram of an operation scenario for a data read event shown according to an embodiment of the present invention. Please refer to Figure 7 , after obtaining the read instruction 71 corresponding to the data read event from the host system 11, the controller 41 may obtain the logical unit information 72 (i.e., the first logical unit information) from the read instruction 71. For example, assuming that the logical unit information 72 reflects logical unit B, the read instruction 71 can be used to indicate reading the data belonging to logical unit B.

[0073] After obtaining the logical unit information 72, the controller 41 may obtain the physical unit information 73 corresponding to the logical unit information 72. For example, the physical unit information 73 reflects physical unit C, and logical unit B is mapped to physical unit C. For example, the controller 41 may query a management table (e.g., a logical-to-physical mapping table) according to the logical unit information 72 to obtain the physical unit information 73. Then, the controller 41 may send the physical unit information 73 to the controller 42.

[0074] Please refer to Figure 8 , continuing with the Figure 7 embodiment, after obtaining the physical unit information 73, the controller 42 may access the memory module 122 according to the physical unit information 73 to obtain the data 81 (i.e., the target data) and the logical unit information 82 (i.e., the second logical unit information) from the memory module 122. The logical unit information 82 may reflect the logical unit to which the data 81 belongs. In particular, the information content of the logical unit information 82 may be the same as or different from the information content of the logical unit information 72.

[0075] For example, in an ideal situation, the information content of the logical unit information 82 would be the same as the information content of the logical unit information 72. However, in a real - world situation, affected by channel noise, the information content of the logical unit information 82 may be different from the information content of the logical unit information 72. If the information content of the logical unit information 82 is different from the information content of the logical unit information 72, then there is a high probability that the currently read data 81 is not the data that the read instruction 71 actually instructs to read. Therefore, when the information content of the logical unit information 82 is different from the information content of the logical unit information 72, if the data 81 is transmitted to the host system 11, a data read error may occur.

[0076] In one embodiment, after reading the data 81 and the logical unit information 82 from the memory module 122, the controller 42 may perform a logical operation 83 (i.e., the second logical operation) on the data 81 and the logical unit information 82 to dynamically generate check information 84 (i.e., the second check information). The controller 41 may store the data 81 and the dynamically generated check information 84 in the buffer memory 24.

[0077] Please refer to Figure 9 , continuing with the embodiment in Figure 8 The controller 41 may obtain the data 81 and the dynamically generated check information 84 from the buffer memory 24. The controller 41 may perform a logical operation 91 (i.e., the first logical operation) on the logical unit information 72 and the data 81 to dynamically generate check information 92 (i.e., the first check information). After generating the check information 92, the controller 41 may perform a verification operation 93 based on the check information 92 and the check information 84 to obtain a verification result 94.

[0078] In one embodiment, if the verification result 94 is a first result (e.g., the check information 92 is the same as the check information 84), the controller 42 may perform a transmission operation 95 to respond to the read instruction 71. For example, in the transmission operation 95, the controller 41 may transmit the data 81 to the host system 11 to respond to the read instruction 71. However, in one embodiment, if the verification result 94 is a second result (e.g., the check information 92 is different from the check information 84), the controller 41 may perform an error handling 96 corresponding to the write instruction 71. For example, in the error handling 96, the controller 41 may send an error message to the host system 11 to notify the host system 11 that the reading of the data 81 has failed. Thus, it can be ensured that the data (e.g., the data 81) finally returned to the host system 11 is indeed the data required by the read instruction 71, thereby effectively improving the operation stability of the storage device 12.

[0079] Figure 10 is a flowchart of a data access method according to an embodiment of the present invention. Please refer to Figure 10, in step S1001, in response to a data access event, according to the target data and the first logical unit information corresponding to the target data, first check information is generated at a first verification location inside the storage device, where the data access event indicates storing the target data to a memory module or reading the target data from the memory module.

[0080] In step S1002, according to the target data and the second logical unit information corresponding to the target data, second check information is generated at a second verification location inside the storage device, where the second verification location is different from the first verification location.

[0081] In step S1003, according to the first check information and the second check information, a verification operation is performed to obtain a verification result.

[0082] In step S1004, according to the verification result, an operation corresponding to the data access event is performed.

[0083] However, Figure 10 the steps have been described in detail above and will not be elaborated here. It should be noted that, Figure 10 the steps can be implemented as multiple pieces of program code or circuits, and the present invention does not limit this. In addition, Figure 10 the method of can be used in combination with the above exemplary embodiments or used alone, and the present invention does not limit this.

[0084] In summary, the data access method and storage device proposed by the embodiments of the present invention can allow the execution of corresponding access operations only on the premise of ensuring that the logical unit information used by the storage device is consistent with the logical unit information indicated by the host system. Thus, it is possible to reduce end-to-end access errors (i.e., error detection or error correction not simply for user data) caused by the inconsistency between the logical unit information used by the storage device and the logical unit information indicated by the host system, thereby improving the operation stability of the storage device.

[0085] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data access method, characterized in that, For a storage device, wherein the storage device is connected to a host system, the storage device includes a memory module, and the data access method includes: In response to a data access event, according to target data and first logical unit information corresponding to the target data, generate first check information at a first verification location inside the storage device, wherein the data access event indicates storing the target data into the memory module or reading the target data from the memory module; According to the target data and second logical unit information corresponding to the target data, generate second check information at a second verification location inside the storage device, wherein the second verification location is different from the first verification location; According to the first check information and the second check information, perform a verification operation to obtain a verification result; and According to the verification result, perform an operation corresponding to the data access event.

2. The data access method according to claim 1, wherein the storage device includes a first controller and a second controller, the first verification location is located in the first controller, the second verification location is located in the second controller, the first controller is communicatively connected to the host system, and the second controller is used to control the memory module.

3. The data access method according to claim 1, wherein the first check information reflects a first operation result of performing a first logical operation on the target data and the first logical unit information, and the second check information reflects a second operation result of performing a second logical operation on the target data and the second logical unit information.

4. The data access method according to claim 1, wherein both the first check information and the second check information include cyclic redundancy check codes.

5. The data access method according to claim 1, wherein the verification operation is used to confirm whether the first check information is the same as the second check information.

6. The data access method according to claim 1, wherein the step of performing the verification operation according to the first check information and the second check information to obtain the verification result includes: Compare the first check information and the second check information to obtain the verification result.

7. The data access method according to claim 1, further includes: If the data access event is a data write event for the target data, obtain the first logical unit information from a write instruction corresponding to the data write event by a first controller inside the storage device; And Transmit the first logical unit information from the first controller to a second controller inside the storage device as the second logical unit information.

8. The data access method according to claim 7, wherein performing the operation corresponding to the data access event according to the verification result includes: If the verification result is a first result, write the target data and the second logical unit information into the memory module to respond to the write instruction; And If the verification result is the second result, perform error handling corresponding to the write instruction.

9. The data access method according to claim 1, further comprising: If the data access event is a data read event for the target data, obtain the first logical unit information from the read instruction corresponding to the data read event by a first controller inside the storage device; Obtain physical unit information corresponding to the first logical unit information by the first controller; and Obtain the target data and the second logical unit information from the memory module by a second controller inside the storage device according to the physical unit information.

10. The data access method according to claim 9, wherein performing the operation corresponding to the data access event according to the verification result includes: If the verification result is the first result, transmit the target data to the host system to respond to the read instruction; and If the verification result is the second result, perform error handling corresponding to the read instruction.

11. A storage device, characterized in that, Comprising: A connection interface for connecting to a host system; A memory module; and A memory controller connected to the connection interface and the memory module, wherein the memory controller is configured to: In response to a data access event, generate first check information at a first verification location inside the storage device according to the target data and the first logical unit information corresponding to the target data, wherein the data access event indicates storing the target data to the memory module or reading the target data from the memory module; Generate second check information at a second verification location inside the storage device according to the target data and the second logical unit information corresponding to the target data, wherein the second verification location is different from the first verification location; Perform a verification operation according to the first check information and the second check information to obtain a verification result; and Perform an operation corresponding to the data access event according to the verification result.

12. The storage device according to claim 11, wherein the memory controller includes a first controller and a second controller, the first verification location is located in the first controller, the second verification location is located in the second controller, the first controller is used for communicating with the host system, and the second controller is used for controlling the memory module.

13. The storage device according to claim 11, wherein the first check information reflects a first operation result of performing a first logical operation on the target data and the first logical unit information, and the second check information reflects a second operation result of performing a second logical operation on the target data and the second logical unit information.

14. The storage device according to claim 11, wherein both the first check information and the second check information include cyclic redundancy check codes.

15. The storage device according to claim 11, wherein the verification operation is used to confirm whether the first check information is the same as the second check information.

16. The storage device according to claim 11, wherein the operation for the memory controller to perform the verification operation according to the first check information and the second check information to obtain the verification result includes: Comparing the first check information and the second check information to obtain the verification result.

17. The storage device according to claim 11, wherein the memory controller is further configured to: If the data access event is a data write event for the target data, a first controller inside the memory controller obtains the first logical unit information from a write instruction corresponding to the data write event; and The first controller transmits the first logical unit information to a second controller inside the memory controller as the second logical unit information.

18. The storage device according to claim 17, wherein according to the verification result, the operation corresponding to the data access event includes: If the verification result is a first result, writing the target data and the second logical unit information into the memory module to respond to the write instruction; And If the verification result is a second result, performing error handling corresponding to the write instruction.

19. The storage device according to claim 11, wherein the memory controller is further configured to: If the data access event is a data read event for the target data, a first controller inside the storage device obtains the first logical unit information from a read instruction corresponding to the data read event; The first controller obtains physical unit information corresponding to the first logical unit information; and A second controller inside the storage device obtains the target data and the second logical unit information from the memory module according to the physical unit information.

20. The storage device according to claim 19, wherein the memory controller performs the operation corresponding to the data access event according to the verification result includes: If the verification result is a first result, transmitting the target data to the host system to respond to the read instruction; And If the verification result is a second result, performing error handling corresponding to the read instruction.

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