Program slice generation method and device and electronic equipment

Abstract

The invention discloses a program slice generation method and device and electronic equipment, and relates to the technical field of load modeling. And the electronic equipment only compensates the memory access instruction which affects the execution correctness of the instruction stream data, so that the data stored in the memory access address with data abrupt change is recovered. Due to the fact that the electronic equipment does not need to compensate any instruction, the compensation instruction and the corresponding jump instruction of the instruction stream in the program slice generated by the electronic equipment are reduced, the execution frequency of the compensation instruction is reduced, and on the basis that the execution correctness of the instruction stream is guaranteed, the difference between the program slice and the original application program is reduced.

Description

Technical Field

[0001] This application relates to the technical field of load modeling, and in particular, to a method, device, and electronic device for generating program slices. Background Art

[0002] With the development of big data, artificial intelligence (AI), and cloud computing technologies, related application programs have been continuously developed. As the problems that application programs can solve increase, the code volume of application programs becomes larger and larger, increasing the difficulty of developing and analyzing application programs. During the development process of an application program, the program is sliced to obtain subprograms. The slice has the characteristics of a small instruction scale and similarity to the original business behavior. By running the slice instead of the original business, it can assist in improving the efficiency of chip design and development. During the process of generating a program slice, instructions with data mutations are detected; during the running process of the program slice, if any instruction with a data mutation is detected, it is replaced with a jump instruction and jumps to a compensation instruction preset in the program slice. After restoring the mutated data at the specified address, the original instruction is executed. However, when the number of executions of the compensation instruction is too large, the compensation instruction accounts for a relatively high proportion in the entire program slice, resulting in a completely inconsistent instruction flow between the program slice and the original business, and a large difference between the program slice and the original application program. Summary of the Invention

[0003] This application provides a method, device, and electronic device for generating program slices, which reduces the difference between the program slice and the original application program while ensuring the correctness of the execution of the instruction flow.

[0004] This application adopts the following technical solutions.

[0005] In a first aspect, this application provides a method for generating a program slice. The generation method can be applied to an electronic device or a component in an electronic device. The generation method includes: obtaining a slice request, and obtaining instruction flow data corresponding to the slice request in the application program according to the slice request. The instruction flow data includes multiple instructions in the application program. And, generating a program slice according to the multiple instructions and the mutated memory access instructions among the multiple instructions. The mutated memory access instructions include: memory access instructions that affect the execution correctness of the instruction flow data. The program slice includes: the instruction flow data and a compensation instruction for the mutated memory access instruction. The compensation instruction is used to: restore the data corresponding to the memory access address indicated by the mutated memory access instruction to the data expected to be accessed by the mutated memory access instruction.

[0006] In this application, the electronic device only compensates the memory access instructions that affect the execution correctness of the instruction stream data, so as to restore the data stored at the memory access address where the data mutation occurs. Since the electronic device does not need to compensate any instruction, the number of compensation instructions and the corresponding jump instructions in the instruction stream of the program slice generated by the electronic device is reduced, and the number of executions of the compensation instructions is reduced. On the basis of ensuring the execution correctness of the instruction stream, the difference between the program slice and the original application program is reduced.

[0007] In an alternative implementation, before the above-mentioned electronic device generates a program slice according to multiple instructions and the mutated memory access instructions among the multiple instructions, the generation method provided in this application further includes: The electronic device determines a first instruction of the memory access instruction type from the multiple instructions, and determines whether the first memory access address in the first instruction is stored in the memory analysis table. The memory analysis table includes: multiple memory access addresses, and the data expected to be accessed by each memory access address among the multiple memory access addresses. If the first memory access address is stored in the memory analysis table, and the data stored at the first memory access address is inconsistent with the data expected to be accessed by the first instruction stored in the memory analysis table, the electronic device determines the first instruction as a mutated memory access instruction.

[0008] In this application, when the data stored at the memory access address in the memory access instruction is inconsistent with the data expected to be accessed by the memory access instruction, the electronic device determines the memory access instruction as a mutated memory access instruction. Since the generated program slice only compensates the memory access instructions that affect the execution correctness of the instruction stream data, the number of executions of the compensation instructions is reduced. On the basis of ensuring the execution correctness of the instruction stream, the difference between the program slice and the original application program is reduced.

[0009] In an alternative implementation, before the electronic device generates a program slice, the generation method provided in this application further includes: The electronic device determines a second instruction of the memory access instruction type from the multiple instructions, and determines whether the second memory access address in the second instruction is stored in the memory analysis table; The memory analysis table includes: multiple memory access addresses, and the data expected to be accessed by each memory access address among the multiple memory access addresses. If the second memory access address is not stored in the memory analysis table, the electronic device creates an entry for the second instruction in the memory analysis table. The entry includes: the second memory access address and the data stored in the storage space corresponding to the second memory access address.

[0010] In this application, the electronic device can update the memory access addresses not stored in the memory analysis table and the data corresponding to the memory access addresses, so that in the subsequent analysis process of the instruction stream data, the electronic device can also analyze the data expected to be accessed by different memory access instructions including different memory access addresses according to the updated memory analysis table, avoiding the problem of reduced accuracy of the mutated memory access instructions caused by the fact that the memory analysis table does not contain all the data expected to be accessed in the instruction stream data, which is beneficial to reducing the difference between the program slice and the original application program on the basis of ensuring the correct execution of the instruction stream.

[0011] In an alternative implementation, the electronic device generates a program slice according to multiple instructions and the mutated memory access instructions in the multiple instructions, including: the electronic device obtains the memory address table and the memory access instruction table of the instruction stream data; wherein, the memory address table includes: the memory access addresses that affect the correct execution of the instruction stream data. The memory access instruction table is used to record: the instruction addresses of the mutated memory access instructions in the multiple instructions, the execution times of each memory access address where the data mutates, and the memory access data. The electronic device updates the memory access instruction table according to the memory address table to obtain the updated memory access instruction table, and there are no duplicate memory access addresses between the updated memory access instruction table and the memory address table. The electronic device obtains the compensation instructions for all the memory access addresses in the updated memory access instruction table, and generates a program slice according to the instruction stream data and the compensation instructions for all the memory access addresses.

[0012] In this application, the electronic device records the memory access addresses that affect the correct execution of the instruction stream data through the memory address table, and updates the memory access instruction table according to the memory address table, so that there are no duplicate memory access addresses between the updated memory access instruction table and the memory address table, that is: the electronic device removes the memory access instructions that do not affect the correct execution of the instruction stream data from the memory access instruction table. Thus, in the process of the electronic device obtaining the compensation instructions for the mutated memory access instructions, only the mutated memory access instructions in the memory access instruction table are compensated, which is beneficial to further reducing the compensation instructions and the corresponding jump instructions of the instruction stream in the program slice generated by the electronic device, reducing the execution times of the compensation instructions during the running of the program slice, and reducing the difference between the program slice and the original application program on the basis of ensuring the correct execution of the instruction stream.

[0013] In an alternative implementation, the above-mentioned memory access addresses that affect the correct execution of the instruction stream data include one or both of the following: the memory access address where the data mutation will affect the control flow of the instruction stream data, and the memory access address of the mutated register, where the mutated register is: the register whose value mutation will affect the correct execution of the instruction stream data.

[0014] In an alternative implementation, after the electronic device determines that the first instruction is a mutated memory access instruction, the generation method provided in this application further includes: the electronic device writes the first instruction and the first memory access address into a memory access instruction table, which is used to record: the instruction addresses of the mutated memory access instructions among multiple instructions, the execution times of the memory access addresses for each data mutation, and the memory access data. During the process of the electronic device obtaining the compensation instruction for the mutated memory access instruction, only the mutated memory access instructions in the memory access instruction table are compensated, which helps to reduce the compensation instructions and the corresponding jump instructions in the instruction stream of the program slice generated by the electronic device, reduces the execution times of the compensation instructions during the running process of the program slice, and reduces the differences between the program slice and the original application program while ensuring the execution correctness of the instruction stream.

[0015] In an alternative implementation, the electronic device obtains a memory address table of the instruction stream data, including: the electronic device initializes the memory dependency tables of all registers, where the memory dependency table is used to record: the addresses on which the memory access address or the value of the register depends. All these registers include: input registers, output registers, and other registers. And, the electronic device reads the third instruction in the instruction stream data.

[0016] In a feasible example, if the third instruction is a memory access instruction, the electronic device obtains the third memory access address in the third instruction and determines the output register associated with the third memory access address. And, the electronic device assigns the memory dependency table of the third memory access address to the memory dependency table of the output register associated with the third memory access address, and writes all the addresses in the memory dependency table of the third memory access address into the memory address table.

[0017] In another feasible example, if the third instruction is a calculation instruction, the electronic device determines the input register and the output register associated with the third instruction from all the registers. And, the electronic device clears the value of the output register associated with the third instruction, and assigns the memory dependency table of the input register associated with the third instruction to the memory dependency table of the output register associated with the third instruction.

[0018] In an alternative implementation, the above slice request carries an instruction start identifier and an instruction end identifier. The electronic device obtains the instruction stream data corresponding to the slice request in the application program, including: the electronic device determines the fourth instruction in the application program according to the instruction start identifier in the slice request, and, determines the fifth instruction in the application program according to the instruction end identifier in the slice request. The electronic device obtains the instruction stream data in the application program with the fourth instruction as the start instruction and the fifth instruction as the end instruction, and the multiple instructions in the instruction stream data include the aforementioned fourth instruction and fifth instruction.

[0019] In an alternative implementation, the above-mentioned multiple instructions include one or a combination of the following: computational instructions, memory access instructions, branch jump instructions, termination instructions, and irrelevant instructions.

[0020] In a second aspect, the present application provides a program slice generation device. The generation device is applied to an electronic device or a component in an electronic device, and the generation device includes a software module or unit that executes the method of the first aspect or any alternative implementation manner in the first aspect.

[0021] Exemplarily, the program slice generation device includes: a first acquisition module, a second acquisition module, and an instruction assembly module. The first acquisition module is configured to acquire a slice request. The second acquisition module is configured to acquire instruction stream data corresponding to the slice request in the application program according to the slice request, and the instruction stream data includes multiple instructions in the application program. The instruction assembly module is configured to generate a program slice according to the multiple instructions and the mutated memory access instructions among the multiple instructions. The mutated memory access instructions include: memory access instructions that affect the execution correctness of the instruction stream data, and the program slice includes: the instruction stream data and compensation instructions for the mutated memory access instructions, and the compensation instructions are used to: restore the data corresponding to the memory access address indicated by the mutated memory access instruction to the data expected to be accessed by the mutated memory access instruction.

[0022] Optionally, the generation device provided in the present application further includes: an instruction processing module, configured to: determine a first instruction of the memory access instruction type from the multiple instructions. Determine whether the first memory access address in the first instruction is stored in the memory analysis table, and the memory analysis table includes: multiple memory access addresses, and data expected to be accessed by each memory access address among the multiple memory access addresses. If the first memory access address is stored in the memory analysis table and the data stored at the first memory access address is inconsistent with the data expected to be accessed by the first instruction stored in the memory analysis table, then determine that the first instruction is a mutated memory access instruction.

[0023] Optionally, the above-mentioned instruction processing module is further configured to: determine a second instruction of the memory access instruction type from the multiple instructions. Determine whether the second memory access address in the second instruction is stored in the memory analysis table, and the memory analysis table includes: multiple memory access addresses, and data expected to be accessed by each memory access address among the multiple memory access addresses. If the second memory access address is not stored in the memory analysis table, create an entry for the second instruction in the memory analysis table, and the entry includes: the second memory access address and the data stored in the storage space corresponding to the second memory access address.

[0024] Optionally, the instruction assembly module is specifically configured to: obtain the memory address table and the memory access instruction table of the instruction stream data. The memory address table includes: the memory access addresses that affect the execution correctness of the instruction stream data. The memory access instruction table is used to record: the instruction addresses of the mutated memory access instructions in multiple instructions, the execution times of the memory access addresses of each data mutation, and the memory access data. The instruction assembly module is further specifically configured to: update the memory access instruction table according to the memory address table to obtain an updated memory access instruction table. There are no duplicate memory access addresses between the updated memory access instruction table and the memory address table. The instruction assembly module is specifically configured to: obtain the compensation instructions for all memory access addresses in the updated memory access instruction table, and generate a program slice according to the instruction stream data and the compensation instructions for all memory access addresses.

[0025] Optionally, the memory access addresses that affect the execution correctness of the instruction stream data include one or both of the following: the memory access addresses where data mutation affects the control flow of the instruction stream data, and the memory access addresses of the mutated registers, where the mutated registers are: the registers whose values mutate and affect the execution correctness of the instruction stream data.

[0026] Optionally, the instruction processing module is further configured to: write the first instruction and the first memory access address into the memory access instruction table, and the memory access instruction table is used to record: the instruction addresses of the mutated memory access instructions in multiple instructions, the execution times of the memory access addresses of each data mutation, and the memory access data.

[0027] Optionally, the instruction assembly module is specifically configured to: initialize the memory dependency table of all registers, and the memory dependency table is used to record: the addresses on which the memory access addresses or the register values depend. All registers include: input registers, output registers, and other registers. The instruction assembly module is further specifically configured to: read the third instruction in the instruction stream data, if the third instruction is a memory access instruction, obtain the third memory access address in the third instruction, and determine the output register associated with the third memory access address. The instruction assembly module is further specifically configured to: assign the memory dependency table of the third memory access address to the memory dependency table of the output register associated with the third memory access address, and write all the addresses in the memory dependency table of the third memory access address into the memory address table.

[0028] Optionally, the instruction assembly module is further specifically configured to: if the third instruction is a calculation instruction, determine the input register and the output register associated with the third instruction from all registers. Clear the value of the output register associated with the third instruction, and assign the memory dependency table of the input register associated with the third instruction to the memory dependency table of the output register associated with the third instruction.

[0029] In a third aspect, the present application provides an electronic device. The electronic device includes a memory, a processor, and a computer program stored in the memory. When the processor executes the computer program, the steps of the method of the first aspect or any optional implementation of the first aspect are implemented.

[0030] In a fourth aspect, the present application provides a computer-readable storage medium storing a computer program / instruction, which, when executed by a processor, implements the steps of the method of the first aspect or any optional implementation of the first aspect.

[0031] In a fifth aspect, the present application provides a computer program product, which includes a computer program / instructions, and when the computer program / instructions are executed by a processor, implements the steps of the method of the first aspect or any optional implementation of the first aspect.

[0032] Regarding the beneficial effects of the technical solutions provided in aspects 2 to 5, reference may be made to the description of aspect 1 or any optional implementation of aspect 1, and no further description is given here. Based on the implementations provided in the above aspects, this application can also be further combined to provide more implementations. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of the structure of an application development system provided for this application;

[0034] Figure 2 A schematic diagram of the program slicing and testing architecture provided by this application;

[0035] Figure 3 A schematic diagram of a method for generating program slices provided in this application Figure 1 ;

[0036] Figure 4 A schematic diagram of a method for generating program slices provided in this application Figure 2 ;

[0037] Figure 5 A schematic diagram of a method for generating program slices provided in this application Figure 3 ;

[0038] Figure 6 A schematic diagram of a method for generating program slices provided in this application Figure 4 ;

[0039] Figure 7 A schematic diagram of updating a memory access instruction table provided by this application;

[0040] Figure 8 A schematic diagram of obtaining the memory address table provided for this application;

[0041] Figure 9 A schematic diagram of compensation for data mutation provided for this application;

[0042] Figure 10 A schematic diagram of the structure of a program slice generation device provided for this application. Specific implementation manners

[0043] This application provides a method for generating a program slice. The electronic device only compensates the memory access instructions that affect the execution correctness of the instruction stream data, so as to restore the data stored at the memory access address where data mutation occurs. Since the electronic device does not need to compensate any instruction, the compensation instructions and corresponding jump instructions in the instruction stream of the program slice generated by the electronic device are reduced, and the execution times of the compensation instructions are reduced. On the basis of ensuring the execution correctness of the instruction stream, the difference between the program slice and the original application program is reduced.

[0044] This application can be applied not only to current scenarios such as load modeling technology or application program development, but also to future scenarios such as load modeling technology or application program development. The terms used in the implementation manner part of this application are only used to explain the specific embodiments of this application, rather than aiming to limit this application. Some concepts that this application may involve will be briefly introduced below.

[0045] Binary executable file: It refers to the machine language representation form of a program, usually stored in binary form and can only be read and executed by a computer. A binary executable file refers to the final executable file generated after compiling the program source code and can be directly run on a computer.

[0046] Instruction stream: It refers to the instruction sequence during the running of a program.

[0047] Slice: It refers to identifying a characteristic interval during the execution of a program and intercepting the instruction stream and execution context (registers and memory) of this interval. The combination of the two is the program slice.

[0048] Compensation instruction: An additional instruction to maintain the correct execution of the original program instruction stream.

[0049] Application load modeling: It refers to the process of modeling and analyzing the load of an application program. Load refers to the workload generated during the running of an application program, including the number of requests, the type of requests, the size of requests, the frequency of requests, etc. Application load modeling can help developers and system administrators better understand the performance characteristics of the application program, so as to optimize the system configuration and resource allocation and improve the performance and reliability of the system.

[0050] Instruction stream trace: An instruction stream refers to the execution order of a series of instructions in a computer program. An instruction trace refers to recording the execution status of each instruction during program execution, including information such as instruction address, instruction opcode, and operands. Instruction traces can be used for program analysis, performance optimization, debugging, etc. In software such as simulators, debuggers, and performance analysis tools, instruction traces are often used to record the execution status of programs.

[0051] Program slicing is a program analysis technique that can cut out a part of the program code based on a specific input or output of the program to form a subroutine. This subroutine can be executed independently without executing the entire program. Program slicing can help programmers better understand the behavior of the program, locate errors and defects in the program, and optimize the performance of the program.

[0052] The application of workload reduction technology is one of the important means for modeling application workloads: By analyzing the instruction execution frequency using machine learning algorithms, the most representative typical intervals in the original application can be obtained. Then, through dynamic instruction instrumentation, instruction encodings, related data, and memory addresses are recorded, and finally, these instructions and data are assembled into an executable program fragment (slice).

[0053] The program slicing technique is to take the (region of interest, ROI) part of the original application program, collect the dynamic instruction execution stream (instruction stream) of the original program by running the original program, and repackage the instructions corresponding to the ROI part into a binary executable file. By executing this binary executable file, a dynamic instruction execution stream (instruction stream) consistent with the original program can be generated. For example, an electronic device can obtain multiple ROI program fragments and their corresponding weights through an interval selection algorithm, then use the slicing technique to create slices from multiple ROI program fragments, and finally use a simulator to simulate multiple ROI program fragments. According to the weights corresponding to each ROI slice, the performance of the complete application program can be fitted.

[0054] For the sake of clear and concise description of the following embodiments, first, the electronic devices applicable to this application are introduced, such as Figure 1 as shown Figure 1A structural schematic diagram of an application development system provided by this application. The application development system includes: an electronic device 110, an acceleration device 115, and a client device 120. The electronic device 110 is a common computer device. A user can input a slicing request to the electronic device 110 through the client device 120. The electronic device 110 slices the application program according to the slicing request, and the electronic device 110 also outputs the generated program slice to the client device 120. The client device 120 is a terminal device, including but not limited to a personal computer, a server, a mobile phone, a tablet computer, or a smart device, etc.

[0055] The electronic device 110 includes an input / output (I / O) interface 114, a processor 111, and a memory 112. The I / O interface 114 is used to communicate with devices located outside the electronic device 110. For example, the client device 120 inputs data and sends slices to the electronic device 110 through the I / O interface 114. After the electronic device 110 processes the input data or request, it then sends the output result of the processed data or request to the client device 120 through the I / O interface 114.

[0056] The processor 111 is the operation core and control core of the electronic device 110. It may include: a central processing unit (CPU), an application specific integrated circuit, other general purpose processors, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. In actual applications, the electronic device 110 may also include multiple processors. The processor 111 may include one or more processor cores. An operating system and other software programs are installed in the processor 111, so that the processor 111 can access the memory 112 and various Peripheral Component Interconnect express (PCIe) devices.

[0057] The processor 111 is connected to the memory 112 via a double data rate (DDR) bus or other types of buses. The memory 112 is the main memory of the electronic device 110. The memory 112 is usually used to store various running software in the operating system, input data received from the client device 120, and output results to be sent to the client device 120 in the future. To improve the access speed of the processor 111, the memory 112 needs to have the advantage of fast access speed. In traditional computer devices, dynamic random access memory (DRAM) is usually used as the memory 112. In addition to DRAM, the memory 112 can also be other random access memories, such as static random access memory (SRAM), etc. Additionally, the memory 112 can also be read only memory (ROM). For read only memory, for example, it can be programmable read only memory (PROM), erasable programmable read only memory (EPROM), etc. The number and type of the memory 112 are not limited in this embodiment.

[0058] Optionally, in order to perform persistent storage of data, a data storage system 113 is also provided in the application development system. The data storage system 113 can be located outside the electronic device 110 (as Figure 1 shown), and exchanges data with the electronic device 110 through a network. Optionally, the data storage system 113 can also be located inside the host. For example, the data storage system 113 exchanges data with the processor 111 through the bus 116. At this time, the data storage system 113 appears as a hard disk.

[0059] The acceleration device 115 is used to perform compression tasks or decompression tasks. The processor 111 sends the received AI task and input data to the acceleration device 115. After the acceleration device 115 completes the AI task according to the input data, it sends the processing result to the processor 111. As Figure 1 shown, the acceleration device 115 can be directly inserted into the card slot on the motherboard of the electronic device 110 and exchanges data with the processor 111 through the bus 116. It should be noted that Figure 1The bus 116 in it can also be replaced by a bus acceleration device 115 of a PCIe bus, a Compute Express Link (CXL), a Universal Serial Bus (USB) protocol, or other protocols for data transmission.

[0060] In addition, the above acceleration device 115 may not be directly inserted into the card slot on the motherboard of the electronic device 110, but may be located in the acceleration device. For example, the acceleration device is a device independent of the electronic device 110, such as an acceleration card. At this time, the electronic device 110 can be connected to the acceleration device 115 through a wired network such as a network cable, or can be connected to the acceleration device 115 through a wireless hotspot or a wireless network such as Bluetooth. If the acceleration device 115 is used to process application development tasks, such as slicing an application program, the acceleration device can be implemented by one or more chips. For example, the chip includes any one of a CPU, a Graphics Processing Unit (GPU), a Neural-Network Processing Unit (NPU), a Tensor Processing Unit (TPU), an FPGA, and an ASIC. Among them, the GPU is also called a display core, a visual processor, and a display chip, and is a microprocessor dedicated to image operation on personal computers, workstations, game consoles, and some mobile devices (such as tablets, smartphones, etc.). The NPU simulates human neurons and synapses at the circuit layer, and directly processes a large number of neurons and synapses with a deep learning instruction set, and one instruction completes the processing of a group of neurons. The ASIC is suitable for an integrated circuit product for a single purpose.

[0061] Regarding the process of program slicing for application load modeling, the following Figure 2 provides a possible implementation process. Figure 2 is a schematic diagram of an architecture for program slicing and testing provided by this application. The architecture for program slicing and testing includes: an instruction stream collection tool, an instruction stream assembly tool, and related tools for chip microarchitecture exploration. These tools can be deployed on one electronic device (such as Figure 1 the electronic device 110 in it), or can be deployed on different electronic devices (such as Figure 1 the electronic device 110 and the acceleration device 115 in it).

[0062] Please refer to Figure 2 , the process of program slicing and testing includes the following ① to ⑤.

[0063] ①. The instruction stream collection tool can analyze the execution frequency of instructions in the original application program through machine learning algorithms and other methods, and obtain the most representative typical intervals (program typical intervals) in the original application program.

[0064] In some alternative examples, the program typical intervals can also be specified by the user.

[0065] ②. Process the program typical intervals determined by the instruction stream collection tool to obtain one or more sets of instruction stream data.

[0066] Among them, each set of instruction stream data includes: some instructions in the application program and the data to be used by these instructions.

[0067] ③. The instruction stream assembly tool slices the instruction stream data determined by the instruction stream collection tool to obtain program slices.

[0068] Taking one program slice corresponding to one set of instruction stream data as an example, this program slice not only includes this set of instruction stream data, but also includes the compensation instructions corresponding to this set of instruction stream data.

[0069] ④. For all the program slices determined in ③ above, determine a complete set of program slices according to the program interval weights of each program slice.

[0070] For example, the complete set of program slices = the instruction intervals corresponding to each program slice × the weights corresponding to each instruction interval.

[0071] ⑤. The electronic device inputs the complete set of program slices into the relevant tools for chip microarchitecture exploration, and performs parameter iteration on the microarchitecture of the chip, thereby assisting in the development of the chip and the application program.

[0072] The above ⑤ can be applied to processes such as the co - design of software and hardware of the chip. For example, the co - design of software and hardware of the chip refers to the close cooperation and interaction between hardware design and software design during the chip design process. In traditional chip design, hardware design and software design are carried out separately, while in the co - design of software and hardware of the chip, hardware design and software design are carried out simultaneously, and the interaction and cooperation between them are closer. In the co - design of software and hardware of the chip, hardware designers and software designers need to cooperate closely, jointly formulate the design specifications and functional requirements of the chip, and carry out the design and development of hardware and software simultaneously. Hardware designers need to consider the software requirements and provide necessary hardware support for the software; software designers need to understand the hardware design and implementation and provide necessary software support for the hardware. The co - design of software and hardware of the chip can improve the design efficiency and quality of the chip, reduce the design cost and time. At the same time, it can also improve the reliability and stability of the chip and provide better support for the application of the chip.

[0073] In this embodiment, the relevant tools for chip microarchitecture exploration may include chip emulators, etc. A chip emulator is a tool used to verify and test chip designs. A chip emulator can simulate the behavior of a chip so that designers can test and debug the design before actually manufacturing the chip. A chip emulator usually includes an emulation engine that can simulate the circuit behavior of the chip and provide some debugging and analysis tools to help designers identify and solve problems. A chip emulator can help designers discover and solve problems before chip manufacturing, thereby saving time and cost and improving the reliability and performance of the chip. For example, a chip emulator is an independent software that simulates the functions of the entire chip, including internal arithmetic and logic units (ALUs) / memories / input-outputs (IOs) / accelerator algorithms, etc., enabling the corresponding object code files and data streams to run on a personal computer in the same way as in the chip. Due to the different emulation details of various types of chip emulators, their running speeds are also different. For example, the speed of an RTL-level emulator is approximately 1 - 10 Hz, the running speed of a single-core performance emulator with accurate clocks is 1 - 10 kHz, the running speeds of trace analysis emulators and processor abstraction models are 10 - 100 KIPS, and the running speed of instruction set function emulators is 1 - 100 MIPS. It can be seen that the emulation speed of a chip emulator is much lower than the execution speed of a chip sample. For a complete real application, the total number of instructions is above the trillion scale. Therefore, the time cost of running the complete program code on a chip emulator is unacceptable.

[0074] Next, the function of the program slice that can be achieved by the instruction stream assembly tool described above will be described in detail. Based on the electronic device 110 shown in Figure 2 , a possible implementation provided by an embodiment of the present application is shown in Figure 1 as follows. Figure 3 As shown, Figure 3 is a flowchart showing the method for generating a program slice provided by the present application. Figure 1 . The generating method may be implemented by an electronic device, such as the electronic device 110 shown in Figure 1 . The method for generating the program slice includes the following S310 to S330.

[0075] S310. The electronic device obtains a slice request.

[0076] Exemplarily, the slice request is determined by the electronic device according to the range set by the user.

[0077] For example, the user selects the ROI part in the application, such as setting the start identifier and end identifier of the instruction, and the electronic device generates the above slice request according to the start identifier and end identifier of the instruction.

[0078] Exemplarily, the slice request is generated by the electronic device according to a typical program slice interval.

[0079] Exemplarily, the slice request is sent by other devices received by the electronic device.

[0080] The above three ways of obtaining the slice request are only optional ways provided in this embodiment and should not be construed as a limitation to this application.

[0081] S320. The electronic device obtains the instruction stream data corresponding to the slice request in the application according to the slice request.

[0082] The instruction stream data includes multiple instructions in the application.

[0083] Exemplarily, the multiple instructions include one of the following instructions or a combination of several types of instructions: calculation instructions, memory access instructions, branch jump instructions, termination instructions, and irrelevant instructions.

[0084] The calculation instruction is used to execute a simple calculation process, that is, the value of the output register associated with the calculation instruction is only affected by the value of the input register.

[0085] Memory access instruction: This type of instruction calculates the memory access address through the address register and affects the output register through the value on the memory access address. Optionally, the memory access instruction may also include calculation semantics at the same time, and this application does not limit this.

[0086] Branch jump instruction: Also known as a jump instruction, it is an instruction that directly affects the control flow.

[0087] Termination instruction: An instruction that clears the memory dependency of the output register.

[0088] Irrelevant instruction: The execution status and result are irrelevant to the value of any register, and it does not affect the value of any register after execution, such as the nop instruction.

[0089] Optionally, the instruction stream data obtained in this embodiment may further include the following: register initial values, PC address, instruction encoding, memory access address, memory access data size, and memory access data, etc. The register initial values are the initial values of all registers associated with the execution of the instruction stream data. The PC address is the address of the instruction in the instruction stream data in the electronic device. For example, the PC address can be a sixteen-bit binary number. The instruction encoding refers to the value determined by encoding the instruction. The memory access address is the address of the memory access data to be accessed by the instruction, and the memory access data size refers to the data volume of the memory access data, and the unit can be bit or byte.

[0090] In some feasible situations, the instruction stream data may also be referred to as an instruction stream trace file or an instruction stream trace, and will not be repeated hereinafter.

[0091] Regarding the process of the electronic device executing the above S320, an optional implementation manner is provided in an embodiment of the present application, as Figure 4 shown Figure 4 is a flowchart of a method for generating a program slice provided by the present application Figure 2 . Taking the above slice request carrying an instruction start identifier and an instruction end identifier as an example for description, the above S320 includes the following S320a and S320b.

[0092] S320a. The electronic device determines the fourth instruction in the application program according to the instruction start identifier in the slice request, and determines the fifth instruction in the application program according to the instruction end identifier in the slice request.

[0093] S320b. The electronic device takes the fourth instruction as the start instruction and the fifth instruction as the end instruction, and obtains the instruction stream data in the application program.

[0094] The multiple instructions in the instruction stream data include the above-mentioned fourth instruction and fifth instruction.

[0095] As a possible specific example, the process of the electronic device obtaining the instruction stream data may rely on dynamic instruction instrumentation and dynamic instruction translation tools. For example, the main steps for the electronic device to obtain the instruction stream data are: instruction stream instrumentation and instruction stream recording.

[0096] Instruction stream instrumentation is achieved by dynamic binary instrumentation (DBI) / dynamic binary translation (DBT) tools to insert instrumentation before and after the instructions to be executed. Among them, a recording logic for the instruction address and instruction encoding is inserted before the instruction to be executed, and a recording logic for the memory access address and memory access data is inserted after the instruction to be executed.

[0097] Instruction stream recording means that after the electronic device runs the instrumented program, basic instruction information and instruction memory access information are recorded before and after each execution of the instruction, and a separate instruction stream data file is generated in real time.

[0098] The above examples are only optional ways for obtaining the instruction stream data provided in this embodiment, and should not be construed as a limitation to this application. In some alternative ways, the electronic device may also use other instrumentation tools or instruction stream data recording tools, etc.

[0099] In this embodiment, the electronic device determines the instruction range of the instruction stream data according to the instruction start identifier and instruction end identifier carried in the slice request, so that the instruction range of the program slice generated by the electronic device is consistent with that of the slice expected by the user, which is conducive to assisting the accuracy of load modeling and thus improving the efficiency of software and hardware co-design.

[0100] Please continue to refer to Figure 3 , the method for generating a program slice provided in the embodiment of this application further includes the following S330.

[0101] S330. The electronic device generates a program slice according to multiple instructions and the mutated memory access instructions among the multiple instructions.

[0102] Among them, the mutated memory access instruction includes: a memory access instruction that affects the execution correctness of the instruction stream data. Exemplarily, the memory access instruction that affects the execution correctness of the instruction stream data refers to: a memory access instruction that affects the output result of the executed instruction stream data.

[0103] The program slice generated by the electronic device includes: the instruction stream data and a compensation instruction for the mutated memory access instruction, and the compensation instruction is used to: restore the data corresponding to the memory access address indicated by the mutated memory access instruction to the data expected to be accessed by the mutated memory access instruction.

[0104] In this embodiment, the electronic device only compensates for the memory access instructions that affect the execution correctness of the instruction stream data, so as to restore the data stored at the memory access address where data mutation occurs.

[0105] Since the electronic device does not need to compensate for any instruction, the compensation instructions and corresponding jump instructions in the instruction stream of the program slice generated by the electronic device are reduced, and the execution times of the compensation instructions are reduced. On the basis of ensuring the execution correctness of the instruction stream, the difference between the program slice and the original application program is reduced.

[0106] Regarding the above identification method or determination method of the mutated memory access instruction, the following embodiment provides an optional implementation manner in conjunction with the accompanying drawings, as Figure 5 shown, Figure 5 is a schematic flowchart of a method for generating a program slice provided in this applicationFigure 3 This generation method can be executed by an electronic device. For the hardware implementation of the electronic device, reference can be made to Figure 1 the relevant description, which will not be elaborated here. Combining the above Figure 3 and Figure 4 content, before the above S330, the generation method provided by the embodiments of the present application further includes the following S321 to S327.

[0107] S321. The electronic device determines a first instruction of the memory access instruction type from multiple instructions.

[0108] For example, for instruction stream data, the electronic device sequentially reads the next instruction and its related data in the instruction stream trace file (instruction stream data).

[0109] S322. The electronic device determines whether the first memory access address in the first instruction is stored in the memory analysis table.

[0110] The memory analysis table includes: multiple memory access addresses, and for each memory access address in the multiple memory access addresses, the data expected to be accessed. Exemplarily, the memory analysis table is used to record the dynamic values of all addresses in the current instruction.

[0111] Next, an example is used to exemplarily illustrate the content stored in the memory analysis table.

[0112] For example, when the electronic device analyzes the nth instruction among multiple instructions, assuming that the nth instruction is ldrb x0,[x1], and the value of x1 is 0x7b4c3e51e4, and the value of the x0 register is 0x3, as shown in Table 1 below.

[0113] Table 1

[0114]

[0115]

[0116] For another example, when the electronic device analyzes the mth instruction (the mth instruction is an instruction whose execution order is after the nth instruction among multiple instructions) among multiple instructions, assuming that the mth instruction is strb x7,[x1], and the value of x1 is 0x7b4c3e51e4, and the value of x7 is 0x7, then the electronic device modifies the value in the memory analysis table to 0x7, as shown in Table 2 below.

[0117] Table 2

[0118] Address (or memory access address) Value (data expected to be accessed at the memory access address) 0x7b4c3e51e3 0x0 0x7b4c3e51e4 0x7 ··· ···

[0119] As described above, the memory analysis table is mainly used to store the data expected to be accessed by all memory addresses when executing specific instructions, that is, the "expected value" of the memory address. This memory analysis table is used to analyze whether data mutation occurs.

[0120] S323. If the first memory access address is stored in the memory analysis table and the data stored in the first memory access address is inconsistent with the data expected to be accessed by the first instruction stored in the memory analysis table, the electronic device determines that the first instruction is a mutated memory access instruction.

[0121] Exemplarily, the electronic device determines whether the data stored in the first memory access address is consistent with the data expected to be accessed by the first instruction stored in the memory analysis table. When the first instruction carries the first memory access address, the data expected to be accessed by the first instruction is the data expected to be accessed by the first memory access address in the memory analysis table.

[0122] If the data stored in the first memory access address is consistent with the data expected to be accessed by the first instruction stored in the memory analysis table, the data in the first memory access address has not undergone data mutation.

[0123] If the data stored in the first memory access address is inconsistent with the data expected to be accessed by the first instruction stored in the memory analysis table, the data in the first memory access address has undergone data mutation, and the first instruction is a mutated memory access instruction.

[0124] The following provides a specific example of determining a mutated memory access instruction: For example, it is determined that at address 0x0, "data mutation" has occurred.

[0125] For example, when the electronic device analyzes the nth instruction among multiple instructions, assuming the instruction is ldrb x0, [x1], and the value of x1 is 0x7b4c3e51e4, and the value of the x0 register is 0x3, as shown in Table 3 below.

[0126] Table 3

[0127] Address (or memory access address) Value (data expected to be accessed at the memory access address) 0x7b4c3e51e3 0x0 0x7b4c3e51e4 0x3 ··· ···

[0128] From the nth to the mth instruction, in the instruction stream trace of this thread, no other instruction modifies the address 0x7b4c3e51e4. Then, when the electronic device analyzes the mth instruction, assuming the instruction is ldrb x7, [x1], and the value of x1 is 0x7b4c3e51e4, and the value of the x8 register is 0x5, as shown in Table 4 below.

[0129] Table 4

[0130] Address (or memory access address) Value (data expected to be accessed at the memory access address) 0x7b4c3e51e3 0x0 0x7b4c3e51e4 0x5 ··· ···

[0131] It can be analyzed from Table 4 and Table 3 that there is no other operation that assigns a value to 0x7b4c3e51e4 between the v-th instruction and the m-th instruction, but the value has changed. Then, the memory access address 0x7b4c3e51e4 is determined to have "data mutation", and the m-th instruction is the mutated memory access instruction.

[0132] To effectively manage the mutated memory access instructions, after S323 above, the generation method provided in the embodiments of the present application may further include the following S324.

[0133] S324. The electronic device writes the first instruction and the first memory access address into the memory access instruction table.

[0134] The memory access instruction table is used to record: the instruction addresses of the mutated memory access instructions among multiple instructions, the execution times of each memory access address with data mutation, and the memory access data.

[0135] The above memory access instruction table refers to the memory access instruction table with data mutation: since the memory access instruction will access one or more specific addresses, when the value of a certain address undergoes data mutation, the current memory access instruction is called a memory access instruction with data mutation (i.e., a mutated memory access instruction).

[0136] As an optional implementation, in addition to the instruction addresses of the above mutated memory access instructions, the execution times of each memory access address with data mutation, and the memory access data and other information, the memory access instruction table may further include: instruction encoding, the address where data mutation occurs, and the execution times and other information, as shown in Table 5 below.

[0137] Table 5

[0138]

[0139] In this embodiment, the address where data mutation occurs can be determined according to the memory access address and the memory access data. During the process of the electronic device obtaining the compensation instruction for the mutated memory access instruction, only the instructions (mutated memory access instructions) already recorded in the memory access instruction table are compensated, which is beneficial to reducing the compensation instructions and the corresponding jump instructions in the instruction stream of the program slice generated by the electronic device, reducing the execution times of the compensation instructions during the running process of the program slice, and reducing the difference between the program slice and the original application program on the basis of ensuring the execution correctness of the instruction stream.

[0140] Please continue to refer to Figure 5 In the above Figure 3 Before S330 shown, the generation method provided in the embodiments of the present application further includes the following S325 to S327.

[0141] S325. The electronic device determines a second instruction of the memory access instruction type from multiple instructions.

[0142] In some cases, the second instruction may be a memory access instruction different from the first instruction described above.

[0143] S326. The electronic device determines whether the second memory access address in the second instruction is stored in the memory analysis table.

[0144] The memory analysis table includes: a plurality of memory access addresses, and for each memory access address in the plurality of memory access addresses, the data expected to be accessed. For more content about the memory analysis table, reference can be made to the relevant descriptions in Table 1 to Table 4 above, which will not be elaborated here.

[0145] If the second memory access address is stored in the memory analysis table, the electronic device compares the data stored at the second memory access address with the data expected to be accessed at the second memory access address, and determines whether the two are consistent. If they are not consistent, it is determined that the second instruction is a mutated memory access instruction.

[0146] If the second memory access address is not stored in the memory analysis table, S327 is executed.

[0147] S327. The electronic device creates an entry for the second instruction in the memory analysis table.

[0148] The entry created by the electronic device in the memory analysis table above includes: the second memory access address and the data stored in the storage space corresponding to the second memory access address. For the entries of the memory analysis table, reference can be made to the descriptions in Table 1 to Table 4 above. In addition, the memory analysis table may further include the byte length of the memory access address, such as 1 byte or other quantities, etc.

[0149] In this embodiment, the electronic device can update the memory access address not stored in the memory analysis table and the data corresponding to the memory access address, so that in the subsequent analysis process of the instruction stream data, the electronic device can also analyze the data expected to be accessed by different memory access instructions including different memory access addresses according to the updated memory analysis table, avoiding the problem of reduced accuracy of the mutated memory access instruction caused by the fact that the memory analysis table does not include all the data expected to be accessed in the instruction stream data, which is beneficial to reducing the difference between the program slice and the original application program while ensuring the execution correctness of the instruction stream.

[0150] Regarding the process of the above-mentioned electronic device generating a program slice, a feasible specific implementation manner is provided below in conjunction with the accompanying drawings, as follows Figure 6 As shown, Figure 6 is a schematic flowchart of a method for generating a program slice provided by the present application Figure 4 . This generation method is executed by an electronic device. For example, S330 described above may include Figure 6 S610 to S640 shown.

[0151] S610: The electronic device obtains a memory address table and a memory access instruction table of instruction stream data.

[0152] The memory access instruction table is used to record: the instruction address of the mutation memory access instruction in multiple instructions, the execution count of each data mutation memory access address, and the access data. The contents of the memory access instruction table can be found in the relevant description of Table 5 above and will not be repeated here.

[0153] The memory address table includes: memory access addresses that affect the execution correctness of instruction stream data.

[0154] Exemplarily, memory access addresses that affect the execution correctness of instruction stream data include: memory access addresses where a data mutation will affect the control flow of the instruction stream data. For example, the data expected to be stored at a certain memory access address is Data 1, and the next instruction expected to be executed is Instruction 1. However, after the electronic device reads the data stored at the memory access address, it discovers that the data actually stored at the memory access address is Data 2, and the next instruction actually executed is Instruction 2. The data at this memory access address has undergone a mutation (Data 1 → Data 2), resulting in a mutation in the control flow of the instruction stream. In this case, the memory access address is determined to be a memory address that affects the execution correctness of the instruction stream data.

[0155] In another exemplary embodiment, the memory access address that affects the execution correctness of instruction stream data includes the memory access address of a mutation register, such as a register whose value undergoes a data mutation that affects the execution correctness of the instruction stream data. When a register is used as a memory access address register, if the register value mutation affects the execution correctness of the program, the memory access address of the register is determined to be the memory access address that affects the execution correctness of the instruction stream data.

[0156] Also illustratively, the memory access address that affects the execution correctness of the instruction stream data includes: the memory access address of the control flow of the instruction stream data affected by the data mutation, and the memory access address of the mutation register mentioned above.

[0157] The above three examples are only feasible implementation methods provided in this embodiment and should not be understood as limitations on this application. Other memory access addresses that may affect the execution correctness of instruction stream data can also be recorded in the memory address table, and this application does not limit this.

[0158] Optionally, the format of the memory access address (or memory address) that affects the execution correctness of the instruction stream data stored in the memory address table may be as shown in Table 6 below.

[0159] Table 6

[0160] Serial number Address 1 0x4000c0 2 0x4000c1 ··· ··· n Address n

[0161] For the process of obtaining the memory address table of the electronic device, you can refer to the followingFigure 8 The embodiments shown are not elaborated here.

[0162] S620. The electronic device updates the memory access instruction table according to the memory address table to obtain an updated memory access instruction table.

[0163] There are no duplicate memory access addresses between the above-mentioned updated memory access instruction table and the memory address table.

[0164] Regarding the specific implementation manner of S620, a possible example is provided below in combination with Figure 7 A possible example is provided. As Figure 7 shown, Figure 7 FIG. is a schematic diagram of updating a memory access instruction table provided by the present application. Exemplarily, the above S620 may include the following S621 to S624.

[0165] S621. The electronic device reads an instruction from the memory access instruction table.

[0166] For example, the electronic device reads instructions in the order in the memory access instruction table.

[0167] S622. The electronic device reads the address of the next data mutation in the entry of the one instruction in the memory access instruction table.

[0168] For example, the address of the data mutation is 0x7b4c3e51e0 in Table 5.

[0169] S623. The electronic device determines whether the address read in S622 is stored in the memory address table.

[0170] If yes, execute S624; if not, return to execute S621 until the electronic device traverses all instructions in the memory access instruction table.

[0171] S624. The electronic device deletes the address read in S622 from the memory access instruction table.

[0172] Regarding the implementation manners of the above S621 to S624, a feasible specific example is provided below in combination with Table 7, as shown in Table 7.

[0173] Table 7

[0174]

[0175] After the program analysis is completed, it is found that the value on the address addr3 does not affect the control flow (or program control flow), and the compensation instruction for this address can be reduced, which is beneficial to minimizing the compensation in the program slice and maximizing the similarity between the program slice and the original service.

[0176] In the embodiment of the present application, the electronic device records the memory access addresses that affect the execution correctness of the instruction stream data through a memory address table, and updates the memory access instruction table according to the memory address table, so that there are no duplicate memory access addresses between the updated memory access instruction table and the memory address table, that is: the electronic device removes the memory access instructions that do not affect the execution correctness of the instruction stream data from the memory access instruction table.

[0177] Please continue to refer to Figure 6 , the generation method provided by the embodiment of the present application further includes S630 and S640 below.

[0178] S630. The electronic device obtains the compensation instructions for all memory access addresses in the updated memory access instruction table.

[0179] The process of how to compensate for the mutated memory access instructions can be referred to the following Figure 9 illustrated embodiment, which will not be elaborated here.

[0180] S640. The electronic device generates a program slice according to the instruction stream data and the compensation instructions for all memory access addresses.

[0181] Thus, in the process of the electronic device obtaining the compensation instructions for the mutated memory access instructions, only the mutated memory access instructions in the memory access instruction table are compensated, which is beneficial to further reducing the compensation instructions and corresponding jump instructions of the instruction stream in the program slice generated by the electronic device, reducing the execution times of the compensation instructions during the running process of the program slice, and reducing the difference between the program slice and the original application program on the basis of ensuring the execution correctness of the instruction stream.

[0182] Regarding the above process of obtaining the memory address table, the following Figure 8 provides a possible example. As Figure 8 shown, Figure 8 is a schematic diagram of obtaining the memory address table provided by the present application. The above process of the electronic device obtaining the memory address includes S801 to S809 below. [[ID=**29]]

[0183] S801. The electronic device initializes the memory dependency table of all registers. <****

[0184] The above all registers include: input registers, output registers, and other registers.

[0185] The process for the electronic device to perform initialization can be to clear the values in the registers. Or, the process for the electronic device to perform initialization can be to set the values in the registers to invalid values, and the invalid values can be set values, such as 0, 1, or others.

[0186] The above memory dependency table is used to record: the addresses on which the memory access address or the value of the register depends. Exemplarily, the memory dependency table contains the values at the addresses on which the address or register depends, meaning that the value of the register is affected by all the address sets in the table. The structure of the memory dependency table can be as shown in Table 8 or Table 9 below.

[0187] Table 8

[0188] Memory address / Memory access address Dependency 0x41c274 0x7b4c3e5c00, 0x7b4c3e5c01, 0x7b4c3e5d00 0x41c275 0x7b4f3f5de0 … … addr addr1, addr2, indicating that the value at addr is affected by addr1 and addr2

[0189] Table 9

[0190] Register Dependency [[ID=8...]]Register 1 0x7b4c3e4c30, 0x7b4c3e4c31 Register 2 0x7b4c3e4c30 … … Register n addr1, addr2, addr n, indicating that the value of general register n is affected by addr1, addr2, and addr n

[0191] Among them, the memory dependency table shown in Table 8 is used to record: the addresses on which the value (data) at the memory access address depends. For example, the data stored at the memory access address 0x41c275 is affected by the value (data) at the address 0x7b4f3f5de0.

[0192] The memory dependency table shown in Table 9 is used to record: the addresses on which the value (data) in the register depends. For example, the data stored in register 2 is affected by the value (data) at the address 0x7b4c3e4c30.

[0193] S802. The electronic device reads the third instruction in the instruction stream data.

[0194] In a possible scenario, the third instruction is any instruction in the instruction stream data.

[0195] The above S802 may include: the electronic device sequentially reads the instructions and data in the instruction stream trace file according to the order of multiple instructions in the instruction stream data, so as to obtain the above third instruction and the data corresponding to the third instruction (such as the data required to execute the third instruction or the data for memory access, etc.). Subsequently, the electronic device determines the type of the third instruction and performs different steps according to the type of the third instruction. An exemplary description is given below in combination with the content of S803 to S809.

[0196] If the third instruction is a memory access instruction, then execute S803 and S804.

[0197] S803. The electronic device obtains the third memory access address in the third instruction and determines the output register associated with the third memory access address.

[0198] Exemplarily, the electronic device can obtain the derivation relationship table of the instruction stream data, and determine the output register associated with the third memory access address according to the derivation relationship table. The derivation relationship table may include information such as instruction mask, instruction opcode, output register, input register, memory access address register, etc. Taking a part of the aarch64 instruction set as an example, the derivation relationship table may be as shown in Table 10 below.

[0199] Table 10

[0200] Instruction opcode Instruction mask Input register Output register Address register Instruction name 0x1a000000 0x7fe0fc00 rn, rm Rd / adc 0xffe00c00 0x38600800 / rt Rn, rm ldrb

[0201] Among them, the instruction mask and the instruction opcode are used to determine the instruction type. By performing an AND operation on the instruction encoding and the instruction mask, the instruction opcode can be obtained. The output register represents the result after the operation of this instruction and is the affected register. The value of the input register directly affects the value of the output register. The input register and the output register are not necessarily explicit. For example, bl x0, blr x1, b.ne.

[0202] The above derivation relationship table is only an example provided in this embodiment and should not be understood as that the electronic device can only determine information such as the input register and output register associated with the instruction through the derivation relationship table. In some alternative implementation manners, the electronic device can also determine the register associated with the instruction through other means, and the present application does not limit this.

[0203] S804. The electronic device assigns the memory dependency table of the third memory access address to the memory dependency table of the output register associated with the third memory access address, and writes all the addresses in the memory dependency table of the third memory access address into the memory address table.

[0204] If the third instruction is not a memory access instruction but a jump instruction, the electronic device executes S805.

[0205] S805. The electronic device writes all the addresses in the memory dependency table of the input register associated with the third instruction into the memory address table.

[0206] If the third instruction is not a memory access instruction or a jump instruction but a calculation instruction, the electronic device executes S806 and S807.

[0207] S806. The electronic device determines the input register and output register associated with the third instruction from all the registers.

[0208] The specific implementation manner for the electronic device to determine the register associated with the third instruction can refer to the description of the foregoing S803 and will not be elaborated here.

[0209] S807. The electronic device clears the value of the output register associated with the third instruction and assigns the memory dependence table of the input register associated with the third instruction to the memory dependence table of the output register associated with the third instruction.

[0210] If the third instruction is not a memory access instruction, a jump instruction, or a calculation instruction but a termination instruction, the electronic device executes S808.

[0211] S808. The electronic device assigns the memory dependence table of the input register associated with the third instruction to the memory dependence table of the output register associated with the third instruction.

[0212] Furthermore, the electronic device determines whether the analysis of the instruction stream data is completed. If the electronic device has not completed the analysis of the instructions in the instruction stream data, it returns to execute S802; if the electronic device has completed the analysis of the instructions in the instruction stream data, it executes S809.

[0213] S809. The electronic device obtains the memory address table.

[0214] For the specific format of the memory address table, refer to the content of Table 6 above, which will not be repeated here.

[0215] Next, an exemplary description is given of the process by which the electronic device compensates for the mutated memory access instruction, as Figure 9 shown, Figure 9 which is a schematic diagram of data mutation compensation provided by this application. The data mutation compensation process includes the following ① to ⑥.

[0216] ①. The electronic device saves the context, which mainly refers to the registers that will be used in the compensation code.

[0217] ②. The electronic device increments by 1 the variable representing the number of executions of this instruction.

[0218] ③. The electronic device obtains the memory access address and memory access data for this time according to the number of instruction executions.

[0219] ④. The electronic device restores the correct data to the address, for example, rewrites the data on the address Ldr to b.

[0220] ⑤. The electronic device restores the context.

[0221] ⑥. The electronic device executes the original memory access instruction.

[0222] Combining the above ① to ⑥, this embodiment also provides a feasible specific example: The electronic device first ensures that the data at the specified address is correct; currently, this instruction is executed for the nth time. According to the memory access instruction table, the electronic device should access the nth address and obtain the nth data. Therefore, the data on addr n is first restored to data n (str data n, addr n). After the electronic device restores the correct data (data n), the original instruction is executed, thus solving the problem caused by data mutation. On the basis of ensuring the correct execution of the instruction stream, the difference between the program slice and the original application program is reduced.

[0223] It should be noted that the above derivation relation table, memory dependency table, memory analysis table, memory access instruction table, memory address table, etc. are all examples provided in this embodiment. In some cases, the content included in each table can also be recorded and stored in other forms other than tables. This application does not limit this.

[0224] It can be understood that in order to implement the functions in the above embodiments, the electronic device includes the corresponding hardware structures and / or software modules for executing each function. Those skilled in the art should easily realize that, combining the units and method steps of the examples described in the embodiments disclosed in this application, this application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed in the way of hardware or computer software driving hardware depends on the specific application scenario and design constraint conditions of the technical solution.

[0225] In the above text, in combination with Figures 1 to 9 , the method for generating a program slice provided according to this embodiment is described in detail. Next, in combination with Figure 10 , the device for generating a program slice provided according to this embodiment will be described.

[0226] Figure 10 FIG. is a schematic structural diagram of a device for generating a program slice provided by this application. The generating device 1000 can be used to implement the functions of the electronic device in the above method embodiments, and thus can also achieve the beneficial effects possessed by the above method embodiments. In this embodiment, the generating device 1000 can be an electronic device as shown in Figure 1 , or the electronic device provided in subsequent embodiments. It should be understood that the generating device 1000 can also be a module (such as a chip) applied to any of the foregoing electronic devices.

[0227] Such as Figure 10As shown in the figure, the program slice generation device 1000 includes: a first acquisition module 1010, a second acquisition module 1020, and an instruction assembly module 1030. The first acquisition module 1010 is configured to acquire a slice request. The second acquisition module 1020 is configured to acquire instruction stream data corresponding to the slice request in the application program according to the slice request, and the instruction stream data includes a plurality of instructions in the application program. The instruction assembly module 1030 is configured to generate a program slice according to the plurality of instructions and the mutated memory access instructions among the plurality of instructions. The mutated memory access instructions include: memory access instructions that affect the execution correctness of the instruction stream data, and the program slice includes: the instruction stream data and compensation instructions for the mutated memory access instructions, and the compensation instructions are used to: restore the data corresponding to the memory access address indicated by the mutated memory access instruction to the data expected to be accessed by the mutated memory access instruction.

[0228] Optionally, the generation device provided in this application further includes: an instruction processing module, configured to: determine a first instruction of the memory access instruction type from the plurality of instructions. Determine whether the first memory access address in the first instruction is stored in the memory analysis table, and the memory analysis table includes: a plurality of memory access addresses, and the data expected to be accessed by each memory access address among the plurality of memory access addresses. If the first memory access address is stored in the memory analysis table and the data stored in the first memory access address is inconsistent with the data expected to be accessed by the first instruction stored in the memory analysis table, then determine that the first instruction is a mutated memory access instruction.

[0229] Regarding the specific functions of the above first acquisition module 1010, second acquisition module 1020, instruction assembly module 1030, instruction processing module, and other possible modules, they can be combined and obtained from the above embodiments, and will not be elaborated here.

[0230] It can be understood that Figure 10 The device shown is only an example provided in this embodiment. According to different slicing processes, the generation device 1000 may include more or fewer units, and this application does not limit this.

[0231] When the generation device is implemented by hardware, the hardware can be implemented by a processor, a chip, or a chip system. The chip system includes one or more chips, and each chip includes an interface circuit and a control circuit. The interface circuit is configured to receive data from other devices outside the chip and transmit it to the control circuit, or send the data from the control circuit to other devices outside the chip. The control circuit and the interface circuit are used to implement the method of any possible implementation manner in the above embodiments through logic circuits or by executing code instructions. The beneficial effects can be referred to the description of any aspect in the above embodiments, and will not be elaborated here.

[0232] It can be understood that the processor in the embodiments of the present application can be a CPU, or other general-purpose processors, digital signal processors (DSPs), ASICs, FPGAs, or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The general-purpose processor can be a microprocessor or any conventional processor.

[0233] In addition, Figure 10 the generating device 1000 in [[ ]] can also be implemented by an electronic device, such as Figure 10 the generating device 1000 in [[ ]] can be implemented by a controller. For example, the controller includes a control circuit and an interface circuit. The interface circuit is used to obtain a slicing request and cooperate with the control circuit to execute the method for generating a program slice in any of the foregoing embodiments.

[0234] Or, Figure 10 the generating device 1000 in [[ ]] can be implemented by an electronic device, and the electronic device can be the electronic device 110 shown in Figure 1 , which will not be elaborated here.

[0235] The method steps in this embodiment can be implemented in a hardware manner or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, and the software modules can be stored in a RAM, flash memory, ROM, PROM, EPROM, EEPROM, register, hard disk, removable hard disk, CD-ROM, or any other form of storage medium well-known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC. In addition, the ASIC can be located in an electronic device. Of course, the processor and the storage medium can also exist as discrete components in a network device or a terminal device.

[0236] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are executed in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user device, or other programmable devices. The computer program or instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer program or instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center in a wired or wireless manner. The computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium, such as a floppy disk, a hard disk, or a magnetic tape; it may also be an optical medium, such as a digital video disc (DVD); or it may be a semiconductor medium, such as a solid state drive (SSD).

[0237] As described above, the above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present application can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for generating program slices, characterized in that, The method includes: Obtaining a slicing request; Obtaining instruction stream data corresponding to the slicing request in the application according to the slicing request, where the instruction stream data includes multiple instructions in the application; Generating a program slice according to the multiple instructions and mutated memory access instructions among the multiple instructions; the mutated memory access instructions include: memory access instructions that affect the execution correctness of the instruction stream data, and the program slice includes: the instruction stream data and compensation instructions for the mutated memory access instructions, and the compensation instructions are used to: restore the data corresponding to the memory access address indicated by the mutated memory access instruction to the data expected to be accessed by the mutated memory access instruction.

2. The method according to claim 1, wherein Before generating the program slice according to the multiple instructions and the mutated memory access instructions among the multiple instructions, the method further includes: Determining a first instruction of the memory access instruction type from the multiple instructions; Judging whether a first memory access address in the first instruction is stored in the memory analysis table; the memory analysis table includes: multiple memory access addresses, and data expected to be accessed by each memory access address among the multiple memory access addresses; If the first memory access address is stored in the memory analysis table and the data stored at the first memory access address is inconsistent with the data expected to be accessed by the first instruction stored in the memory analysis table, determining that the first instruction is a mutated memory access instruction.

3. The method according to claim 1 or 2, characterized in that, Before generating the program slice according to the multiple instructions and the mutated memory access instructions among the multiple instructions, the method further includes: Determining a second instruction of the memory access instruction type from the multiple instructions; Judging whether a second memory access address in the second instruction is stored in the memory analysis table; the memory analysis table includes: multiple memory access addresses, and data expected to be accessed by each memory access address among the multiple memory access addresses; If the second memory access address is not stored in the memory analysis table, creating an entry for the second instruction in the memory analysis table, where the entry includes: the second memory access address and the data stored in the storage space corresponding to the second memory access address.

4. The method according to claim 2 or 3, characterized in that, The generating the program slice according to the multiple instructions and the mutated memory access instructions among the multiple instructions includes: Obtaining a memory address table and a memory access instruction table of the instruction stream data; Wherein, the memory address table includes: memory access addresses that affect the execution correctness of the instruction stream data; the memory access instruction table is used to record: the instruction addresses of the mutated memory access instructions among the multiple instructions, the execution times of each memory access address where data mutates, and the accessed data; Updating the memory access instruction table according to the memory address table to obtain an updated memory access instruction table; there are no duplicate memory access addresses between the updated memory access instruction table and the memory address table; Obtaining compensation instructions for all memory access addresses in the updated memory access instruction table; Generating a program slice according to the instruction stream data and the compensation instructions for all memory access addresses.

5. The method according to claim 4, wherein The memory access address that affects the execution correctness of the instruction stream data includes one or both of the following: the memory access address where data mutation affects the control flow of the instruction stream data, and the memory access address of the mutated register, where the mutated register is a register whose value mutation affects the execution correctness of the instruction stream data.

6. The method according to claim 2, characterized in that, After determining that the first instruction is a mutated memory access instruction, it further includes: Writing the first instruction and the first memory access address into the memory access instruction table, where the memory access instruction table is used to record: the instruction addresses of the mutated memory access instructions among the multiple instructions, the execution times of each memory access address with data mutation, and the memory access data.

7. The method according to claim 4 or 5, characterized in that The obtaining of the memory address table of the instruction stream data includes: Initializing the memory dependency tables of all registers, where the memory dependency tables are used to record: the addresses on which the memory access addresses or the values of the registers depend; all the registers include: input registers, output registers, and other registers; Reading the third instruction in the instruction stream data; If the third instruction is a memory access instruction, obtaining the third memory access address in the third instruction and determining the output register associated with the third memory access address; Assigning the memory dependency table of the third memory access address to the memory dependency table of the output register associated with the third memory access address, and writing all the addresses in the memory dependency table of the third memory access address into the memory address table.

8. The method according to claim 7, characterized in that, The obtaining of the memory address table of the instruction stream data further includes: If the third instruction is a calculation instruction, determining the input register and the output register associated with the third instruction from all the registers; Clearing the value of the output register associated with the third instruction, and assigning the memory dependency table of the input register associated with the third instruction to the memory dependency table of the output register associated with the third instruction.

9. The method according to any one of claims 1-8, characterized in that, The slice request carries an instruction start identifier and an instruction end identifier; The obtaining of the instruction stream data corresponding to the slice request in the application program according to the slice request includes: Determining the fourth instruction in the application program according to the instruction start identifier in the slice request, and determining the fifth instruction in the application program according to the instruction end identifier in the slice request; Taking the fourth instruction as the start instruction and the fifth instruction as the end instruction to obtain the instruction stream data in the application program, where the multiple instructions in the instruction stream data include the fourth instruction and the fifth instruction.

10. The method according to any one of claims 1-9, characterized in that, The multiple instructions include one or several combinations of the following: calculation instructions, memory access instructions, branch jump instructions, termination instructions, and irrelevant instructions.

11. An apparatus for generating program slices, characterized in that, The device includes: A first obtaining module, configured to obtain a slice request; A second obtaining module, configured to obtain the instruction stream data corresponding to the slice request in the application program according to the slice request, where the instruction stream data includes multiple instructions in the application program; An instruction assembly module, configured to generate a program slice according to the multiple instructions and the mutated memory access instructions among the multiple instructions; the mutated memory access instructions include: memory access instructions that affect the execution correctness of the instruction stream data, and the program slice includes: the instruction stream data and compensation instructions for the mutated memory access instructions, and the compensation instructions are used to: restore the data corresponding to the memory access address indicated by the mutated memory access instruction to the data expected to be accessed by the mutated memory access instruction.

12. The device according to claim 11, characterized in that, The apparatus further includes: An instruction processing module, configured to: determine a first instruction of the memory access instruction type from the multiple instructions; determine whether a first memory access address in the first instruction is stored in a memory analysis table, where the memory analysis table includes: multiple memory access addresses, and data expected to be accessed by each memory access address among the multiple memory access addresses; if the first memory access address is stored in the memory analysis table and the data stored at the first memory access address is inconsistent with the data expected to be accessed by the first instruction stored in the memory analysis table, determine that the first instruction is a mutated memory access instruction.

13. The device according to claim 11 or 12, characterized in that, The apparatus further includes: An instruction processing module, configured to: determine a second instruction of the memory access instruction type from the multiple instructions; determine whether a second memory access address in the second instruction is stored in a memory analysis table, where the memory analysis table includes: multiple memory access addresses, and data expected to be accessed by each memory access address among the multiple memory access addresses; if the second memory access address is not stored in the memory analysis table, create an entry for the second instruction in the memory analysis table, where the entry includes: the second memory access address and the data stored in the storage space corresponding to the second memory access address.

14. The device according to claim 12 or 13, characterized in that, The instruction assembly module is specifically configured to: obtain a memory address table and a memory access instruction table of the instruction stream data; where the memory address table includes: memory access addresses that affect the execution correctness of the instruction stream data; the memory access instruction table is used to record: the instruction addresses of the mutated memory access instructions among the multiple instructions, the execution times of each memory access address where data mutates, and the accessed data. The instruction assembly module is further specifically configured to: update the memory access instruction table according to the memory address table to obtain an updated memory access instruction table; there are no duplicate memory access addresses between the updated memory access instruction table and the memory address table. The instruction assembly module is specifically configured to: obtain compensation instructions for all memory access addresses in the updated memory access instruction table, and generate a program slice according to the instruction stream data and the compensation instructions for all memory access addresses.

15. The device according to claim 14, characterized in that, The memory access addresses that affect the execution correctness of the instruction stream data include one or both of the following: memory access addresses where data mutation will affect the control flow of the instruction stream data, and memory access addresses of mutated registers, where the mutated register is: a register whose value mutates and will affect the execution correctness of the instruction stream data.

16. The device according to claim 12, wherein The instruction processing module is further configured to: write the first instruction and the first memory access address into a memory access instruction table, where the memory access instruction table is used to record: the instruction addresses of the mutated memory access instructions among the multiple instructions, the execution times of the memory access addresses for each data mutation, and the memory access data.

17. The device according to claim 14 or 15, characterized in that, The instruction assembly module is specifically configured to: initialize the memory dependency tables of all registers, where the memory dependency tables are used to record: the addresses on which the memory access addresses or the values of the registers depend; all the registers include: input registers, output registers, and other registers; The instruction assembly module is further specifically configured to: read the third instruction in the instruction stream data, if the third instruction is a memory access instruction, obtain the third memory access address in the third instruction, and determine the output register associated with the third memory access address; The instruction assembly module is further specifically configured to: assign the memory dependency table of the third memory access address to the memory dependency table of the output register associated with the third memory access address, and write all the addresses in the memory dependency table of the third memory access address into a memory address table.

18. The device according to claim 17, characterized in that, The instruction assembly module is further specifically configured to: if the third instruction is a calculation instruction, determine the input register and the output register associated with the third instruction from all the registers; clear the value of the output register associated with the third instruction, and assign the memory dependency table of the input register associated with the third instruction to the memory dependency table of the output register associated with the third instruction.

19. An electronic device, characterized in that, Comprising: A memory, a processor, and a computer program stored on the memory; The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 10.

20. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer programs / instructions, and when the computer programs / instructions are executed by the processor, the steps of the method according to any one of claims 1 to 10 are implemented.

21. A computer program product, characterized in that, Comprising computer programs / instructions, and when the computer programs / instructions are executed by the processor, the steps of the method according to any one of claims 1 to 10 are implemented.

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