Unit statistical time sequence prediction method based on graph neural network

Abstract

The invention relates to a unit statistical time sequence prediction method based on a graph neural network, and the method comprises the steps: S1, obtaining a standard unit netlist, extracting all transistors and other elements in the standard unit netlist as a first type of nodes and a second type of nodes, building a first edge based on the connection relation between the other elements and the transistors, and building a second edge based on the connection relation between the first edge and the second edge; constructing an initial heterogeneous graph; s2, according to the basic principle of a circuit, simplifying the initial graph by using a redundant parasitic deletion method, restoring the first type of nodes deleted in the simplification process, and constructing virtual edges for the first type of nodes without direct connection elements to connect the nearest other first type of nodes to obtain a simplified heterogeneous graph; s3, according to element types corresponding to two nodes connected with each edge in the simplified heterogeneous graph, establishing an adjacent matrix for each type of connection, and constructing a corresponding feature matrix; and S4, inputting the constructed adjacency matrix and the feature matrix into the trained heterogeneous graph attention network to obtain a statistical delay prediction result. Compared with the prior art, accurate and efficient statistical time sequence representation can be carried out on the standard cell library.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic design automation, and in particular to a unit statistical timing prediction method based on a graph neural network. Background Art

[0002] Standard cells are the cornerstone of digital circuit design and verification, and their accurate timing modeling is crucial for the timing performance constraints in the design process. However, with the evolution of process nodes, the global fluctuations caused by process, voltage, and temperature (PVT) and the local fluctuations caused by on-chip process parameter fluctuations have a more and more serious impact on the timing fluctuations of cells. Therefore, statistical static timing analysis based on a standard cell statistical timing library is required to ensure the accuracy and reliability of timing sign-off. However, the construction of a multi-PVT standard cell statistical timing characterization library considering process fluctuations depends on a large number of Monte Carlo (MC) simulations, which is the standard method of existing commercial processes, with high modeling accuracy but huge simulation overhead. In addition, the models proposed in traditional research use fewer simulations to model the statistical timing of simple cells such as inverters, but usually cannot establish a unified statistical timing model for different cells under multi-PVT conditions, and ignore the impact of parasitic effects on the unit statistical timing, resulting in low modeling accuracy.

[0003] In recent years, machine learning (ML)-based methods have gradually been used for the statistical timing characterization of standard cell libraries, where simple regression models and neural networks (NNs) are used to utilize the correlation between timing variations and physical parameters and operating conditions. However, most methods are trained separately for each standard cell, or even for each specific timing arc and each PVT corner, resulting in poor generalization ability and the need for cumbersome training for the standard cell library. To address this problem, graph neural networks (GNNs) have gradually become a powerful tool for building a general timing model for different standard cells, where the netlist topology of the standard cell is represented as a graph, and the timing and physical information are extracted as graph node features. Nevertheless, most existing GNN-based methods ignore the layout-related parasitic resistors and capacitors (RCs), which have profound and diverse effects on the timing characteristics of the standard cell library, especially for the timing characteristics of advanced processes. In addition, the issue of training set selection has not been explored in previous learning-based timing characterization methods, and the selection of the training set directly affects the generalization ability of the model for unseen data and the considerable simulation effort required to generate these data.

[0004] Therefore, those skilled in the art need to solve the problem of difficult to accurately and efficiently perform statistical timing characterization on the standard cell library. Summary of the Invention

[0005] The object of the present invention is to provide a unit statistical time series prediction method based on a graph neural network.

[0006] The object of the present invention can be achieved by the following technical solutions:

[0007] A unit statistical time series prediction method based on a graph neural network, comprising:

[0008] Step S1: Obtain a standard cell netlist, extract all transistors and other components in the standard cell netlist as the first type of nodes and the second type of nodes respectively, and establish a first edge based on the connection relationship between other components and transistors to construct an initial heterogeneous graph;

[0009] Step S2: According to the basic circuit principle, simplify the initial graph using a redundant parasitic deletion method, restore the first type of nodes deleted during the simplification process, and construct virtual edges to connect the first type of nodes without directly connected components to the nearest other first type of nodes to obtain a simplified heterogeneous graph;

[0010] Step S3: According to the component types corresponding to the two nodes connected by each edge in the simplified heterogeneous graph, establish an adjacency matrix for each type of connection and construct a corresponding feature matrix;

[0011] Step S4: Input the constructed adjacency matrix and feature matrix into a trained heterogeneous graph attention network to obtain a statistical delay prediction result.

[0012] The specific steps of step S1 include:

[0013] Step S1-1: Obtain a standard cell netlist, and extract all transistors in the standard cell netlist as the first type of nodes and other components as the second type of nodes;

[0014] Step S1-2: Identify one by one whether there is a direct connection between each other component and each transistor. If there is a direct connection relationship between any other component and any transistor, establish a first edge for connecting the corresponding first type of node and the corresponding second type of node, and construct an initial heterogeneous graph.

[0015] The steps of step S2 include:

[0016] Step S2-1: Determine the on and off states of the transistors in the target timing arc according to the signal propagation of the target timing arc;

[0017] Step S2-2: Use the first type of nodes corresponding to the on transistors as the reserved first type of nodes, mark the second type of nodes corresponding to other components directly connected to any reserved first type of node as reserved second type of nodes, and mark the first edge connecting any reserved transistor and reserved component as a reserved edge;

[0018] Step S2-3: Retain all the nodes and the first edges marked as retained type-one nodes, retained type-two nodes, and retained edges in the initial heterogeneous graph, and delete the other nodes and the first edges to obtain a first heterogeneous graph;

[0019] Step S2-4: For each deleted type-one node, determine one by one whether there is a direct connection with any retained type-two node. If so, restore the type-one node and the first edge between the type-one node and the corresponding retained type-two node. Otherwise, restore the type-one node and construct a virtual edge between the type-one node and its nearest retained type-one node to obtain a simplified heterogeneous graph.

[0020] In the above Step S2-4, the nearest retained type-one node is specifically obtained according to the standard cell netlist.

[0021] The above Step S3 includes:

[0022] Step S3-1: Traverse all the first edges and virtual edges in the simplified heterogeneous graph, and classify the edges with the same types of the two nodes connected by any edge into the same connection class, where the same node types means belonging to the same type-one nodes or the same small class of type-two nodes, and each other component type corresponds to a small class of type-two nodes;

[0023] Step S3-2: Establish an adjacency matrix for each connection class, and the number of rows and columns of the adjacency matrix respectively correspond to the number of nodes of the two connected types;

[0024] Step S3-3: Construct a feature matrix according to the component information corresponding to all the nodes in the adjacency matrix.

[0025] The above component information includes process corner characteristics and timing characteristics.

[0026] The construction process of the above heterogeneous graph attention network includes:

[0027] Build an embedding layer: The first-layer embedding layer performs a mapping transformation on the feature vectors of the nodes to provide initial embedding vectors for the subsequent HGAT layers. At the same time, the existence of the embedding layer ensures the consistency and standardization of the input data;

[0028] Construct the HGAT layer, build a K-layer heterogeneous graph attention network to perceive the local structure information of the graph within the K-hop neighborhood, and introduce a residual connection in the intermediate layer embedding of each graph node to directly add to the output embedding of the subsequent layer. Finally, input the updated graph node embeddings of all into the pooling layer to obtain the heterogeneous graph embedding of the cell netlist considering parasitics;

[0029] The obtained cell graph embedding and global feature embedding are concatenated and used as the input of the multi-layer perceptron network for regression prediction to obtain the predicted value of the statistical delay. Then, the error between the predicted value and the true value is calculated, and the gradient of the error is calculated. The trainable parameters and weight matrix are optimized to minimize the error.

[0030] In view of the different contributions of the embeddings of transistors, parasitic resistors, and parasitic capacitors to the model, in the pooling layer, the embeddings of each type of graph node are first subjected to mean pooling respectively, and then certain weights are set to perform weighted pooling on the embeddings of different types of graph nodes to obtain the graph embedding.

[0031] A method and device for unit statistical timing prediction based on a graph neural network, including a memory, a processor, and a program stored in the memory. When the processor executes the program, the above-mentioned method is implemented.

[0032] A storage medium, on which a program is stored, and when the program is executed, the above-mentioned method is implemented.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] 1. A method for unit statistical timing modeling based on a graph neural network is provided. The standard cell circuit netlist after parasitic parameter extraction is converted into a topological graph composed of nodes and edges. An adjacency matrix is constructed according to the connection relationship between the nodes, and the initial feature vectors of each node are extracted to obtain a feature matrix, which is input into the heterogeneous graph neural network module. The feature information of neighbor nodes is aggregated, combined with the active learning method, and the statistical delay of the standard cell after layout is predicted.

[0035] 2. A standard cell statistical timing prediction model based on a graph neural network is introduced to estimate the standard cell statistical timing, significantly reducing the time overhead of standard cell statistical library building after layout. Thus, a reliable standard cell can be provided to designers or tools faster, reducing design iterations and the time cost of chip design.

[0036] 3. An active learning-based training set selection mechanism is introduced, which can significantly enhance the training results of the model and reduce the data acquisition requirements, significantly reducing the time overhead of standard cell statistical library building after layout, thereby reducing the time cost of chip design, which is of great significance for accelerating the digital integrated circuit design process. Description of the Drawings

[0037] Figure 1 It is a unit statistical timing model framework based on a heterogeneous graph attention network;

[0038] Figure 2 It is the definition of the heterogeneous graph of the standard cell;

[0039] Figure 3 For redundant parasitic resistance and resistance deletion;

[0040] Figure 4 For constructing a heterogeneous graph adjacency matrix;

[0041] Figure 5 For the heterogeneous graph attention network structure;

[0042] Figure 6 For the standard cell statistical timing prediction and verification framework;

[0043] Figure 7 For the main step flow diagram of the method of this application. Specific implementation manner

[0044] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. This embodiment is implemented on the premise of the technical solution of the present invention, and detailed implementation manners and specific operation processes are given, but the protection scope of the present invention is not limited to the following embodiments.

[0045] A unit statistical timing prediction method based on a graph neural network, as Figure 1 and Figure 7 shown, includes:

[0046] Step S1: Obtain a standard cell netlist, extract all transistors and other components in the standard cell netlist as the first type of nodes and the second type of nodes respectively, and establish a first edge based on the connection relationship between other components and transistors to construct an initial heterogeneous graph, specifically including:

[0047] Step S1-1: Obtain a standard cell netlist, and extract all transistors in the standard cell netlist as the first type of nodes and other components as the second type of nodes;

[0048] Step S1-2: Identify one by one whether there is a direct connection between each other component and each transistor. If there is a direct connection relationship between any other component and any transistor, establish a first edge for connecting the corresponding first type of node and the corresponding second type of node, and construct an initial heterogeneous graph.

[0049] As Figure 2 shown, convert the standard cell netlist into a graph data structure. Regard transistors, resistors, and capacitors in the circuit netlist of the standard cell as nodes. For Figure 2The standard cells shown in part (a) are partial combinational logic standard cells provided by a foundry under the TSMC 22nm process, including various logic cells such as NAND gates, inverters, OR gates, XNOR gates, XOR gates, multiplexers, etc. Use Python to extract different connection relationships of internal nodes of the cells from the RAW netlist (netlist without parasitic parameter information) and the LPE netlist (netlist with parasitic parameters), so as to construct the required adjacency matrix. Specifically, there are a total of 4 transistors, namely T1, T2, T3, and T4, and there are also resistors R1 and R2, and capacitors C1, C2, and C3. A total of 4 first-class nodes and 5 second-class nodes are obtained. For the second-class nodes, the capacitors and resistors are different sub-categories, namely 3 second-class nodes and 2 second-class nodes. The final result is as Figure 2 shown in the initial heterogeneous graph of (b).

[0050] Step S2: According to the basic circuit principle, use the redundant parasitic deletion method to simplify the initial graph, restore the first-class nodes deleted during the simplification process, and construct virtual edges for the first-class nodes without directly connected components to connect the nearest other first-class nodes to obtain a simplified heterogeneous graph.

[0051] Among them, the design of the redundant parasitic deletion method is to balance the number of different types of nodes, avoid the model having a specific node bias, thus ignoring the overall graph structure information and misleading the model learning. Since the different timing arcs of the cell are essentially different charge and discharge paths and the process of transistors charging and discharging different parasitic capacitors and load capacitors through different parasitic resistance networks on the path, the contribution of other devices not on this path to the timing statistics of the timing arc can be ignored. Therefore, the heterogeneous graph representation of the cell can be simplified according to the connection structure on the timing arc, highlighting the physical structure of different timing arcs while balancing the number of different types of nodes, so that the model can fully understand the timing behavior of different timing arcs.

[0052] Specifically, it includes:[[]]

[0053] Step S2-1: According to the signal propagation of the target timing arc, determine the on and off states of each transistor in the target timing arc. Among them, the transistors in the cell can be respectively identified as active and non-active transistors according to their on and off states in the timing arc. As Figure 3 shown in part (a), when the input pin A1 receives a falling edge, an output rising edge will propagate to the output pin Z N , where the transistor T1 is active through the timing arc marked with a red dotted line, while the other transistors are identified as non-active transistors.

[0054] Step S2-2: Take the first type of nodes corresponding to the turned-on transistors as the reserved first type of nodes, mark the second type of nodes corresponding to other components directly connected to any reserved first type of node as the reserved second type of nodes, and mark the first edges connecting any reserved transistor and reserved component as the reserved edges;

[0055] In this process, the corresponding parasitic resistors and capacitors are extracted according to the turned-on transistors in the previous step. As previously explained, only the parasitic resistors and capacitors on the charge and discharge paths have a decisive impact on the timing of this timing arc, while other parasitic resistors and capacitors can be regarded as redundant. Therefore, we traverse the entire cell netlist considering parasitics based on the turned-on transistors determined in the previous step, extract the parasitic resistors and capacitors directly connected to the turned-on transistors in the netlist as the parasitic network representing this timing arc, and delete the remaining resistors and capacitors. As Figure 3 shown in part (b) of, transistor T1 is the turned-on transistor, and parasitic resistor R2 and parasitic capacitor C3 are retained, thus obtaining a simplified parasitic network structure based on the timing arc.

[0056] Step S2-3: Retain all the nodes and first edges marked as reserved first type of nodes, reserved second type of nodes, and reserved edges in the initial heterogeneous graph, and delete other nodes and first edges to obtain the first heterogeneous graph;

[0057] Step S2-4: For all the deleted first type of nodes, judge one by one whether there is a direct connection with any reserved second type of node. If so, restore the first type of node and the first edge between the first type of node and the corresponding reserved second type of node. Otherwise, restore the first type of node and construct a virtual edge between the first type of node and the nearest reserved first type of node to obtain the simplified heterogeneous graph. Generally, the nearest reserved first type of node is specifically obtained through the standard cell diagram without parasitic parameters.

[0058] This process includes the revival of transistor nodes and the construction of virtual edges. Although key information is obtained in the process of extracting the key transistors, parasitic resistors, and capacitors on the charge and discharge paths of the timing arc, this method may lose the information representing the entire cell structure. Because there may be similar physical structures of timing arcs between different standard cells. For example, there is a timing arc of A1-Z with only one turned-on transistor in both NAND2 and NAND3 N timing arc. In order to accurately and fully distinguish the differences between different cells, this application adopts the transistor node "revival" strategy, that is, re-extract the transistors deleted in the second step to construct a heterogeneous graph and completely retain the basic structural features of the cell. Subsequently, traverse the original netlist and reconstruct the connection relationships between the reserved nodes according to the connection relationships of the internal nodes. As Figure 3As shown in (c), transistors T2, T3, and T4 are re-extracted, and then the edges connecting the nodes are also reconstructed, such as the edge between T2 and C3. However, due to the deletion of certain parasitic resistors and capacitors, there are open circuits in the complete transistor structure, that is, the actual electrical connections are lost. Therefore, starting from the open transistors in the original netlist, search for paths to other transistors. As long as there is any path between two transistors, a virtual connection edge is constructed between them, such as between T3 and T4.

[0059] Step S3: According to the component types corresponding to the two nodes connected by each edge in the simplified heterogeneous graph, for each type of connection, establish an adjacency matrix and construct a corresponding feature matrix, including:

[0060] Step S3-1: Traverse all the first edges and virtual edges in the simplified heterogeneous graph, and classify the edges with the same types of the two nodes connected by any edge into the same connection class. Among them, the same node type means belonging to the same first type of nodes or the same subclass of the second type of nodes, and each type of other component corresponds to a subclass of the second type of nodes;

[0061] Step S3-2: Establish an adjacency matrix for each connection class, and the number of rows and columns of the adjacency matrix respectively correspond to the number of nodes of the two types connected;

[0062] In this application, a simplified unit heterogeneous graph representation is generated, and then the corresponding adjacency matrix and node feature vectors are obtained. Based on the aforementioned 9 different types of edges, as Figure 4 shown, 9 adjacency matrices need to be constructed to represent each type of edge, including: the edge representing the connection between transistors, the edge representing the connection between a transistor and a resistor, the edge representing the connection between a transistor and a capacitor, the edge representing the connection between a resistor and a transistor, the edge representing the connection between resistors, the edge representing the connection between a resistor and a capacitor, the edge representing the connection between a capacitor and a transistor, the edge representing the connection between a capacitor and a resistor, and the edge representing the connection between capacitors.

[0063] Step S3-3: Construct a feature matrix according to the component information corresponding to all nodes in the adjacency matrix. Generally, the component information includes process corner characteristics and timing characteristics.

[0064] Step S4: Input the constructed adjacency matrix and feature matrix into the trained heterogeneous graph attention network to obtain the statistical delay prediction result.

[0065] As Figure 5 shown, the constructed heterogeneous graph attention network takes the adjacency matrix and feature matrix as inputs, consists of an embedding layer, multiple GNN layers, a merging layer, and a fully connected layer, and uses the unit statistical delay as the label for model prediction to estimate the unit statistical delay after layout.

[0066] The construction process of the heterogeneous graph attention network includes:

[0067] Build an embedding layer. The first-layer embedding layer of the module maps the feature vectors of nodes in the dimension space, providing initial embedding vectors for the subsequent HGAT layers. At the same time, the existence of the embedding layer ensures the consistency and standardization of the input data, which can improve the stability of model training.

[0068] Construction of the HGAT layer. During the model learning process, the update of nodes will aggregate the information of different types of neighbor nodes with different weights according to the adjacency matrices of different edge types. Similarly, build a K-layer heterogeneous graph attention network to perceive the local structure information of the graph within the K-hop neighborhood, and introduce a residual connection in the intermediate-layer embedding of each type of graph node to directly add to the output embedding of the subsequent layer. Finally, input the updated graph node embeddings of all into the pooling layer to obtain the heterogeneous graph embedding of the cell netlist considering parasitics. Given that the embeddings of transistors, parasitic resistors, and parasitic capacitors contribute differently to the model, first perform mean pooling on each type of graph node in the pooling layer, and then set certain weights to perform weighted pooling on the embeddings of different types of nodes to obtain the graph embedding.

[0069] Concatenate the obtained cell graph embedding and the global feature embedding, and use it as the input of the multi-layer perceptron network for regression prediction to obtain the predicted value of the statistical delay. Then calculate the error between the predicted value and the true value, and calculate the gradient of the error. Optimize the trainable parameters and weight matrices to minimize the error.

[0070] In this embodiment, during the training of the heterogeneous graph attention network, an initial sample set is selected from the prepared sample data and the data in the initial sample set is characterized to obtain labels. Then, an active learning method is used to sequentially select new samples from the unlabeled samples according to a certain ratio. After characterization, these samples are added to the training sample pool and trained. Finally, the remaining data is used to verify the model's prediction accuracy and time cost. The active learning training set selection method first constructs an initial training sample data set. All samples consisting of different timing arcs of all units under different operating conditions (PVT, input transition time, output load capacitance) are randomly shuffled and combined into a full set of unlabeled samples. These samples have not been simulated to obtain corresponding statistical timing labels. Then, based on the set number of samples in the initial training set, the first d samples are repeatedly Monte Carlo simulated using a simulation tool to obtain corresponding statistical timing label values. The simulated samples and corresponding labels are then added to the initially empty simulated sample set. Next, the samples with the maximum uncertainty are repeatedly selected from the unsimulated samples and simulated to obtain corresponding label values. Next, the heterogeneous graph attention network is trained using the simulated labeled sample set. Then, the trained model is used to predict all unlabeled samples through m cycles to obtain the uncertainty of the samples. Samples with large uncertainty are simulated and added to the simulated sample set. The above process is repeated until the set number of samples is reached. Finally, if Figure 6 As shown in Figure 2, the trained heterogeneous graph attention network is verified.

[0071] If the above functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

Claims

1. A unit statistical time series prediction method based on graph neural network, characterized in that Including: Step S1: Obtain a standard cell netlist, extract all transistors and other components in the standard cell netlist as the first type of nodes and the second type of nodes respectively, and establish first edges based on the connection relationships between other components and transistors to construct an initial heterogeneous graph; Step S2: According to the basic circuit principle, simplify the initial graph using the redundant parasitic deletion method, restore the first type of nodes deleted during the simplification process, and construct virtual edges to connect the first type of nodes without directly connected components to the nearest other first type of nodes to obtain a simplified heterogeneous graph; Step S3: According to the component types corresponding to the two nodes connected by each edge in the simplified heterogeneous graph, establish an adjacency matrix for each type of connection and construct a corresponding feature matrix; Step S4: Input the constructed adjacency matrix and feature matrix into the trained heterogeneous graph attention network to obtain a statistical delay prediction result.

2. The unit statistical time series prediction method based on graph neural network according to claim 1, wherein The specific content of step S1 includes: Step S1-1: Obtain a standard cell netlist, and extract all transistors in the standard cell netlist as the first type of nodes and other components as the second type of nodes; Step S1-2: Identify one by one whether there is a direct connection between each other component and each transistor. If there is a direct connection relationship between any other component and any transistor, establish a first edge for connecting the corresponding first type of node and the corresponding second type of node to construct an initial heterogeneous graph.

3. A unit statistical time series prediction method based on a graph neural network according to claim 2, wherein, The step S2 includes: Step S2-1: Determine the on and off states of the transistors in the target timing arc according to the signal propagation of the target timing arc; Step S2-2: Take the first type of nodes corresponding to the on transistors as the reserved first type of nodes, mark the second type of nodes corresponding to the other components directly connected to any reserved first type of node as the reserved second type of nodes, and mark the first edges connecting any reserved transistor and the reserved component as the reserved edges; Step S2-3: Retain all the nodes and first edges marked as reserved first type of nodes, reserved second type of nodes, and reserved edges in the initial heterogeneous graph, and delete other nodes and first edges to obtain a first heterogeneous graph; Step S2-4: For all the deleted first type of nodes, judge one by one whether there is a direct connection with any reserved second type of node. If so, restore the first type of node and the first edge between the first type of node and the corresponding reserved second type of node. Otherwise, restore the first type of node and construct a virtual edge between the first type of node and the nearest reserved first type of node to obtain a simplified heterogeneous graph.

4. A unit statistical time series prediction method based on a graph neural network according to claim 1, characterized in that, In step S2-4, the nearest reserved first type of node is specifically obtained according to the standard cell netlist.

5. The unit statistical time series prediction method based on a graph neural network according to claim 1, characterized in that, The step S3 includes: Step S3-1: Traverse all the first edges and virtual edges in the simplified heterogeneous graph, and classify the edges with the same types of the two nodes connected by any edge into the same connection class, where the same node types mean belonging to the same first type of nodes or the same small class of the second type of nodes, and each type of other component corresponds to a small class of the second type of nodes; Step S3-2: Establish an adjacency matrix for each connection class, and the number of rows and columns of the adjacency matrix respectively correspond to the number of nodes of the two types of connections; Step S3-3: Construct a feature matrix based on the component information corresponding to all nodes in the adjacency matrix.

6. A unit statistical time series prediction method based on a graph neural network according to claim 1, characterized in that The component information includes process corner characteristics and timing characteristics.

7. A unit statistical time series prediction method based on a graph neural network according to claim 1, characterized in that, The construction process of the heterogeneous graph attention network includes: Construct an embedding layer: The first-layer embedding layer performs a mapping transformation on the feature vectors of the nodes in the dimensional space, provides initial embedding vectors for the subsequent HGAT layers, and at the same time, the existence of the embedding layer ensures the consistency and standardization of the input data; Construction of the HGAT layer, build K layers of heterogeneous graph attention networks to perceive the local structure information of the graph within the K-hop neighborhood, and introduce residual connections in the intermediate layer embeddings of each type of graph node to directly add to the output embeddings of the subsequent layer. Finally, input the updated graph node embeddings of all into the pooling layer to obtain the heterogeneous graph embedding of the cell netlist considering parasitics; Concatenate the obtained cell graph embedding and the global feature embedding, use them as the input of the multi-layer perceptron network for regression prediction to obtain the predicted value of the statistical delay. Then calculate the error between the predicted value and the true value, and calculate the gradient of the error. Optimize the trainable parameters and weight matrices to minimize the error.

8. The unit statistical time series prediction method based on graph neural network according to claim 7, wherein Given that the embeddings of transistors, parasitic resistors, and parasitic capacitors contribute differently to the model, in the pooling layer, first perform mean pooling on the embeddings of each type of graph node respectively, and then set certain weights to perform weighted pooling on the embeddings of different types of graph nodes to obtain the graph embedding.

9. A unit statistical time series prediction method and device based on a graph neural network, comprising a memory, a processor, and a program stored in the memory, characterized in that, When the processor executes the program, it implements the method described in any one of claims 1-8.

10. A storage medium, on which a program is stored, characterized in that, When the program is executed, it implements the method described in any one of claims 1-8.

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