Digital circuit optimization method and system based on logic clustering

Abstract

The present invention discloses a digital circuit optimization method and system based on logic clustering. The method comprises the following steps: S1, collecting fan-out information of all registers in a circuit netlist; S2, based on the register fan-out information, screening registers whose fan-out number is greater than a first preset threshold, whose logic level is greater than a second preset threshold, and which are located on a critical path, and generating a candidate register list; S3, obtaining first-level combinational logic information of the register fan-out; S4, clustering logic units based on the first-level combinational logic information, and dividing physically adjacent logic units into the same cluster according to their physical position relationships; S5, associating the clustered logic units and adjusting their connection relationships; S6, performing equivalence checking; and S7, re-layouting the circuit according to the modified netlist. The present invention can effectively reduce the physical distance of the timing path, optimize the timing performance of the circuit, and is suitable for large-scale integrated circuit design.

Description

Technical Field

[0001] The present invention mainly relates to the field of integrated circuit design, and in particular to a digital circuit optimization method and system based on logic clustering. Background Art

[0002] In CMOS digital circuit design, registers are key components of timing paths, and timing optimization is one of the key steps to ensure circuit performance. As the scale of integrated circuits continues to expand, the scale of timing paths grows exponentially, and timing convergence is increasingly affected by exponentially growing physical rules. Especially when dealing with large fan-out registers (i.e., one register drives hundreds or thousands of subsequent logic cells), timing optimization of these paths becomes extremely challenging. Currently, commercial electronic design automation (EDA) tools typically use the method of inserting inverters or buffer trees to optimize such timing paths when dealing with large fan-out registers. However, current methods have the following shortcomings:

[0003] 1. Improper placement of inverters / buffers. Commercial EDA tools typically insert inverters or buffers based on global optimization algorithms, but these algorithms often fail to fully consider the characteristics of local timing paths. For example, in some cases, inverters or buffers are inserted on non-critical paths, resulting in wasted resources. On critical paths, insufficient inverters or buffers are inserted, failing to effectively reduce signal transmission delay.

[0004] 2. Lack of adequate consideration of physical layout: Commercial EDA tools often overlook the impact of physical layout when inserting inverters or buffers. For example, rather than driving related logic cells together in close proximity, the insertion of inverters or buffers can lead to interweaving of the components, increasing signal line lengths and introducing additional delay and power consumption. Furthermore, this poor physical layout can lead to routing congestion, further impairing circuit performance.

[0005] In summary, current commercial EDA tools, when handling large fan-out registers, suffer from issues such as inappropriate inverter / buffer insertion placement and insufficient consideration of physical layout, making them difficult to meet the demands of high-performance microprocessor design. Therefore, a timing optimization method that can efficiently handle large fan-out registers is urgently needed to overcome the shortcomings of existing technologies and improve the performance and reliability of circuit designs. Summary of the Invention

[0006] In view of the technical problems existing in the prior art, the present invention provides a digital circuit optimization method and system based on logic clustering for achieving efficient optimization of timing paths.

[0007] In order to solve the above technical problems, the technical solution proposed by the present invention is:

[0008] A digital circuit optimization method based on logic clustering, comprising the steps of:

[0009] S1. Count register fan-out information: Count the fan-out information of all registers in the circuit netlist, that is, the number of all subsequent logic units directly driven by the register output signal or indirectly driven across inverters and buffers, and generate a fan-out information table;

[0010] S2. Generate a candidate register list: Based on the fan-out information of all registers, select registers whose fan-out number is greater than a first preset threshold, whose logic level is greater than a second preset threshold, and which are located on the critical path, and generate a candidate register list final_reg_list;

[0011] S3. Obtain register fan-out first-level combinational logic information: For each register in the candidate register list final_reg_list, obtain its fan-out first-level combinational logic information; the first-level combinational logic refers to the combinational logic unit directly driven by the register output signal and indirectly driven across the inverter / buffer;

[0012] S4, first-level combination logic clustering: Based on the first-level combination logic information obtained in S3, cluster the logical units and divide physically adjacent logical units into the same cluster according to their physical location relationship;

[0013] S5. Modify the netlist after clustering: After completing the logic clustering, modify the netlist of the circuit, that is, associate the clustered logic units together and adjust their connection relationships;

[0014] S6, equivalence check: After the netlist modification is completed, an equivalence check is performed to ensure that the modified circuit function is consistent with the original circuit; if the equivalence check passes, proceed to the next step; otherwise, return to step S5 to correct the connection relationship;

[0015] S7. Re-layout and re-routing: Re-layout and re-route the circuit according to the modified netlist.

[0016] Preferably, the specific steps of S1 include:

[0017] S101, traverse all registers in the circuit netlist and record the output signal of each register;

[0018] S102, analyzing the logic units driven by each output signal, including the combinational logic unit, the inverter unit, and the buffer unit, adding the combinational logic unit to the combination list com_list, and adding the inverter unit and the buffer unit to the inverter and buffer unit list inv_buf_list;

[0019] S103. Find other combinational logic units driven by the inverter unit and the buffer unit. For each inverter unit and buffer unit in inv_buf_list, sequentially search for all combinational logic units directly driven by their output signals and all combinational logic units driven across inverters or buffers, and add these combinational logic units to the combination list com_list.

[0020] S104 , counting the number of combinational logic units fanned out by each register in the combination list com_list in step S103 , and generating a fan-out information table.

[0021] Preferably, the specific steps of S2 include:

[0022] S201, set a threshold for the fan-out number, filter out registers whose fan-out number is greater than the threshold, and form an initial candidate register list init0_reg_list;

[0023] S202 , screening out registers on the long path whose logic levels exceed a preset threshold from the candidate register list init0_reg_list to form a new candidate register list init1_reg_list;

[0024] S203 , analyzing the timing information of each register in the new candidate register list init1_reg_list, determining whether each register in init1_reg_list is in the critical path, selecting registers on the critical path, and thereby determining the final candidate register list final_reg_list.

[0025] Preferably, the candidate register list final_reg_list includes one or more elements including register name, register fan-out quantity, timing path length, and whether the register is in a critical path.

[0026] Preferably, the specific steps of S3 include:

[0027] S301. Traverse the candidate register list final_reg_list, obtain the output signal of each register, analyze the logic unit driven by each output signal, including the combinational logic unit, inverter unit, and buffer unit, add the combinational logic unit to the combination list com_list, and add the inverter unit and buffer unit to inv_buf_list;

[0028] S302. Find other combinational logic units driven by the inverter unit and the buffer unit. For each inverter unit and buffer unit in inv_buf_list, sequentially search for all combinational logic units directly driven by their output signals and all combinational logic units driven across inverters or buffers, and add these combinational logic units to the combination list com_list.

[0029] S303 , counting the number of combinational logic units fanned out by each register in the combination list com_list of step S302 , and generating a fan-out information table.

[0030] Preferably, the specific steps of S4 include:

[0031] S401, specify the size of the cluster according to the logical characteristics and fan-out constraints, denoted as Num;

[0032] S402. Calculate the number of initial clusters: For each register in the candidate register list final_reg_list, calculate the relationship between the number of elements Num_ele in the corresponding combination list com_list and the multiple of the cluster size Num, and use the multiple value rounddown (Num_ele / Num) as the initial number of clusters init_cl_num; where rounddown means rounding down;

[0033] S403. Initialize the center coordinates of each cluster: randomly select Num+1 units from the combination list com_list, calculate the mean of their physical positions, and use this as the initial value of the center coordinates of the current cluster; repeat this process init_cl_num times to obtain the initial values ​​of the center coordinates of all clusters;

[0034] S404, initializing clusters: traverse each logical unit in the combination list com_list, calculate the distance between its physical position and the initial value of each cluster center coordinate, and classify the logical unit into the cluster with the closest distance;

[0035] S405, cluster optimization: recalculate the mean of the physical locations of the logical units in each cluster, and use this mean to update the center coordinates of the cluster; repeat this process several times until the benefit brought by the update is lower than a certain set threshold, and then stop the loop;

[0036] S406 , recording cluster information: recording the final cluster number f_cl_num corresponding to each register, and the element list in each cluster.

[0037] Preferably, the specific steps of S5 include:

[0038] S501, for each register in the candidate register list final_reg_list and its corresponding cluster, first disconnect the original connection of each unit input pin in the cluster;

[0039] S502. For each cluster, determine the phase relationship between its phase and the register output: if the cluster is in phase with the register output, insert a buffer between the register output and the cluster, and connect the output of the buffer to the input pin of each unit in the cluster; if the cluster is in anti-phase with the register output, insert an inverter, and connect the output of the inverter to the input pin of each unit in the cluster;

[0040] S503, connecting the input of the inserted buffer or inverter to the register output, and removing other inverter or buffer loads on the register output;

[0041] S504: Save the modified netlist.

[0042] The present invention also discloses a digital circuit optimization system based on logic clustering, comprising a memory and a processor connected to each other, wherein a computer program is stored in the memory, and when the computer program is run by the processor, the steps of the above method are executed.

[0043] Compared with the prior art, the advantages of the present invention are:

[0044] The present invention's digital circuit optimization method based on logic clustering achieves efficient optimization of timing paths through steps such as counting register fan-out information, clustering combinational logic, modifying the netlist, performing equivalence checks, and re-layout and routing. Specifically, the present invention first comprehensively counts the register fan-out information in the circuit netlist, accurately identifying the number and distribution of logic units driven by each register; based on this data, a list of candidate registers is further generated to screen out those registers that have a significant impact on the timing path. This process not only accurately locates critical timing paths but also provides clear targets for subsequent optimization operations.

[0045] During the optimization process, the present invention avoids the common resource waste and signal delay problems in traditional methods by rationally arranging the insertion positions of inverters or buffers. For example, in some traditional optimization methods, the insertion of buffers or inverters is often not targeted, which may lead to unnecessary resource occupation or introduce additional delays. However, by analyzing the fan-out information and timing path length of the register, the present invention can accurately insert inverters or buffers according to actual needs, thereby effectively improving the signal driving capability and transmission quality without adding additional delay, and significantly improving the timing optimization effect.

[0046] In summary, the digital circuit optimization method based on logic clustering of the present invention can accurately identify key timing paths by counting register fan-out information and generating a list of candidate registers, and reasonably arrange the insertion position of inverters or buffers to avoid resource waste and signal delay problems, thereby improving the timing optimization effect. The present invention reasonably clusters related logic units through logic clustering, netlist modification and re-layout wiring, and drives them nearby in the physical layout, which can effectively reduce the length of the timing path and optimize the timing performance of the circuit. Compared with traditional timing optimization methods, the present invention has higher efficiency and better optimization effect, and is particularly suitable for large-scale integrated circuit design.

[0047] This invention addresses two major flaws in existing commercial EDA tools for processing large fan-out registers: improper inverter / buffer insertion placement and neglect of physical layout. This method precisely identifies optimization targets and prioritizes large fan-out registers (final_reg_list) that significantly impact timing through fan-out statistics and critical path screening, thus avoiding resource waste. This method combines physical layout with logical clustering, clustering logic cells based on their physical location to shorten interconnect distances, reduce signal propagation delays, and minimize routing congestion risks. Furthermore, when inserting buffers / inverters, it removes redundant loads, balances drive capabilities, and improves signal integrity.

[0048] This invention ensures functional consistency of optimized circuits through equivalence checking, avoids the introduction of logical errors, and achieves high reliability. The digital circuit optimization method and system based on logic clustering support integration with mainstream EDA tools and are suitable for large-scale circuit design. Implementing this method on a core module in a sub-20nm process reduced the maximum setup timing violation by 11ps and the number of timing violations by 11.1%, significantly improving design performance. This method also has the advantage of being scalable to other optimization scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 A flowchart of a digital circuit optimization method based on logic clustering is provided for an embodiment of the present invention.

[0050] Figure 2 A flowchart of obtaining register fan-out first-level combinational logic information provided by an embodiment of the present invention.

[0051] Figure 3 This is a flowchart of the first-level combinational logic clustering provided by an embodiment of the present invention.

[0052] Figure 4 This is a flow chart of modifying a netlist after clustering provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0053] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0054] like Figure 1 As shown, the digital circuit optimization method based on logic clustering provided by the embodiment of the present invention includes the following steps:

[0055] S1. Count register fan-out information: Count the fan-out information of all registers in the circuit netlist, that is, the number of all subsequent logic units directly driven by the register output signal or indirectly driven across inverters and buffers, and generate a fan-out information table;

[0056] S2. Generate a candidate register list: Based on the fan-out information of all registers counted in S1, screen out registers that have a greater impact on the timing path (registers with a fan-out number greater than a first preset threshold, a number of logic levels greater than a second preset threshold, and located on the critical path), and generate a candidate register list final_reg_list. The candidate register list final_reg_list includes elements such as register name, register fan-out number, timing path length, and whether it is located on the critical path.

[0057] S3. Obtain register fan-out first-level combinational logic information: For each register in the candidate register list final_reg_list, obtain its fan-out first-level combinational logic information; the first-level combinational logic refers to the combinational logic unit directly driven by the register output signal and indirectly driven across the inverter / buffer;

[0058] S4, first-level combination logic clustering: Based on the first-level combination logic information obtained in S3, the logical units are clustered. The clustering algorithm divides physically adjacent logical units into the same cluster according to their physical location relationship. The clustered logical units can be treated as a whole to facilitate subsequent optimization operations.

[0059] S5. Modify the netlist after clustering: After completing the logic clustering, modify the circuit netlist; associate the clustered logic units together and adjust their connection relationships; the netlist modification can reduce the physical distance of the timing path, thereby optimizing the timing performance of the circuit;

[0060] S6. Equivalence check: After the netlist modification is complete, an equivalence check is performed to ensure that the modified circuit functions the same as the original circuit. Equivalence checking is performed using formal verification or simulation tools to ensure that the optimization operation does not introduce functional errors. If inconsistencies are found, return to step S5 to correct the connection relationship.

[0061] S7. Re-place and route: Finally, the circuit is re-placed and routed based on the modified netlist. Re-place and route includes steps such as placement, clock tree synthesis, global routing, and detailed routing. During placement, the buffers / inverters inserted in step S5 must not be optimized. All other steps remain the same as before.

[0062] In this embodiment, the specific steps of step S1 include:

[0063] S101, traverse all registers in the circuit and record the output signal of each register;

[0064] S102, analyzing the logic units driven by each output signal, including the combinational logic unit, the inverter unit, and the buffer unit, adding the combinational logic unit to the combination list com_list, and adding the inverter unit and the buffer unit to the inverter and buffer unit list inv_buf_list;

[0065] S103. Find other combinational logic units driven by the inverter unit and the buffer unit. For each inverter unit and buffer unit in inv_buf_list, sequentially search for all combinational logic units directly driven by their output signals and all combinational logic units driven across inverter units or buffer units, and add these combinational logic units to the combination list com_list.

[0066] S104 , counting the number of combinational logic units fanned out by each register in the combination list com_list, and generating a fan-out information table.

[0067] In this embodiment, the specific steps of step S2 include:

[0068] S201, set a threshold for the fan-out number, filter out registers whose fan-out number is greater than the threshold, and form an initial candidate register list init0_reg_list;

[0069] S202 , analyzing the length of the timing path, filtering out registers on the long path whose logic levels exceed a preset threshold from the candidate register list init0_reg_list, and forming a new candidate register list init1_reg_list;

[0070] S203 , analyze the timing information of each register in the new candidate register list init1_reg_list, determine whether each register in init1_reg_list is in the critical path (if the timing path slack value is negative, the register is determined to be in the critical path), select the registers on the critical path, and thus determine the final candidate register list final_reg_list.

[0071] like Figure 2 As shown, the specific steps of step S3 include:

[0072] S301. Traverse the candidate register list final_reg_list, obtain the output signal of each register, analyze the logic unit driven by each output signal, including the combinational logic unit, inverter unit, and buffer unit, add the combinational logic unit to the combination list com_list, and add the inverter unit and buffer unit to inv_buf_list;

[0073] S302. Find other combinational logic units driven by the inverter unit and the buffer unit. For each inverter unit and buffer unit in inv_buf_list, sequentially search for all combinational logic units directly driven by their output signals and all combinational logic units driven across inverters or buffers, and add these combinational logic units to the combination list com_list.

[0074] S303: Count the number of combinational logic units fanned out by each register in the combination list com_list in step S302 and generate a fan-out information table. For each register in the combination list com_list, record the type, connected pins pin, and physical location information loc of each first-level combinational logic unit.

[0075] like Figure 3 As shown, the specific steps of step S4 include:

[0076] S401: According to the logic characteristics and fan-out constraints, the size of the cluster is specified, which is recorded as Num. In this embodiment, in order to ensure that the constraints such as timing and electromigration are comprehensively considered, the cluster size is set to 24.

[0077] S402. Calculate the number of initial clusters: For each register in the candidate register list final_reg_list, calculate the relationship between the number of elements Num_ele in the corresponding com_list and the multiple of the cluster size Num, and use the multiple value rounddown (Num_ele / Num) as the initial number of clusters init_cl_num, where rounddown means rounding down.

[0078] S403, initialize the center coordinates of each cluster: randomly select Num+1 units from com_list, calculate the mean of their physical positions, and use this as the initial value of the center coordinates of the current cluster; repeat the above process init_cl_num times to obtain the initial values ​​of the center coordinates of all clusters;

[0079] S404, initializing clusters: traverse each unit in com_list, calculate the distance between its physical position and the initial value of each cluster center coordinate, and classify the unit into the cluster with the closest distance;

[0080] S405, cluster optimization: recalculate the mean of the physical locations of the logical units in each cluster, and use this mean to update the center coordinates of the cluster; repeat this process several times until the benefit brought by the update is lower than a certain set threshold, and then stop the loop;

[0081] S406 , recording cluster information: recording the final cluster number f_cl_num corresponding to each register, and the element list in each cluster.

[0082] like Figure 4 As shown, the specific steps of step S5 include:

[0083] S501, for each register in the candidate register list final_reg_list and its corresponding cluster, first disconnect the original connection of each unit input pin in the cluster;

[0084] S502. For each cluster, determine the phase relationship between its phase and the register output: if the cluster is in phase with the register output, insert a buffer between the register output and the cluster, and connect the output of the buffer to the input pin of each unit in the cluster; if the cluster is in anti-phase with the register output, insert an inverter, and connect the output of the inverter to the input pin of each unit in the cluster;

[0085] S503, connecting the input of the inserted buffer or inverter to the register output, and removing other inverter or buffer loads on the register output;

[0086] S504: Save the modified netlist.

[0087] The present invention's digital circuit optimization method based on logic clustering achieves efficient optimization of timing paths through steps such as counting register fan-out information, clustering combinational logic, modifying the netlist, performing equivalence checks, and re-layout and routing. Specifically, the present invention first comprehensively counts the register fan-out information in the circuit netlist, accurately identifying the number and distribution of logic units driven by each register; based on this data, a list of candidate registers is further generated to screen out those registers that have a significant impact on the timing path. This process not only accurately locates critical timing paths but also provides clear targets for subsequent optimization operations.

[0088] During the optimization process, the present invention avoids the common resource waste and signal delay problems in traditional methods by rationally arranging the insertion positions of inverters or buffers. For example, in some traditional optimization methods, the insertion of buffers or inverters is often not targeted, which may lead to unnecessary resource occupation or introduce additional delays. However, by analyzing the fan-out information and timing path length of the register, the present invention can accurately insert inverters or buffers according to actual needs, thereby effectively improving the signal driving capability and transmission quality without adding additional delay, and significantly improving the timing optimization effect.

[0089] In summary, the digital circuit optimization method based on logic clustering of the present invention can accurately identify key timing paths by counting register fan-out information and generating a list of candidate registers, and reasonably arrange the insertion position of inverters or buffers to avoid resource waste and signal delay problems, thereby improving the timing optimization effect. The present invention reasonably clusters related logic units through logic clustering, netlist modification and re-layout wiring, and drives them nearby in the physical layout, which can effectively reduce the length of the timing path and optimize the timing performance of the circuit. Compared with traditional timing optimization methods, the present invention has higher efficiency and better optimization effect, and is particularly suitable for large-scale integrated circuit design.

[0090] This invention addresses two major flaws in existing commercial EDA tools for processing large fan-out registers: improper inverter / buffer insertion placement and neglect of physical layout. This method precisely identifies optimization targets and prioritizes large fan-out registers (final_reg_list) that significantly impact timing through fan-out statistics and critical path screening, thus avoiding resource waste. This method combines physical layout with logical clustering, clustering logic cells based on their physical location to shorten interconnect distances, reduce signal propagation delays, and minimize routing congestion risks. Furthermore, when inserting buffers / inverters, it removes redundant loads, balances drive capabilities, and improves signal integrity.

[0091] This invention ensures functional consistency of optimized circuits through equivalence checking, avoids the introduction of logical errors, and achieves high reliability. The digital circuit optimization method and system based on logic clustering support integration with mainstream EDA tools and are suitable for large-scale circuit design. Implementing this method on a core module in a sub-20nm process reduced the maximum setup timing violation by 11ps and the number of timing violations by 11.1%, significantly improving design performance. This method also has the advantage of being scalable to other optimization scenarios.

[0092] An embodiment of the present invention further provides a digital circuit optimization system based on logical clustering, comprising an interconnected memory and a processor, wherein the memory stores a computer program that, when executed by the processor, performs the steps of the above-described method. The optimization system of the present invention corresponds to the above-described optimization method and similarly possesses the advantages described for the above-described optimization method. The present invention can also implement all or part of the processes in the above-described method embodiments through hardware associated with computer program instructions. The computer program can be stored in a computer-readable storage medium, which, when executed by the processor, can implement the steps of the above-described method embodiments. The computer program includes computer program code, which can be in source code form, object code form, executable file, or some intermediate form. Computer-readable storage media include any entity or device capable of carrying computer program code, recording media, USB flash drives, removable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunications signals, and software distribution media. The memory is used to store computer programs and / or modules. The processor implements various functions by running or executing the computer programs and / or modules stored in the memory, as well as accessing data stored in the memory. The memory may include high-speed random access memory (RAM) and non-volatile memory, such as a hard disk, internal memory, a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a flash memory card, at least one disk storage device, a flash memory device, or other volatile solid-state storage device.

[0093] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions based on the principles of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A digital circuit optimization method based on logic clustering, characterized in that: Including steps: S1. Count register fan-out information: Count the fan-out information of all registers in the circuit netlist, that is, the number of all subsequent logic units directly driven by the register output signal or indirectly driven across inverters and buffers, and generate a fan-out information table; S2. Generate a candidate register list: Based on the fan-out information of all registers, select registers whose fan-out number is greater than a first preset threshold, whose logic level is greater than a second preset threshold, and which are located on the critical path, and generate a candidate register list final_reg_list; S3. Obtain register fan-out first-level combinational logic information: For each register in the candidate register list final_reg_list, obtain its fan-out first-level combinational logic information; the first-level combinational logic refers to the combinational logic unit directly driven by the register output signal and indirectly driven across the inverter / buffer; S4, first-level combination logic clustering: Based on the first-level combination logic information obtained in S3, the logical units are clustered: physically adjacent logical units are divided into the same cluster according to the physical location relationship of the logical units; S5. Modify the netlist after clustering: After completing the logic clustering, modify the netlist of the circuit, that is, associate the clustered logic units together and adjust their connection relationships; S6, equivalence check: After the netlist modification is completed, an equivalence check is performed to ensure that the modified circuit function is consistent with the original circuit; if the equivalence check passes, proceed to the next step; otherwise, return to step S5 to correct the connection relationship; S7, re-layout and routing: re-layout and routing the circuit according to the modified netlist; The specific steps of S3 include: S301. Traverse the candidate register list final_reg_list, obtain the output signal of each register, analyze the logic unit driven by each output signal, including the combinational logic unit, inverter unit, and buffer unit, add the combinational logic unit to the combination list com_list, and add the inverter unit and buffer unit to inv_buf_list; S302. Find other combinational logic units driven by the inverter unit and the buffer unit. For each inverter unit and buffer unit in inv_buf_list, sequentially search for all combinational logic units directly driven by their output signals and all combinational logic units driven across inverters or buffers, and add these combinational logic units to the combination list com_list. S303, counting the number of combinational logic units fanned out by each register in the combination list com_list of step S302, and generating a fan-out information table; The specific steps of S4 include: S401, specify the size of the cluster according to the logical characteristics and fan-out constraints, denoted as Num; S402. Calculate the number of initial clusters: For each register in the candidate register list final_reg_list, calculate the relationship between the number of elements Num_ele in the corresponding combination list com_list and the multiple of the cluster size Num, and use the multiple value rounddown (Num_ele / Num) as the initial number of clusters init_cl_num; where rounddown means rounding down; S403. Initialize the center coordinates of each cluster: randomly select Num+1 units from the combination list com_list, calculate the mean of their physical positions, and use this as the initial value of the center coordinates of the current cluster; repeat this process init_cl_num times to obtain the initial values ​​of the center coordinates of all clusters; S404, initializing clusters: traverse each logical unit in the combination list com_list, calculate the distance between its physical position and the initial value of each cluster center coordinate, and classify the logical unit into the cluster with the closest distance; S405, cluster optimization: recalculate the mean of the physical locations of the logical units in each cluster, and use this mean to update the center coordinates of the cluster; repeat this process several times until the benefit brought by the update is lower than a certain set threshold, and then stop the loop; S406 , recording cluster information: recording the final cluster number f_cl_num corresponding to each register, and the element list in each cluster.

2. The digital circuit optimization method based on logic clustering according to claim 1, characterized in that: The specific steps of S1 include: S101, traverse all registers in the circuit netlist and record the output signal of each register; S102, analyzing the logic units driven by each output signal, including the combinational logic unit, the inverter unit, and the buffer unit, adding the combinational logic unit to the combination list com_list, and adding the inverter unit and the buffer unit to the inverter and buffer unit list inv_buf_list; S103. Find other combinational logic units driven by the inverter unit and the buffer unit. For each inverter unit and buffer unit in inv_buf_list, sequentially search for all combinational logic units directly driven by their output signals and all combinational logic units driven across inverters or buffers, and add these combinational logic units to the combination list com_list. S104 , counting the number of combinational logic units fanned out by each register in the combination list com_list in step S103 , and generating a fan-out information table.

3. The digital circuit optimization method based on logic clustering according to claim 1, characterized in that: The specific steps of S2 include: S201, set a threshold for the fan-out number, filter out registers whose fan-out number is greater than the threshold, and form an initial candidate register list init0_reg_list; S202 , screening out registers on the long path whose logic levels exceed a preset threshold from the candidate register list init0_reg_list to form a new candidate register list init1_reg_list; S203 , analyzing the timing information of each register in the new candidate register list init1_reg_list, determining whether each register in init1_reg_list is in the critical path, selecting registers on the critical path, and thereby determining the final candidate register list final_reg_list.

4. The digital circuit optimization method based on logic clustering according to claim 3, characterized in that: The candidate register list final_reg_list includes one or more elements such as register name, register fan-out number, timing path length, and whether the register is in a critical path.

5. The digital circuit optimization method based on logic clustering according to any one of claims 1 to 4, characterized in that: The specific steps of S5 include: S501, for each register in the candidate register list final_reg_list and its corresponding cluster, first disconnect the original connection of each unit input pin in the cluster; S502. For each cluster, determine the phase relationship between its phase and the register output: if the cluster is in phase with the register output, insert a buffer between the register output and the cluster, and connect the output of the buffer to the input pin of each unit in the cluster; if the cluster is in anti-phase with the register output, insert an inverter, and connect the output of the inverter to the input pin of each unit in the cluster; S503, connecting the input of the inserted buffer or inverter to the register output, and removing other inverter or buffer loads on the register output; S504: Save the modified netlist.

6. A digital circuit optimization system based on logic clustering, comprising a memory and a processor connected to each other, wherein a computer program is stored in the memory, characterized in that: When the computer program is executed by a processor, the computer program performs the steps of the method according to any one of claims 1 to 5.

Images