Interface circuit design method based on artificial intelligence

Abstract

The invention provides an artificial intelligence-based interface circuit design method, which comprises the following steps of: S1, acquiring an RTL code for describing a logic structure of a digital circuit, and generating a digital circuit layout according to the RTL code by utilizing a preset neural network model; s2, acquiring a preset process library and design parameters of the analog circuit, and generating an analog circuit layout by using a preset neural network model according to the process library and the design parameters of the analog circuit; and S3, fusing the digital circuit layout and the analog circuit layout by using a preset neural network model to obtain the layout of the interface circuit.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit (IC) design, specifically to the field of chip interface circuit design, and more specifically, to an artificial intelligence-based interface circuit design method. Background Art

[0002] With the wide application of Chiplet technology, the importance of interface circuits has become increasingly prominent. The high-speed communication and low-latency requirements between Chiplets make the design of interface circuits a key factor in the performance of the entire system. The traditional manual design process not only requires a large amount of time and effort but is also error-prone. Especially in the scenario of multi-Chiplet integration, the complexity of interface circuits further increases.

[0003] Existing Electronic Design Automation (EDA) tools can assist in the design process, but designers still need to manually write a large number of scripts and configuration files. Especially when dealing with complex interface protocols and signal integrity issues, the frequency of manual adjustment is extremely high, resulting in an extended design cycle. It can be seen that when designers use EDA tools to complete the design work, although it can play a certain auxiliary design function, a large amount of time cost still needs to be paid, resulting in low efficiency in the current interface circuit design.

[0004] It should be noted that: This background art is only used to introduce relevant information of the present invention to facilitate understanding of the technical solution of the present invention, but it does not mean that the relevant information is necessarily prior art. The relevant information is submitted and disclosed together with the solution of the present invention. Without evidence indicating that the relevant information was publicly available before the filing date of the present invention, the relevant information should not be regarded as prior art. Summary of the Invention

[0005] Therefore, the object of the present invention is to overcome the above-mentioned defects of the prior art and provide an artificial intelligence-based interface circuit design method.

[0006] The object of the present invention is achieved by the following technical solutions:

[0007] According to the first aspect of the present invention, there is provided an artificial intelligence-based interface circuit design method, including: Step S1: Obtain RTL code for describing the logical structure of a digital circuit, and use a preset neural network model to generate a digital circuit layout based on the RTL code; Step S2: Obtain a preset process library and design parameters of an analog circuit, and use a preset neural network model to generate an analog circuit layout based on the process library and the design parameters of the analog circuit; Step S3: Use a preset neural network model to fuse the digital circuit layout and the analog circuit layout to obtain the layout of the interface circuit.

[0008] Optionally, step S1 includes: generating RTL code using a neural network model according to a preset template of an interface circuit and design parameters of a digital circuit input by a user; generating an automated test vector and a script for calling a simulation tool for the generated RTL code using the neural network model; calling a logic simulation tool using the script for calling the simulation tool to perform simulation testing and optimization according to the automated test vector to obtain optimized RTL code; calling a logic synthesis tool to convert the optimized RTL code into a digital circuit netlist; and sequentially completing layout planning, clock tree generation, and routing according to the digital circuit netlist and design constraints of the digital circuit to obtain a digital circuit layout.

[0009] Optionally, the RTL code is code input by the user or code generated using a neural network model according to a preset template of an interface circuit and design parameters of a digital circuit input by the user.

[0010] Optionally, step S2 includes: obtaining design parameters of an analog circuit, an analog circuit netlist, and a process library; performing module and device layout according to the analog circuit netlist and the process library to obtain an initial layout of the analog circuit; and optimizing devices in the initial layout of the analog circuit according to the design parameters of the analog circuit.

[0011] Optionally, the design parameters of the analog circuit include: power supply voltage, current limit, signal swing, transmission rate, and load matching requirements. Among them, optimizing the devices in the initial layout of the analog circuit includes: adjusting the bias current of the bias circuit according to the power supply voltage and current limit; adjusting the size and operating point of the differential pair transistors according to the signal swing; and adjusting the cut-off frequency and bandwidth of the filter according to the transmission rate and load matching requirements.

[0012] Optionally, step S3 includes: obtaining multiple constraint conditions for the merged layout, and using a preset neural network model to merge the digital circuit layout and the analog circuit layout on the basis of considering the multiple constraint conditions to obtain a layout of the interface circuit.

[0013] Optionally, the multiple constraint conditions include: an anti-interference constraint, which indicates a constraint condition for preventing signal interference between the digital circuit layout and the analog circuit layout; a power consumption management constraint, which indicates the total power consumption budget and the power consumption budget of each functional module within the digital circuit layout and the analog circuit layout; and / or a thermal distribution constraint, which indicates a constraint condition related to temperature control of the circuit.

[0014] According to a second aspect of the present invention, there is provided an electronic device, comprising: one or more processors; and a memory, wherein the memory is used to store executable instructions; the one or more processors are configured to implement the steps of the method described in the first aspect by executing the executable instructions. Description of the Drawings

[0015] The embodiments of the present invention will be further described below with reference to the drawings, where:

[0016] Figure 1 It is a schematic flow chart of a method for designing an interface circuit based on artificial intelligence according to an embodiment of the present invention;

[0017] Figure 2 It is another schematic flow chart of a method for designing an interface circuit based on artificial intelligence according to an embodiment of the present invention;

[0018] Figure 3 It is a schematic flow chart of a method for automatic design of a digital circuit according to an embodiment of the present invention;

[0019] Figure 4 It is a schematic diagram of an automatic design process of an analog part of an interface circuit according to an embodiment of the present invention. Detailed Embodiments

[0020] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the drawings through specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0021] As mentioned in the background art section, when designers use EDA tools to complete design work, although it can play a certain auxiliary design function, a large amount of time cost still needs to be paid, resulting in low current interface circuit design efficiency. After analysis, the inventor believes that although existing tools can assist in design to a certain extent, they have deficiencies in the following aspects: (1) Low automation level: The existing EDA tools have a low automation level in interface circuit design and cannot achieve full-process automation from parameter input to layout generation. Designers still need to manually write a large number of scripts and configuration files. Especially when dealing with complex interface protocols and signal integrity issues, the frequency of manual adjustment is extremely high, resulting in an extended design cycle. (2) Poor flexibility: Existing Register Transfer Level (RTL) code generation tools lack flexibility and cannot automatically generate optimized RTL code according to different application scenarios. For example, when data is transferred between different types of dielets, the timing requirements, power consumption budgets, and bandwidth requirements of the interface circuit are different, and existing tools are difficult to automatically adapt to these changes, resulting in low design efficiency. (3) High complexity: The backend design process (such as placement and routing, clock tree synthesis, etc.) needs to be completed by human engineers with rich experience and professional knowledge, and the automation level is limited. Especially when dealing with multi-dielet integration, how to ensure signal integrity, power management, and thermal distribution between dielets poses higher requirements for engineers. Existing tools lack support for these issues, resulting in a huge amount of debugging and verification work during the design process. In response to this, the method of the present invention uses a neural network model to design the digital circuit layout and the analog circuit layout respectively, and finally performs layout fusion to obtain the layout of the interface circuit to be determined, thereby improving the design efficiency of the interface circuit and promoting the faster development of the industry.

[0022] Referring to Figure 1 , there is provided an interface circuit design method based on artificial intelligence, including step S1: obtaining RTL code for describing the logical structure of a digital circuit, and using a preset neural network model to generate a digital circuit layout according to the RTL code; step S2: obtaining a preset process library and design parameters of an analog circuit, and using a preset neural network model to generate an analog circuit layout according to the process library and the design parameters of the analog circuit; and / or step S3: using a preset neural network model to fuse the digital circuit layout and the analog circuit layout to obtain the layout of the interface circuit.

[0023] According to an embodiment of the present invention, referring to Figure 2, the artificial intelligence-based interface circuit design method includes: pre-tuning and deploying an interface circuit design automation neural network model, and using the neural network model to perform digital circuit layout design, analog circuit layout design, and layout merging, and output the layout of the interface circuit. Among them, the process of digital circuit layout design includes generating RTL code according to the design parameters of the digital circuit and / or generating the layout of the digital part of the interface (i.e., the digital circuit layout) according to the RTL code. The process of analog circuit layout design includes: sequentially performing process library parsing, circuit parameter optimization, and signal integrity optimization according to the design parameters of the analog circuit, and generating the layout of the analog part of the interface (i.e., the analog circuit layout).

[0024] To better understand the present invention, the following will separately describe each step in detail in combination with specific embodiments.

[0025] Step S1: Obtain the RTL code for describing the logical structure of the digital circuit, and use a preset neural network model to generate the digital circuit layout according to the RTL code.

[0026] According to an embodiment of the present invention, the RTL code is generated by a neural network model according to the template of the preset interface circuit and the design parameters of the digital circuit input by the user. Step S1 includes: generating RTL code by a neural network model according to the template of the preset interface circuit and the design parameters of the digital circuit input by the user; using the neural network model to generate an automated test vector and a script for calling a simulation tool for the generated RTL code; the neural network model uses the script for calling the simulation tool to call a logic simulation tool to perform simulation testing and optimization according to the automated test vector to obtain the optimized RTL code; the neural network model calls a logic synthesis tool to convert the optimized RTL code into a digital circuit netlist; the neural network model sequentially completes floorplanning, clock tree generation, and routing according to the digital circuit netlist and the design constraints of the digital circuit to obtain the digital circuit layout.

[0027] According to an embodiment of the present invention, there is provided a method for automatically designing a digital circuit based on a neural network model, which can automatically generate RTL code that meets the requirements according to the design parameters of the digital circuit input by the user, and call the EDA tool chain to complete the subsequent design steps. Schematically, first, the user inputs the design parameters of the digital circuit, which include the parameters of the data link layer and the protocol layer of the interface circuit. The parameters of the data link layer include the number of interface channels, the transmission rate, and the buffer size; the parameters of the protocol layer include the protocols used for each interface. The pre-set neural network model for automatic digital circuit design will automatically generate the corresponding RTL code according to the design parameters input by the user. Moreover, the neural network model can automatically generate test vectors and call a logic simulation tool to verify the correctness of the RTL code. If the RTL code is correct, the neural network model will generate a synthesis script for scheduling the backend tools of the digital integrated circuit, and by executing each script in the synthesis script, schedule the EDA tools integrated in the physical design tool chain to complete logic synthesis, floorplanning, placement, clock tree synthesis, and routing in sequence, and finally output the digital circuit layout; otherwise, the neural network model can correct the RTL code by itself, or indicate the error location and modification suggestions of the RTL code for the user to modify, and use the neural network model to verify the modified RTL code again.

[0028] According to an embodiment of the present invention, referring to Figure 3 , the present invention provides a method for automatically designing a digital circuit based on a neural network model, which can automatically generate RTL code that meets the requirements according to the parameters input by the user, and call the EDA tool chain to complete the subsequent design steps. Schematically, the method for automatically designing the digital circuit includes the following steps:

[0029] (1) Parameter input

[0030] The user inputs the design parameters of the digital circuit, such as the number of interface channels, the transmission rate, the buffer size, the protocols used, etc., through a graphical user interface (GUI) or a command line interface (CLI).

[0031] (2) Generate RTL code

[0032] The neural network model automatically generates corresponding RTL code according to the parameters input by the user. A code library can be preset, which contains RTL code templates for a series of protocols. Select the corresponding template according to the input protocol, and then determine the various parameters in the code template according to the content in the design parameters, so as to generate RTL code. This process includes selecting a suitable template according to the design parameters and instantiating it. Each protocol has a corresponding template. For example, when using Protocol A, use the template corresponding to Protocol A, and then according to the buffer size, transmission rate, and number of channels, the instance of the specific interface can be determined. In addition, the code in the code library can be optimized by human experts or other neural network models to achieve the best balance between performance and power consumption.

[0033] (3)Automated Testing and Verification

[0034] The neural network model generates automated test vectors and scripts for simulation tools, and calls the logic simulation tool for simulation verification to ensure the correctness of the generated RTL code.

[0035] (4)Generate Synthesis Script

[0036] The neural network model automatically generates a synthesis script, calls the synthesis tool, performs logic synthesis and optimization, and generates a digital circuit netlist (Netlist). The synthesis tool will optimize the design according to the constraint conditions specified by the user (such as timing, power consumption, area, etc.) to ensure that the generated netlist meets the design requirements.

[0037] (5)Floorplanning and Optimization

[0038] (a)Floorplanning: The neural network model generates a floorplanning script, calls the physical design tool, and automatically places IP cores and standard cells according to the digital circuit netlist and design requirements to obtain an initial layout. An IP core refers to a pre-designed functional module. It can be relatively small, such as a multiplier, or larger, such as a CPU. A standard cell refers to the basic logic circuit in a digital integrated circuit, such as an AND gate, an OR gate, and a NOT gate. The goal of floorplanning is to optimize the overall layout of the chip, ensure the minimum distance between key modules, and at the same time meet the constraints of timing, power consumption, and area.

[0039] (b)Layout Optimization: The neural network model will optimize the initial layout according to the preset optimization rules to obtain an optimized layout. For example: According to the timing analysis results, automatically adjust the positions of the cells on the critical path in the initial layout to ensure timing convergence. In other words, input the generated timing report into the neural network model, and the neural network model outputs a script to adjust the critical path, and the tool then calls this script to complete this task. Another example is that factors such as signal integrity and parasitic effects can also be considered to optimize the layout to reduce noise interference and signal delay.

[0040] (6) Generate a clock tree synthesis script

[0041] (a)Clock tree generation: The neural network model automatically generates a clock tree synthesis script, calls the physical design tool, and automatically generates a balanced clock tree according to the topology of the clock network (such as H-tree, fishbone tree, etc.). For example: The neural network model inserts buffers based on the physical positions of timing units (such as registers, etc.) in the optimized layout, calculates the optimal path of the clock signal to each timing unit, and generates a clock tree according to the optimal path. The goal of clock tree synthesis is to ensure the uniform distribution of the clock signal throughout the chip, minimizing clock skew and jitter.

[0042] (b)Clock optimization: The neural network model can also automatically adjust the branch structure of the clock tree and the buffer insertion position according to the timing analysis results to ensure the stability and reliability of the clock signal. In addition, according to power consumption optimization, the dynamic power consumption of the clock tree can be reduced.

[0043] (7)Generate a routing script

[0044] (a)Global routing: The neural network model automatically generates a global routing script, calls the physical design tool, and automatically divides the metal layers according to the design requirements to determine the path of the interconnecting wires. The goal of global routing is to provide a preliminary routing scheme for subsequent detailed routing and ensure the priority of critical signal paths.

[0045] (b)Detailed routing: The neural network model automatically generates a detailed routing script, calls the physical design tool, and determines the position of each interconnecting wire according to the result of global routing. The goal of detailed routing is to ensure the correct connection of all signal paths while meeting the requirements of timing, power consumption, and signal integrity.

[0046] (8)Generate a layout script for the digital circuit layout, automatically generate a layout output script, call the physical design tool, and export the final physical design data in a standard format (such as GDSII or OASIS). The generated layout file can be used for subsequent manufacturing to ensure the manufacturability of the design.

[0047] (9)Generate DRC / LVS scripts

[0048] The neural network model generates DRC (Design Rule Check) / LVS (Layout Versus Schematic) scripts to call DRC and LVS checks.

[0049] (a)DRC check: The neural network model automatically generates a DRC check script, calls the design rule check tool, and verifies whether the generated layout meets the requirements of the manufacturing process. The goal of DRC check is to ensure that the geometries, spacings, widths, etc. in the layout conform to the process rules and avoid defects during the manufacturing process.

[0050] (b)LVS check: The neural network model automatically generates an LVS check script, calls the layout versus schematic comparison tool, and verifies whether the generated layout is consistent with the original circuit principle. Figure 1 The goal of LVS check is to ensure that the network connections in the layout exactly match the logical connections in the schematic and avoid design errors.

[0051] (c)Repair suggestions: If any problems are found in the DRC or LVS check, the neural network model will generate a detailed error report and provide repair suggestions to help users quickly solve the problems.

[0052] According to another embodiment of the present invention, the RTL code can also be the code input by the user. In some cases, the RTL code can be pre-designed and input by the user. Subsequently, the back-end design of the chip is completed using the method of the present invention.

[0053] Step S2: Obtain the preset process library and the design parameters of the analog circuit, and use the preset neural network model to generate the analog circuit layout according to the process library and the design parameters of the analog circuit.

[0054] According to an embodiment of the present invention, step S2 includes: obtaining the design parameters of the analog circuit, the analog circuit netlist, and the process library; performing module and device layout according to the analog circuit netlist and the process library to obtain the initial analog circuit layout; and optimizing the devices in the initial analog circuit layout according to the design parameters of the analog circuit.

[0055] According to an embodiment of the present invention, the design parameters of an analog circuit include: power supply voltage, current limit, signal swing, transmission rate, and load matching requirements. Among them, optimizing the devices in the initial layout of the analog circuit includes: adjusting the bias current of the bias circuit according to the power supply voltage and current limit; adjusting the size and operating point of the differential pair transistors according to the signal swing; adjusting the cut-off frequency and bandwidth of the filter according to the transmission rate and load matching requirements. Traditional analog circuit design relies on experienced engineers to manually adjust parameters and optimize the circuit structure, which is not only time-consuming but also error-prone. The present invention automatically generates scripts for EDA tools through a neural network model, realizing the full-process automation of analog circuit design, significantly improving the design efficiency and ensuring the quality and consistency of the design. First, the user inputs the parameters of the physical layer of the interface circuit, including transmission rate, signal swing, power supply voltage, current limit, load matching requirements, etc., and imports the layout of the analog circuit and the process library used. A neural network model dedicated to the automation of analog circuit design will automatically parse the process library and, according to the parameters input by the user, automatically optimize the key parameters of the analog circuit and determine the size of each transistor in the circuit. Then, according to the number of metal layers and parasitic effects in the process library, the appropriate metal layer is automatically selected for wiring, and constraints such as noise, signal delay, and thermal effects are considered, and finally a reliable layout file is generated.

[0056] According to an embodiment of the present invention, the design of the analog part (physical layer) of the interface circuit is a crucial part of the interface circuit, especially in high-speed and high-precision application scenarios. Traditional analog circuit design relies on experienced engineers to manually adjust parameters and optimize the circuit structure, which is not only time-consuming but also error-prone. The present invention automatically generates scripts for EDA tools through a neural network model, realizing the full-process automation of analog circuit design, significantly improving the design efficiency and ensuring the quality and consistency of the design. Schematically, the schematic diagram of the automated design process of the analog part of the interface circuit is as Figure 4 shown, including:

[0057] (1) The user inputs the design parameters, netlist, and process library of the analog circuit

[0058] Input the design parameters of the analog circuit. For example, the user inputs the parameters of the physical layer of the interface through the GUI or CLI input interface and imports the analog circuit netlist file. The parameters of the physical layer of the interface such as transmission rate, signal swing, power supply voltage, current limit, load matching requirements, etc. The design parameters will directly affect the design of the analog circuit. The process library contains standard cells, device models, parasitic parameter extraction rules, and design rule check files. Among them, standard cells are a set of pre-designed circuit modules with fixed functions, used to build digital integrated circuits. Standard cells include basic logic gates (such as AND gates, OR gates, NOT gates, etc.), flip-flops, multiplexers, etc. Device models are mathematical models that describe the electrical characteristics of semiconductor devices (such as transistors, diodes, resistors, capacitors, etc.). Parasitic parameter extraction rules are rules used to guide the extraction of various parameters (resistance, capacitance, delay, etc.) of the circuit from the layout. The parameters extracted by the parasitic parameter extraction rules can be used as the input for subsequent simulations. The design rule check (DRC) file contains multiple rules (requirements) that the numerical circuit layout needs to meet, such as the minimum distance between two connections, the maximum fan-out of a gate circuit, etc.

[0059] (2)Process library parsing

[0060] The user selects the required process library through the graphical user interface (GUI) or command line interface (CLI). A process library parsing script can be generated by the neural network model and called by the process library parsing tool to complete.

[0061] (3)Circuit parameter optimization

[0062] The neural network model generates an initial circuit based on the design parameters input by the user and automatically adjusts the sizes of the transistors in the circuit to obtain the circuit optimized for the first time. For example, the neural network model will adjust the bias current of the bias circuit according to the power supply voltage and current limit; adjust the sizes and operating points of the differential pair transistors according to the signal swing. The neural network model will adjust the cut-off frequency and bandwidth of the filter according to the transmission rate and load matching requirements; optimize the resistance and capacitance values of the feedback network according to the noise requirements.

[0063] (4)Signal integrity optimization

[0064] The neural network model performs signal integrity optimization on the circuit optimized for the first time to obtain the circuit optimized for the second time. For example: Automatically adjust the length and width of the interconnects in the circuit optimized for the first time according to the influence of signal integrity and parasitic effects to reduce crosstalk and reflection. In addition, the neural network model will also optimize the layout of the power supply and ground wires to ensure the power supply stability and noise immunity of the analog circuit.

[0065] (5)Generate the layout of the analog circuit

[0066] Based on the circuit after the second optimization, the neural network model automatically selects appropriate metal layers for routing according to the number of metal layers and parasitic effects in the process library, and generates an analog circuit layout file. For critical signal paths, the neural network model is configured to preferentially select metal layers with low resistance and low inductance to reduce signal delay and noise interference. Automatically optimize the layout of power and ground lines to ensure the power supply stability and noise immunity of the analog circuit. The neural network model reasonably allocates the width and spacing of power and ground lines according to power consumption requirements and noise sensitivity to avoid power fluctuations. In addition, the neural network model can also be configured to automatically adjust the positions of key components based on the influence of thermal effects to ensure uniform heat distribution. For high-power components, the neural network model increases the heat dissipation path to avoid performance degradation or reliability issues caused by overheating. Finally, an analog circuit layout file (such as a GDSII layout file) is generated.

[0067] (6)DRC and LVS checks

[0068] DRC check: The neural network model automatically generates a DRC check script and calls the design rule check tool to verify whether the generated layout meets the requirements of the manufacturing process. The goal of the DRC check is to ensure that the geometries, spacings, widths, etc. in the layout conform to the process rules and avoid defects during the manufacturing process.

[0069] LVS check: The neural network model automatically generates an LVS check script and calls the layout versus schematic comparison tool to verify whether the generated layout is consistent with the original circuit principle Figure 1 match. The goal of the LVS check is to ensure that the network connections in the layout exactly match the logical connections in the schematic and avoid design errors.

[0070] The neural network model can provide repair suggestions based on the results of DRC and LVS checks. For example, if any problems are found in the DRC or LVS check, the neural network model will generate a detailed error report and provide repair suggestions to help designers quickly solve the problems. The system will also automatically generate a corrected layout file to ensure the correctness and manufacturability of the design.

[0071] Step S3: Use a preset neural network model to fuse the digital circuit layout and the analog circuit layout to obtain the layout of the interface circuit.

[0072] According to an embodiment of the present invention, step S3 includes: obtaining a plurality of constraint conditions for the merged layout, and using a preset neural network model to merge the digital circuit layout and the analog circuit layout on the basis of considering the plurality of constraint conditions to obtain the layout of the interface circuit. After the neural network model obtains the digital circuit layout and the analog circuit layout of the interface, it will automatically call an EDA tool to merge the two layouts to form a complete die interface circuit layout. This process not only requires high-precision interconnect design, but also needs to ensure the optimization of signal integrity, power management, and thermal distribution.

[0073] According to an embodiment of the present invention, the plurality of constraint conditions include: an anti-interference constraint, which indicates a constraint condition for preventing signal interference between the digital circuit layout and the analog circuit layout; a power management constraint, which indicates the total power consumption budget and the power consumption budgets of each functional module within the digital circuit layout and the analog circuit layout; and / or a thermal distribution constraint, which indicates a constraint condition related to the temperature control of the circuit. In an artificial intelligence-based automated interface circuit design system, the merging of the digital circuit layout and the analog circuit layout is a crucial step. As the process nodes continue to shrink, the interface layout design becomes increasingly complex, and the elements to be considered in the layout merging process are also increasing. Especially for high-speed interfaces and low-noise analog signals, any minor layout or wiring errors may lead to performance degradation or functional failure. Therefore, the layout merging process must comprehensively consider the following key elements: Signal integrity: Ensure that there is no interference between digital signals and analog signals, especially between high-speed differential signals and sensitive analog signals, and avoid reflection, crosstalk, and noise problems. Power management: Optimize the layout of power and ground lines, ensure reasonable power consumption distribution between different modules, and reduce the impact of dynamic power consumption and static power consumption, especially in the scenario of multi-die integration. Thermal distribution: Through reasonable heat dissipation path design and heat sink layout, ensure that the temperature of the chip under high load is controlled within a safe range, and avoid performance degradation or reliability problems caused by overheating.

[0074] According to an embodiment of the present invention, the above neural network model can be obtained by fine-tuning a publicly available pre-trained large model with knowledge related to integrated circuits, the user manuals of various tools, and / or a large amount of script code. Alternatively, the implementer can also design the structure of the neural network model by himself, and then train it with knowledge related to integrated circuits, the user manuals of various tools, and / or a large amount of script code. In addition, the neural network model can have different sub-models or functional branches to respectively predict the design of different parts of the interface circuit. [[ID=⑧]]

[0075] Generally speaking, the present invention utilizes a pre-trained neural network model, comprehensively considers the above constraints, efficiently combines the layout of the digital part (data link layer, protocol layer) and the analog part (physical layer) of the interface, outputs the layout of the final interface circuit, and has excellent performance in ensuring interface functions, power consumption, signal integrity, and anti-interference ability. A full-process automated interface circuit method based on a neural network model provided by the present invention solves the problems of low automation degree, poor flexibility, and high complexity in the existing design process, and improves the efficiency of interface circuit design.

[0076] It should be noted that although the above steps are described in a specific order, it does not mean that the steps must be executed in the above specific order. In fact, some of these steps can be executed concurrently or even the order can be changed, as long as the required functions can be achieved.

[0077] The present invention can be a system, a method, and / or a computer program product. The computer program product can include a computer-readable storage medium having thereon computer-readable program instructions for causing a processor to implement various aspects of the present invention.

[0078] The computer-readable storage medium can be a tangible device that holds and stores instructions for use by an instruction execution device. The computer-readable storage medium can include, for example, but is not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (non-exhaustive list) of the computer-readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanically encoded device such as a punched card or raised structures in grooves having instructions stored thereon, and any suitable combination of the foregoing.

[0079] The embodiments of the present invention have been described above. The above description is exemplary and not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art in the technical field without departing from the scope and spirit of the described embodiments. The selection of the terms used herein is intended to best explain the principles of the embodiments, the practical application, or the improvement of the technology in the market, or to enable other ordinary skilled persons in the technical field to understand the embodiments disclosed herein.

Claims

1. An interface circuit design method based on artificial intelligence, characterized in that, Including: Step S1: Obtain the RTL code for describing the logical structure of a digital circuit, and use a preset neural network model to generate a digital circuit layout based on the RTL code; Step S2: Obtain a preset process library and design parameters of an analog circuit, and use a preset neural network model to generate an analog circuit layout based on the process library and the design parameters of the analog circuit; Step S3: Use a preset neural network model to fuse the digital circuit layout and the analog circuit layout to obtain the layout of the interface circuit.

2. The method according to claim 1, wherein The said Step S1 includes: According to the template of the preset interface circuit and the design parameters of the digital circuit input by the user, use a neural network model to generate RTL code; Use a neural network model to generate automated test vectors and a script for calling a simulation tool for the generated RTL code; Use the script for calling the simulation tool to call a logic simulation tool to perform simulation testing and optimization according to the automated test vectors, and obtain the optimized RTL code; Call a logic synthesis tool to convert the optimized RTL code into a digital circuit netlist; According to the digital circuit netlist and the design constraints of the digital circuit, complete floorplanning, clock tree generation, and routing in sequence to obtain the digital circuit layout.

3. The method according to claim 2, wherein The said RTL code is the code input by the user or the code generated by using a neural network model according to the template of the preset interface circuit and the design parameters of the digital circuit input by the user.

4. The method according to claim 1, characterized in that, The said Step S2 includes: Obtain the design parameters of the analog circuit, the analog circuit netlist, and the process library; According to the analog circuit netlist and the process library, perform module and device placement to obtain the initial layout of the analog circuit; According to the design parameters of the analog circuit, optimize the devices in the initial layout of the analog circuit.

5. The method according to claim 4, characterized in that The design parameters of the analog circuit include: power supply voltage, current limit, signal swing, transmission rate, and load matching requirements. Among them, optimizing the devices in the initial layout of the analog circuit includes: Adjust the bias current of the bias circuit according to the power supply voltage and current limit; Adjust the size and operating point of the differential pair transistors according to the signal swing; Adjust the cut-off frequency and bandwidth of the filter according to the transmission rate and load matching requirements.

6. The method according to claim 1, characterized in that, The said Step S3 includes: Obtain multiple constraint conditions for the merged layout, and use a preset neural network model to merge the digital circuit layout and the analog circuit layout on the basis of considering the said multiple constraint conditions to obtain the layout of the interface circuit.

7. The method according to claim 6, characterized in that, The said multiple constraint conditions include: Anti-interference constraint, which indicates the constraint condition for preventing signal interference between the digital circuit layout and the analog circuit layout; Power consumption management constraint, which indicates the total power consumption budget and the power consumption budget of each functional module within the digital circuit layout and the analog circuit layout; and / or Thermal distribution constraint, which indicates the constraint condition related to the temperature control of the circuit.

8. A computer program product, including a computer program / instructions, when the computer program / instructions are executed by a processor, the steps of the method described in any one of claims 1-7 are implemented.

9. A computer-readable storage medium, characterized in that, A computer program is stored thereon, and the computer program can be executed by a processor to implement the steps of the method described in any one of claims 1-7.

10. An electronic device, characterized in that, Including: One or more processors; And A memory, where the memory is used to store executable instructions; The one or more processors are configured to implement the steps of the method according to any one of claims 1-7 by executing the executable instructions.

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