Strong minority carrier injection type low on-state voltage drop thyristor device and preparation method

Abstract

The present invention relates to the technical field of thyristor devices, and more specifically to a strong minority carrier injection type thyristor device with low on-state voltage drop and a preparation method thereof, comprising: a front base region formed with a plurality of trenches, a front emitter region at the bottom of each trench, a gate metal layer above the sidewalls and wrapped with a passivation layer; and a front electrode metal layer formed above the front emitter region. To address the problem of poor trigger current consistency in thyristor devices in the prior art, a trench junction process is introduced, wherein a plurality of trench structures are prepared in the front base region to form a front emitter region, and a gate metal layer is formed at the top of the sidewalls of the trenches, thereby realizing a lateral trigger structure. Under the same chip area, the area of ​​the front emitter region at the bottom of the trench is significantly larger than that of a planar front emitter region, thereby reducing the on-state voltage drop. At the same time, because the trigger current of the device is realized through the laterally formed trench junction, the trigger path is shorter, which can effectively reduce the trigger current span.

Description

Technical Field

[0001] The present invention relates to the technical field of thyristor devices, and in particular to a strong minority carrier injection type thyristor device with low on-state voltage drop and a preparation method thereof. Background Art

[0002] A silicon controlled rectifier (SCR), also known as a thyristor, is a high-power electrical component constructed from a four-layer PNPN semiconductor material with three PN junctions and three electrodes. The bidirectional thyristor (BTS) is a development of the conventional thyristor. It can replace two thyristors connected in parallel with opposite polarity and requires only a single trigger circuit, making it an ideal AC switching device. Thyristors are widely used in power electronics technology. In automatic control systems, they can serve as high-power drivers, enabling low-power devices to control high-power equipment. They are widely used in AC and DC motor speed control systems, power regulation systems, and servo systems. Thyristors are divided into unidirectional thyristors and bidirectional thyristors. A bidirectional thyristor, also known as a three-terminal bidirectional thyristor (TRIAC), is structurally equivalent to two unidirectional thyristors connected in opposite directions. This type of thyristor has bidirectional conduction capabilities. Its on / off state is determined by the gate electrode G. The bidirectional thyristor is also provided with T2 electrodes and T1 electrodes on the front and back sides of the device respectively. Usually, the electrode in the opposite direction of the gate is recorded as the T1 electrode, and the electrode on the same side of the gate is recorded as the T2 electrode. The T1 electrode and T2 electrode will switch back and forth between the cathode and the anode according to the direction of the applied current.

[0003] For example, patent document CN201320272681.8 provides a planar thyristor device chip, belonging to the field of chip design technology. The planar thyristor device chip comprises a silicon substrate, an oxygen-doped polysilicon passivation layer, a lower silicon dioxide layer, a phosphosilicate glass layer, an upper silicon dioxide layer, and gate region lead hole windows and cathode region lead hole windows sequentially arranged on the surface of the silicon substrate. The chip is characterized in that a nitrogen-doped polysilicon layer is provided between the oxygen-doped polysilicon passivation layer and the lower silicon dioxide layer. The silicon substrate comprises an N-single crystal silicon wafer, on which an isolated diffused P+ region, an anode P region, a gate P region, and a cathode N+ region are provided. Five protective layers are formed on the chip surface: an oxygen-doped polysilicon passivation layer, a nitrogen-doped polysilicon layer, a lower silicon dioxide layer, a phosphosilicate glass layer, and an upper silicon dioxide layer. Parameters such as breakdown voltage and trigger current of this planar thyristor device chip are stable.

[0004] However, due to process limitations, the traditional planar thyristor structure has a trigger current span of more than 15mA in mass-produced devices, resulting in poor consistency. It also suffers from issues such as high on-state voltage drop. Summary of the Invention

[0005] In view of the above problems existing in the prior art, a strong minority carrier injection type thyristor device with low on-state voltage drop is provided; on the other hand, a preparation method for manufacturing the thyristor device is also provided.

[0006] The specific technical solution is as follows: A strong minority carrier injection type low on-state voltage drop thyristor device, comprising: a front base region, the front base region having a first doping type; a plurality of trenches are formed in the front base region, and a front emitter region is formed at the bottom of each of the trenches; the front emitter region has a second doping type; a gate metal layer is formed above the side wall of each of the trenches; a front electrode metal layer is formed above the front emitter region; a passivation layer is used to separate the gate metal layer and the front electrode metal layer.

[0007] On the other hand, it also includes: a substrate having the second doping type; the front base region is formed above the substrate; a back base region is formed below the substrate; the back base region has the first doping type; and a back electrode metal layer is formed below the back base region.

[0008] On the other hand, the front emission region is formed at the bottom of the groove; the side wall has an exposed portion in contact with the front electrode metal layer; the front electrode metal layer short-circuits the exposed portion and the front emission region, and forms an ohmic contact on each contact surface respectively.

[0009] In another aspect, the longitudinal height of the exposed portion is greater than 3 microns.

[0010] On the other hand, through diffusion isolation regions are formed on the left and right sides of the thyristor device respectively; protection trenches are formed on both sides of the front base region, and the protection trenches are filled with a passivation glass layer.

[0011] On the other hand, at least one back-side emitting region is formed at the bottom of the back-side base region; the back-side emitting region has the second doping type; and the back-side emitting region is in contact with the back-side electrode metal layer.

[0012] A preparation method, which is used to form the above-mentioned thyristor device; the preparation method comprises: step S1: forming a front base region above a substrate, then etching a groove in the front base region and doping to form a front emitter region, and making an exposed portion on the side of the groove; step S2: making a gate metal layer and a passivation layer above the side wall of the groove; step S3: forming a front electrode metal layer above the front emitter region and the passivation layer; step S4: forming a back base region and a back electrode metal layer below the substrate.

[0013] On the other hand, the step S1 includes: step S11: doping the substrate to form the front base region; step S12: etching a plurality of the grooves in the front base region; step S13: ion implantation doping the grooves to form the front emitter regions respectively; step S14: wet etching the front emitter region to form the exposed portion.

[0014] On the other hand, the step S2 includes: step S21: pre-growing the portion of the front electrode metal layer in the groove to fill the groove and perform surface flattening; step S22: oxidizing the front electrode metal layer to form an oxide layer to define the area above the side wall by the oxide layer; step S23: growing the gate metal layer in the area between the oxide layers and passivating to form the passivation layer.

[0015] On the other hand, the step S3 includes: step S31: etching the oxide layer to expose the front electrode metal layer; step S32: continuing to grow the front electrode metal layer to fill and completely wrap the passivation layer.

[0016] The above technical solution has the following advantages or beneficial effects: In response to the problem of poor consistency of the trigger current of the thyristor device in the prior art, this solution introduces a trench junction process, prepares multiple trench structures in the front base region, and dopes the bottom of the trench to form a front emitter region, and forms a gate metal layer at the top of the side wall of the trench, thereby realizing a lateral trigger structure. Under the same chip area, the area of ​​the front emitter region at the bottom of the trench will be significantly larger than that of the planar front emitter region, thereby reducing the conduction voltage drop; at the same time, since the trigger current of the device is realized through the laterally formed trench junction, the trigger path is shorter, which can effectively reduce the trigger current span. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The embodiments of the present invention will be described more fully with reference to the accompanying drawings, which are provided for illustration and description only and are not intended to limit the scope of the present invention.

[0018] Figure 1 is an overall schematic diagram of an embodiment of the present invention;

[0019] Figure 2 is a schematic diagram of another embodiment of the present invention;

[0020] Figure 3 Schematic diagram of the preparation method of an embodiment of the present invention;

[0021] Figure 4 Schematic diagram of a substrate according to an embodiment of the present invention;

[0022] Figure 5A schematic diagram of a front base region according to an embodiment of the present invention;

[0023] Figure 6 A schematic diagram of a groove according to an embodiment of the present invention;

[0024] Figure 7 This is a schematic diagram of the front emitting area of ​​an embodiment of the present invention;

[0025] Figure 8 Schematic diagram of a passivation glass layer according to an embodiment of the present invention;

[0026] Figure 9 A schematic diagram of trench filling according to an embodiment of the present invention;

[0027] Figure 10 Schematic diagram of an oxide layer according to an embodiment of the present invention;

[0028] Figure 11 A schematic diagram of a gate according to an embodiment of the present invention;

[0029] Figure 12 Schematic diagram of the front electrode according to an embodiment of the present invention;

[0030] Figure 13 Schematic diagram of a depassivation layer in an embodiment of the present invention;

[0031] Figure 14 Schematic diagram of the back surface process in an embodiment of the present invention;

[0032] Figure 15 This is a schematic diagram of step S1 of an embodiment of the present invention;

[0033] Figure 16 This is a schematic diagram of step S2 of an embodiment of the present invention;

[0034] Figure 17 Schematic diagram of step S3 of an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0036] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0037] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0038] The present invention includes: a strong minority carrier injection type low conduction voltage drop thyristor device, such as Figure 1 As shown, it includes: a front base region 2, the front base region 2 has a first doping type; a plurality of trenches are formed in the front base region 2, and a front emitter region 3 is formed at the bottom of each trench; the front emitter region 3 has a second doping type; a gate metal layer 4 is formed above the side wall of each trench; a front electrode metal layer 5 is formed above the front emitter region 3; a passivation layer 6 is used to separate the gate metal layer 4 and the front electrode metal layer 5.

[0039] Specifically, in response to the problem of poor consistency in the triggering current of thyristor devices in the prior art, a trench junction process is introduced in this embodiment, a plurality of trench structures are prepared in the front base region, and a front emitter region 3 is formed by doping at the bottom of the trench, and a gate metal layer 4 is formed at the top of the side wall of the trench, thereby realizing a lateral triggering structure. Under the same chip area, the area of ​​the front emitter region at the bottom of the trench will be significantly larger than that of the planar front emitter region, thereby reducing the conduction voltage drop; at the same time, since the triggering current of the device is realized through the laterally formed trench junction, the triggering path is shorter, which can effectively reduce the triggering current span.

[0040] Specifically, the planar thyristor device in the prior art usually forms multiple front emitter regions 3 on one side of the front base region by ion implantation, forms a front metal electrode above the corresponding position of the front emitter region, and forms a gate electrode on the other side.

[0041] Comparing the above device structure with that of the present embodiment, it can be seen that in the present embodiment, the front base region 2 is pre-etched to form a trench of a certain depth, and then doping is performed along the bottom edge of the trench to form the front emitter region 3. Because the trench has a certain curvature during the etching process, and the front emitter region 3 climbs up the sidewalls to a certain height along the shape of the trench during the doping process, the area of ​​each front emitter region 3 is increased compared to the traditional planar type, thereby increasing the conductive area and reducing the on-state voltage drop.

[0042] Based on the structure of the front emitter region 3 described above, a portion of the front base region 2 that has not been trench-etched is retained at the edge of the front base region 2 and in the area between two adjacent trenches as the trench sidewall region. Directly above this sidewall region, a gate metal layer 4 is formed by evaporation or metal deposition, and is isolated from the front electrode metal layer 5 above the front emitter region 3 by a passivation layer 6.

[0043] It should be noted that, on a cellular scale, the gate metal layers 4 in each cellular structure are interconnected in two-dimensional directions to form a whole.

[0044] Based on the above device structure, when the corresponding trigger voltage is applied to the gate, each gate metal layer 4 obtains the same trigger voltage, and then the gate metal layer 4 moves downward along the side wall structure of the groove, and triggers the formed horizontal trench junction after reaching the depth of the front emitter area 3. The trigger channel is also shorter than that of traditional planar devices. Under the same process fluctuations, the short trigger path will result in smaller trigger current fluctuations, so that the device trigger current IGT has good consistency, and the trigger current span can be within 5MA.

[0045] At the same time, the structure has a consistent trigger path within the chip, and the trigger consistency within the chip is high. The high trigger consistency will avoid local current concentration during the chip re-triggering process, thereby improving the device's surge capability and di / dt capability.

[0046] In the implementation process, the above technical solution is mainly embodied in a bidirectional thyristor device, which includes a substrate 1 having a second doping type. Taking an N-type device as an example, the substrate 1 is lightly N-type doped.

[0047] A front base region 2 is formed above the substrate 1 by ion implantation. The front base region 2 has a first doping type, which is P-type doping in this embodiment.

[0048] First, a plurality of trenches are etched in the front base region 2 according to a predetermined interval. Each trench is evenly distributed in the lateral direction, and the bottom end of the trench is still located in the front base region 2.

[0049] A front emitter region 3 is formed at the bottom of the trench by ion implantation. The front emitter region 3 has a first doping type, which is a heavily N-type doping in this embodiment.

[0050] By controlling the time of ion implantation, the front emitter region 3 can cover the lower sidewall of the trench to a certain extent, but it is usually necessary to expose a certain length of the upper sidewall to provide a conductive path for the front electrode.

[0051] A gate metal layer 4 of a certain height is grown above the trench, and multiple gate metal layers 4 are interconnected on a two-dimensional scale.

[0052] The surface of the gate metal layer 4 , including the upper surface and the side surfaces, is subjected to sacrificial oxidation treatment to form a passivation layer 6 . The passivation layer 6 is used to isolate the gate metal layer 4 from the front electrode metal layer 5 .

[0053] The front electrode metal layer 5 is formed above the front emitter region 3 and contacts the front base region 2 via the sidewalls of the trench to form a conductive channel. In a bidirectional thyristor device, the front electrode metal layer 5 is used as a T2 electrode.

[0054] Since the front emitter region 3 is formed at the bottom of the trench and the gate metal layer 4 is grown above the side wall of the trench, the front electrode metal layer 5 grows upward from the front emitter region 3 to completely fill the space at the bottom of the trench, and continues to grow upward along the space defined by the passivation layer 6 wrapped outside the gate metal layer 4 until it covers the passivation layer 6 and is connected together above the passivation layer 6 of each gate metal layer 4 to form a complete front electrode metal layer 5.

[0055] A backside base region 7 is further prepared below the substrate 1 through a backside process. The backside base region 7 has a first doping type, which is N-type doping in this embodiment.

[0056] The bottom of the back base region 7 is metallized to form a back electrode metal layer 8. When in use, the back base region electrode serves as the T1 electrode at the bottom of the device to connect to an external circuit.

[0057] In one embodiment, the front emitter region 3 is formed at the bottom of the trench; there is an exposed portion on the side wall that contacts the front electrode metal layer 5; the front electrode metal layer 5 short-circuits the exposed portion and the front emitter region, and forms an ohmic contact on each contact surface respectively.

[0058] Specifically, to achieve the formation of trench junctions and conductive channels, in this embodiment, multiple trenches are etched in the P-type doped front base region 2, and then doping is performed along the bottom edges of the trenches to form an N-type doped front emitter region 3. A heterogeneous trench junction is formed along the bottom arc of the trench in the diffusion direction toward the front base region 2.

[0059] On this basis, to achieve the formation of a conductive channel, the range of ion implantation is controlled so that the upper half of the trench is not doped, and this portion serves as the exposed front base region 2. At this time, by growing a front electrode metal layer 5 above the front emitter region 3 and completely filling the trench area, the front electrode metal layer 5 can short-circuit the front emitter region 3 and the front base region 2 in the area of ​​the sidewall. By controlling the contact surface to form an ohmic contact, the electric field in this portion is modulated, which is conducive to the formation of a conductive channel.

[0060] In one embodiment, the longitudinal height of the exposed portion is greater than 3 microns.

[0061] Specifically, in order to achieve a lower on-state voltage drop of the device, in this embodiment, the longitudinal height of the undoped exposed portion in the side wall area of ​​the groove is controlled to be greater than 3 microns, thereby achieving a lateral conductive channel of a certain width, that is, a conductive channel between the front base region 2 and the front electrode metal layer 5, which is conducive to achieving a low on-state voltage drop.

[0062] In one embodiment, a through diffusion isolation region 9 is formed on the left and right sides of the thyristor device respectively; and a protection trench is formed on both sides of the front base region, and the protection trench is filled with a passivation glass layer 10 .

[0063] Specifically, to achieve better device protection, in this embodiment, after forming a front base region 2 of sufficient length, a pair of protection trenches are formed at the edge of the device by etching, and the protection trenches are filled with a passivation glass layer 10 to achieve good device sealing. The bottom of the trenches generally needs to reach the depth of the front base region 2 and partially penetrate into the substrate 1.

[0064] Furthermore, to achieve better device protection, in this embodiment, a through diffusion isolation region 9 is formed on both sides of the thyristor device through a through isolation diffusion process, and both side edges of the thyristor device are wrapped to achieve good passivation characteristics.

[0065] In one embodiment, Figure 2 As shown, at least one back-side emission region 11 is formed at the bottom of the back-side base region 7 ; the back-side emission region 11 has the second doping type; and the back-side emission region 11 is in contact with the back-side electrode metal layer 8 .

[0066] Specifically, depending on the device design, in this embodiment, at least one back emitter region 11 is formed in the back base region 7 by back injection, and the back emitter region 11 has a second doping type, which is N-type doping in the N device embodiment.

[0067] One or more back-side emitting regions 11 are provided, the lower surface of which is in direct contact with the back-side base electrode 8 , and the upper surface of which is located in the back-side base region 7 .

[0068] A preparation method for forming the above-mentioned thyristor device; Figure 3 As shown, the preparation method includes: step S1: forming a front base region above the substrate, then etching a groove in the front base region and doping to form a front emitter region, and making an exposed portion on the side of the groove; step S2: making a gate metal layer and a passivation layer above the side wall of the groove; step S3: forming a front electrode metal layer above the front emitter region and the passivation layer; step S4: forming a back base region and a back electrode metal layer below the substrate.

[0069] Specifically, to realize the trench junction structure, in this embodiment, a solution is chosen to first etch the trench, dope, then form a gate metal layer and a passivation layer above the sidewalls of the trench, and finally fill the front electrode metal layer.

[0070] Specifically, if Figure 4As shown, first, a substrate A1 is prepared. An N-type substrate with a thickness of 350 μm is used. N-type doping is performed. After photolithography, aluminum is implanted and then through-diffusion is performed to form a through-diffusion isolation region A11. After the diffusion is completed, double-sided CMP polishing is performed to make the surface of the substrate A1 flat. Then, as shown in FIG. Figure 5 As shown, P-type boron is diffused on both sides of the front surface of the substrate A1 to form a front base region A2. A double-sided diffusion process can also be used to form the front base region A2 and the back base region A3.

[0071] For the front base area A2, such as Figure 6 As shown, photolithography is first performed to define the window where the groove is located, and then etching is performed to obtain a deep groove through the etching process.

[0072] Then, if Figure 7 As shown, photolithography is performed again and phosphorus elements are implanted to form a front emitting region A4 with N-type doping.

[0073] Subsequently, the front emitter region A4 formed on the sidewall of the trench is selectively removed by wet etching, so that the front base region A2 in the upper half of the trench is exposed to form an exposed portion. Here, the etching depth needs to be controlled to achieve a specific length of the exposed portion.

[0074] Then, if Figure 8 As shown, the left and right sides of the groove of the front base area A2 are defined by photolithography and development, and the parts located inside the through diffusion isolation area A11 are defined to obtain protection grooves. The protection grooves are obtained by etching deep grooves, and the bottom of the protection grooves reaches the part of the substrate A1.

[0075] Subsequently, a glass passivation layer A5 is grown by photoresist.

[0076] Then, the area where metal needs to be grown is defined by photolithography and development, so that the metal can grow in the groove from above the front emission area A4.

[0077] like Figure 9 As shown, an aluminum metal layer is grown by sputtering, evaporation or other equivalent methods as part of the front electrode metal layer A6, and then ultrasonic debonding is performed and the surface of the device is planarized.

[0078] Then, if Figure 10 As shown, an oxide layer is grown on the upper surface of the front electrode metal layer A6 to define an area where a gate metal layer A7 is to be grown subsequently.

[0079] After the oxide layer is grown, the area above the trench sidewall is photoetched to remove excess oxide layer to ensure that the gate metal layer A7 can be normally grown above the trench sidewall.

[0080] like Figure 11As shown, aluminum metal is then grown and gradually accumulated to form a gate metal layer A7 with a certain height. At the same time, the gate metal layers A7 should be controlled to be interconnected in the two-dimensional direction.

[0081] After the gate metal layer A7 is formed, a passivation layer A8 is deposited on the surface of the gate metal layer A7, including the upper surface and the side surfaces.

[0082] like Figure 12 As shown, after forming the passivation layer A8, the oxide layer in the trench is dry-opened and removed to expose the front electrode metal layer A6 in the trench below.

[0083] At this time, the front electrode metal layer A6 continues to grow on the basis of the original front electrode metal layer A6 until the area between the adjacent gate metal layer A7 and the passivation layer A8 is completely filled, forming a complete front electrode metal layer A6.

[0084] like Figure 13 As shown, the passivation layer A8 on the surface of the outermost gate metal layer A7 is subsequently removed to expose the gate metal layer A7.

[0085] Finally, the back side is doped to form the back side base region A3; if the double-side diffusion process has been performed, this step can be omitted; Figure 14 As shown, a back electrode metal layer A9 is prepared below, and a back-side doping process may be performed as needed to form a back-side emission region.

[0086] In one embodiment, Figure 15 As shown, step S1 includes: step S11: doping the substrate to form a front base region; step S12: etching multiple grooves in the front base region; step S13: ion implantation doping the grooves to form front emitter regions respectively; step S14: wet etching the front emitter region to form an exposed portion.

[0087] Specifically, substrate A1 is first fabricated. An N-type substrate with a thickness of 350μm is used. N-type doping is performed, and aluminum implantation is performed by photolithography followed by through-diffusion to form the through-diffusion isolation region A11. After diffusion is complete, double-sided CMP polishing is performed to smooth the surface of substrate A1. Then, P-type boron diffusion is performed on both sides of substrate A1 to form the front base region A2.

[0088] For the front base area A2, photolithography is first performed to define the window where the groove is located, and then etching is performed to obtain a deep groove through the etching process.

[0089] Then, photolithography is performed again and phosphorus elements are implanted to form a front emitting region A4 with N-type doping.

[0090] Subsequently, the front emitter region A4 formed on the sidewall of the trench is selectively removed by wet etching, so that the front base region A2 in the upper half of the trench is exposed to form an exposed portion. Here, the etching depth needs to be controlled to achieve a specific length of the exposed portion.

[0091] In one embodiment, Figure 16 As shown, step S2 includes: step S21: pre-growing a portion of the front electrode metal layer in the groove to fill the groove and perform surface flattening; step S22: oxidizing the front electrode metal layer to form an oxide layer to define the area above the side wall through the oxide layer; step S23: growing a gate metal layer in the area between the oxide layers and passivating it to form a passivation layer.

[0092] In one embodiment, Figure 17 As shown, step S3 includes: step S31: etching the oxide layer to expose the front electrode metal layer; step S32: continuing to grow the front electrode metal layer to fill and completely wrap the passivation layer.

[0093] Specifically, in order to prepare the gate and the front electrode, the area where the metal needs to be grown is first defined by photolithography and development, so that the metal can grow in the groove from above the front emitter area A4.

[0094] An aluminum metal layer is grown by sputtering, evaporation or other equivalent methods to serve as part of the front electrode metal layer A6, and then ultrasonic debonding is performed and the surface of the device is planarized.

[0095] Then, an oxide layer is grown on the upper surface of the front electrode metal layer A6 to define an area where the gate metal layer A7 is to be grown subsequently.

[0096] After the oxide layer is grown, the area above the trench sidewall is photoetched to remove excess oxide layer to ensure that the gate metal layer A7 can be normally grown above the trench sidewall.

[0097] Then, aluminum metal is grown and gradually accumulated to form a gate metal layer A7 with a certain height. At the same time, the gate metal layers A7 should be controlled to be interconnected in the two-dimensional direction.

[0098] After the gate metal layer A7 is formed, a passivation layer A8 is deposited on the surface of the gate metal layer A7, including the upper surface and the side surfaces.

[0099] After forming the passivation layer A8, the oxide layer in the trench is dry-opened and removed to expose the front electrode metal layer A6 in the trench below. At this point, growth continues on top of the existing front electrode metal layer A6 until it completely fills the area between the adjacent gate metal layer A7 and passivation layer A8, forming a complete front electrode metal layer A6.

[0100] The above are only preferred embodiments of the present invention and do not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A strong minority carrier injection type low on-state voltage drop thyristor device, characterized in that: include: a front base region, the front base region having a first doping type; A plurality of trenches are formed in the front base region, and a front emitter region is formed at the bottom of each trench; The front emitter region has a second doping type; A gate metal layer is formed above the sidewall of each of the trenches; A front electrode metal layer is formed above the front emitting region; The gate metal layer and the front electrode metal layer are separated by a passivation layer; The front emitting region is formed at the bottom of the trench; The sidewall has an exposed portion in contact with the front electrode metal layer; The front electrode metal layer short-circuits the exposed portion and the front emission region, and forms an ohmic contact on each contact surface.

2. The thyristor device according to claim 1, characterized in that: Also includes: a substrate having the second doping type; The front base region is formed above the substrate; a back base region, wherein the back base region is formed below the substrate; The back base region has the first doping type; A back electrode metal layer is formed below the back base region.

3. The thyristor device according to claim 1, characterized in that: The longitudinal height of the exposed portion is greater than 3 microns.

4. The thyristor device according to claim 1, characterized in that: A pair of diffusion isolation regions are formed on the left and right sides of the thyristor device respectively; Protection grooves are formed on both sides of the front base region, and the protection grooves are filled with a passivation glass layer.

5. The thyristor device according to claim 2, characterized in that: At least one back emitting region is formed at the bottom of the back base region; The back emitting region has the second doping type; The back emission region contacts the back electrode metal layer.

6. A preparation method, characterized in that: The preparation method is used to form the thyristor device according to any one of claims 1 to 5; The preparation method comprises: Step S1: forming a front base region above the substrate, then etching a trench in the front base region and doping to form a front emitter region, and forming an exposed portion on the side of the trench; Step S2: forming a gate metal layer and a passivation layer above the sidewalls of the trench; Step S3: forming a front electrode metal layer on the front emission region and the passivation layer; Step S4: forming a back base region and a back electrode metal layer below the substrate.

7. The preparation method according to claim 6, characterized in that The step S1 comprises: Step S11: doping the substrate to form the front base region; Step S12: etching a plurality of trenches in the front base region; Step S13: performing ion implantation and doping on the trenches to form the front emitter regions respectively; Step S14: performing wet etching on the front emitter region to form the exposed portion.

8. The preparation method according to claim 7, characterized in that The step S2 comprises: Step S21: forming a portion of the front electrode metal layer pre-grown in the groove to fill the groove and perform surface planarization; Step S22: oxidizing the front electrode metal layer to form an oxide layer, so as to define an area above the sidewall by the oxide layer; Step S23: growing the gate metal layer in the region between the oxide layers and passivating the layer to form the passivation layer.

9. The preparation method according to claim 8, characterized in that The step S3 comprises: Step S31: etching the oxide layer to expose the front electrode metal layer; Step S32: Continue growing the front electrode metal layer to fill and completely wrap the passivation layer.

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