Instruction set extension method and system, chip and storage medium

Abstract

The invention provides an instruction set extension method and system, a chip and a storage medium, and the method comprises the steps: obtaining a scene type of a target application scene, and extracting a demand index corresponding to the target application scene according to the scene type; determining a corresponding instruction demand frequency according to the scene type, and performing function clustering on the instruction; determining a target instruction set hierarchical extension architecture in candidate instruction set hierarchical extension architectures according to the demand indexes; and according to an instruction function clustering result, dividing a target instruction into a corresponding section of the target instruction set hierarchical extension architecture. According to the embodiment of the invention, through scenarized demand analysis, instruction function clustering, dependency optimization and multi-level extension architecture design, dynamic adaptation, performance optimization and hardware friendliness improvement of an instruction set architecture are realized, the energy efficiency ratio and resource utilization rate of different systems can be improved, and the system performance is improved. The problems that in a traditional instruction set architecture, instruction distribution is low in efficiency, function modularization is lacked, and hardware friendliness is insufficient are solved.

Description

Technical Field

[0001] The present application relates to the field of computer systems, and in particular to a computing method, system, chip and storage medium based on a two-stage pipeline. Background Art

[0002] Instruction set architecture design is an important topic in computer systems. A fixed instruction set architecture is difficult to apply to different application scenarios because factors such as computing hardware resources, instruction parsing complexity, current required instruction scale, and instruction expansion requirements are all different in different application scenarios.

[0003] Existing instruction set architecture design and expansion technologies include static instruction set design, where all instruction functions are hard-coded before chip tape-out; two-level extended instruction set architecture, which divides the instruction set into base instructions and first-level extended instructions, distinguished by opcode prefixes or extension bits; and domain-specific instruction sets, which design dedicated instruction sets for specific fields (such as AI and image processing) and hardwareize high-frequency operations. All of these technologies suffer from problems such as insufficient instruction expansion flexibility, wasted instruction storage space, and high error rates. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to provide a dynamically configured mixed-base calculation method, system, chip and storage medium.

[0005] In a first aspect, an embodiment of the present invention provides an instruction set extension method, the method comprising:

[0006] Obtaining the scenario type of the target application scenario, and extracting the demand indicators corresponding to the target application scenario according to the scenario type;

[0007] Determine the corresponding instruction demand frequency according to the scenario type and perform functional clustering on the instructions;

[0008] Determining a target instruction set hierarchical extension architecture from candidate instruction set hierarchical extension architectures according to the requirement indicators;

[0009] According to the result of the instruction function clustering, the target instructions are divided into corresponding sections of the target instruction set hierarchical extension architecture.

[0010] Optionally, determining a target instruction set hierarchical extension architecture from candidate instruction set hierarchical extension architectures according to the requirement indicator specifically includes:

[0011] Determining a second candidate instruction set hierarchical extension architecture based on a degree of matching between a performance requirement indicator in the requirement indicator and the candidate instruction set hierarchical extension architecture;

[0012] If the second candidate instruction set hierarchical extension architecture is one, determining the second candidate instruction set hierarchical extension architecture as the target instruction set hierarchical extension architecture;

[0013] Otherwise, the target instruction set hierarchical extension architecture is determined according to the matching degree between the hardware requirement indicator in the requirement indicator and the second candidate instruction set hierarchical extension architecture.

[0014] Optionally, dividing the target instructions into corresponding sections of the target instruction set hierarchical extension architecture according to the result of the instruction function clustering specifically includes:

[0015] Classifying a preset number of high-frequency instructions into a basic instruction area of the target instruction set hierarchical extension architecture, and classifying other instructions into an extended instruction area of the target instruction set hierarchical extension architecture;

[0016] said dividing the instructions of the same cluster into the same section of the target instruction set hierarchical extension architecture according to the result of said instruction function clustering;

[0017] Arrange dependent instructions into the same section.

[0018] Optionally, the performing instruction function clustering specifically includes:

[0019] Determining the number of target clusters according to the scenario type of the target application scenario;

[0020] The instruction function, operand type, and data dependency of the instructions corresponding to the scenario type are used as input features of the instructions, and the instructions corresponding to the scenario type are clustered according to the target cluster number.

[0021] Optionally, determining the corresponding instruction demand frequency according to the scenario type specifically includes:

[0022] Select corresponding statistical tools and test cases according to the scenario type;

[0023] quantifying and compiling the test cases using the statistical tool, and tracking and collecting the number of executions of each instruction in the test cases;

[0024] The instruction demand frequency is obtained by filtering low-frequency instructions in the execution times and merging synonymous instructions.

[0025] Optionally, the candidate instruction set hierarchical extension architecture includes a basic instruction architecture, a first-level extension architecture and a second-level extension architecture.

[0026] Optionally, the scenario types include edge computing scenarios, lightweight AI scenarios, and high-performance computing scenarios.

[0027] In a second aspect, an embodiment of the present invention provides an instruction set extension system, characterized in that the system includes:

[0028] A demand determination module is used to obtain the scenario type of the target application scenario and extract the demand indicators corresponding to the target application scenario according to the scenario type;

[0029] An instruction analysis module is used to determine the corresponding instruction demand frequency according to the scenario type and perform functional clustering on the instructions;

[0030] An architecture determination module, configured to determine a target instruction set hierarchical extension architecture from among candidate instruction set hierarchical extension architectures according to the requirement indicators;

[0031] The instruction partitioning module is used to partition the target instructions into corresponding sections of the target instruction set hierarchical extension architecture according to the result of the instruction function clustering.

[0032] In a third aspect, an embodiment of the present invention provides a chip, characterized in that the chip includes:

[0033] one or more processors;

[0034] a memory for storing one or more programs;

[0035] When the one or more programs are executed by the one or more processors, the one or more processors execute the method as described in the first aspect.

[0036] In a fourth aspect, an embodiment of the present invention provides a storage medium having computer program instructions stored thereon, characterized in that when the computer program instructions are executed, the instruction processing method described in the first aspect is implemented.

[0037] The instruction set expansion method, system, chip and storage medium provided by the embodiments of the present invention realize dynamic adaptation and performance optimization of the instruction set architecture by extracting demand indicators and determining instruction frequency according to the target application scenario, so that the instruction set architecture is accurately adapted to the scenario requirements, avoiding over-design or insufficient performance, and improving hardware resource utilization; determining the number of target clusters based on the scenario type, and performing cluster analysis in combination with instruction function, operand type, and data dependency; by preferentially allocating high-frequency instructions to the basic instruction area and low-frequency instructions to the extension area, and dividing the same cluster cluster or instructions with dependencies into the same segment, pipeline pauses caused by cross-segment instruction dependencies are reduced, high-frequency instruction decoding delays are reduced, and instruction execution throughput is improved. In summary, the present invention realizes dynamic adaptation, performance optimization and hardware friendliness of the instruction set architecture through scenario-based demand analysis, instruction function clustering, dependency optimization and multi-level extension architecture design, which can significantly improve the energy efficiency and resource utilization of different systems, and solves the problems of inefficient instruction distribution, lack of functional modularization, and insufficient hardware friendliness in traditional instruction set architectures. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments of the present application.

[0039] Figure 1 A flowchart of an instruction set expansion method provided by an embodiment of the present invention;

[0040] Figure 2 A schematic diagram of a flow chart of an instruction function clustering method provided by an embodiment of the present invention;

[0041] Figure 3 A schematic diagram of the structure of the instruction set extension system provided by an embodiment of the present invention;

[0042] Figure 4 A schematic diagram of the structure of a chip provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0044] Similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and should not be understood as indicating or implying relative importance.

[0045] Instruction set architecture design is an important topic in computer systems. A fixed instruction set architecture is difficult to apply to different application scenarios because factors such as computing hardware resources, instruction parsing complexity, current required instruction scale, and instruction expansion requirements are all different in different application scenarios.

[0046] Existing instruction set architecture design and expansion technologies include static instruction set design, where all instruction functions are hard-coded before chip tape-out; two-level extended instruction set architecture, which divides the instruction set into base instructions and first-level extended instructions, distinguished by opcode prefixes or extension bits; and domain-specific instruction sets, which design dedicated instruction sets for specific fields (such as AI and image processing) and hardwareize high-frequency operations. All of these technologies suffer from problems such as insufficient instruction expansion flexibility, wasted instruction storage space, and high error rates.

[0047] Based on this, the embodiment of the present invention proposes an instruction set expansion method, as shown in the attached Figure 1 As shown, the method specifically includes the following steps.

[0048] Step S110 , obtaining the scenario type of the target application scenario, and extracting the demand indicators corresponding to the target application scenario according to the scenario type.

[0049] In the field of instruction set design, traditional design methods have the following pain points: in the early stages of design, requirements are only described in general terms based on common scenarios, resulting in a mismatch between instruction set performance and actual scenarios; or over-design (such as configuring high-power hardware for all scenarios) or insufficient design (such as failing to meet the real-time requirements of industrial scenarios) leads to a mismatch between scenario requirements; changes in scenario requirements (such as upgrading from a short-term dedicated meter chip to a mid-term iterative TinyML chip) require redesigning the instruction architecture, extending the development cycle by more than 6 months.

[0050] The embodiment of the present invention aims to propose a method that can flexibly expand instructions according to scenario requirements. Through scenario type classification and quantitative extraction of demand indicators, a strong correlation between instruction design requirements and scenario characteristics is established to achieve scenario-driven instruction architecture customization.

[0051] The scenario type in this step refers to the classification label of the target application scenario, which reflects the core characteristics and constraints of the scenario. Scenario types include edge computing scenarios, lightweight AI scenarios, and high-performance computing scenarios. The demand indicators in this step refer to the quantitative performance, functions, hardware constraints and other indicators that the instruction set architecture design must meet in the target application scenario. Specifically, they include throughput, latency, energy efficiency, instruction set size, life cycle, chip area budget, power consumption budget, clock frequency, etc. The specific indicators included can be set according to user needs. For example, the demand indicators in a target application scenario include throughput ≥ 1TOPS, latency < 10ms, and chip area ≤ 2mm 2 wait.

[0052] The following provides a specific execution process of this step. First, according to the text description of the input target scenario (such as "low-power AI chip for smart meters"). At this time, keyword extraction can be performed to obtain the scenario type of the target application scenario and related demand indicators: for example, extract "electricity meter" to associate the scenario type "edge computing", extract "low power consumption" to associate the demand indicator "<5mW" about power consumption constraints. Then, query the entry corresponding to "edge computing" in the scenario matrix table, automatically fill in the key features such as computing type (real-time control), real-time requirements (<10ms), life cycle (short-term dedicated), and generate the following demand indicators: performance-related indicators, throughput ≥10MOPS, delay <10ms, energy efficiency ratio ≥0.1MOPS / W; function-related indicators, support PID control algorithm, instruction set size ≤64; hardware constraint-related indicators, area ≤0.8mm 2 , power consumption ≤ 5mW, clock frequency ≤ 50MHz. The "Scenario Matrix" is maintained and generated based on the historical feature data of each target application scenario. Based on the target scenario characteristics, the corresponding classification labels in the matrix can be matched to automatically extract the associated demand indicators.

[0053] Step S120 : determining the corresponding instruction demand frequency according to the scenario type, and performing functional clustering on the instructions.

[0054] This step is about scenario-based instruction frequency analysis and functional clustering. Existing general-purpose instruction sets such as RISC-V contain a large number of low-frequency instructions. For example, the usage rate of floating-point division in edge computing scenarios is less than 0.1%, resulting in a waste of hardware resources and an unnecessary increase of 15% to 30% in chip area. In addition, due to the lack of distinction between hardware implementation differences of functionally similar instructions (such as ADD and ADDI), the complexity of instruction decoding increases and the delay increases by 2 to 3 cycles. Furthermore, for example, the instruction requirements of AI scenarios (such as TinyML) and industrial control scenarios (such as PID controllers) are significantly different, but traditional instruction design does not distinguish between scenario characteristics, resulting in a significant decrease in energy efficiency. This step realizes dynamic customization of the instruction set through scenario-driven instruction frequency analysis and functional clustering, filters low-frequency instructions, reduces hardware area overhead, and reduces instruction decoding power consumption. Clustering generates scenario-based instruction sets to improve the application efficiency of instruction sets.

[0055] The instruction frequency in this step refers to the percentage of times a particular instruction is called in the target scenario, reflecting the importance of the instruction. Functional clustering of instructions refers to providing a basis for assigning subsequent instructions to different locations based on characteristics such as instruction function, operand type, and data dependencies.

[0056] When counting instruction frequencies, different instruction tracking tools can be selected based on different scenarios. Specifically, the corresponding statistical tool and test case can be selected based on the scenario type. Next, the statistical tool is used to quantify and compile the test case, tracking and collecting the execution count of each instruction in the test case. Finally, the low-frequency instructions in the execution count are filtered out and synonymous instructions are merged to obtain the instruction demand frequency.

[0057] For example, for AI scenarios, you can use TensorFlow Lite Micro's profile tool to generate instruction heatmaps, recording the number of calls and cycles for each instruction. For general scenarios, you can use the LLVM compiler to generate perf instruction count reports to count the frequency of instructions in typical use cases. When counting instruction frequencies, you can use filtering and merging rules to remove instructions with a frequency of less than 1% and merge instructions with similar functions but different encodings, thereby reducing instruction redundancy and improving instruction set utilization.

[0058] When performing functional clustering on instructions, the following steps S210 to S220 can be used to implement it, as shown in the attached figure. Figure 2 shown.

[0059] Step S210: determining the target cluster quantity according to the scenario type of the target application scenario.

[0060] Step S220 , taking the instruction function, operand type, and data dependency of the instructions corresponding to the scenario type as input features of the instructions, and clustering the instructions corresponding to the scenario type according to the target number of clusters.

[0061] Specifically, general instruction clustering cannot adapt to the differences in instruction requirements in different scenarios. For example, edge computing scenarios only require a small number of core instructions, but traditional methods still cluster according to the general target clustering number K value (such as K = 50), resulting in waste of hardware resources; on the contrary, AI scenarios require high-granularity clustering (such as K = 15-20), but traditional methods may lose functional associations due to the small K value.

[0062] Therefore, this step first determines the target number of clusters based on the scenario type: K = 3 to 5 for low-complexity edge computing scenarios, and K = 10 to 20 for high-complexity AI scenarios. Here, you can either manually set the K value based on scenario requirements (e.g., K = 3 for industrial controllers, K = 12 for speech recognition chips), or use cross-validation to evaluate the clustering quality (such as silhouette coefficient and modularity) under different K values and select the optimal K value.

[0063] Secondly, the instruction function, operand type, and data dependency of the instructions corresponding to the scenario type need to be used as input features of the instruction, and the instructions corresponding to the scenario type need to be clustered with the target number of clusters. Instruction function refers to the consideration that multiple instructions are used to implement a certain type of function, such as arithmetic operation instructions, memory access instructions, control flow instructions, etc. Operand type refers to the data dimension of the instruction operand, which affects the design of the hardware execution unit. Data dependency refers to the read and write dependency between instructions when multiple instructions are executed, reflecting the coupling of functional modules. Specifically, the function label can be extracted through instruction semantic analysis tools (such as LLVM's MCInst parser), the operand dimension can be parsed through instruction encoding, and the instruction dependency graph can be generated through static program analysis. The specific clustering algorithm can use K-Means clustering, calculate the Euclidean distance from the instruction feature to the cluster center, and finally generate an instruction function clustering graph. If necessary, the core instructions and boundary instructions of each cluster can also be generated.

[0064] The above-mentioned steps of this technology realize scenario-based customization of instruction sets through scenario-driven dynamic clustering quantity determination and multi-dimensional input feature extraction, laying the foundation for the subsequent precise allocation of resources, improvement of instruction energy efficiency, and utilization efficiency of the instruction set extended by the instructions.

[0065] Step S130 , determining a target instruction set hierarchical extension architecture from candidate instruction set hierarchical extension architectures according to the requirement indicator.

[0066] To meet the requirements for instruction quantity and functionality in different application scenarios, the extensible instruction set architecture in the embodiments of the present invention provides a variety of flexible expansion methods. Different candidate instruction set hierarchical expansion architectures can be selected and combined according to the specific needs of system designers to achieve efficient expansion of the instruction set. The following uses three expansion methods as examples, but the embodiments of the present invention are not limited to the following three methods.

[0067] (1) Basic instruction architecture: The smallest implementation unit of the instruction set, using the basic 4-bit opcode as the instruction operation code opcode, only supports a maximum of 16 core function instructions, such as arithmetic operations, memory access, etc.

[0068] (2) Level 1 extension architecture: After the base 4-bit opcode, 8 bits are extended as extended opcodes. In one possible implementation, the 13 opcodes 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, and 1100 in the base 4-bit opcodes correspond to 13 basic instructions and together form the basic instruction partition. The remaining three opcodes 1101, 1110, and 1111 are extension slots. The opcodes in extended mode are 1101+XXXXXXXX, 1110+XXXXXXXX, or 1111+XXXXXXXX. In this example, a maximum of 781 instructions can be supported.

[0069] (3) Secondary extension architecture: After the basic 4-bit opcode, first extend 8 bits as the first-level extended opcode. Depending on the needs, further extend 4 or 8 bits to form a secondary extension. For example, with 1111 as the extended instruction slot, extend it backward 8 bits to obtain 256 extended instructions. If a larger extension is required, it can be extended by another 4 or 8 bits on this basis. Specifically, when 512 instructions are exhausted, a total instruction code length of 16 or 20 bits can be used, and multiple available expansion slots can be reserved for expansion, which can basically cover the instructions corresponding to all existing functional requirements.

[0070] In summary, the first-level extension architecture in the candidate instruction set hierarchical extension architecture is to add a first-level extension field to the basic architecture to support more instructions and functional modularity. The second-level extension architecture is to add a second-level extension field based on the first-level extension.

[0071] The existing technology generally only considers the size of the instruction set when selecting different candidate instruction set hierarchical extension architectures. In addition to considering the size of the instruction set when screening and determining the target instruction set hierarchical extension architecture, the embodiment of the present invention can refer to multiple evaluation indicators. The indicators mainly include performance requirement indicators and hardware requirement indicators. The performance requirement indicators can include high-frequency instruction delay: <2 cycles (critical for real-time control scenarios), energy efficiency ratio: >2TOPS / W (critical for battery-powered devices), etc. Hardware requirement indicators can include: chip area: <1mm 2 (critical for IoT devices), power consumption: <30mW (critical for smart watches), etc. It is worth noting that the above indicators are only exemplary, and the specific performance requirement indicators and hardware requirement indicators and their thresholds used in this step can be set according to user needs, and are not specifically limited in the embodiments of the present invention.

[0072] When screening and determining the target instruction set hierarchical extension architecture, the embodiment of the present invention first performs a first round of screening based on the performance requirement index, that is, follows the performance priority rule. For example, if the high-frequency instruction delay is a bottleneck in the performance requirement index (such as a real-time control scenario, the delay needs to be <2 cycles), then the basic architecture or the first-level extension architecture can be selected; for example, if the energy efficiency ratio is the key in the requirement index (such as a battery-powered device, the energy efficiency ratio needs to be >2TOPS / W), then the second-level extension architecture can be selected. After this round of screening, the second candidate instruction set hierarchical extension architecture may be one or more. If it is one, the second candidate instruction set hierarchical extension architecture is the target instruction set hierarchical extension architecture.

[0073] If there are multiple second candidate instruction set hierarchical extension architectures, a second round of screening based on hardware requirement indicators is performed. For example, if the chip area is limited (such as IoT devices, which need to be less than 1mm 2 ), then the second-level extension architecture can be further selected from the first-level extension architecture and the second-level extension architecture as the target instruction set hierarchical extension architecture; for example, if the power consumption is acceptable (such as industrial controller, power consumption <50mW), then the first-level extension architecture can be selected from the basic instruction architecture and the first-level extension architecture as the target instruction set hierarchical extension architecture.

[0074] Step S140 : dividing the target instructions into corresponding sections of the target instruction set hierarchical extension architecture according to the result of the instruction function clustering.

[0075] When storing instructions, the multi-level instruction set architecture faces the problem of how to allocate different instructions to non-ventilated segments. The principles followed by the embodiments of the present invention when allocating include high-frequency instruction priority, functional modularization, and hardware friendliness. Specifically, it is necessary to count the execution frequency of instructions (such as MOV instructions account for >30%) and give priority to allocating them to the basic instruction area; secondly, it is necessary to divide function-related instructions (such as AI acceleration instructions: quantized convolution, ReLU activation) into the same segment; finally, it is necessary to avoid cross-segment instruction dependencies (such as basic instructions must not depend on extension area instructions) to reduce pipeline pauses.

[0076] The following is an exemplary description of the instruction allocation process. After counting the instruction execution frequency, it is determined that MOV instructions account for 35% and ADD instructions account for 20%, and such high-frequency instructions (frequency > 10%) are allocated to the basic instruction segment. Then, the instruction function similarity is calculated based on the instruction clustering results (such as the Jaccard similarity of quantized convolution and ReLU activation is 0.85). Instructions with similarity > 0.8 are clustered into the same segment, and the segment can be regarded as a dedicated area for AI-type instructions. Finally, it is necessary to verify and check the instruction dependencies (such as MOV instructions must not depend on DMA transfer instructions). If there is cross-segment dependency, the instruction segment division result is adjusted (such as moving the DMA transfer instruction to the memory access area), and the final output is the instruction segment division result, that is, the complete instruction set extension result.

[0077] After completing the instruction set expansion action, the embodiment of the present invention can also perform hardware resource allocation and decoder design, design the decoder logic according to the instruction set scale, and allocate hardware resources. Specifically, a multi-level decoder can be designed according to the target instruction set expansion architecture. For example, for a two-level expansion architecture, a first-level decoder can be designed: processing basic instructions (4 bits), using combinational logic implementation, with a delay of ≤1 cycle; a second-level decoder: processing first-level expansion instructions (8 bits), using a pipeline design, with a delay of ≤2 cycles; a third-level decoder: processing second-level expansion instructions (4 / 8 bits), using a microcode engine or reconfigurable logic implementation, with a delay of ≤3 cycles.

[0078] Finally, the embodiment of the present invention can also perform simulation verification and iterative optimization on the target instruction set hierarchical extension architecture, verify the correctness of the instruction set architecture through simulation tools, and optimize the instruction encoding and hardware design. In actual applications, Verilator or VCS can be used to verify the decoder logic and timing, and Gem5 or QEMU can be used to test instruction utilization and functional coverage to verify the correctness of all instructions and measure whether performance indicators such as throughput, latency, and power consumption meet user requirements. If the requirements are not met, the utilization rate can be improved by further opcode reallocation or instruction merging, or the latency can be reduced through pipeline optimization or logic gate multiplexing (target ≤ 5 cycles), or the power consumption can be reduced through DVFS or NTC technology (target ≥ 100OPS / mW).

[0079] The instruction set extension method provided by the embodiment of the present invention realizes the dynamic adaptation and performance optimization of the instruction set architecture by extracting demand indicators and determining instruction frequency according to the target application scenario, so that the instruction set architecture is accurately adapted to the scenario requirements, avoiding over-design or insufficient performance, and improving the utilization of hardware resources; determining the number of target clusters based on the scenario type, and performing cluster analysis in combination with the instruction function, operand type, and data dependency; by preferentially allocating high-frequency instructions to the basic instruction area and low-frequency instructions to the extension area, and dividing the same cluster cluster or instructions with dependencies into the same segment, the pipeline pauses caused by cross-segment instruction dependencies are reduced, the decoding delay of high-frequency instructions is reduced, and the throughput of instruction execution is improved. In summary, the present invention realizes the dynamic adaptation, performance optimization and hardware friendliness of the instruction set architecture through scenario-based demand analysis, instruction function clustering, dependency optimization and multi-level extension architecture design, which can significantly improve the energy efficiency and resource utilization of different systems, and solves the problems of inefficient instruction distribution, lack of functional modularization, and insufficient hardware friendliness in traditional instruction set architecture.

[0080] Based on any of the above embodiments, Figure 3 As shown, an embodiment of the present invention provides an instruction set extension system, characterized in that the system includes:

[0081] The demand determination module 310 is used to obtain the scenario type of the target application scenario and extract the demand indicators corresponding to the target application scenario according to the scenario type;

[0082] The instruction analysis module 320 is used to determine the corresponding instruction demand frequency according to the scenario type and perform functional clustering on the instructions;

[0083] An architecture determination module 330 is configured to determine a target instruction set hierarchical extension architecture from among candidate instruction set hierarchical extension architectures according to the requirement indicator;

[0084] The instruction partitioning module 340 is configured to partition target instructions into corresponding sections of the target instruction set hierarchical extension architecture according to the result of the instruction function clustering.

[0085] The instruction set extension system provided by the embodiment of the present invention realizes the dynamic adaptation and performance optimization of the instruction set architecture by extracting demand indicators and determining instruction frequency according to the target application scenario, so that the instruction set architecture is accurately adapted to the scenario requirements, avoiding over-design or insufficient performance, and improving the utilization of hardware resources; determining the number of target clusters based on the scenario type, and performing cluster analysis in combination with the instruction function, operand type, and data dependency; by preferentially allocating high-frequency instructions to the basic instruction area and low-frequency instructions to the extension area, and dividing the same cluster cluster or instructions with dependencies into the same segment, the pipeline pauses caused by cross-segment instruction dependencies are reduced, the decoding delay of high-frequency instructions is reduced, and the throughput of instruction execution is improved. In summary, the present invention realizes the dynamic adaptation, performance optimization and hardware friendliness of the instruction set architecture through scenario-based demand analysis, instruction function clustering, dependency optimization and multi-level extension architecture design, which can significantly improve the energy efficiency and resource utilization of different systems, and solve the problems of inefficient instruction distribution, lack of functional modularization, and insufficient hardware friendliness in traditional instruction set architecture.

[0086] Based on any of the above embodiments, Figure 4 The schematic diagram of the physical structure of a chip provided by an embodiment of the present invention is shown. The electronic device may include: a processor (processor) 410, a communication interface (Communications Interface) 420, a memory (memory) 430 and a communication bus 440. The processor 410, the communication interface 420, and the memory 430 communicate with each other via the communication bus 440. The processor 410 can call the logic instructions in the memory 430 to execute the following method:

[0087] Obtaining the scenario type of the target application scenario, and extracting the demand indicators corresponding to the target application scenario according to the scenario type;

[0088] Determine the corresponding instruction demand frequency according to the scenario type and perform functional clustering on the instructions;

[0089] Determining a target instruction set hierarchical extension architecture from candidate instruction set hierarchical extension architectures according to the requirement indicators;

[0090] According to the result of the instruction function clustering, the target instructions are divided into corresponding sections of the target instruction set hierarchical extension architecture.

[0091] In addition, the logic instructions in the above-mentioned memory 430 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the technical solution of the embodiment of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in the embodiment of the present invention. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0092] On the other hand, an embodiment of the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method provided in each of the above embodiments is implemented, for example, including:

[0093] Obtaining the scenario type of the target application scenario, and extracting the demand indicators corresponding to the target application scenario according to the scenario type;

[0094] Determine the corresponding instruction demand frequency according to the scenario type and perform functional clustering on the instructions;

[0095] Determining a target instruction set hierarchical extension architecture from candidate instruction set hierarchical extension architectures according to the requirement indicators;

[0096] According to the result of the instruction function clustering, the target instructions are divided into corresponding sections of the target instruction set hierarchical extension architecture.

[0097] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0098] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, or of course, by hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the existing technology can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or certain parts of the embodiments.

[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A method for extending an instruction set, characterized in that: The method comprises: Obtaining the scenario type of the target application scenario, and extracting the demand indicators corresponding to the target application scenario according to the scenario type; Determine the corresponding instruction demand frequency according to the scenario type and perform functional clustering on the instructions; Determining a target instruction set hierarchical extension architecture from candidate instruction set hierarchical extension architectures according to the requirement indicators; According to the result of the instruction function clustering, the target instructions are divided into corresponding sections of the target instruction set hierarchical extension architecture.

2. The instruction set extension method according to claim 1, wherein: Determining a target instruction set hierarchical extension architecture from candidate instruction set hierarchical extension architectures according to the requirement indicator specifically includes: Determining a second candidate instruction set hierarchical extension architecture based on a degree of matching between a performance requirement indicator in the requirement indicator and the candidate instruction set hierarchical extension architecture; If the second candidate instruction set hierarchical extension architecture is one, determining the second candidate instruction set hierarchical extension architecture as the target instruction set hierarchical extension architecture; Otherwise, the target instruction set hierarchical extension architecture is determined according to the matching degree between the hardware requirement indicator in the requirement indicator and the second candidate instruction set hierarchical extension architecture.

3. The instruction set extension method according to claim 1, wherein: The step of dividing the target instructions into corresponding sections of the target instruction set hierarchical extension architecture according to the result of the instruction function clustering specifically includes: Classifying a preset number of high-frequency instructions into a basic instruction area of the target instruction set hierarchical extension architecture, and classifying other instructions into an extended instruction area of the target instruction set hierarchical extension architecture; said dividing the instructions of the same cluster into the same section of the target instruction set hierarchical extension architecture according to the result of said instruction function clustering; Arrange dependent instructions into the same section.

4. The instruction set extension method according to claim 1, wherein: The instruction function clustering specifically includes: Determining the number of target clusters according to the scenario type of the target application scenario; The instruction function, operand type, and data dependency of the instructions corresponding to the scenario type are used as input features of the instructions, and the instructions corresponding to the scenario type are clustered according to the target cluster number.

5. The instruction set extension method according to claim 1, wherein: The determining of the corresponding instruction demand frequency according to the scenario type specifically includes: Select corresponding statistical tools and test cases according to the scenario type; quantifying and compiling the test cases using the statistical tool, and tracking and collecting the number of executions of each instruction in the test cases; The instruction demand frequency is obtained by filtering low-frequency instructions in the execution times and merging synonymous instructions.

6. The instruction set extension method according to claim 1, wherein: The candidate instruction set hierarchical extension architecture includes a basic instruction architecture, a first-level extension architecture and a second-level extension architecture.

7. The instruction set extension method according to claim 1, wherein: The scenario types include edge computing scenarios, lightweight AI scenarios and high-performance computing scenarios.

8. An instruction set extension system, characterized in that: The system comprises: A demand determination module is used to obtain the scenario type of the target application scenario and extract the demand indicators corresponding to the target application scenario according to the scenario type; An instruction analysis module is used to determine the corresponding instruction demand frequency according to the scenario type and perform functional clustering on the instructions; an architecture determination module, configured to determine a target instruction set hierarchical extension architecture from among candidate instruction set hierarchical extension architectures according to the requirement indicators; The instruction partitioning module is used to partition the target instructions into corresponding sections of the target instruction set hierarchical extension architecture according to the result of the instruction function clustering.

9. A chip, characterized in that: The chip includes: one or more processors; a memory for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors are enabled to perform the method according to any one of claims 1 to 7.

10. A storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed, the ternary calculation method according to any one of claims 1 to 7 is implemented.

Images