Repair method and device for retention time violation, computer equipment, readable storage medium and program product

Abstract

The invention relates to a retention time violation repairing method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: acquiring each clock path in the integrated circuit and corresponding path information; determining candidate nodes and the number of delay units corresponding to the candidate nodes from the clock path according to the path information; and inserting the number of the delay units into the corresponding candidate nodes. By adopting the method, the retention time violation in the integrated circuit can be repaired at one time, and the repair efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a hold time violation repair method, apparatus, computer equipment, computer-readable storage medium, and computer program product. Background Art

[0002] Fixing timing violations, especially hold violations, accounts for a significant portion of digital chip physical design work, often requiring dozens of iterations to achieve full timing closure. The number of buffers or inverters inserted to fix hold violations can occupy approximately 5% to 10% of the chip's total area. Traditional tools typically fix hold violations by inserting delay cells into the data path, leaving the clock path unchanged. This lengthens the data path to meet hold time requirements.

[0003] Since dozens of iterations are required to achieve complete timing convergence, the hold time repair time is long, which reduces the efficiency of hold time repair. Summary of the Invention

[0004] Based on this, it is necessary to provide a method, device, computer equipment, computer-readable storage medium and computer program product for repairing hold time violations that can reduce repair time and improve repair efficiency in response to the above technical problems.

[0005] In a first aspect, the present application provides a hold time violation repair method, the method comprising:

[0006] Obtain each clock path and corresponding path information in the integrated circuit;

[0007] Determining a candidate node and a number of delay units corresponding to the candidate node from the clock path according to the path information;

[0008] Insert the number of each delay unit into the corresponding candidate node.

[0009] In one embodiment, the clock path includes a startup clock path; the path information includes a clock node and a timing violation amount; and determining a candidate node and a number of delay units corresponding to the candidate node from the clock path based on the path information includes:

[0010] Determining a candidate node from the clock nodes of the startup clock path according to a first target model; wherein the first target model is determined based on the clock nodes;

[0011] The number of delay units of each candidate node is determined based on the candidate nodes and a second target model; wherein the second target model is determined based on the timing violation amount.

[0012] In one embodiment, before determining the candidate node from the clock nodes of the startup clock path according to the first target model, the method includes:

[0013] For each clock node, determine a first objective function based on the acquired parameters of the clock node, wherein the parameters include a number, a number of clock paths with timing violations for the clock node, and a number of clock paths with the fewest clock paths passing through the clock node;

[0014] Determining a first constraint condition based on the clock nodes of each of the start-up clock paths being less than or equal to a target number; wherein the target number is determined based on the number of the clock nodes;

[0015] The first objective model is determined based on the first objective function and the first constraint condition.

[0016] In one embodiment, the clock path includes a capture clock path; and before determining the insertion amount of each candidate node based on the candidate node and the second target model, the method includes:

[0017] For each clock path including the candidate node, determine a second objective function based on the obtained target timing violation of the clock path; wherein the target timing violation represents the timing violation remaining after the number of delay units is inserted into the clock path including the candidate node;

[0018] For each clock path including the candidate node, a second constraint condition is determined based on the acquired timing violation amount of the clock path, the target timing violation amount of the clock path, the number of first delay units, and the number of second delay units; wherein the number of first delay units indicates the insertion amount of the clock node on the capture clock path where any target sequential device is located when the starting sequential device is used as the starting sequential device; the number of second delay units indicates the insertion amount of the clock node on the start clock path where the endpoint sequential device is located when any sequential device is used as the endpoint sequential device; the target sequential device indicates the sequential device driven by the candidate node;

[0019] The second objective model is determined based on the second objective function and the second constraint condition.

[0020] In one embodiment, the second constraint condition includes a hold path constraint condition and a setup path constraint condition, and determining the second constraint condition based on the acquired timing violation amount of the clock path, the target timing violation amount of the clock path, the number of first delay units, and the number of second delay units includes:

[0021] determining a hold path constraint condition according to a timing violation amount of the clock path, a target timing violation amount of the clock path, and a difference between the number of the second delay units and the number of the first delay units;

[0022] determining, based on a difference between the number of the first delay units and the number of the second delay units, a path constraint condition;

[0023] A second constraint condition is determined according to the maintain path constraint condition and the establish path constraint condition.

[0024] In one embodiment, obtaining each clock path in the integrated circuit includes:

[0025] Obtaining the order of each clock node and the order of sequential devices in the integrated circuit; wherein the sequential devices include sequential devices driven by the clock nodes, and the clock nodes do not include logically equivalent nodes;

[0026] The clock path is determined according to the order of the clock nodes and the order of the sequential devices.

[0027] In a second aspect, the present application further provides a hold time violation repair device, the device comprising:

[0028] An acquisition module, configured to acquire each clock path in the integrated circuit and corresponding path information;

[0029] a determination module, configured to determine a candidate node and a number of delay units corresponding to the candidate node from the clock path according to the path information;

[0030] An inserting module is used to insert the number of each delay unit into the corresponding candidate node.

[0031] In a third aspect, the present application further provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above method when executing the computer program.

[0032] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the above method when executed by a processor.

[0033] In a fifth aspect, the present application also provides a computer program product, comprising a computer program, which implements the steps of the above method when executed by a processor.

[0034] The hold time violation repair method, apparatus, computer device, computer-readable storage medium, and computer program product described above first obtain each clock path in the integrated circuit and its corresponding path information; second, determine candidate nodes and the number of delay cells corresponding to the candidate nodes from the clock paths based on the path information; and finally, insert each delay cell into the corresponding candidate node. By determining all candidate nodes in the integrated circuit based on the path information and calculating the number of delay cells corresponding to all candidate nodes, the hold time violation repair can be quickly completed by simply inserting the number of delay cells corresponding to the selected node into the corresponding candidate node. This avoids dozens of iterations required to complete the hold time repair, reduces the hold time repair time, and thus improves repair efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments of the present application or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying any creative work.

[0036] Figure 1 A schematic diagram of a timing violation circuit in one embodiment;

[0037] Figure 2 1 is a flow chart of a method for repairing a hold time violation in one embodiment;

[0038] Figure 3 A schematic diagram of a process for determining the number of delay units corresponding to a candidate node in one embodiment;

[0039] Figure 4 A schematic diagram of a process for determining a first target model in one embodiment;

[0040] Figure 5 A schematic diagram of a timing violation circuit in another embodiment;

[0041] Figure 6 A schematic diagram of a process for determining a second target model in one embodiment;

[0042] Figure 7 A schematic diagram of a process for determining a second constraint condition in one embodiment;

[0043] Figure 8 A schematic diagram of a process for obtaining a clock path in one embodiment;

[0044] Figure 9 is a structural block diagram of a hold time violation repair device in another embodiment;

[0045] Figure 10 FIG. 1 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0047] like Figure 1 As shown, the rectangle represents the register, and the cloud-like pattern represents the combinational logic. Figure 1 There are two groups of registers, Group 1 and Group 2. Assume that a large number of registers in Group 2 have hold timing violations. The conventional repair method is to insert delay units on the data paths of these registers. However, due to the complex data path logic, it is often necessary to insert a delay unit on each data path to fix all timing violations.

[0048] This application is based on the principle that the parent register of Group 2 is Group 1, and Group 1's launch clock path shares a common point. By inserting a delay unit at this common point, the launch clock path for all registers in Group 2 can be lengthened, thereby reducing the number of timing violations in Group 2. Compared to inserting delay units separately in each data path, this significantly reduces the number of delay units inserted, saving area.

[0049] In one embodiment, Figure 2 As shown, a method for repairing a hold time violation is provided. This embodiment uses the method applied to a terminal as an example for illustration. It is understood that the method can also be applied to a server, or to a system including a terminal and a server, and implemented through interaction between the terminal and the server. In this embodiment, the method includes the following steps S202 to S206. Among them:

[0050] Step S202: Acquire each clock path in the integrated circuit and corresponding path information.

[0051] The layout design of an integrated circuit is implemented using components such as buffers, registers, and inverters. Each clock path includes at least one of these components. Path information can include clock points and timing slack.

[0052] Optionally, the server uses Primetime, a timing signoff tool, to write out information for each clock path in the integrated circuit. Each signoff corner must be written out, including the setup corner and the hold corner.

[0053] Step S204 : determining candidate nodes and the number of delay units corresponding to the candidate nodes from the clock path according to the path information.

[0054] Among them, the candidate node refers to the common point of the clock path with timing violation, such as Figure 1 The buffer in the buffer can drive the first group of registers Group1 while also driving the next level register of the first group of registers Group1, the second group of registers Group2.

[0055] Optionally, the server determines each candidate node in the integrated circuit from a clock path according to a clock point; and the server determines the number of delay units corresponding to each candidate node according to a timing slack corresponding to the clock node.

[0056] Optionally, the server generates an eco script based on the number of delay units inserted into each candidate node, inserts the delay unit into each candidate node, verifies the improvement of the timing violation, and when the verification is passed, the server executes the insertion of each delay unit into the corresponding candidate node.

[0057] Step S206: insert the number of each delay unit into the corresponding candidate node.

[0058] Optionally, before the server inserts each delay unit into the corresponding candidate node, it can generate an eco-script and insert delay units into each candidate node to verify the improvement in timing violations. If verification is passed, the server inserts each delay unit into the corresponding candidate node. Verification is considered passed if the total hold time timing violation is reduced while not causing setup time violations or hold time violations.

[0059] Table 1. Hold time violation and setup time violation after inserting delay cells

[0060]

[0061] Table 1 shows a significant improvement in hold time violations after inserting 402 delay cells in a specific integrated circuit project. The best result was a 38% reduction in corner TNS. Furthermore, no additional violations were generated in the setup corner.

[0062] In the above-described hold time violation repair method, each clock path in the integrated circuit and its corresponding path information are first obtained. Second, candidate nodes and the number of delay cells corresponding to the candidate nodes are determined from the clock paths based on the path information. Finally, the number of delay cells in each candidate node is inserted into the corresponding candidate node. By determining all candidate nodes in the integrated circuit based on the path information and calculating the number of delay cells corresponding to all candidate nodes, the hold time violation can be quickly repaired by inserting the number of delay cells corresponding to the selected node into the corresponding candidate node at once. This avoids dozens of iterations required to complete the hold time repair, reduces the hold time repair time, and thus improves repair efficiency.

[0063] In an exemplary embodiment, Figure 3 As shown, the clock path includes a startup clock path; the path information includes clock nodes and timing violation amounts; and determining candidate nodes and the number of delay units corresponding to the candidate nodes from the clock path based on the path information includes steps S302 to S304. Among them:

[0064] Step S302 : determining a candidate node from clock nodes of the start clock path according to the first target model.

[0065] The first target model is determined using linear programming based on each clock node in the integrated circuit. Candidate nodes must meet two conditions: first, the candidate node must appear more frequently on the launch clock path than on the capture clock path; and second, the candidate node must be a common point on at least A clock paths in the integrated circuit, for example, A = 1000.

[0066] Optionally, the server establishes a first target model in advance through linear programming based on the selection conditions of the candidate nodes. Then, the server determines the candidate nodes from the clock nodes of the start clock path based on the first target model. Figure 1 As shown, the candidate node is a common point in the startup clock path, that is, a buffer.

[0067] Optionally, the server determines a plurality of candidate nodes from the clock nodes of each start clock path in the integrated circuit according to the pre-built first target model. The plurality of candidate nodes determined according to the first target model must be candidate nodes that meet both the first and second conditions above.

[0068] Step S304 : determining the number of delay units of each candidate node based on the candidate node and the second target model.

[0069] The second target model is determined based on the amount of timing violations. The number of delay units for each candidate node, determined based on the second target model, must meet two conditions: first, the number of delay units inserted must effectively reduce the total number of hold violations on the path where the candidate node resides; second, the number of delay units inserted must not degrade the setup time of the path where the candidate node resides.

[0070] Optionally, the server uses the linear programming method again to establish a second target model based on the conditions for determining the number of delay units of the candidate nodes. The server determines the number of delay units of each candidate node based on the candidate nodes and the second target model.

[0071] Optionally, the server determines the number of delay units for each candidate node based on a pre-built second target model. The number of delay units for each candidate node determined based on the second target model must satisfy the conditions of effectively reducing the total number of hold violations on the path where the candidate node is located and not degrading the setup time of the path where the candidate node is located.

[0072] In this embodiment, the pre-built first target model and second target model can be used to determine candidate nodes in the integrated circuit and the number of delay units corresponding to each candidate node at one time, thereby shortening the timing sign-off cycle and reducing repair time.

[0073] In an exemplary embodiment, Figure 4 As shown, before determining the candidate node from the clock nodes of the start clock path according to the first target model, the process includes steps S402 to S406.

[0074] Step S402 : For each clock node, determine a first objective function based on the acquired parameters of the clock node.

[0075] The parameters include the number, the number of clock paths with timing violations in the clock node, and the number of clock paths that pass through the least number of clock nodes.

[0076] Optionally, the server obtains the number of each clock node in the integrated circuit, denoted as Pn, which is a binary value (0 or 1) with n as the subscript. The server also counts the number of all clock nodes in the integrated circuit, denoted as N. The server obtains the number of clock paths with timing violations for the clock node denoted as Pn, denoted as Fn. The server also obtains the number of clock paths that pass through the clock node with the fewest number of clock paths, denoted as A. A indicates that the number of clock paths that pass through the clock node cannot be less than A, for example, A is 100.

[0077] The server determines the first objective function according to the number of the clock node, the number of clock paths with timing violations in the clock node, and the number of clock paths that pass through the clock node at least, as shown in formula (1).

[0078] Formula (1)

[0079] Where N is the number of all clock nodes; Pn is the number of clock nodes, which is a binary value (0 or 1) with n as the subscript; Fn is the number of clock paths with timing violations through the clock node numbered Pn; and A is the number of clock paths with the fewest clock nodes.

[0080] Step S404 : determining a first constraint condition based on the number of clock nodes of each startup clock path being less than or equal to a target number.

[0081] The target number is determined based on the number of clock nodes.

[0082] Optionally, the server determines the first constraint condition based on the fact that the number of clock nodes on each launch clock path is less than or equal to the target number n, that is, at most n points on each launch clock path are selected, as shown in formula (2).

[0083] Formula (2)

[0084] Where m is the number of the clock node, M is the number of clock nodes on this path, and Pm is a binary value with m as the subscript.

[0085] Step S406: Determine a first target model based on the first target function and the first constraint condition.

[0086] Optionally, the server determines a first target model based on the first objective function formula (1) and the first constraint formula (2). Under the constraint that each clock path with a timing violation has at most n clock nodes as candidate nodes, the frequency of the candidate nodes appearing on the launch clock path is greater than the frequency of the candidate nodes appearing on the capture clock path; and the candidate nodes are common points on at least A paths, that is, when formula (1) is maximized, the server obtains the common points on the clock paths, and these common points will be used as candidate nodes for clock tree adjustment.

[0087] The first objective function:

[0088] Formula (1)

[0089] The first constraint is:

[0090] Formula (2)

[0091] Where N is the number of all clock nodes; Pn is the number of clock nodes, which is a binary value (0 or 1) with n as the subscript; Fn is the number of clock paths with timing violations at the clock node numbered Pn; A is the number of clock paths that pass through the fewest clock nodes; m is the number of clock nodes, and M is the number of clock nodes on this path. Pm is a binary value with m as the subscript.

[0092] It should be noted that the construction principle of the first target model is as follows:

[0093] like Figure 5 As shown in the figure, assuming that there are a large number of hold time timing violations from register 1reg1 to the first register group reg group1, the capture clock path is: path1: buf0 -> buf3 -> buf6 -> buf5 -> reg* / CK. The startup clock path is: path2: buf0 -> buf1 -> buf2.

[0094] To fix hold time violations, we need to select suitable clock nodes in path2's buf as candidate nodes. Now let's examine each of these buffers one by one. For buf0, this clock node is on both the launch and capture clock paths, so inserting a delay cell here has no effect. Regarding buf1 and buf2, buf1 drives both reg1 and reg2. buf2 only drives reg1, so the choice of which clock node to use as a candidate depends on the situation of reg2: if there are also numerous hold violations from reg2 to reg group2, then clock node buf1 is clearly a more suitable candidate because inserting a delay cell on buf1 can simultaneously fix the hold violations for reg group2. The above discussion assumes that both reg1 and reg2 have sufficient hold margins, and that both reg group1 and reg group2 have sufficient setup margins.

[0095] Using a linear optimization algorithm, we can determine which candidate node, buf1 or buf2, is superior based on the number of violation paths. It's important to note that this step only selects candidate nodes for delay cell insertion. Whether these candidate nodes can effectively fix the timing violation by inserting a delay cell will be determined in subsequent steps.

[0096] In this embodiment, a first objective model is constructed through the first objective function and the first constraint condition, and several candidate nodes can be obtained at one time through the first objective model, thereby reducing the iteration time during repair.

[0097] In an exemplary embodiment, Figure 6 As shown, the clock path includes a capture clock path; before determining the insertion amount of each candidate node based on the candidate node and the second target model, steps S602 to S606 are included.

[0098] Step S602 : For each clock path including the candidate node, determine a second objective function based on the acquired target timing violation of the clock path.

[0099] The target timing violation represents the remaining timing violation after the number of delay units is inserted into the clock path containing the candidate node.

[0100] Optionally, for each clock path containing a candidate node, the server obtains the remaining timing violation slack of each clock path containing the candidate node after inserting a certain number of delay units. When the target timing violation slack of the clock path obtained by the server is minimized, a second objective function is established, as shown in Formula (3).

[0101] Second objective function:

[0102] min Formula (3)

[0103] Where M is the number of all clock paths, m is the number of the clock path, and Rm is the remaining slack of the clock path numbered m after the delay unit is inserted.

[0104] Step S604 : for each clock path including the candidate node, determine a second constraint condition based on the acquired timing violation of the clock path, the target timing violation of the clock path, the number of first delay units, and the number of second delay units.

[0105] Among them, the number of first delay units P capture [j] indicates the insertion amount of the clock node on the capture clock path where the starting point sequential device is located when any target sequential device is used as the starting point sequential device; the number of second delay units P launch [m] indicates the insertion amount of the clock node on the start clock path where any timing device is located when the destination timing device is used as the destination timing device; the target timing device indicates the timing device driven by the candidate node.

[0106] like Figure 5 In the example, when the candidate node is buf2, buf2 only drives reg1 as the target sequential device. The number of the first delay unit P capture [j] is the number of candidate nodes numbered j inserted into capture, which means that all paths from reg1 to reggroup1 must not have setup violations. launch [m] is the insertion amount of the candidate node numbered m on the startup clock path, that is, the hold of reg3 -> reg1 cannot have a violation.

[0107] Optionally, for each clock path containing a candidate node, a maintain path constraint and an establish path constraint are determined based on the acquired timing violation amount of the clock path, the target timing violation amount of the clock path, the number of first delay units, and the number of second delay units, and the maintain path constraint and the establish path constraint are jointly determined to determine the second constraint condition.

[0108] Step S606: Determine a second target model based on the second target function and the second constraint condition.

[0109] Optionally, the server determines the second target model according to the second target function formula (3) and the second constraint condition.

[0110] Second objective function:

[0111] min Formula (3)

[0112] Where M is the number of all clock paths, m is the number of the clock path, and Rm is the remaining slack of the clock path numbered m after the delay unit is inserted.

[0113] The second constraint condition includes maintaining path constraints and establishing path constraints.

[0114] It should be noted that the construction principle of the second model is as follows:

[0115] like Figure 5 Assume that in the previous step, there are a large number of hold violations in reg1->reg group1, and buf2 is selected as a candidate node. Then, it is necessary to examine the setup and hold timing of all registers driven by this buffer. In the figure, buf2 only drives reg1, so after inserting a delay unit on buf2, examine reg1:

[0116] There is a second constraint:

[0117] 1. Establish path constraints: All clock paths from reg1 to reg group1 must not have setup violations.

[0118] 2. Hold path constraint: The hold from reg3 -> reg1 cannot be violated.

[0119] The second objective function is to minimize the total negative slack (TNS): the hold of reg1, or the sum of the hold slack of all paths from reg1 to reg group 1, is added to the total TNS for the entire IC. The total TNS reaches a minimum value under different insertion points and insertion amounts. This minimum value is the target of the second objective function.

[0120] In this embodiment, a second objective model is constructed using a second objective function and a second constraint. This second objective model can be used to determine the number of delay units corresponding to several candidate nodes at once, reducing the iteration time required for repair. Compared to inserting delay units separately on each data path, this application significantly reduces the number of delay units inserted by inserting them at the candidate nodes, thereby saving area.

[0121] In an exemplary embodiment, Figure 7 As shown, the second constraint condition includes a maintain path constraint condition and a setup path constraint condition, and the second constraint condition is determined based on the acquired timing violation amount of the clock path, the target timing violation amount of the clock path, the number of the first delay unit and the number of the second delay unit, including steps S702 to S706. Wherein:

[0122] Step S702 : determining a hold path constraint condition according to the timing violation of the clock path, the target timing violation of the clock path, and the difference between the number of the second delay units and the number of the first delay units.

[0123] Optionally, for each hold path, there is a constraint condition, as shown in formula (4). The server obtains the timing violation of the clock path, the target timing violation of the clock path, and the difference between the number of the second delay units and the number of the first delay units, and takes the sum of the three to be greater than or equal to 0 as the hold path constraint condition.

[0124] slack[i] + R[i] + P launch [m] –P capture [j]>=0 Formula (4)

[0125] Where slack[i] is the timing violation of the clock path numbered i; R[i] is the remaining slack after inserting the buffer, which is the target timing violation of the clock path; P launch [m] is the insertion amount of candidate node numbered m on the startup clock path, that is, the number of second delay units; Pcapture[j] is the insertion amount of candidate node numbered j on the capture clock path, that is, the number of first delay units.

[0126] Step S704 : determining a path constraint condition to be established according to the difference between the number of the first delay units and the number of the second delay units.

[0127] Optionally, for each setup path, there is a constraint condition, as shown in formula (5). The server obtains the number of first delay units and the number of second delay units, and uses the difference between the number of first delay units and the number of second delay units as the path setup constraint condition.

[0128] -P launch [m] +P capture [j]>=0 Formula (5)

[0129] Where, P launch [m] is the insertion amount of candidate node numbered m on the startup clock path, that is, the number of second delay units; Pcapture[j] is the insertion amount of candidate node numbered j on the capture clock path, that is, the number of first delay units.

[0130] Step S706: Determine a second constraint condition based on the maintained path constraint condition and the established path constraint condition.

[0131] Optionally, the server determines the second constraint condition according to the path constraint condition maintaining formula (4) and the path constraint condition establishing formula (5).

[0132] In this embodiment, the second constraint condition is determined by ensuring that the amount of inserted delay can effectively reduce the total amount of maintenance violations and that the amount of inserted delay cannot deteriorate the setup time. The second target model can be constructed and solved to obtain the number of delay units of the candidate node at one time.

[0133] In an exemplary embodiment, Figure 8 As shown, obtaining each clock path in the integrated circuit includes steps S802 to S804.

[0134] Step S802 , obtaining the sequence of clock nodes and sequential devices in the integrated circuit; wherein the sequential devices include sequential devices driven by clock nodes, and the clock nodes do not include logically equivalent nodes.

[0135] A clock node can be a buffer, but does not include a logically equivalent buffer or inverter. A sequential device is a device driven by a clock node, such as a register driven by a buffer.

[0136] Optionally, the server obtains the sequence of clock nodes and the sequence of timing devices in the integrated circuit.

[0137] Step S804 : determining a clock path according to the sequence of the clock nodes and the sequence of the sequential devices.

[0138] Optionally, the order of the clock nodes of the server and the order of the timing devices determine the clock path, such as Figure 5As shown, the path from reg2 to reg group 2 has at least one clock path from reg2 to each reg in reg group 2: the launch clock path's nodes: buf0 -> buf1 -> buf4 -> reg2 / CK; and the capture clock path's nodes: buf0 -> buf3 -> buf7 -> reg* / CK (where reg* is any reg in reggroup 2). Note that buf3 and buf6 are connected one-to-one on the capture clock path, so only one of these two nodes needs to be listed.

[0139] For example, the path from reg1 to reg group 1 has at least one clock path from reg1 to each reg in reg group 1: the launch clock path's nodes are buf0 -> buf1 -> buf2 -> reg1 / CK; and the capture clock path's nodes are buf0 -> buf3 -> buf5 -> reg* / CK (where reg* is any reg in reg group 1). Note that buf3 and buf6 are connected one-to-one on the capture clock path, so only one of these two nodes needs to be written.

[0140] Similarly, the launch time path and capture time path of the path from reg3 to reg group1 can also be determined. It should be noted that the clock node does not include a logically equivalent buffer or inverter, that is, Figure 5 Medium cloud pattern.

[0141] In this embodiment, the startup clock path and the capture clock path are determined by the order of the clock nodes of the server and the order of the timing devices, and the clock nodes in the integrated circuit are written as completely as possible without excluding logically equivalent clock nodes, thereby simplifying the linear programming model.

[0142] In an exemplary embodiment, a server uses Primetime, a timing signoff tool, to write out information corresponding to each clock path in an integrated circuit. Each signoff corner must be written out, including the setup corner and the hold corner.

[0143] The server determines a candidate node from the clock nodes of the start clock path according to the first target model.

[0144] The first objective model includes a first objective function and a first constraint condition.

[0145] The first objective function:

[0146] Formula (1)

[0147] The first constraint is:

[0148] Formula (2)

[0149] Where N is the number of all clock nodes; Pn is the number of clock nodes, which is a binary value (0 or 1) with n as the subscript; Fn is the number of clock paths with timing violations at the clock node numbered Pn; A is the number of clock paths that pass through the fewest clock nodes; m is the number of clock nodes, and M is the number of clock nodes on this path. Pm is a binary value with m as the subscript.

[0150] The server determines the number of delay units to be inserted corresponding to the candidate node according to the candidate node and the second target model.

[0151] The second objective model includes a second objective function and a second constraint condition, and the second constraint condition includes a path maintenance constraint condition and a path establishment constraint condition.

[0152] Second objective function:

[0153] min Formula (3)

[0154] Maintain path constraints:

[0155] slack[i] + R[i] + P launch [m] –P capture [j]>=0 Formula (4)

[0156] Create path constraints:

[0157] -P launch [m] +P capture [j]>=0 Formula (5)

[0158] Where M is the number of all clock paths. m is the number of the clock path. Rm is the remaining slack of the clock path numbered m after the delay unit is inserted. slack[i] is the timing violation of the clock path numbered i; R[i] is the remaining slack after the buffer is inserted, which is the target timing violation of the clock path; P launch [m] is the insertion amount of candidate node numbered m on the startup clock path, that is, the number of second delay units; Pcapture[j] is the insertion amount of candidate node numbered j on the capture clock path, that is, the number of first delay units.

[0159] Before the server inserts each delay unit into the corresponding candidate node, it can generate an eco script and insert delay units into each candidate node to verify the improvement in timing violations. If verification is passed, the server inserts each delay unit into the corresponding candidate node. Verification is considered passed if the total hold time timing violation is reduced while not causing setup time violations or hold time violations.

[0160] It should be understood that, although the various steps in the flowcharts involved in the various embodiments described above are displayed in sequence according to the instructions of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the flowcharts involved in the various embodiments described above can include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0161] Based on the same inventive concept, embodiments of the present application also provide a hold time violation repair device for implementing the hold time violation repair method described above. The implementation solution provided by this device is similar to the implementation solution described in the above method. Therefore, the specific limitations of one or more hold time violation repair device embodiments provided below can be found in the above-mentioned limitations of the hold time violation repair method and will not be repeated here.

[0162] In an exemplary embodiment, Figure 9 As shown, a hold time violation repair device is provided, comprising: an acquisition module 901, a determination module 902 and an insertion module 903, wherein:

[0163] An acquisition module 901 is configured to acquire each clock path and corresponding path information in the integrated circuit;

[0164] A determination module 902 is configured to determine a candidate node and the number of delay units corresponding to the candidate node from a clock path according to the path information;

[0165] The inserting module 903 is configured to insert the number of each delay unit into the corresponding candidate node.

[0166] In an exemplary embodiment, the clock path includes a startup clock path; the path information includes a clock node and a timing violation amount; the determination module 902 includes:

[0167] a candidate node determination unit, configured to determine a candidate node from clock nodes of a start clock path according to a first target model; wherein the first target model is determined based on clock nodes;

[0168] The delay unit quantity determination unit is used to determine the quantity of delay units of each candidate node based on the candidate node and the second target model; wherein the second target model is determined based on the timing violation amount.

[0169] In an exemplary embodiment, a hold time violation repair apparatus further includes:

[0170] The first target model generation module is used to determine a first target function for each clock node based on the acquired parameters of the clock node; wherein the parameters include the number, the number of clock paths with timing violations at the clock node, and the number of clock paths with the least number of clock nodes; determine a first constraint condition based on the clock nodes of each startup clock path being less than or equal to the target number; wherein the target number is determined based on the number of clock nodes; and determine a first target model based on the first target function and the first constraint condition.

[0171] In an exemplary embodiment, a hold time violation repair apparatus includes a clock path including a capture clock path; and further includes:

[0172] A second target model generation module is used to determine, for each clock path containing a candidate node, a second target function based on the target timing violation of the clock path obtained; wherein the target timing violation represents the timing violation remaining after the number of delay units is inserted into the clock path containing the candidate node; for each clock path containing a candidate node, a second constraint condition is determined based on the timing violation of the clock path obtained, the target timing violation of the clock path, the number of first delay units, and the number of second delay units; wherein the number of first delay units indicates the insertion amount of the clock node on the capture clock path where the starting timing device is located when any target timing device is used as the starting timing device; the number of second delay units indicates the insertion amount of the clock node on the start clock path where the end timing device is located when any timing device is used as the end timing device; the target timing device indicates the timing device driven by the candidate node; and a second target model is determined based on the second target function and the second constraint condition.

[0173] In an exemplary embodiment, the second constraint condition includes a path-maintaining constraint condition and a path-establishing constraint condition, and the second target model generating module includes:

[0174] a hold path constraint condition determination unit, configured to determine a hold path constraint condition based on a timing violation amount of the clock path, a target timing violation amount of the clock path, and a difference between the number of the second delay units and the number of the first delay units;

[0175] a path constraint condition determination unit, configured to determine a path constraint condition according to a difference between the number of the first delay units and the number of the second delay units;

[0176] The second constraint condition determining unit is configured to determine the second constraint condition according to the maintaining path constraint condition and the establishing path constraint condition.

[0177] In an exemplary embodiment, the acquisition module is further used to obtain the order of each clock node and the order of timing devices in the integrated circuit; wherein the timing device includes a timing device driven by a clock node, and the clock node does not include logically equivalent nodes; the clock path is determined according to the order of each clock node and the order of the timing devices.

[0178] Each module in the above-mentioned hold time violation repair device can be implemented in whole or in part through software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in the computer device in the form of software, so that the processor can call and execute the corresponding operations of each module.

[0179] In an exemplary embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as shown in FIG. Figure 10 As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, abbreviated as I / O) and a communication interface. The processor, memory and input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The database of the computer device is used to store hold time violation repair data. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a hold time violation repair method is implemented.

[0180] Those skilled in the art will understand that Figure 10 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0181] In one embodiment, a computer device is further provided, including a memory and a processor. The memory stores a computer program, and the processor implements the steps in the above method embodiments when executing the computer program.

[0182] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0183] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0184] Those skilled in the art will understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. In particular, any reference to memory, database, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The databases involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the various embodiments provided herein may be, but are not limited to, general-purpose processors, central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), programmable logic devices (PLDs), quantum computing-based data processing logic devices, artificial intelligence (AI) processors, and the like.

[0185] The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0186] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A hold time violation repair method, characterized in that: The method comprises: Obtain each clock path and corresponding path information in the integrated circuit; Determining a candidate node and a number of delay units corresponding to the candidate node from the clock path according to the path information; Insert the number of each delay unit into the corresponding candidate node.

2. The method according to claim 1, characterized in that The clock path includes a startup clock path; the path information includes a clock node and a timing violation amount; The determining, from the clock path according to the path information, a candidate node and a number of delay units corresponding to the candidate node, includes: Determining a candidate node from the clock nodes of the startup clock path according to a first target model; wherein the first target model is determined based on the clock nodes; The number of delay units of each candidate node is determined based on the candidate nodes and a second target model; wherein the second target model is determined based on the timing violation amount.

3. The method according to claim 2, characterized in that Before determining a candidate node from the clock nodes of the startup clock path according to the first target model, the method includes: For each clock node, determine a first objective function based on the acquired parameters of the clock node, wherein the parameters include a number, a number of clock paths with timing violations for the clock node, and a number of clock paths with the fewest clock paths passing through the clock node; Determining a first constraint condition based on the clock nodes of each of the start-up clock paths being less than or equal to a target number; wherein the target number is determined based on the number of the clock nodes; The first objective model is determined based on the first objective function and the first constraint condition.

4. The method according to claim 2, characterized in that The clock path includes a capture clock path; before determining the insertion amount of each candidate node based on the candidate node and the second target model, the method includes: For each clock path including the candidate node, determine a second objective function based on the obtained target timing violation of the clock path; wherein the target timing violation represents the timing violation remaining after the number of delay units is inserted into the clock path including the candidate node; For each clock path including the candidate node, a second constraint condition is determined based on the acquired timing violation amount of the clock path, the target timing violation amount of the clock path, the number of first delay units, and the number of second delay units; wherein the number of first delay units indicates the insertion amount of the clock node on the capture clock path where any target sequential device is located when the starting sequential device is used as the starting sequential device; the number of second delay units indicates the insertion amount of the clock node on the start clock path where the endpoint sequential device is located when any sequential device is used as the endpoint sequential device; the target sequential device indicates the sequential device driven by the candidate node; The second objective model is determined based on the second objective function and the second constraint condition.

5. The method according to claim 4, characterized in that The second constraint condition includes a maintain path constraint condition and a setup path constraint condition, and determining the second constraint condition based on the acquired timing violation amount of the clock path, the target timing violation amount of the clock path, the number of first delay units, and the number of second delay units includes: determining a hold path constraint condition according to a timing violation amount of the clock path, a target timing violation amount of the clock path, and a difference between the number of the second delay units and the number of the first delay units; determining, based on a difference between the number of the first delay units and the number of the second delay units, a path constraint condition; A second constraint condition is determined according to the maintain path constraint condition and the establish path constraint condition.

6. The method according to claim 1, characterized in that The obtaining of each clock path in the integrated circuit includes: Obtaining the order of each clock node and the order of sequential devices in the integrated circuit; wherein the sequential devices include sequential devices driven by the clock nodes, and the clock nodes do not include logically equivalent nodes; The clock path is determined according to the order of the clock nodes and the order of the sequential devices.

7. A hold time violation repair device, characterized in that: The device comprises: An acquisition module, configured to acquire each clock path in the integrated circuit and corresponding path information; a determination module, configured to determine a candidate node and a number of delay units corresponding to the candidate node from the clock path according to the path information; An inserting module is used to insert the number of each delay unit into the corresponding candidate node.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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