Image sensor and high dynamic range adaptive imaging method

Abstract

The present disclosure provides an image sensor and a high dynamic range adaptive imaging method, wherein the image sensor includes: a pixel array, including an array-arranged photodiode acquisition circuit that generates an image charge signal in response to incident light, the photodiode acquisition circuit including a dual conversion gain transistor and a row selection transistor; a pre-read module for receiving an initial sample of the pixel photoresponse signal before the read phase and comparing it with a threshold signal to generate a control signal; a read module for driving the photodiode acquisition circuit according to the control signal to read only the pixel electrical signal under the selected path for output; and a synthesis module for generating a path label corresponding to the pixel electrical signal and synthesizing an image. The present disclosure can determine the optimal signal gain mode for output by performing a rapid pre-read judgment before the read phase, effectively improving the frame rate, reducing power consumption, and achieving dynamic range optimization.

Description

Technical Field

[0001] The present disclosure relates to the field of image sensors, and in particular to an image sensor and a high dynamic range adaptive imaging method. Background Art

[0002] Image sensors are electronic devices that convert light signals into electrical signals. They are a crucial component of modern optoelectronic technology and are widely used in devices such as cameras, webcams, smartphones, and drones. The core function of an image sensor is to capture light and generate corresponding image data, and its performance directly impacts image quality. Image sensors typically consist of multiple pixel circuits, each responsible for sensing the light intensity at its corresponding location. Pixel circuits typically include a photodiode (PD), multiple transistors, and related circuit structures to collect, store, read, and transmit light signals.

[0003] Image sensors currently face numerous challenges in achieving high dynamic range (HDR) imaging. This is particularly true in scenarios with strong lighting contrast, such as backlit environments and outdoor scenes with day-to-night variations. Existing single-gain imaging methods are unable to capture details in both dark and bright areas, resulting in over- or underexposure. To address this issue, the industry has proposed a variety of dynamic range extension technologies, including multi-frame synthesis and dual conversion gain (DCG). Among these, the LOFIC structure, which supports different gain paths at the pixel end, is gradually becoming a mainstream solution.

[0004] Figure 1 It is a photodiode acquisition circuit in the image sensor of the prior art. Figure 1 As shown in the figure, in existing lateral overflow integrating capacitor (LOFIC) technology, whenever electrons overflow, they flow through the photodiode (PD), floating diffusion node (FD), and LOFIC capacitor in sequence. All electrons are read out, thereby increasing the dynamic range.

[0005] However, existing LOFIC methods usually read the signals of the high gain level signal (HCG) and low gain level signal (LCG) paths simultaneously in each frame of image (as shown below Figure 1 Its main defects include:

[0006] 1. Since signals from two paths are read, the reading time and data volume are doubled, severely limiting frame rate performance.

[0007] 2. In actual output, only one gain path signal is usually retained for display or processing, while the reading and transmission of the other path wastes resources and increases overall power consumption.

[0008] 3. The dynamic range synthesis operation relies on the back-end image signal processor (ISP), which increases system latency and reduces flexibility.

[0009] 4. The above problems are particularly prominent in applications such as mobile devices that have high requirements for battery life and real-time response.

[0010] Although the existing LOFIC technology can achieve dynamic range expansion through dual-gain (high-gain HCG and low-gain LCG) paths, it still has many shortcomings in practical applications. Specifically:

[0011] 1. Each frame of the image requires reading signals from two gain paths simultaneously, which results in an exponential increase in the amount of data and prolonged reading time, severely restricting the system's frame rate performance.

[0012] 2. Usually, only the signal from one of the gain paths is used for subsequent image processing or display, while the other is discarded, resulting in redundant signal acquisition and transmission, which in turn leads to increased energy consumption.

[0013] 3. The dynamic range synthesis process relies on the back-end image signal processor (ISP), which not only increases system processing latency but also reduces the flexibility of the overall solution.

[0014] 4. These problems are particularly evident in mobile terminal devices that have strict requirements on low power consumption and high response speed, becoming a key factor restricting their further application.

[0015] In view of this, the present invention provides an image sensor and a high dynamic range adaptive imaging method.

[0016] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0017] To address the above-mentioned issues, the present invention proposes an image sensor and a high dynamic range adaptive imaging method, which overcome the difficulties of the existing technology. By performing a quick pre-reading judgment before the reading stage, it can decide whether to set this pixel to high-gain or low-gain mode, retaining only the optimal signal for output, effectively improving the frame rate, reducing power consumption, and bringing about dynamic range optimization.

[0018] An embodiment of the present invention provides an image sensor, comprising:

[0019] A pixel array comprising a photodiode acquisition circuit arranged in an array and generating an image charge signal in response to incident light, wherein the photodiode acquisition circuit comprises at least a dual conversion gain transistor for switching a readout path and a row select transistor for generating a pre-read voltage signal based on a floating diffusion node;

[0020] a pre-read module, configured to receive an initial sample of a pixel photoelectric response signal before a read phase, and compare the pre-read voltage signal with a threshold signal to generate a control signal for controlling the photodiode acquisition circuit;

[0021] a reading module, configured to select one of at least two gain paths according to the control signal, and drive the photodiode acquisition circuit based on the control signal to read only the pixel electrical signal in the selected path for output; and

[0022] The synthesis module is used to generate a path label corresponding to the pixel electrical signal and synthesize the image.

[0023] Preferably, the photodiode acquisition circuit forms at least two readout paths of gain signals based on the state of the dual conversion gain transistor;

[0024] A first end of the pre-reading module is connected to the gate of the dual-conversion gain transistor, and a second end is connected to the first end of the row selection transistor. The pre-reading module generates the control signal to control the conduction state of the dual-conversion gain transistor based on a comparison result of a pre-reading voltage signal received at the second end of the row selection transistor and the threshold signal, so as to output a gain signal based on a readout path of only one gain signal.

[0025] Preferably, the photodiode acquisition circuit includes:

[0026] a photodiode that photogenerates image charge in response to incident light;

[0027] a floating diffusion node coupled to receive first overflow image charge from the photodiode;

[0028] a floating diffusion capacitor coupled between the floating diffusion node and a ground terminal;

[0029] a transfer transistor coupled between the photodiode and the floating diffusion node to transfer the image charge to the floating diffusion node;

[0030] a capacitive connection node coupled to receive the second overflowed image charge from the floating diffusion node, the dual conversion gain transistor coupled between the floating diffusion node and the capacitive connection node;

[0031] a reset transistor coupled between a reset voltage signal and the capacitor connection node;

[0032] a lateral overflow integrating capacitor coupled between the capacitor connection node and a ground terminal;

[0033] A source follower, wherein a first end of the source follower is coupled to a drain voltage signal, a gate is coupled to the floating diffusion node, and a first end of the row selection transistor is coupled to a second end of the source follower; in a pre-reading stage after an exposure stage, the pre-reading module controls the state of the dual conversion gain transistor based on a comparison result of a pre-reading voltage signal received from the row selection transistor and a threshold signal, so as to output only one gain signal of a high gain level signal or a low gain level signal.

[0034] Preferably, the low gain level signal is a mixed charge of the first overflowing image charge and the second overflowing image charge read out based on the low gain path, and the high gain level signal is the first overflowing image charge read out based on the high gain path.

[0035] Preferably, the pre-reading module includes a comparator, two input terminals of the comparator are respectively connected to the second terminal of the row selection transistor and the threshold signal, and an output terminal of the comparator is connected to the gate of the dual conversion gain transistor.

[0036] Preferably, the synthesis module mixes the output signal of the pre-reading module with the image digital signal of the corresponding photodiode as the pixel output signal of the corresponding photodiode, and arranges and combines the pixel output signals according to pixel positions to generate a picture.

[0037] Preferably, the method further comprises: a row decoding module for selecting pixels row by row from top to bottom.

[0038] Preferably, it also includes:

[0039] a readout control transistor, one end of which is connected to the gate of the dual conversion gain transistor and the other end of which is connected to the pre-reading module, wherein the readout control transistor is turned on only during the reading phase;

[0040] The gate of the dual-conversion gain transistor is connected to an exposure control transistor external to the row selector of the image sensor, one end of the dual-conversion gain transistor is connected to the gate of the dual-conversion gain transistor, and the other end is connected to an exposure control signal. The exposure control transistor remains turned on only in the reset phase and the exposure phase.

[0041] An embodiment of the present invention provides a high dynamic range adaptive imaging method, which uses the above-mentioned image sensor and includes:

[0042] S110, resetting each node to an initial state;

[0043] S120, a photodiode collection circuit for generating an image charge signal from the pixel array in response to incident light;

[0044] S130, performing initial sampling on the pixel photoelectric response signal before the reading phase, and comparing the pre-read voltage signal with a threshold signal to generate a control signal for controlling the photodiode acquisition circuit;

[0045] S140, selecting one of at least two gain paths according to the control signal, and driving the photodiode acquisition circuit based on the control signal to read only the pixel electrical signal in the selected path for output; and

[0046] S150: Generate a path label corresponding to the pixel electrical signal and synthesize a picture.

[0047] An embodiment of the present invention provides another high dynamic range adaptive imaging method, which uses the above-mentioned image sensor and includes:

[0048] S210, reset phase, reset each node to the initial state;

[0049] S220, exposure stage, the photodiode accumulates photogenerated electrons to generate a pixel photoelectric response signal, the electrons overflowing from the photodiode enter the floating diffusion capacitor, and the electrons overflowing from the floating diffusion capacitor enter the lateral overflow integration capacitor;

[0050] S230, in a pre-reading stage, performing initial sampling on the pixel photoelectric response signal to obtain a pre-read voltage signal, comparing the pre-read voltage signal with a threshold signal, and generating a control signal for controlling the photodiode acquisition circuit;

[0051] S240, a reading stage, for selecting one of at least two gain paths according to the control signal, and driving the photodiode acquisition circuit based on the control signal to read only the pixel electrical signal under the selected path for output; and

[0052] S250 , a merging stage, mixing the output signal of the pre-reading module with the image digital signal of the corresponding photodiode as the pixel output of the corresponding photodiode.

[0053] Preferably, in said S230, it includes:

[0054] S231, sampling the reference reset voltage in a high gain mode to implement correlated double sampling; and

[0055] S232 , turning off the dual conversion gain transistor, transferring only the charge in the photodiode to the floating diffusion node, and collecting a pre-read voltage signal in a high gain mode path as a pre-read voltage signal.

[0056] Preferably, in the S240, the following steps are included:

[0057] S241, comparing the pre-read voltage signal with a threshold signal, and generating a gate signal of the dual conversion gain transistor accordingly, thereby generating a read gain path for the pixel; and

[0058] S242. According to the read gain path, only one gain path reading is performed, and a mixed charge of the first overflow image charge and the second overflow image charge read out based on the low gain path is output, or the first overflow image charge read out based on the high gain path is output.

[0059] The present invention proposes an image sensor and a high dynamic range adaptive imaging method, which can be based on the LOFIC dynamic range reading method of adaptive path selection. By performing a fast pre-reading judgment before the reading stage, it decides whether to set this pixel to high gain or low gain mode, retaining only the optimal signal for output, fundamentally solving the limitations of the existing LOFIC structure in power consumption, frame rate and processing complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0061] Figure 1 It is a photodiode acquisition circuit in an image sensor in the prior art.

[0062] Figure 2 This is a module schematic diagram of an image sensor provided by an embodiment of the present disclosure.

[0063] Figure 3 is a circuit diagram of an image sensor provided by an embodiment of the present disclosure.

[0064] Figure 4 4 is a module relationship diagram of the image sensor provided by the embodiment of the present disclosure in the pre-reading stage.

[0065] Figure 5 This is a schematic diagram of the image sensor provided by an embodiment of the present disclosure in the pre-reading stage.

[0066] Figure 64 is a module relationship diagram of the image sensor provided by the embodiment of the present disclosure during the reading phase.

[0067] Figure 7 is a timing diagram of the image sensor provided by an embodiment of the present disclosure.

[0068] Figure 8 FIG. 4 is a circuit diagram of an image sensor according to another variation of an embodiment of the present disclosure. DETAILED DESCRIPTION

[0069] The following describes the embodiments of the present application through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present application from the content disclosed in the present application. The present application can also be implemented or applied through different specific embodiments. The details in the present application can also be modified or changed according to different viewpoints and application systems without departing from the spirit of the present application. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other unless they conflict.

[0070] The following is a detailed description of the embodiments of the present application with reference to the accompanying drawings so that those skilled in the art can easily implement the present application. The present application can be embodied in many different forms and is not limited to the embodiments described herein.

[0071] In the description of this application, reference to the terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of this application. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art may combine and integrate different embodiments or examples described in this application, as well as features of different embodiments or examples, unless otherwise contradictory.

[0072] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include at least one such feature. In the context of this application, "plurality" means two or more, unless otherwise specifically defined.

[0073] In order to clearly describe the present application, components not related to the description are omitted, and the same or similar components throughout the specification are given the same reference numerals.

[0074] Throughout this specification, when a device is said to be "connected" to another device, this includes not only "direct connection" but also "indirect connection" with other elements interposed therebetween. Furthermore, when a device is said to "include" a certain component, unless otherwise stated, this does not exclude the inclusion of other components but rather implies that the device may include other components.

[0075] When a device is said to be "on" another device, it may be directly on the other device, but there may also be other devices between it. In contrast, when a device is said to be "directly on" another device, there are no other devices between it.

[0076] Although the terms first, second, etc. are used in some instances herein to represent various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, the first interface and the second interface, etc. are represented. Furthermore, as used in this article, the singular forms "one," "an," and "the" are intended to also include the plural forms, unless there is a contrary indication in the context. It should be further understood that the terms "comprise," "include," and "include" indicate the presence of features, steps, operations, elements, components, items, types, and / or groups, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, types, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B, or C" or "A, B, and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B, and C." Exceptions to this definition only occur when the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0077] The technical terms used herein are intended only to refer to specific embodiments and are not intended to limit this application. The singular form used herein also includes the plural form unless the statement explicitly indicates otherwise. The term "comprising" as used in this specification is intended to specify specific features, regions, integers, steps, operations, elements, and / or components and does not exclude the presence or addition of other features, regions, integers, steps, operations, elements, and / or components.

[0078] Although not defined differently, all terms used herein, including technical and scientific terms, have the same meanings as those generally understood by those skilled in the art to which this application belongs. Terms defined in commonly used dictionaries are to be interpreted as having meanings consistent with the relevant technical literature and current teachings, and unless otherwise defined, they should not be overly interpreted as ideal or formulaic meanings.

[0079] Figure 2FIG. 1 is a schematic diagram of a module of an image sensor provided by an embodiment of the present disclosure. Figure 2 As shown, the present invention provides an image sensor comprising: a pixel array 1, a pre-read module 2, a read module 3, a row decoding module 4, and a synthesis module 5. The pixel array 1 includes an array of photodiode acquisition circuits that generate image charge signals in response to incident light. The photodiode acquisition circuits include at least a dual-conversion gain transistor T2 for switching the readout path and a row select transistor T5 that generates a pre-read voltage signal V4 based on a floating diffusion node FD. The pre-read module 2 receives an initial sample of the pixel photoresponse signal before the readout phase and compares the pre-read voltage signal V4 with a threshold signal V5 to generate a control signal for controlling the photodiode acquisition circuit. The read module 3 selects one of at least two gain paths based on the control signal and drives the photodiode acquisition circuit based on the control signal, reading only the pixel electrical signals in the selected path for output. The row decoding module 4 selects pixels row by row from top to bottom. Synthesis module 5 is used to generate a path label for the corresponding pixel electrical signal. Specifically, it generates the path label based on the mapping relationship between the pixel electrical signal read in a gain path and the corresponding pre-read voltage signal V4 for the same pixel. The corresponding pixel information in image 6 is then generated based on the corresponding pixel electrical signal and pre-read voltage signal V4 in the mapping relationship, ultimately synthesizing the image. The present invention provides an image sensor based on a LOFIC (Lateral Overflow Integration Capacitor) structure that improves frame rate, expands dynamic range, and optimizes power consumption. This method can be widely used in image acquisition devices such as consumer electronics, smart terminals, industrial vision, in-vehicle camera systems, and security monitoring, requiring high frame rate, high dynamic range, and low power consumption. LOFIC (Lateral Overflow Integration Capacitor) technology is an innovative sensor design technique designed to improve camera imaging quality in complex lighting environments. The core principle of LOFIC technology is to add a high-density capacitor next to each photodiode to collect photoelectrons that may overflow due to saturation. When the number of photoelectrons converted by a photodiode exceeds its carrying limit, the excess photoelectrons will flow into adjacent capacitors, effectively retaining highlight information, avoiding overexposure, and making the captured photos closer to the light and shadow effects in reality.

[0080] In a preferred embodiment, the photodiode acquisition circuit forms at least two gain signal readout paths based on the state of the dual-conversion gain transistor T2. A first terminal of the pre-reading module 2 is connected to the gate of the dual-conversion gain transistor T2, and a second terminal is connected to the first terminal of the row-select transistor T5. Based on a comparison result of a pre-read voltage signal V4 received at the second terminal of the row-select transistor T5 with a threshold signal V5, the pre-reading module 2 generates a control signal to control the conduction state of the dual-conversion gain transistor T2, thereby outputting a gain signal based on only one gain signal readout path, but this is not limited to the embodiment.

[0081] Figure 3 is a circuit diagram of an image sensor provided by an embodiment of the present disclosure. Figure 4 FIG is a diagram showing the module relationship of the image sensor provided by the embodiment of the present disclosure in the pre-reading stage. Figure 3 and 4 As shown, in a preferred embodiment, the photodiode acquisition circuit includes:

[0082] The photodiode PD photogenerates image charges in response to incident light.

[0083] The floating diffusion node FD is coupled to receive first overflowing image charges from the photodiode PD. After exposure, the image charges overflowing from the photodiode PD enter the floating diffusion node FD.

[0084] The floating diffusion capacitor C1 is coupled between the floating diffusion node FD and the ground.

[0085] The transfer transistor T1 is coupled between the photodiode PD and the floating diffusion node FD to transfer image charges to the floating diffusion node FD.

[0086] The capacitive connection node MIM is coupled to receive the second overflowed image charges from the floating diffusion node FD. After exposure, the image charges further overflowed from the floating diffusion node FD enter the capacitive connection node MIM.

[0087] The dual conversion gain transistor T2 is coupled between the floating diffusion node FD and the capacitor connection node MIM.

[0088] The reset transistor T3 is coupled between the reset voltage signal V1 and the capacitor connection node MIM.

[0089] The lateral overflow integrating capacitor C2 is coupled between the capacitor connection node MIM and the ground terminal.

[0090] A source follower T4 has a first terminal coupled to the drain voltage signal V2, and a gate coupled to the floating diffusion node FD. A first terminal of the row select transistor T5 is coupled to a second terminal of the source follower T4. In a pre-read phase following the exposure phase, the pre-read module 2 controls the state of the dual-conversion gain transistor T2 based on a comparison result between the pre-read voltage signal V4 received from the row select transistor T5 and the threshold signal V5, thereby outputting only one of a high gain level signal and a low gain level signal, but the present invention is not limited thereto.

[0091] In a preferred embodiment, the low gain level signal is a mixed charge obtained by mixing the first overflow image charge and the second overflow image charge read out based on the low gain path (a readout mode after the first overflow image charge and the second overflow image charge are shared), and the high gain level signal is a readout mode after the first overflow image charge is read out based on the high gain path (a readout mode after the first overflow image charge and the second overflow image charge are separated), but the present invention is not limited to this.

[0092] In a preferred embodiment, pre-read module 2 is a conversion gain setting unit (hereinafter referred to as the "CG setting unit"). CG (conversion gain) is the ratio of accumulated electrons converted to voltage. Photons entering a pixel generate electrons due to the photoelectric inductance of the PD (photodiode). These electrons are transferred to the FD (floating diffusion) node under the control of the TG (transfer gate), thereby generating a voltage signal. Finally, after the signal-to-noise ratio is improved by the amp (amplifier), the analog-to-digital converter (A / D) outputs a digital signal. Therefore, if the photoelectric material of the PD (photodiode) is not enhanced, the larger the FD capacitance, the smaller the CG conversion gain, and thus the smaller the converted voltage signal, but this is not limited to this.

[0093] In a preferred embodiment, the pre-reading module 2 includes a comparator, two input terminals of the comparator are respectively connected to the second terminal of the row selection transistor T5 and the threshold signal, and the output terminal is connected to the gate of the dual conversion gain transistor T2, but the present invention is not limited thereto.

[0094] In a preferred embodiment, the reading module 3 is an analog-to-digital converter module, but is not limited thereto.

[0095] Figure 5 FIG is a schematic diagram of the image sensor provided by the embodiment of the present disclosure in the pre-reading stage. Figure 5As shown, in a preferred embodiment, the pre-reading module 2 includes a comparator, the two input terminals of the comparator are respectively connected to the second terminal of the row selection transistor T5 and the threshold signal, and the output terminal is connected to the gate of the dual conversion gain transistor T2, but not limited thereto.

[0096] Figure 6 FIG is a diagram showing the module relationship of the image sensor provided by the embodiment of the present disclosure during the reading phase. Figure 6 As shown, in a preferred embodiment, the synthesis module 5 mixes the output signal of the pre-reading module 2 with the image digital signal of the corresponding photodiode PD as the pixel output signal of the corresponding photodiode PD, and arranges and combines the pixel output signals according to the pixel position to generate the picture 6, but is not limited to this.

[0097] The present invention also provides a high dynamic range adaptive imaging method, using the above image sensor (see Figure 2 ),include:

[0098] S110: Reset each node to an initial state.

[0099] S120 , a photodiode collection circuit for generating an image charge signal in response to incident light in the pixel array 1 .

[0100] S130 , performing an initial sampling of the pixel photoelectric response signal before the reading phase, and comparing the pre-read voltage signal with the threshold signal to generate a control signal for controlling the photodiode acquisition circuit.

[0101] S140, selecting one of at least two gain paths according to the control signal, and driving the photodiode acquisition circuit based on the control signal to read only the pixel electrical signal under the selected path for output.

[0102] S150 , generating path labels corresponding to pixel electrical signals and synthesizing picture 6.

[0103] The present invention also provides a high dynamic range adaptive imaging method, using the above image sensor (see Figure 2 and 3 ),include:

[0104] S210, reset phase, reset each node to an initial state.

[0105] S220, exposure stage, the photodiode PD accumulates photogenerated electrons to generate a pixel photoelectric response signal, the electrons overflowing from the photodiode PD enter the floating diffusion capacitor C1, and the electrons overflowing from the floating diffusion capacitor C1 enter the lateral overflow integration capacitor C2.

[0106] S230, pre-reading stage, performing initial sampling on the pixel photoelectric response signal to obtain a pre-read voltage signal V4, comparing the pre-read voltage signal V4 with the threshold signal V5, and generating a control signal for controlling the photodiode acquisition circuit.

[0107] S240, a reading phase, for selecting one of at least two gain paths according to a control signal, and driving a photodiode acquisition circuit based on the control signal to read only the pixel electrical signal under the selected path for output. And

[0108] S250 , a merging stage, mixing the output signal of the pre-reading module 2 with the image digital signal of the corresponding photodiode PD to serve as the pixel output signal of the corresponding photodiode PD.

[0109] In a preferred embodiment, in S230, the following steps are included:

[0110] S231, sampling the reference reset voltage in high gain mode to implement correlated double sampling. And

[0111] S232 , turning off the dual conversion gain transistor T2 , transferring only the charge in the photodiode PD to the floating diffusion node FD, and collecting the pre-read voltage signal V4 in the high gain mode path as the pre-read voltage signal, but not limited thereto.

[0112] In a preferred embodiment, in S240, the following steps are included:

[0113] S241, compare the pre-read voltage signal with the threshold signal V5, and generate a gate signal of the dual conversion gain transistor T2 accordingly, thereby generating a read gain path for the pixel.

[0114] S242. According to the read gain path, only one gain path reading is performed to output a mixed charge of the first overflow image charge and the second overflow image charge read out based on the low gain path, or output the first overflow image charge read out based on the high gain path, but not limited thereto.

[0115] The specific implementation of the present invention is as follows:

[0116] See also Figure 2 、 4 As shown in FIG5 , FIG6 , the pixel array 1 in the image sensor of the present invention includes a photodiode acquisition circuit arranged in an array and generating an image charge signal in response to incident light. The photodiode acquisition circuit includes at least a dual conversion gain transistor T2 for switching the readout path (see FIG6 ). Figure 3 ) and floating diffusion node FD (see Figure 3 ) generates a row selection transistor T5 of the pre-read voltage signal V4 (see Figure 3The pre-reading module 2 is used to receive the initial sampling of the pixel photoelectric response signal before the reading phase (see Figure 2 The pre-read voltage signal V4 is compared with the threshold signal V5 to generate a column-level control signal V9 for controlling the photodiode acquisition circuit (see Figure 2 The dual conversion gain transistor T2 in the pixel array 1 changes its conduction state according to the column-level control signal V9, forming different gain paths. The reading module 3 is used to select one of the at least two gain paths according to the control signal, and drive the photodiode acquisition circuit based on the control signal to read only the pixel electrical signal under the selected path for output (see Figure 2 In this embodiment, the reading module 3 is an analog-to-digital converter module ADC. The row decoding module 4 is used to select pixels row by row from top to bottom. Before the reading phase, the photodiode acquisition circuit of each column can be pre-read to the pre-reading module 2. In this embodiment, the pre-reading module 2 is a conversion gain selection unit. The synthesis module 5 is used to generate the path label corresponding to the pixel electrical signal and synthesize the image 6 (see Figure 2 (See process labeled "④" in the figure). The photodiode acquisition circuit forms at least two gain signal readout paths based on the state of the dual-conversion gain transistor T2. A first terminal of the pre-read module 2 is connected to the gate of the dual-conversion gain transistor T2, and a second terminal is connected to the first terminal of the row select transistor T5. Based on the comparison result of the pre-read voltage signal V4 received at the second terminal of the row select transistor T5 and the threshold signal V5, the pre-read module 2 generates a control signal to control the conduction state of the dual-conversion gain transistor T2, thereby outputting a gain signal based on only one gain signal readout path.

[0117] Specifically, at the system level, the shutter and exposure process of the present invention are the same as those of the existing LOFIC technology. The difference lies in the process after exposure. The present invention mainly uses five steps: reset, exposure, pre-reading (conversion gain selection), signal reading, and image synthesis. Its technical solution can be implemented through the following scheme:

[0118] First, see Figure 2 As shown, the pixel array 1 generates a photodiode collection circuit for generating image charge signals in response to incident light.

[0119] See also Figure 4 As shown in the figure, the pixel photoelectric response signal is initially sampled before the readout phase, and the output signal (HCG) is "pre-read" in the form of a voltage signal (denoted as V4) to the conversion gain selection unit (CGsetting unit) in each column. The pre-read voltage signal is compared with the threshold signal to generate a control signal for controlling the photodiode acquisition circuit.

[0120] See also Figure 5 As shown, in the conversion gain selection unit, the pre-read voltage signal V4 is compared with the set threshold signal V5. If V4 > V5, a high-level voltage V7 is output; if V4 < V5, a low-level voltage V8 is output. This result is used as the input for the column-level signal (i.e., the column-level control signal V9 of the dual conversion gain transistor T2). Finally, the column-level control signal V9 output by the conversion gain selection unit can be a low-gain level signal or a high-gain level signal.

[0121] See also Figure 6 As shown, the dual-conversion gain transistors T2 in the corresponding rows are set to different levels based on their column-level control signal V9. Pixel array 1 ultimately reads either a high-gain signal (HCG signal) or a low-gain signal (LCG signal) in a conventional manner and outputs it to reading module 3 (analog-to-digital converter module ADC) for analog-to-digital conversion. The photodiode acquisition circuit in pixel array 1 selects one of at least two gain paths based on column-level control signal V9 and drives the photodiode acquisition circuit based on the control signal, reading only the pixel electrical signals in the selected path for output. The low-gain signal is a mixture of the first and second overflow image charges read out via the low-gain path. The high-gain signal is the first overflow image charge read out via the high-gain path.

[0122] Finally, the image signal and the selected conversion gain information (CG value) are combined into an image map (Map) and output to synthesis module 5. Synthesis module 5 mixes the output signal of pre-read module 2 with the image digital signal of the corresponding photodiode PD to obtain the pixel output signal of the corresponding photodiode PD. Based on the mapping relationship between the pixel output signal read under a gain path of the same pixel and the corresponding pre-read voltage signal V4, a path label is generated. The pixel output signal corresponding to the mapping relationship is mixed with the pre-read voltage signal V4 to produce the corresponding pixel information in image 6. The pixel output signals are then arranged and combined according to the pixel positions to generate image 6.

[0123] See also Figure 3 As shown, at the pixel level, the circuit diagram and timing control of the present invention are as follows: Photodiode acquisition circuit (see Figure 3) includes: a photodiode PD, a floating diffusion node FD, a floating diffusion capacitor C1, a transfer transistor T1, a capacitive connection node MIM, a dual-conversion gain transistor T2, a reset transistor T3, a lateral overflow integrating capacitor C2, a source follower T4, and a row select transistor T5. The photodiode PD generates image charge in response to incident light. The floating diffusion node FD is coupled to receive first overflowing image charge from the photodiode PD. After exposure, the image charge overflowing from the photodiode PD enters the floating diffusion node FD. The floating diffusion capacitor C1 is coupled between the floating diffusion node FD and ground. The transfer transistor T1 is coupled between the photodiode PD and the floating diffusion node FD to transfer the image charge to the floating diffusion node FD. The capacitive connection node MIM is coupled to receive second overflowing image charge from the floating diffusion node FD. After exposure, further image charge overflowing from the floating diffusion node FD enters the capacitive connection node MIM. The dual-conversion gain transistor T2 is coupled between the floating diffusion node FD and the capacitive connection node MIM. The reset transistor T3 is coupled between the reset voltage signal V1 and the capacitive connection node MIM. The lateral overflow integrating capacitor C2 is coupled between the capacitor connection node MIM and ground. The first terminal of the source follower T4 is coupled to the drain voltage signal V2, and the gate is coupled to the floating diffusion node FD. The first terminal of the row select transistor T5 is coupled to the second terminal of the source follower T4. During the pre-read phase following the exposure phase, the pre-read module 2 controls the state of the dual-conversion gain transistor T2 based on the comparison result of the pre-read voltage signal V4 received from the row select transistor T5 and the threshold signal V5, so as to output only one gain signal: a high gain level signal or a low gain level signal. The low gain level signal is a mixed charge of the first overflow image charge and the second overflow image charge read out via the low gain path, while the high gain level signal is the first overflow image charge read out via the high gain path. The pre-read module 2 is a comparator, with its two input terminals connected to the second terminal of the row select transistor T5 and the threshold signal, respectively, and its output terminal connected to the gate of the dual-conversion gain transistor T2. The synthesis module 5 mixes the output signal of the pre-reading module 2 with the image digital signal of the corresponding photodiode PD as the pixel output signal of the corresponding photodiode PD, and arranges and combines the pixel output signals according to the pixel positions to generate the picture 6.

[0124] Also, see Figure 7As shown in the figure, the pixel-level timing operation steps include: node reset phase, exposure phase, pre-read phase, comparison phase, and read phase. Among them, Reset is the node reset phase (clearing PD, FD, and MIM signals); Exposure is the exposure phase; Pre-Read is the pre-read phase; CG setting is the CG setting, where the gain setting (the Pre-read signal is derived based on H-SHR and Pre-RO, and T2 is switched by comparing the Pre-read signal with the reference signal); Read OUT is the read phase; H-SHR is the high-gain reset level; Pre-RO is the pre-read level; H / L SHS is the high-gain / low-gain signal level; L SHR is the low-gain reset level; Charge transfer is charge transfer (PD signal is transferred to FD). The specific pixel-level timing operation steps are as follows:

[0125] 1. Node reset phase (Reset)

[0126] First, by turning on T3 (reset signal), T2 (conversion gain control), and T1 (transmission gate) in sequence, the floating diffusion node (FD) and the MIM node (metal-insulator-metal-capacitor connection node) in the pixel are reset to the initial level to ensure consistency in subsequent operations.

[0127] 2. Exposure

[0128] Next, the pixel enters the exposure process, where the photodiode PD generates image charge in response to incident light. After exposure, the image charge overflowing from the photodiode PD can enter the floating diffusion node FD, and further overflowing from the floating diffusion node FD can enter the capacitor connection node MIM. For example, the photodiode (PD) begins to accumulate photogenerated electrons. When the light intensity is low, the electrons do not reach the overflow threshold and are all stored in the PD, keeping the FD voltage high. Alternatively, when the light intensity is high, electrons overflow into the FD, causing its voltage to drop. Further excess electrons will flow into the MIM node and be collected by the lateral overflow integration capacitor (C2), thus achieving charge storage with a large dynamic range.

[0129] 3. Pre-Read

[0130] After exposure, a pre-read operation is performed. The specific steps are as follows: First, the reference reset voltage is sampled in high-gain mode (HCG), implementing the first stage of correlated double sampling (CDS). Then, T2 is disabled, transferring only the charge in the PD to the FD, and collecting the pixel signal in the high-gain (HCG) path as a "pre-read signal." The pre-read decision mechanism of the present invention quickly performs a "pre-read voltage" (V4) on each column of pixel signals before the actual readout. A comparator compares this voltage with a set threshold signal (V5) to determine whether the pixel should use the high-gain (HCG) or low-gain (LCG) path.

[0131] 4. Comparison stage (CG setting)

[0132] This pre-read signal is compared with a set threshold, and a column-level control signal V9 (high or low) is generated accordingly, determining the pixel's final read gain path (HCG or LCG). In this invention's column-wise dynamic gain control (DCG) control, each column generates an independent column-level control signal V9 based on the pre-read judgment result. This control controls the T2 switch to select and switch the pixel gain path. This system offers the advantages of high flexibility and low overhead, making it suitable for high-resolution arrays.

[0133] 5. Read Out

[0134] Finally, according to the signal state of the column-level control signal V9, switch T2 is turned on or off during the main read phase, thereby performing a single gain path read. The low-gain level signal (LCG) represents a mixture of the first and second overflow image charges read out via the low-gain path (at this time, T2 is on, allowing the image charge at the floating diffusion node FD to be mixed with the image charge at the capacitive connection node MIM, and the resulting mixture is read out). The high-gain level signal (HCG) represents the first overflow image charge read out via the high-gain path (at this time, T2 is off, separating the image charge at the floating diffusion node FD from the image charge at the capacitive connection node MIM, with only the image charge at the floating diffusion node FD being read out). The gain setting for each pixel varies depending on the pre-read result, achieving adaptive gain control. This invention implements a selective gain readout mechanism, reading only the currently predicted HCG or LCG signal. This avoids the redundant operation of existing LOFICs that simultaneously read two paths, significantly reducing the amount of read data, improving frame rate, and lowering power consumption.

[0135] Therefore, the control signal of T2 in the present invention can be converted into a column-level signal (but not limited to this). The following timing considerations will be made for the V9 signal:

[0136] 1. During the exposure phase, the T2 switch remains closed to avoid affecting the normal charge accumulation and transfer within the pixel.

[0137] 2. When entering the readout phase and updating the V9 signal, pixels in different rows of the same column may still be exposed, potentially introducing a slight interference from the gate pulse of dual-conversion-gain transistor T2. However, in the overflow region, since electron transfer has already begun, the impact of the gate pulse of dual-conversion-gain transistor T2 is minimal, and the impact on the final image quality is considered limited.

[0138] 3. Since dual-conversion-gain transistor T2 is off most of the time, we only need to ensure that when shuttering a row of pixels, pixels in other rows of the same column are not in the pre-reading phase to avoid mutual interference. In this way, column-level control signal V9 can be used to switch the gate of dual-conversion-gain transistor T2 without affecting pixels in other rows of the same column, ensuring the security and independence of column-level dual-conversion-gain transistor T2 control.

[0139] Finally, a gain path selection map (CG Map) corresponding to the image data is generated and output along with the pixel data for accurate analysis and synthesis by the back-end ISP or processor. This simplifies post-processing while maintaining high dynamic range imaging quality. This invention boasts a modular architecture and scalability, adapting to pixel-level, column-level, or global control architectures. It is compatible with existing LOFIC designs, requiring minimal hardware modifications for ease of mass production and integration. It can be expanded to include advanced features such as more gain paths, multi-level threshold determination, and regionalized control.

[0140] Figure 8 FIG. 1 is a circuit diagram of an image sensor according to another variation of the embodiment of the present disclosure. Figure 8 As shown in the figure, since the DCG setting for each pixel is independent and unique, the T7 signal must be integrated within the pixel unit, and the T6 signal is designed as a row select transistor for unified control, thus saving more space in the pixel unit design. The readout control transistor T7 has one end connected to the gate of the dual-conversion-gain transistor T2 and the other end connected to the pre-read module 2. Readout control transistor T7 is only turned on during the read phase. The gate of the dual-conversion-gain transistor T2 is connected to an exposure control transistor T6 external to the row selector of the image sensor. One end is connected to the gate of the dual-conversion-gain transistor T2 and the other end is connected to an exposure control signal V6. Exposure control transistor T6 remains on only during the reset and exposure phases.

[0141] Compared with the prior art, the present invention has the following significant technical advantages:

[0142] (1) Improve frame rate: Since only the pixel signals of the selected gain path are read, the reading time required for each frame image and the subsequent image signal processing time are greatly reduced.

[0143] (2) Reduce power consumption: Eliminate redundant paths for signal acquisition and analog-to-digital conversion, and reduce the overall power consumption of the sensor.

[0144] (3) Dynamic range optimization: By introducing a medium gain path and adjustable judgment logic, the imaging capability of medium brightness areas is enhanced, making the HDR effect more natural.

[0145] (4) Reduce system complexity: Move the gain selection logic to the sensor end to reduce the back-end ISP synthesis burden and simplify system design.

[0146] (5) Easy to integrate and expand: This architecture can be implemented on existing image sensor platforms at a low cost and has good compatibility and scalability.

[0147] In view of this, the present invention proposes an image sensor and a high dynamic range adaptive imaging method, which can be based on the LOFIC dynamic range reading method of adaptive path selection. By performing a quick pre-reading judgment before the reading stage, it decides whether to set this pixel to high gain or low gain mode, and only retains the optimal signal for output, fundamentally solving the limitations of the existing LOFIC structure in power consumption, frame rate and processing complexity.

[0148] The above content is a further detailed description of the present disclosure in conjunction with specific optional implementation methods, and the specific implementation of the present disclosure should not be considered to be limited to these descriptions. For those skilled in the art of the present disclosure, without departing from the concept of the present disclosure, they can also make several simple deductions or substitutions, which should be considered to fall within the scope of protection of the present disclosure.

Claims

1. An image sensor, characterized in that: include: A pixel array (1) includes a photodiode collection circuit arranged in an array and generating an image charge signal in response to incident light, wherein the photodiode collection circuit includes at least a dual conversion gain transistor (T2) for switching a readout path and a row selection transistor (T5) for generating a pre-read voltage signal (V4) based on a floating diffusion node (FD); A pre-reading module (2) is used to receive an initial sampling of a pixel photoelectric response signal before a reading phase, and compare the pre-reading voltage signal (V4) with a threshold signal (V5) to generate a control signal for controlling the photodiode acquisition circuit; A reading module (3) is used to select one of at least two gain paths according to the control signal, and drive the photodiode acquisition circuit based on the control signal to read only the pixel electrical signal under the selected path for output; as well as A synthesis module (5) is used to generate a path label corresponding to the pixel electrical signal and synthesize an image; The photodiode acquisition circuit forms a readout path for at least two gain signals based on the state of the dual conversion gain transistor (T2); a first end of the pre-reading module (2) is connected to the gate of the dual conversion gain transistor (T2), and a second end is connected to the first end of the row selection transistor (T5); the pre-reading module (2) generates the control signal to control the conduction state of the dual conversion gain transistor (T2) based on a comparison result of a pre-reading voltage signal (V4) received at the second end of the row selection transistor (T5) and the threshold signal (V5), so as to output a gain signal based on the readout path of only one gain signal; The photodiode acquisition circuit includes: a photodiode (PD) that photogenerates image charge in response to incident light; a floating diffusion node (FD) coupled to receive first overflow image charges from the photodiode (PD); a floating diffusion capacitor (C1) coupled between the floating diffusion node (FD) and a ground terminal; a transfer transistor (T1) coupled between the photodiode (PD) and the floating diffusion node (FD) to transfer the image charge to the floating diffusion node (FD); a capacitive connection node (MIM) coupled to receive the second overflow image charge from the floating diffusion node (FD), the dual conversion gain transistor (T2) coupled between the floating diffusion node (FD) and the capacitive connection node (MIM); a reset transistor (T3), coupled between the reset voltage signal (V1) and the capacitor connection node (MIM); a lateral overflow integrating capacitor (C2) coupled between the capacitor connection node (MIM) and the ground terminal; A source follower (T4), wherein a first end of the source follower (T4) is coupled to a drain voltage signal (V2), a gate is coupled to the floating diffusion node (FD), and a first end of the row selection transistor (T5) is coupled to a second end of the source follower (T4); in a pre-reading phase after an exposure phase, the pre-reading module (2) controls the state of the dual conversion gain transistor (T2) based on a comparison result between the pre-reading voltage signal (V4) received from the row selection transistor (T5) and a threshold signal (V5), so as to output only one gain signal of a high gain level signal or a low gain level signal; a readout control transistor (T7), one end of which is connected to the gate of the dual conversion gain transistor (T2) and the other end of which is connected to the pre-reading module (2), wherein the readout control transistor (T7) is only turned on during the reading phase; The gate of the dual-conversion gain transistor (T2) is connected to an exposure control transistor (T6) externally disposed in a row selector of the image sensor, one end of the dual-conversion gain transistor (T2) is connected to the gate of the dual-conversion gain transistor (T2), and the other end is connected to an exposure control signal (V6). The exposure control transistor (T6) remains turned on only in a reset phase and an exposure phase.

2. The image sensor according to claim 1, wherein The low gain level signal is a mixed charge of the first overflowing image charge and the second overflowing image charge read out based on the low gain path, and the high gain level signal is the first overflowing image charge read out based on the high gain path.

3. The image sensor according to claim 1, wherein The pre-reading module (2) comprises a comparator, wherein two input terminals of the comparator are respectively connected to the second terminal of the row selection transistor (T5) and the threshold signal, and an output terminal is connected to the gate of the dual conversion gain transistor (T2).

4. The image sensor according to claim 1, wherein The synthesis module (5) mixes the output signal of the pre-reading module (2) with the image digital signal of the corresponding photodiode (PD) as the pixel output signal of the corresponding photodiode (PD), and arranges and combines the pixel output signals according to pixel positions to generate a picture.

5. The image sensor according to claim 1, wherein Also includes: The row decoding module (4) is used for selecting pixels row by row from top to bottom.

6. A high dynamic range adaptive imaging method, characterized in that: The image sensor according to claim 1 comprises: S210, reset phase, reset each node to the initial state; S220, exposure stage, the photodiode (PD) accumulates photogenerated electrons to generate a pixel photoelectric response signal, the electrons overflowing from the photodiode (PD) enter the floating diffusion capacitor (C1), and the electrons overflowing from the floating diffusion capacitor (C1) enter the lateral overflow integration capacitor (C2); S230, pre-reading stage, performing initial sampling on the pixel photoelectric response signal to obtain a pre-read voltage signal (V4), comparing the pre-read voltage signal (V4) with a threshold signal (V5), and generating a control signal for controlling the photodiode acquisition circuit; S240, a reading stage, for selecting one of at least two gain paths according to the control signal, and driving the photodiode acquisition circuit based on the control signal to read only the pixel electrical signal under the selected path for output; and S250, a merging stage, mixing the output signal of the pre-reading module (2) with the image digital signal of the corresponding photodiode (PD) as the pixel output signal of the corresponding photodiode (PD).

7. The high dynamic range adaptive imaging method according to claim 6, characterized in that: In the S230, it includes: S231, sampling the reference reset voltage in a high gain mode to implement correlated double sampling; and S232, turning off the dual conversion gain transistor (T2), transferring only the charge in the photodiode (PD) to the floating diffusion node (FD), and collecting the pre-read voltage signal (V4) in the high gain mode path as the pre-read voltage signal.

8. The high dynamic range adaptive imaging method according to claim 6, wherein: In the S240, it includes: S241, comparing the pre-read voltage signal with a threshold signal (V5), and generating a gate signal of the dual conversion gain transistor (T2) accordingly, thereby generating a read gain path for the pixel; and S242. According to the read gain path, only one gain path reading is performed, and a mixed charge of the first overflow image charge and the second overflow image charge read out based on the low gain path is output, or the first overflow image charge read out based on the high gain path is output.

Images