LED chip structure

Abstract

The invention provides an LED chip structure. The LED chip structure comprises an N electrode; the first epitaxial light-emitting structure is located on one side of the N electrode; the first oxide layer is located on the side, away from the N electrode, of the first epitaxial light-emitting structure; the second oxide layer is located on the side, away from the first epitaxial light-emitting structure, of the first oxide layer; the second epitaxial light-emitting structure is located on the side, away from the first oxide layer, of the second oxide layer; the P electrode is located on the side, away from the second oxide layer, of the second epitaxial light-emitting structure; and the first bonding layer is in contact with the first oxide layer and the second oxide layer. According to the structure, the whole-surface bonding of the upper LED chip and the lower LED chip can be realized under the condition of lower temperature and pressure, so that the LED display with high brightness, low power consumption and high resolution is realized.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an LED chip structure. Background Art

[0002] MLED is a general term for Mini LED and Micro LED. Mini LED, also known as sub-millimeter light-emitting diode, is an improved version of traditional LED backlights. Micro LED, a miniaturized and matrixed LED technology, inherits the high efficiency and brightness of inorganic LEDs while offering the energy-saving benefits of self-luminescence without the need for a light source. Compared to traditional display technologies, MLED offers advantages such as long life, wide color gamut, high brightness, and low power consumption, making it a trendsetter for consumer electronics hardware upgrades. To achieve overall power reduction, a stacked Micro LED structure is employed, effectively reducing device power consumption while maintaining normal display brightness and increasing the chip's photoelectric conversion efficiency. For flip-chip Micro LEDs, the light-emitting layers, grown epitaxially on different substrates, undergo a chip-forming process before being stacked. This involves multiple epitaxial growth steps, resulting in a complex fabrication process and high alignment requirements during the transfer process. This can also lead to color unevenness at the electrode connections. In contrast, vertical Micro LEDs are not only easier to implement chip stacking, but also achieve consistent light-emitting areas for the upper and lower light-emitting units, eliminating display unevenness.

[0003] To achieve vertical stacking, the key is the selection of the middle transparent bonding layer. Currently, the conventional choices are patterned metal or transparent conductive oxides such as ITO (indium tin oxide) and IZO (indium zinc oxide). However, patterned metal bonding will reduce the display aperture ratio and have poor current expansion performance. Although ITO-ITO or IZO-IZO bonding can ensure high aperture ratio and current expansion, the direct bonding of transparent conductive oxides such as ITO and IZO requires too high a temperature and pressure, which can damage the device. In addition, the ITO or IZO bonding has low power consumption and a low percentage of full-surface bonding. Summary of the Invention

[0004] The purpose of this application is to provide an LED chip structure that can achieve full-surface bonding of upper and lower LED chips under relatively low temperature and pressure conditions, with high bonding efficiency, thereby achieving high-brightness, low-power consumption, and high-resolution LED display.

[0005] The first aspect of the present application provides an LED chip structure, comprising: an N electrode; a first epitaxial light-emitting structure, the first epitaxial light-emitting structure being located on one side of the N electrode; a first oxide layer, the first oxide layer being located on a side of the first epitaxial light-emitting structure away from the N electrode; a second oxide layer, the second oxide layer being located on a side of the first oxide layer away from the first epitaxial light-emitting structure; a second epitaxial light-emitting structure, the second epitaxial light-emitting structure being located on a side of the second oxide layer away from the first oxide layer; a P electrode, the P electrode being located on a side of the second epitaxial light-emitting structure away from the second oxide layer; and a first bonding layer, the first bonding layer being in contact with the first oxide layer and the second oxide layer.

[0006] In some embodiments of the present application, the second oxide layer is located in the inner region between the second epitaxial light-emitting structure and the first oxide layer, and the second oxide layer is surrounded by the first bonding layer; or, the first oxide layer is located in the inner region between the first epitaxial light-emitting structure and the second oxide layer, and the first oxide layer is surrounded by the first bonding layer.

[0007] In some embodiments of the present application, in the LED chip structure, a second bonding layer is further included between the first oxide layer and the second oxide layer, and the adhesive material used in the second bonding layer is selected from CNT / PS-VBCB composite material.

[0008] In some embodiments of the present application, in the LED chip structure, the thickness of the second adhesive layer is 0.3 μm-2.5 μm, preferably 1.0 μm-1.2 μm.

[0009] In some embodiments of the present application, in the LED chip structure, the first oxide layer and the second oxide layer are each independently selected from an indium zinc oxide layer or an indium tin oxide layer.

[0010] In some embodiments of the present application, in the LED chip structure, the first epitaxial light-emitting structure includes a first N-type GaN layer, a multi-quantum well layer and a first P-type GaN layer; the second epitaxial light-emitting structure includes a second N-type GaN layer, a multi-quantum well layer and a second P-type GaN layer.

[0011] In some embodiments of the present application, the adhesive material used in the first bonding layer is selected from at least one of epoxy resin, acrylic resin, silicone ether resin and CNT / PS-VBCB composite material.

[0012] In some embodiments of the present application, in the CNT / PS-VBCB composite material, CNT and PS-VBCB copolymer are cross-linked to form a conductive network, and the mass ratio of the CNT to the PS-VBCB copolymer is 1:(30-450).

[0013] In some embodiments of the present application, in the CNT / PS-VBCB composite material, the length of the CNT is 1 μm-3 μm, the diameter of the CNT is 1 nm-3 nm, and the aspect ratio of the CNT is (1000-3000):1.

[0014] In some embodiments of the present application, in the CNT / PS-VBCB composite material, the number average molecular weight of the PS-VBCB copolymer is 400,000-700,000; in the PS-VBCB copolymer, the molar ratio of styryl to 4-vinylphenylpropylcyclobutene is 1:(0.5-2).

[0015] In some embodiments of the present application, in the LED chip structure, the silicone ether resin is selected from Resin, Resin, Resin and At least one of the resins.

[0016] The second aspect of the present application provides an LED chip structure, including: an N electrode; a first epitaxial light-emitting structure, the first epitaxial light-emitting structure is located on one side of the N electrode; a second bonding layer, the second bonding layer is located on a side of the first epitaxial light-emitting structure away from the N electrode; a second epitaxial light-emitting structure, the second epitaxial light-emitting structure is located on a side of the second bonding layer away from the first epitaxial light-emitting structure; and a P electrode, the P electrode is located on a side of the second epitaxial light-emitting structure away from the second bonding layer.

[0017] In some embodiments of the present application, in the LED chip structure, the thickness of the second adhesive layer is 0.3 μm-2.5 μm, preferably 1.0 μm-1.2 μm.

[0018] In some embodiments of the present application, in the LED chip structure, the first epitaxial light-emitting structure includes a first N-type GaN layer, a multi-quantum well layer and a first P-type GaN layer; the second epitaxial light-emitting structure includes a second N-type GaN layer, a multi-quantum well layer and a second P-type GaN layer.

[0019] In some embodiments of the present application, the adhesive material used in the second bonding layer is selected from a CNT / PS-VBCB composite material, in which the CNT and PS-VBCB copolymers are cross-linked to form a conductive network, and the mass ratio of the CNT and the PS-VBCB copolymer is 1:(30-450).

[0020] In some embodiments of the present application, in the CNT / PS-VBCB composite material, the length of the CNT is 1 μm-3 μm, the diameter of the CNT is 1 nm-3 nm, and the aspect ratio of the CNT is (1000-3000):1.

[0021] In some embodiments of the present application, in the CNT / PS-VBCB composite material, the number average molecular weight of the PS-VBCB copolymer is 400,000-700,000; in the PS-VBCB copolymer, the molar ratio of styryl to 4-vinylphenylpropylcyclobutene is 1:(0.5-2).

[0022] The third aspect of the present application provides a CNT / PS-VBCB composite material, wherein CNT and PS-VBCB copolymer are cross-linked to form a conductive network, and the mass ratio of the CNT to the PS-VBCB copolymer is 1:(30-450).

[0023] In some embodiments of the present application, the length of the CNT is 1 μm-3 μm, the diameter of the CNT is 1 nm-3 nm, and the aspect ratio of the CNT is (1000-3000):1;

[0024] In some embodiments of the present application, the number average molecular weight of the PS-VBCB copolymer is 400,000-700,000; in the PS-VBCB copolymer, the molar ratio of styryl to 4-vinylphenylpropylcyclobutene is 1:(0.5-2).

[0025] A fourth aspect of the present application provides the use of the above-mentioned CNT / PS-VBCB composite material in the preparation of light-emitting diodes.

[0026] Beneficial effects of this application:

[0027] The LED chip structure provided by the present application can achieve high-strength bonding of the entire ITO / IZO surface under relatively low temperature and pressure conditions, with high bonding efficiency and no damage to the device; the adhesive bonding transmittance is above 95%, the first epitaxial light-emitting structure and the second epitaxial light-emitting structure have the same light-emitting area, there is no display unevenness phenomenon, and the light output of the LED chip structure has little impact, thereby achieving high-brightness, low-power consumption, and high-resolution LED display. The CNT / PS-VBCB composite material provided by the present application has excellent bonding performance and transparency, as well as excellent conductive properties; when the CNT / PS-VBCB composite material is used to prepare the LED chip structure, it can obtain an adhesive layer with high transmittance and good conductivity under relatively low temperature and pressure conditions, achieving full-surface bonding of the upper and lower chips, thereby achieving high-brightness, low-power consumption, and high-resolution LED display.

[0028] Of course, it is not necessary to achieve all the advantages described above at the same time when implementing any product or method of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0030] Figure 1 A schematic diagram of the structure of an LED chip according to an embodiment of the present application;

[0031] Figure 2 This is a schematic structural diagram of an LED chip structure according to another embodiment of the present application;

[0032] Figure 3 Schematic diagram of the cross-sectional structure of the first bonding layer and the first oxide layer or the second oxide layer in the LED chip structure according to another embodiment of the present application;

[0033] Figure 4 This is a schematic structural diagram of an LED chip structure according to another embodiment of the present application;

[0034] Figure 5 This is a schematic flow chart of a method for preparing an LED chip structure according to an embodiment of the present application;

[0035] Figure 6 This is a schematic flow chart of a method for preparing an LED chip structure according to another embodiment of the present application;

[0036] Figure 7This is a schematic structural diagram of an LED chip structure according to another embodiment of the present application;

[0037] Figure 8 Scanning electron microscope (SEM) image of etching P-GaN+MQW+N-GaN during preparation of an LED chip structure according to another embodiment of the present application;

[0038] Figure 9 This is a SEM image of an etched MQW during preparation of an LED chip structure according to another embodiment of the present application;

[0039] Figure 10 This is a schematic flow chart of a method for preparing an LED chip structure according to another embodiment of the present application;

[0040] Figure 11 A schematic structural diagram of a CNT / PS-VBCB composite material according to an embodiment of the present application;

[0041] Figure 12 Schematic diagram of a vinyl group formed after the opening of the four-membered ring in the PS-VBCB copolymer according to one embodiment of the present application and hingedly connected to the vinyl group in VBCB to form a chain;

[0042] Figure 13 A schematic diagram of a PS-VBCB copolymer connected to a CNT according to an embodiment of the present application;

[0043] Figure 14 This is a schematic flow chart of a method for preparing a CNT / PS-VBCB composite material according to an embodiment of the present application;

[0044] Figure 15 This is a scanning electron microscope image of the CNT / PS-VBCB composite material in Example 1 of the present application;

[0045] Figure 16 This is a diagram showing the conductivity test results of the CNT / PS-VBCB composite film layer in Example 1 of the present application;

[0046] Figure 17 This is a graph showing the single pad bonding strength results of the CNT / PS-VBCB composite film layer in Example 1 of the present application;

[0047] Figure 18 This is a roughness effect diagram of the CNT / PS-VBCB composite film layer in Example 1 of the present application;

[0048] Figure 19 This is a roughness effect diagram of the PS-VBCB copolymer film layer in Example 1 of the present application;

[0049] Figure 20This is a mirror image of the roughness effect of the CNT film layer in Example 1 of the present application.

[0050] In the figure, 11. N electrode, 12. first epitaxial light-emitting structure, 13. first oxide layer, 14. first bonding layer, 15. second oxide layer, 16. second epitaxial light-emitting structure, 17. P electrode, 18. second bonding layer, 161. first substrate, 162. first temporary bonding layer, 163. second Si substrate, 164. first SiO2 layer, 165. second temporary bonding layer, 121. third substrate, 171. temporary bonding glue layer, 172. Glass layer, 125. second SiO2 layer, 123. fourth Si substrate. DETAILED DESCRIPTION

[0051] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those skilled in the art based on this application are within the scope of protection of this application.

[0052] The first aspect of the present application provides an LED chip structure, including: an N electrode; a first epitaxial light-emitting structure, the first epitaxial light-emitting structure being located on one side of the N electrode; a first oxide layer, the first oxide layer being located on a side of the first epitaxial light-emitting structure away from the N electrode; a second oxide layer, the second oxide layer being located on a side of the first oxide layer away from the first epitaxial light-emitting structure; a second epitaxial light-emitting structure, the second epitaxial light-emitting structure being located on a side of the second oxide layer away from the first oxide layer; a P electrode, the P electrode being located on a side of the second epitaxial light-emitting structure away from the second oxide layer; and a first bonding layer, the first bonding layer being in contact with the first oxide layer and the second oxide layer.

[0053] The inventors discovered that for full-surface ITO (indium tin oxide) / IZO (indium zinc oxide) bonding in LED chip structures, effective bonding typically requires temperatures above 400°C and pressures exceeding 20,000 N. However, these process conditions significantly damage the LED chip, making it difficult to achieve high-quality display effects. The present application, by providing a first adhesive layer, is able to achieve full-surface high-strength bonding between the first and second oxide layers at bonding temperatures of 100°C-300°C and bonding pressures of 2,000N-8,000N, resulting in high bonding efficiency without damaging the device.

[0054] In some embodiments of the present application, Figure 1As shown, the LED chip structure includes: an N electrode 11; a first epitaxial light-emitting structure 12, the first epitaxial light-emitting structure 12 being located on one side of the N electrode 11; a first oxide layer 13, the first oxide layer 13 being located on a side of the first epitaxial light-emitting structure 12 away from the N electrode 11; a second oxide layer 15, the second oxide layer 15 being located on a side of the first oxide layer 13 away from the first epitaxial light-emitting structure 12; a second epitaxial light-emitting structure 16, the second epitaxial light-emitting structure 16 being located on a side of the second oxide layer 15 away from the first oxide layer 13; and a P electrode 17, the P electrode 17 being located on a side of the second epitaxial light-emitting structure 16 away from the second oxide layer 15. The second oxide layer 15 is located in an inner region between the second epitaxial light-emitting structure 16 and the first oxide layer 13, and is surrounded by a first bonding layer 14. The present application does not particularly limit the thickness of each layer in the LED chip structure, as long as the purpose of the present application can be achieved.

[0055] The present application sets a groove structure on the second oxide layer formed on the surface of the second epitaxial light-emitting structure, and then uses a glue to fill it to form a first bonding layer; then it is bonded with the first oxide layer formed on the surface of the first epitaxial light-emitting structure. The bonding temperature is 100℃-300℃ and the bonding pressure is 2000N-8000N to achieve high-strength bonding of the entire surface, and the bonding efficiency is high without causing damage to the device; the glue bonding transmittance is above 95%, the light-emitting areas of the first epitaxial light-emitting structure and the second epitaxial light-emitting structure are consistent, there is no display unevenness, and the light output of the LED chip structure is less affected, thereby achieving high-brightness, low-power consumption, and high-resolution LED display.

[0056] In some embodiments of the present application, the first bonding layer described in the present application may also be disposed in the peripheral region of the first oxide layer, for example, Figure 2 As shown, the LED chip structure includes: an N electrode 11; a first epitaxial light-emitting structure 12, the first epitaxial light-emitting structure 12 being located on one side of the N electrode 11; a first oxide layer 13, the first oxide layer 13 being located on a side of the first epitaxial light-emitting structure 12 away from the N electrode 11; a second oxide layer 15, the second oxide layer 15 being located on a side of the first oxide layer 13 away from the first epitaxial light-emitting structure 12; a second epitaxial light-emitting structure 16, the second epitaxial light-emitting structure 16 being located on a side of the second oxide layer 15 away from the first oxide layer 13; and a P electrode 17, the P electrode 17 being located on a side of the second epitaxial light-emitting structure 16 away from the second oxide layer 15. The first oxide layer 13 is located in an inner region between the first epitaxial light-emitting structure 12 and the second oxide layer 15, and is surrounded by a first bonding layer 14. The present application does not particularly limit the thickness of each layer in the LED chip structure, as long as the purpose of the present application can be achieved.

[0057] The present application has no particular restrictions on the shape and width of the first bonding layer in the LED chip structure, as long as the purpose of the present application can be achieved. For example, the maximum width of the first bonding layer can be 2μm-4μm, preferably 2μm-3μm; the minimum width can be 0.5μm-2μm, preferably 1μm-2μm. In the present application, Figure 1 For the LED chip structure shown in FIG, the width d of the first bonding layer refers to: the junction of the first bonding layer and the second oxide layer and the outermost side of the first bonding layer along the length and width direction of the second oxide layer; Figure 2 In the LED chip structure shown, the width d of the first bonding layer refers to the distance between the junction of the first bonding layer and the first oxide layer and the outermost side of the first bonding layer along the length and width directions of the first oxide layer.

[0058] In some embodiments of the present application, the cross-sectional top view of the first oxide layer / second oxide layer+first bonding layer is as follows: Figure 3 As shown, the first bonding layer 14 surrounds the first oxide layer 13 or the second oxide layer 15 in a U-shaped pattern. The present application does not particularly limit the width of the U-shaped first bonding layer, as long as the purpose of the present application can be achieved. For example, the maximum width d of the U-shaped first bonding layer can be 2 μm-4 μm, preferably 2 μm-3 μm; the minimum width can be 0.5 μm-2 μm, preferably 1 μm-2 μm.

[0059] In some embodiments of the present application, in the LED chip structure, a second bonding layer is further included between the first oxide layer and the second oxide layer, and the adhesive material used for the second bonding layer is selected from a CNT / PS-VBCB composite material. The CNT / PS-VBCB composite material described in the present application has excellent electrical conductivity and can be coated on the entire surface, resulting in an LED chip structure with better overall performance. In addition, during the preparation of the LED chip structure, a printing process is not necessarily required. For example, the second bonding layer can be prepared by spraying or scraping, which has a higher process tolerance. In addition, the second bonding layer formed by the CNT / PS-VBCB composite material has good high temperature resistance, strong affinity with the first oxide layer and the second oxide layer, does not produce by-products at 200°C-300°C, does not generate gas during the preparation process, and does not peel off from the first oxide layer and the second oxide layer at high temperatures.

[0060] In some embodiments of the present application, Figure 4As shown, the LED chip structure includes: an N electrode 11; a first epitaxial light-emitting structure 12, which is located on one side of the N electrode 11; a first oxide layer 13, which is located on the side of the first epitaxial light-emitting structure 12 away from the N electrode 11; a second bonding layer 18, which is located on the side of the first oxide layer 13 away from the first epitaxial light-emitting structure 12; a second oxide layer 15, which is located on the side of the second bonding layer 18 away from the first oxide layer 13; a second epitaxial light-emitting structure 16, which is located on the side of the second oxide layer 15 away from the first oxide layer 13; a P electrode 17, which is located on the side of the second epitaxial light-emitting structure 16 away from the second oxide layer 15; wherein the second oxide layer 15 is located in the internal area between the second epitaxial light-emitting structure 16 and the second bonding layer 18, and the second oxide layer 15 is surrounded by the first bonding layer 14. It should be noted that the adhesive material used in the first bonding layer 14 can be selected from CNT / PS-VBCB composite materials, or can be selected from at least one of epoxy resin, acrylic resin, and silicone ether resin, preferably CNT / PS-VBCB composite materials; the adhesive material used in the second bonding layer 18 is selected from CNT / PS-VBCB composite materials; there may be no obvious boundary between the first bonding layer 14 and the second bonding layer 18.

[0061] In some embodiments of the present application, in the LED chip structure, the thickness of the second bonding layer is 0.3 μm-2.5 μm, preferably 1.0 μm-1.2 μm. For example, the thickness of the second bonding layer can be 0.3 μm, 0.6 μm, 0.9 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2.1 μm, 2.5 μm, or a range consisting of any two values therebetween. When the thickness of the second bonding layer of the present application is controlled within the above range, the first oxide layer and the second oxide layer can better achieve high-strength full-surface bonding, and the overall conductivity of the LED chip structure is improved.

[0062] In some embodiments of the present application, in the LED chip structure, the first oxide layer and the second oxide layer are each independently selected from an indium zinc oxide (IZO) layer or an indium tin oxide (ITO) layer. The present application uses a high-transmittance, high-conductivity IZO layer or ITO layer as the electrical connection layer of the LED chip structure, which can form a good ohmic contact with the first and second epitaxial light-emitting structures, thereby reducing the operating voltage of the device.

[0063] In some embodiments of the present application, in the LED chip structure, the first epitaxial light-emitting structure includes a first N-type GaN (N-GaN) layer, a multi-quantum well (MQW) layer, and a first P-type GaN (P-GaN) layer; the second epitaxial light-emitting structure includes a second N-type GaN (N-GaN) layer, a multi-quantum well (MQW) layer, and a second P-type GaN (P-GaN) layer. When the first epitaxial light-emitting structure and the second epitaxial light-emitting structure of the present application include an N-GaN layer, an MQW layer, and a P-GaN layer, the light-emitting areas are consistent and the display is uniform, enabling high-brightness, low-power, and high-resolution LED display.

[0064] The present application does not specifically limit the materials of the N-electrode and P-electrode in the LED chip structure, as long as the invention objectives of the present application can be achieved. For example, the materials of the N-electrode and P-electrode can be independently selected from IZO or ITO. The LED chip structure described in the present application may also include other required structures, which are not specifically limited in the present application, as long as the invention objectives of the present application can be achieved. For example, it may include an insulating layer (PVX (DBR)), a metal wiring area (PAD), etc.

[0065] In some embodiments of the present application, the adhesive used in the first bonding layer is selected from at least one of epoxy resin, acrylic resin, silicone ether resin, and CNT / PS-VBCB composite material. The adhesive used in the first bonding layer of the present application is selected from the above range, and the first oxide layer and the second oxide layer achieve high-strength, full-surface bonding, with an adhesive bonding transmittance exceeding 95%. The first and second epitaxial light-emitting structures have consistent light-emitting areas, eliminating display unevenness and minimizing the impact on light output from the LED chip structure, thereby achieving high-brightness, low-power, and high-resolution LED displays.

[0066] In some embodiments of the present application, in a CNT / PS-VBCB composite material, the CNTs and PS-VBCB copolymers are cross-linked to form a conductive network, and the mass ratio of the CNTs to the PS-VBCB copolymers is 1:(30-450), preferably 1:70. For example, the mass ratio of the CNTs to the PS-VBCB copolymers can be 1:30, 1:50, 1:70, 1:100, 1:150, 1:200, 1:250, 1:300, 1:350, 1:400, 1:450, or a range consisting of any two ratios therebetween. When the mass ratio of the CNTs to the PS-VBCB copolymers of the present application is controlled within the above range, the CNT / PS-VBCB composite material has better conductivity, excellent bonding performance, and transparency.

[0067] In some embodiments of the present application, in the CNT / PS-VBCB composite material, the length of the CNT is 1 μm-3 μm, the diameter of the CNT is 1 nm-3 nm, and the aspect ratio of the CNT is (1000-3000):1. For example, the length of the CNT can be 1.0 μm, 1.5 μm, 2.0 μm, 2.5 μm, 3.0 μm, or a range consisting of any two values therebetween. The diameter of the CNT can be 1.0 nm, 1.5 nm, 2.0 nm, 2.5 nm, 3.0 nm, or a range consisting of any two values therebetween. The aspect ratio of the CNT can be 1000:1, 1500:1, 2000:1, 2500:1, 3000:1, or a range consisting of any two ratios therebetween. When the length, diameter, and aspect ratio of the CNTs of the present application are controlled within the above ranges, the CNT / PS-VBCB composite material has better conductivity.

[0068] In some embodiments of the present application, in the CNT / PS-VBCB composite material, the number average molecular weight of the PS-VBCB copolymer is 400,000-700,000; and the molar ratio of styryl groups to 4-vinylphenylpropylcyclobutenyl groups in the PS-VBCB copolymer is 1:(0.5-2). For example, the number average molecular weight of the PS-VBCB copolymer can be 400,000, 450,000, 500,000, 550,000, 600,000, 650,000, 700,000, or a range consisting of any two values therebetween. The molar ratio of styryl groups to 4-vinylphenylpropylcyclobutenyl groups in the PS-VBCB copolymer can be 1:0.5, 1:1, 1:1.5, 1:2, or a range consisting of any two ratios therebetween. The number average molecular weight and the molar ratio of the styrene group and the 4-vinylphenylpropylcyclobutene group of the PS-VBCB copolymer of the present application are controlled within the above ranges, and the CNT / PS-VBCB composite material has better conductivity and excellent bonding performance and transparency.

[0069] In some embodiments of the present application, in the LED chip structure, the silicone ether resin is selected from Resin (solid content 35%), Resin (solid content 46%), Resin (solid content 57%) and At least one of the resins (solid content 63%). The above-mentioned silicone ether resins can all be purchased from Dow Chemical. The silicone ether resin type of the present application is selected from the above range, and the first oxide layer and the second oxide layer can better achieve high-strength full-surface bonding.

[0070] The present application does not impose any particular restrictions on the method for preparing the LED chip structure, as long as the purpose of the invention of the present application can be achieved. For example, the method may include the following steps: forming a first oxide layer on a first epitaxial light-emitting structure; forming a second oxide layer on a second epitaxial light-emitting structure; patterning the second oxide layer and etching a groove in the peripheral area of the second oxide layer; printing a glue material at the groove to form a first bonding layer; laminating the first oxide layer and the second oxide layer together and bonding them using a glue bonding process, wherein the bonding temperature is 100°C-300°C and the bonding pressure is 2000N-8000N; forming an N electrode on the other side of the first epitaxial light-emitting structure and a P electrode on the other side of the second epitaxial light-emitting structure to obtain an LED chip structure. The process methods involved in the above preparation method are all commonly used methods in the art and are not limited in the present application.

[0071] The preparation method of the LED chip structure may also include the following steps: forming a first oxide layer on the first epitaxial light-emitting structure; forming a second oxide layer on the second epitaxial light-emitting structure; patterning the second oxide layer and etching a groove in the outer area of the second oxide layer; coating the CNT / PS-VBCB composite material on the groove and the surface of the second oxide layer; laminating the first oxide layer and the second oxide layer together and bonding them using an adhesive bonding process, wherein the bonding temperature is 100°C-300°C and the bonding pressure is 2000N-8000N; forming an N electrode on the other side of the first epitaxial light-emitting structure and forming a P electrode on the other side of the second epitaxial light-emitting structure to obtain an LED chip structure. The process methods involved in the above preparation method are all commonly used methods in the field and are not limited in this application.

[0072] The following is a flowchart Figure 5 , the steps included in the preparation method of the LED chip structure are further explained.

[0073] (1)Reference Figure 5 As shown in Figure a, a SiO 2 , SiN x or SiON layer with a thickness of >10 nm is formed on the second epitaxial light emitting structure 16 with Si or sapphire as the first substrate 161 as the first temporary bonding layer 162 .

[0074] (2)Reference Figure 5 As shown in FIG. 5 b , the first temporary bonding layer 162 in step (1) is temporarily bonded to the first SiO 2 layer 164 on the second Si substrate 163 to form a second temporary bonding layer 165 .

[0075] (3)Reference Figure 5As shown in Figure c, CMP (chemical mechanical polishing), HF pickling and other processes are used to peel off the first substrate 161 and remove the buffer (buffer layer), and a magnetron sputtering process is used to prepare a second oxide layer (such as an IZO layer) 15 on one side of the second epitaxial light-emitting structure 16 to obtain an upper chip; to ensure good conductivity and high transmittance, the thickness of the second oxide layer 15 is 10nm-100nm.

[0076] (4)Reference Figure 5 As shown in Figure d and Figure d' (top view), the second oxide layer 15 is patterned using a dry etching process to etch out a U-shaped groove with a line width of 2 μm around the perimeter as a glue channel.

[0077] (5)Reference Figure 5 As shown in Figures e and e' (top view), IJP (inkjet printing technology), SIJ printing and other processes are used to print adhesive materials at the round groove to form a transparent first adhesive layer 14; the adhesive material is selected from at least one of epoxy resin, acrylic resin, silicone ether resin and CNT / PS-VBCB composite material; the silicone ether resin is preferably Resin.

[0078] (6)Reference Figure 5 As shown in Figure f, a magnetron sputtering process is used to prepare a first oxide layer (such as an IZO layer) 13 on top of the first epitaxial light-emitting structure 12 with Si as the third substrate 121 to obtain a lower chip; to ensure good conductivity and high transmittance, the thickness of the first oxide layer 13 is 10nm-100nm. Subsequently, the second oxide layer 15 of the upper chip and the first oxide layer 13 of the lower chip are bonded together and bonded using a glue bonding process. The bonding conditions can be set to: a bonding temperature of 150°C, a bonding pressure of 2000N, and a bonding time of 20min. The bonding of the first oxide layer and the second oxide layer in this step can play a conductive role, and the glue bonding plays a role in connecting the upper and lower chips.

[0079] (7)Reference Figure 5 As shown in FIG. 5 g , the second Si substrate 163 and the second temporary bonding layer 165 are removed, and the P electrode 17 is prepared.

[0080] (8)Reference Figure 5 As shown in FIG. 1h, a temporary bonding adhesive layer 171 and a glass layer 172 are prepared on one side of the P electrode 17, and then the third substrate 121 is peeled off and the buffer is removed.

[0081] (9)Reference Figure 5 As shown in Figure i, an N electrode 11 is prepared on one side of the first epitaxial light-emitting structure 12 of the lower chip.

[0082] (10)Reference Figure 5 As shown in Figure j, the LLO (laser lift-off) process is used to remove the temporary bonding adhesive layer 171 and the glass layer 172 to obtain a vertical LED chip structure. If necessary, the glass layer and other required components (not shown) can be prepared on one side of the N electrode 11.

[0083] The following is a flowchart Figure 6 , further describing the steps involved in another method for preparing an LED chip structure.

[0084] (1)Reference Figure 6 As shown in Figure a, a SiO 2 , SiN x or SiON layer with a thickness of >10 nm is formed on the second epitaxial light emitting structure 16 with Si or sapphire as the first substrate 161 as the first temporary bonding layer 162 .

[0085] (2)Reference Figure 6 As shown in FIG. 5 b , the first temporary bonding layer 162 in step (1) is temporarily bonded to the first SiO 2 layer 164 on the second Si substrate 163 to form a second temporary bonding layer 165 .

[0086] (3)Reference Figure 6 As shown in Figure c, CMP, HF pickling and other processes are used to peel off the first substrate 161 and remove the buffer, and a second oxide layer (such as an IZO layer) 15 is prepared on one side of the second epitaxial light-emitting structure 16 by a magnetron sputtering process to obtain an upper chip; to ensure good conductivity and high transmittance, the thickness of the second oxide layer 15 is 10nm-100nm.

[0087] (4)Reference Figure 6 As shown in Figure d and Figure d' (top view), the second oxide layer 15 is patterned using a dry etching process to etch out a U-shaped groove with a line width of 2 μm around the perimeter as a glue channel.

[0088] (5)Reference Figure 6 As shown in Figures e and e' (top view), CNT / PS-VBCB composite material is coated on the groove and the surface of the second oxide layer 15 to form a transparent first bonding layer 14 and a second bonding layer 18. The first bonding layer 14 and the second bonding layer 18 may have no obvious boundaries.

[0089] (6)Reference Figure 6As shown in Figure f, a magnetron sputtering process is used to prepare a first oxide layer (such as an IZO layer) 13 on top of the first epitaxial light-emitting structure 12 with Si as the third substrate 121 to obtain a lower chip; to ensure good conductivity and high transmittance, the thickness of the first oxide layer 13 is 10nm-100nm. Subsequently, the second bonding layer 18 of the upper chip and the first oxide layer 13 of the lower chip are bonded together and bonded using a glue bonding process. The bonding conditions can be set to: bonding temperature of 150°C, bonding pressure of 2000N, and bonding time of 20min. The second bonding layer in this step can play a conductive role and connect the upper and lower chips.

[0090] (7)Reference Figure 6 As shown in FIG. 5 g , the second Si substrate 163 and the second temporary bonding layer 165 are removed, and the P electrode 17 is prepared.

[0091] (8)Reference Figure 6 As shown in FIG. 1h, a temporary bonding adhesive layer 171 and a glass layer 172 are prepared on one side of the P electrode 17, and then the third substrate 121 is peeled off and the buffer is removed.

[0092] (9)Reference Figure 6 As shown in Figure i, an N electrode 11 is prepared on one side of the first epitaxial light-emitting structure 12 of the lower chip.

[0093] (10)Reference Figure 6 As shown in Figure j, the LLO process is used to remove the temporary bonding adhesive layer 171 and the glass layer 172 to obtain a vertical LED chip structure. If necessary, a glass layer and other required components (not shown in the figure) can be prepared on one side of the N electrode 11.

[0094] The second aspect of the present application provides an LED chip structure, such as Figure 7 As shown, the LED chip structure includes: an N electrode 11; a first epitaxial light-emitting structure 12, the first epitaxial light-emitting structure 12 is located on one side of the N electrode 11; a second bonding layer 18, the second bonding layer 18 is located on the side of the first epitaxial light-emitting structure 12 away from the N electrode 11; a second epitaxial light-emitting structure 16, the second epitaxial light-emitting structure 16 is located on the side of the second bonding layer 18 away from the first epitaxial light-emitting structure 12; and a P electrode 17, the P electrode 17 is located on the side of the second epitaxial light-emitting structure 16 away from the second bonding layer 18.

[0095] In some embodiments of the present application, in the LED chip structure, the thickness of the second bonding layer is 0.3 μm-2.5 μm, preferably 1.0 μm-1.2 μm. For example, the thickness of the second bonding layer can be 0.3 μm, 0.6 μm, 0.9 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2.1 μm, 2.5 μm, or a range consisting of any two values therebetween. The thickness of the second bonding layer of the present application is controlled within the above range, and the first oxide layer 13 and the second oxide layer 15 are better able to achieve high-strength full-surface bonding, and the overall conductivity of the LED chip structure is better.

[0096] In some embodiments of the present application, in an LED chip structure, a first epitaxial light-emitting structure includes a first N-type GaN layer, a multi-quantum well layer, and a first P-type GaN layer; and a second epitaxial light-emitting structure includes a second N-type GaN layer, a multi-quantum well layer, and a second P-type GaN layer. When the first and second epitaxial light-emitting structures of the present application include an N-GaN layer, an MQW layer, and a P-GaN layer, the light-emitting regions are consistent, resulting in a uniform display and enabling high-brightness, low-power, and high-resolution LED display.

[0097] The present application does not specifically limit the materials of the N-electrode and P-electrode in the LED chip structure, as long as the invention objectives of the present application can be achieved. For example, the materials of the N-electrode and P-electrode can be independently selected from IZO or ITO. The LED chip structure described in the present application may also include other required structures, which are not specifically limited in the present application, as long as the invention objectives of the present application can be achieved. For example, it may include an insulating layer (PVX (DBR)), a metal wiring area (PAD), etc.

[0098] In some embodiments of the present application, the adhesive material used for the second bonding layer 18 is selected from a CNT / PS-VBCB composite material. In the CNT / PS-VBCB composite material, the CNT and PS-VBCB copolymers are cross-linked to form a conductive network. The mass ratio of the CNT and PS-VBCB copolymers is 1:(30-450), preferably 1:70. For example, the mass ratio of the CNT and PS-VBCB copolymers can be 1:30, 1:50, 1:70, 1:100, 1:150, 1:200, 1:250, 1:300, 1:350, 1:400, 1:450, or a range consisting of any two ratios therebetween. When the mass ratio of the CNT and PS-VBCB copolymers of the present application is controlled within the above range, the CNT / PS-VBCB composite material has better conductivity and excellent bonding performance and transparency. The present application does not specifically limit the thickness of each layer in the LED chip structure, as long as it can achieve the inventive objectives of the present application. The CNT / PS-VBCB composite material used in this application has excellent electrical conductivity, so the CNT / PS-VBCB composite material can be coated on the entire surface to form a second bonding layer without the need for a printing process, and the process has a higher tolerance.

[0099] In some embodiments of the present application, in the CNT / PS-VBCB composite material, the length of the CNT is 1 μm-3 μm, the diameter of the CNT is 1 nm-3 nm, and the aspect ratio of the CNT is (1000-3000):1. For example, the length of the CNT can be 1.0 μm, 1.5 μm, 2.0 μm, 2.5 μm, 3.0 μm, or a range consisting of any two values therebetween. The diameter of the CNT can be 1.0 nm, 1.5 nm, 2.0 nm, 2.5 nm, 3.0 nm, or a range consisting of any two values therebetween. The aspect ratio of the CNT can be 1000:1, 1500:1, 2000:1, 2500:1, 3000:1, or a range consisting of any two ratios therebetween. When the length, diameter, and aspect ratio of the CNTs of the present application are controlled within the above ranges, the CNT / PS-VBCB composite material has better conductivity.

[0100] In some embodiments of the present application, in the CNT / PS-VBCB composite material, the number average molecular weight of the PS-VBCB copolymer is 400,000-700,000; and the molar ratio of styryl groups to 4-vinylphenylpropylcyclobutenyl groups in the PS-VBCB copolymer is 1:(0.5-2). For example, the number average molecular weight of the PS-VBCB copolymer can be 400,000, 450,000, 500,000, 550,000, 600,000, 650,000, 700,000, or a range consisting of any two values therebetween. The molar ratio of styryl groups to 4-vinylphenylpropylcyclobutenyl groups in the PS-VBCB copolymer can be 1:0.5, 1:1, 1:1.5, 1:2, or a range consisting of any two ratios therebetween. The number average molecular weight and the molar ratio of the styrene group and the 4-vinylphenylpropylcyclobutene group of the PS-VBCB copolymer of the present application are controlled within the above ranges, and the CNT / PS-VBCB composite material has better conductivity and excellent bonding performance and transparency.

[0101] The sizes of different layers in the LED chip structure of the present application can be the same or different. There is no special limitation in the present application, as long as the purpose of the invention can be achieved. For example: PAD: 50μm×50μm×8μm; PVX (non-DBR): 101.6μm×101.6μm×4000-6000A; ITO: 30μm×30μm×1500A; P-GaN: 95.42μm×95.42μm; MQW: 95.51μm×95.51μm; N-GaN: 95.6μm×95.6μm. The slope after etching P-GaN+MQW+N-GaN is about 70° (when the etching solution is relatively good). The electron microscope (SEM) image of the etched P-GaN+MQW+N-GaN is as follows: Figure 8 As shown; the slope after MQW etching is about 50°-60° (when the etching solution concentration is low), and the main MQW is observed to be stepped at the nanoscale. The SEM image of the etched P-GaN+MQW+N-GaN is shown as follows Figure 9 As shown, a second bonding layer (CNT / PS-VBCB composite material layer) with a thickness of 1 μm-2 μm covers the lower ITO1500A step and is coated on the entire surface.

[0102] This application does not specifically limit the method for preparing the LED chip structure, as long as the purpose of the invention can be achieved. For example, the method may include the following steps: bonding a first epitaxial light-emitting structure to a second epitaxial structure via a second adhesive layer, wherein the bonding temperature is 100°C-300°C and the bonding pressure is 2000N-8000N; forming an N electrode on the other side of the first epitaxial light-emitting structure and a P electrode on the other side of the second epitaxial light-emitting structure to obtain an LED chip structure. The process methods involved in the above preparation method are all commonly used methods in the field and are not limited by this application.

[0103] The following is a flowchart Figure 10 , the steps included in the preparation method of the LED chip structure are further explained.

[0104] (1)Reference Figure 10 As shown in Figure a, a SiO 2 , SiN x or SiON layer with a thickness of >10 nm is formed on the second epitaxial light emitting structure 16 with Si or sapphire as the first substrate 161 as the first temporary bonding layer 162 .

[0105] (2)Reference Figure 10 As shown in FIG. 5 b , the first temporary bonding layer 162 in step (1) is temporarily bonded to the first SiO 2 layer 164 on the second Si substrate 163 to form a second temporary bonding layer 165 .

[0106] (3)Reference Figure 10 As shown in Figure c, CMP, HF pickling and other processes are used to peel off the first substrate 161 and remove the buffer.

[0107] (4)Reference Figure 10 As shown in FIG. d, the above steps (1), (2) and (3) are repeated to obtain a first epitaxial light emitting structure 12 having a second SiO2 layer 125 and a fourth Si substrate 123 sequentially formed on one side.

[0108] (5)Reference Figure 10 As shown in Figure (e), the second epitaxial light-emitting structure 16 of the upper chip and the first epitaxial light-emitting structure 12 of the lower chip are bonded via a second adhesive layer 18. The bonding conditions can be set as follows: bonding temperature of 150°C, bonding pressure of 2000N, and bonding time of 20 minutes. The second adhesive layer in this step serves as a conductive layer and connects the upper and lower chips.

[0109] (6)Reference Figure 10 As shown in FIG. 5 , the second Si substrate 163 and the second temporary bonding layer 165 are removed, and the P electrode 17 is prepared.

[0110] (7)Reference Figure 10As shown in FIG. 5 g, a temporary bonding adhesive layer 171 and a glass layer 172 are prepared on one side of the P electrode 17, and then the second SiO2 layer 125 and the fourth Si substrate 123 are peeled off and the buffer is removed.

[0111] (8)Reference Figure 10 As shown in Figure h, an N electrode 11 is prepared on one side of the first epitaxial light-emitting structure 12 of the lower chip.

[0112] (9)Reference Figure 10 As shown in Figure 1, the LLO process is used to remove the temporary bonding adhesive layer 171 and the glass layer 172 to obtain a vertical LED chip structure. If necessary, a glass layer and other required components (not shown in the figure) can be prepared on one side of the N electrode 11.

[0113] The third aspect of the present application provides a CNT / PS-VBCB composite material, wherein CNT (carbon nanotube) and PS-VBCB copolymer are cross-linked to form a conductive network, and the mass ratio of CNT and PS-VBCB copolymer is 1: (30-450), preferably 1: 70. For example, the mass ratio of CNT and PS-VBCB copolymer can be 1: 30, 1: 50, 1: 70, 1: 100, 1: 150, 1: 200, 1: 250, 1: 300, 1: 350, 1: 400, 1: 450 or a range consisting of any two ratios therebetween. The mass ratio of CNT and PS-VBCB copolymer in the present application is controlled within the above range, and the CNT / PS-VBCB composite material has better conductivity and has good bonding performance and transparency.

[0114] The structural diagram of CNT / PS-VBCB composite material is shown in Figure 11 As shown, CNT and PS-VBCB copolymers are cross-linked to form a conductive network, and the CNT / PS-VBCB composite material has excellent conductive properties.

[0115] Without being bound by any theory, the inventors of the present application believe that the CNT and PS-VBCB copolymers contain R groups, which can be polystyrene groups converted from polystyrene (PS) or polystyrene-4-vinylbenzocyclobutene groups (e.g., polystyrene-4-vinylbenzocyclobutene groups) converted from polystyrene (PS) and 4-vinylphenylpropylcyclobutene (VBCB). ), or may be a product generated by multiple polystyrene groups and / or multiple polystyrene-4-vinylbenzocyclobutene groups; Figure 11 The wavy lines in the figure can be seen as R bases.

[0116] PS-VBCB copolymer can undergo Diels-Alder reaction when heated at 200℃, and the four-membered ring opens, that is, The vinyl group formed after the four-membered ring is opened can be hinged with the vinyl group in VBCB to form a chain, as shown in the schematic diagram. Figure 12 When PS-VBCB copolymer is connected to CNT, the connection diagram is as shown in Figure 13 shown.

[0117] Without being limited by any theory, the inventors of the present application believe that: PS-VBCB copolymer has excellent properties, including low hygroscopicity, low curing temperature (200-300°C), no by-products, low shrinkage after curing, and wide process tolerance, making it suitable as the main material of the bonding adhesive and can also serve as an encapsulation layer to protect CNTs; connecting CNTs and PS-VBCB copolymer through covalent bonds can form a layer of PS-VBCB copolymer material around the CNT from the material microstructure. The PS-VBCB copolymer acts like a ligand and can reduce the problem of CNT agglomeration to a certain extent; CNTs and IZO have similar resistance magnitudes and can be used to transmit current to illuminate LED chip structures.

[0118] In some embodiments of the present application, the length of the CNT is 1 μm-3 μm, the diameter of the CNT is 1 nm-3 nm, and the aspect ratio of the CNT is (1000-3000): 1. For example, the length of the CNT can be 1.0 μm, 1.5 μm, 2.0 μm, 2.5 μm, 3.0 μm, or a range consisting of any two values therebetween. The diameter of the CNT can be 1.0 nm, 1.5 nm, 2.0 nm, 2.5 nm, 3.0 nm, or a range consisting of any two values therebetween. The aspect ratio of the CNT can be 1000: 1, 1500: 1, 2000: 1, 2500: 1, 3000: 1, or a range consisting of any two ratios therebetween. The length, diameter, and aspect ratio of the CNTs of the present application are controlled within the above ranges, and the CNT / PS-VBCB composite material has better conductivity.

[0119] In some embodiments of the present application, the number-average molecular weight of the PS-VBCB copolymer is 400,000-700,000; the molar ratio of styryl groups to 4-vinylphenylpropylcyclobutenyl groups in the PS-VBCB copolymer is 1:(0.5-2). For example, the number-average molecular weight of the PS-VBCB copolymer can be 400,000, 450,000, 500,000, 550,000, 600,000, 650,000, 700,000, or a range consisting of any two values therebetween. The molar ratio of styryl groups to 4-vinylphenylpropylcyclobutenyl groups in the PS-VBCB copolymer can be 1:0.5, 1:1, 1:1.5, 1:2, or a range consisting of any two ratios therebetween. When the number-average molecular weight and the molar ratio of styryl groups to 4-vinylphenylpropylcyclobutenyl groups of the PS-VBCB copolymer of the present application are controlled within the above ranges, the CNT / PS-VBCB composite material exhibits enhanced conductivity, excellent bonding properties, and good transparency. When the molar ratio of styrene groups to 4-vinylphenylpropylcyclobutene groups in the PS-VBCB copolymer is too high, small molecules are easily released, causing yellowing.

[0120] The present application has no particular limitation on the preparation method of the CNT / PS-VBCB composite material, as long as the purpose of the invention of the present application can be achieved. For example, Figure 14 As shown, the following steps may be included:

[0121] CNTs and a PS-VBCB copolymer are dispersed in an organic solvent and mixed and infiltrated to form a mixture; wherein the CNT content is 0.1 wt% to 1 wt% (preferably 0.5 wt%), and the PS-VBCB copolymer content is 30 wt% to 45 wt% (preferably 35 wt%). The mixture is subjected to solvent evaporation and heated to above 200°C to accelerate the reaction rate and crosslinking, thereby forming a bulk material with the PS-VBCB copolymer and the CNTs, forming an overall conductive network. The organic solvent described herein can be selected from at least one of toluene and mesitylene.

[0122] The fourth aspect of this application provides the use of the CNT / PS-VBCB composite material of the third aspect of this application in the preparation of light-emitting diodes. The CNT / PS-VBCB composite material provided herein has excellent bonding properties and transparency, as well as excellent electrical conductivity. When used to prepare light-emitting diodes, such as LED chip structures, the CNT / PS-VBCB composite material can form an adhesive layer with high transmittance and good conductivity under relatively low temperature and pressure conditions, achieving full-surface bonding of the upper and lower chips, thereby achieving high-brightness, low-power consumption, and high-resolution LED displays.

[0123] Example

[0124] The following examples and comparative examples are provided to more specifically illustrate the embodiments of the present invention. Various tests and evaluations were performed according to the following methods. In addition, unless otherwise specified, "parts" and "%" are based on mass.

[0125] Example 1

[0126] CNTs with a length of 1 μm, a diameter of 1 nm, and an aspect ratio of 1000:1 and PS-VBCB copolymers with a number average molecular weight of 400,000-700,000 are dispersed in a toluene solvent, mixed and infiltrated to obtain a mixture; wherein the mass percentage of CNTs is 0.5wt%, the mass percentage of PS-VBCB copolymers is 35wt%, and the mass percentage of toluene is 64.5wt%; the molar ratio of styrene groups and 4-vinylphenylpropylcyclobutene groups in the PS-VBCB copolymer is 1:1. The above mixture is evaporated by toluene solvent and heated to 200°C to accelerate the reaction rate and crosslink faster. The PS-VBCB copolymer and CNTs form a block material, and the whole forms a conductive network to obtain a CNT / PS-VBCB composite material. The scanning electron microscope (SEM) image of the CNT / PS-VBCB composite material is shown in the figure below. Figure 15 shown.

[0127] CNT / PS-VBCB composite material performance test:

[0128] (a) Transmittance

[0129] Testing method: Mixtures of various concentrations of CNT / PS-VBCB composite material and toluene solvent were sprayed onto a glass support. The solvent was dried to obtain CNT / PS-VBCB composite films with a thickness of 1.0 μm (measured using a step profiler). The CNT / PS-VBCB composite material concentrations, based on the total mass of the mixture, were 0.1 wt%, 0.2 wt%, 0.3 wt%, 0.4 wt%, 0.5 wt%, 0.6 wt%, and 0.7 wt%. The transmittance of the CNT / PS-VBCB composite films was measured using an ultraviolet spectrophotometer in the visible light range of 380 nm to 780 nm.

[0130] Test results: The transmittance of the CNT / PS-VBCB composite film is similar to that of CNT, both reaching over 95%.

[0131] (b) Electrical conductivity

[0132] Test method: A mixture of CNT / PS-VBCB composite material and toluene solvent of different concentrations was sprayed onto a glass carrier, and the solvent was dried to obtain a CNT / PS-VBCB composite film layer with a thickness of 1.0 μm. The mass percentage of the CNT / PS-VBCB composite material based on the total mass of the mixture was 0.1wt%, 0.2wt%, 0.3wt%, 0.4wt%, 0.5wt%, 0.6wt%, and 0.7wt%.

[0133] The resistance of the CNT / PS-VBCB composite film was tested using a multimeter.

[0134] Test results: The results are as follows Figure 16 As shown (resistance opening at different concentrations after 1 application), Figure 16 It can be seen that when the mass percentage of the CNT / PS-VBCB composite material is 0.4wt%-0.7wt%, the resistance of the CNT / PS-VBCB composite material film layer is between 100Ω-2000Ω.

[0135] (c) Bond strength

[0136] Test method: A mixture of CNT / PS-VBCB composite material and toluene solvent was sprayed onto a glass carrier, the solvent was dried to obtain CNT / PS-VBCB composite film layers of different thicknesses, and then another identical glass carrier was placed on the CNT / PS-VBCB composite film layer; wherein, based on the total mass of the mixture, the mass percentage of CNT / PS-VBCB composite material was 0.5wt%; wherein, the thicknesses of the CNT / PS-VBCB composite film layers were 0.3μm, 0.6μm, 0.9μm, 1.2μm, and 1.8μm, respectively.

[0137] The vacuum was evacuated to 1 mbar, and the temperature was raised to 150°C at a rate of 8°C / min. A pressure of 2000 N was applied simultaneously to the upper and lower glass panels, and the temperature and pressure were maintained constant for 20 minutes. The temperature was then increased from 150°C to 200°C at a rate of 8°C / min, with the pressure and atmosphere maintained constant for 60 minutes. The single-pad and full-surface bond strengths of the CNT / PS-VBCB composite film (5 mm x 5 mm) were then tested using a thrust tester.

[0138] Test results: The results are shown in Table 1 and Figure 17 As shown in Table 1 and Figure 17 As can be seen from the figure, the single pad bond strength is 0.06N-0.48N. As can be seen from Table 1, the overall surface bond strength (5mm×5mm) is 325.93N-612.06N. After bonding the entire 5mm×5mm surface, the shear strength is 5MPa-60MPa.

[0139] Table 1 Bond strength test results

[0140]

[0141] Note: “ / ” indicates not shown

[0142] (d) Flatness

[0143] Testing method: A mixture of a CNT / PS-VBCB composite material and a toluene solvent was sprayed onto a glass support, and the solvent was dried to obtain a 1.0 μm thick CNT / PS-VBCB composite film layer. The CNT / PS-VBCB composite material had a mass percentage of 0.5 wt% based on the total mass of the mixture.

[0144] The roughness of the CNT / PS-VBCB composite film and the composite film spin-coated film was tested using a step profiler and atomic force microscope, respectively.

[0145] As a control, a mixture of CNTs with a length of 1 μm, a diameter of 1 nm, and an aspect ratio of 1000:1 and a toluene solvent was sprayed on a glass carrier to obtain a CNT film layer with a thickness of 1.0 μm; wherein the mass percentage of CNTs based on the total mass of the mixture was 0.5 wt%.

[0146] As a control, a mixture of a PS-VBCB copolymer having a number average molecular weight of 500,000 and a toluene solvent was sprayed onto a glass carrier to obtain a PS-VBCB copolymer film layer having a thickness of 1.0 μm; wherein the mass percentage of the PS-VBCB copolymer based on the total mass of the mixture was 0.5 wt %.

[0147] Test results: The results are as follows Figure 18-20 shown. Figure 18 In the middle, Rq = 0.00122 μm, Ra = 0.891 nm, indicating that the roughness of the CNT / PS-VBCB composite film is low; Figure 19 In the figure, Rq = 0.00246 μm, Ra = 0.765 nm, indicating that the roughness of the PS-VBCB copolymer film is relatively low; Figure 20 Agglomerated particles with a particle size greater than 1.0 μm can be seen in the CNT film. These results indicate that the PS-VBCB copolymer has good flatness and can fill the pores and connect the CNTs in an orderly manner, thus reducing CNT agglomeration.

[0148] Example 2

[0149] A SiO2 layer with a thickness of 20 nm is formed on the second epitaxial light-emitting structure (N-GaN+MQW+P-GaN) on the Si substrate; the above-mentioned SiO2 layer is temporarily bonded to the SiO2 layer on another Si substrate to form a temporary bonding layer. Using CMP and other processes, the Si substrate is peeled off and the buffer is removed, and a second oxide layer (IZO layer) with a thickness of 50 nm is prepared on one side of the second epitaxial light-emitting structure by a magnetron sputtering process to obtain an upper chip. The IZO layer is patterned using a dry etching process, and a zigzag groove with a width of 2 μm on all sides is etched as a glue channel. The IJP printing process is used to perform etching at the zigzag groove. Resin printing to form a transparent first bonding layer.

[0150] A first oxide layer (IZO layer) with a thickness of 50 nm was prepared on the first epitaxial light-emitting structure (N-GaN+MQW+P-GaN) with Si as the substrate by using a magnetron sputtering process to obtain a lower chip.

[0151] The IZO layer of the upper chip and the IZO layer of the lower chip are bonded together using an adhesive bonding process. The bonding conditions are set as follows: bonding temperature of 150°C, bonding pressure of 2000N, and bonding time of 20min.

[0152] Remove the Si substrate and temporary bonding layer, and prepare the P electrode. Prepare a temporary bonding glue layer and a Glass layer on one side of the P electrode, then peel off the Si substrate and remove the buffer. Prepare an N electrode on one side of the first epitaxial light-emitting structure of the lower chip. Use the LLO process to remove the temporary bonding glue layer and the Glass layer to obtain a vertical LED chip structure, the structural diagram of which is shown in the figure below. Figure 1 As shown, the first epitaxial light-emitting structure and the second epitaxial light-emitting structure include N-GaN, MQW and P-GaN from bottom to top, and the thickness of each layer of the vertical LED chip structure is from bottom to top: N electrode 200nm, N-GaN 2.5μm, MQW 150nm, P-GaN 250nm, IZO layer 50nm, IZO layer 50nm, N-GaN 2.5μm, MQW 150nm, P-GaN 250nm, P electrode 150nm.

[0153] Example 3

[0154] In addition to using the CNT / PS-VBCB composite material prepared in Example 1 of the present application instead of Except for the resin, the rest is the same as in Example 2.

[0155] Example 4

[0156] In addition to using the CNT / PS-VBCB composite material prepared in Example 1 of the present application instead of The resin is used, and the method of "coating CNT / PS-VBCB composite material at the groove and the surface of the second oxide layer (IZO layer) to form a transparent first bonding layer and a second bonding layer" is used instead of "using IJP printing process to print at the zigzag groove" The resin is printed to form a transparent first bonding layer. The rest is the same as in Example 2. The schematic diagram of the vertical LED chip structure is as shown in FIG. Figure 4 As shown, the thickness of the second bonding layer is 1.0 nm.

[0157] Example 5

[0158] A 20nm-thick SiO2 layer is formed on the second epitaxial light-emitting structure (N-GaN+MQW+P-GaN) on a Si substrate. This SiO2 layer is temporarily bonded to the SiO2 layer on another Si substrate to form a temporary bonding layer. Using a process such as CMP, the Si substrate is peeled off and the buffer is removed to obtain the upper chip. Repeat these steps to obtain the first epitaxial light-emitting structure, with the SiO2 layer and Si substrate formed on one side, to obtain the lower chip.

[0159] The second epitaxial light-emitting structure of the upper chip and the first epitaxial light-emitting structure of the lower chip were bonded together using a second adhesive layer made of a CNT / PS-VBCB composite material. The bonding conditions were set as follows: bonding temperature of 150°C, bonding pressure of 2000N, and bonding time of 20 minutes.

[0160] Remove the Si substrate and temporary bonding layer, and prepare the P electrode. Prepare a temporary bonding glue layer and a Glass layer on one side of the P electrode, then peel off the Si substrate and remove the buffer. Prepare an N electrode on one side of the first epitaxial light-emitting structure of the lower chip. Use the LLO process to remove the temporary bonding glue layer and the Glass layer to obtain a vertical LED chip structure, the structural diagram of which is shown in the figure below. Figure 7 As shown, the first epitaxial light-emitting structure and the second epitaxial light-emitting structure include N-GaN, MQW and P-GaN from bottom to top, and the thickness of each layer of the vertical LED chip structure is as follows from bottom to top: N electrode 200nm, N-GaN 2.5μm, MQW 150nm, P-GaN 250nm, second bonding layer prepared from CNT / PS-VBCB composite material 1.0nm, N-GaN 2.5μm, MQW 150nm, P-GaN 250nm, P electrode 150nm.

[0161] The vertical LED chip structures prepared in Examples 2 to 5 were subjected to effect tests, as follows.

[0162] Test method: Under the same brightness condition of 48k nit, the forward voltage of each vertical LED chip structure was tested using an IVL tester, the current entering each vertical LED chip structure was tested using an ammeter, and the power consumption of each vertical LED chip structure was tested using a power analyzer.

[0163] Test results: The results are shown in Table 2 below.

[0164] Table 2 Vertical LED chip structure effect test

[0165] Forward voltage (Vf) Power consumption (W) LED current (μA) Example 2 4.62 4.19 21 Example 3 4.86 4.38 21 Example 4 5.10 4.76 30 Example 5 5.44 5.36 30

[0166] As can be seen from Table 2, at the same brightness, the vertical LED chip structures prepared in Examples 2 to 5 of the present application all have lower forward voltages, lower power consumption, and lower currents, indicating that the bonding contact surfaces in the vertical LED chip structures prepared in Examples 2 to 5 of the present application are larger. These results demonstrate that the vertical LED chip structures prepared in this application can achieve high-brightness, low-power consumption, and high-resolution LED displays.

[0167] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. An LED chip structure, wherein: The LED chip structure includes: N electrode; a first epitaxial light-emitting structure, wherein the first epitaxial light-emitting structure is located on one side of the N-electrode; a first oxide layer, the first oxide layer being located on a side of the first epitaxial light-emitting structure away from the N electrode; a second oxide layer, the second oxide layer being located on a side of the first oxide layer away from the first epitaxial light-emitting structure; a second epitaxial light-emitting structure, the second epitaxial light-emitting structure being located on a side of the second oxide layer away from the first oxide layer; A P electrode, the P electrode being located on a side of the second epitaxial light-emitting structure away from the second oxide layer; A first bonding layer is in contact with the first oxide layer and the second oxide layer.

2. The LED chip structure according to claim 1, wherein: The second oxide layer is located in an inner region between the second epitaxial light-emitting structure and the first oxide layer, and the second oxide layer is surrounded by the first bonding layer; Alternatively, the first oxide layer is located in an inner region between the first epitaxial light-emitting structure and the second oxide layer, and the first oxide layer is surrounded by the first bonding layer.

3. The LED chip structure according to claim 2, wherein: A second bonding layer is further included between the first oxide layer and the second oxide layer, and the adhesive material used in the second bonding layer is selected from CNT / PS-VBCB composite material.

4. The LED chip structure according to claim 3, wherein: The thickness of the second adhesive layer is 0.3 μm-2.5 μm, preferably 1.0 μm-1.2 μm.

5. The LED chip structure according to claim 1, wherein: The first oxide layer and the second oxide layer are each independently selected from an indium zinc oxide layer or an indium tin oxide layer.

6. The LED chip structure according to claim 1, wherein: The first epitaxial light-emitting structure includes a first N-type GaN layer, a multi-quantum well layer and a first P-type GaN layer; The second epitaxial light-emitting structure includes a second N-type GaN layer, a multi-quantum well layer, and a second P-type GaN layer.

7. The LED chip structure according to claim 1, wherein: The adhesive material used in the first bonding layer is selected from at least one of epoxy resin, acrylic resin, silicone ether resin and CNT / PS-VBCB composite material.

8. The LED chip structure according to any one of claims 3 to 4 and 7, wherein: In the CNT / PS-VBCB composite material, CNT and PS-VBCB copolymer are cross-linked to form a conductive network, and the mass ratio of the CNT to the PS-VBCB copolymer is 1:(30-450); Preferably, the length of the CNT is 1 μm-3 μm, the diameter of the CNT is 1 nm-3 nm, and the aspect ratio of the CNT is (1000-3000):1; Preferably, the number average molecular weight of the PS-VBCB copolymer is 400,000-700,000; and in the PS-VBCB copolymer, the molar ratio of styryl to 4-vinylphenylpropylcyclobutene is 1:(0.5-2).

9. An LED chip structure, wherein: The LED chip structure includes: N electrode; a first epitaxial light-emitting structure, wherein the first epitaxial light-emitting structure is located on one side of the N-electrode; a second bonding layer, the second bonding layer being located on a side of the first epitaxial light-emitting structure away from the N-electrode; a second epitaxial light-emitting structure, the second epitaxial light-emitting structure being located on a side of the second bonding layer away from the first epitaxial light-emitting structure; A P electrode is located on a side of the second epitaxial light-emitting structure away from the second bonding layer.

10. The LED chip structure according to claim 9, wherein: The thickness of the second adhesive layer is 0.3 μm-2.5 μm, preferably 1.0 μm-1.2 μm.

11. The LED chip structure according to claim 9, wherein: The first epitaxial light-emitting structure includes a first N-type GaN layer, a multi-quantum well layer and a first P-type GaN layer; The second epitaxial light-emitting structure includes a second N-type GaN layer, a multi-quantum well layer, and a second P-type GaN layer.

12. The LED chip structure according to any one of claims 9 to 11, wherein: in, The adhesive material used in the second bonding layer is selected from a CNT / PS-VBCB composite material, in which CNT and PS-VBCB copolymer are cross-linked to form a conductive network, and the mass ratio of the CNT to the PS-VBCB copolymer is 1:(30-450); Preferably, the length of the CNT is 1 μm-3 μm, the diameter of the CNT is 1 nm-3 nm, and the aspect ratio of the CNT is (1000-3000):1; Preferably, the number average molecular weight of the PS-VBCB copolymer is 400,000-700,000; and in the PS-VBCB copolymer, the molar ratio of styryl to 4-vinylphenylpropylcyclobutene is 1:(0.5-2).

13. A CNT / PS-VBCB composite material, wherein: CNT and PS-VBCB copolymer are cross-linked to form a conductive network, and the mass ratio of the CNT to the PS-VBCB copolymer is 1:(30-450); Preferably, the length of the CNT is 1 μm-3 μm, the diameter of the CNT is 1 nm-3 nm, and the aspect ratio of the CNT is (1000-3000):1; Preferably, the number average molecular weight of the PS-VBCB copolymer is 400,000-700,000; and in the PS-VBCB copolymer, the molar ratio of styryl to 4-vinylphenylpropylcyclobutene is 1:(0.5-2).

14. Use of the CNT / PS-VBCB composite material according to claim 13 in the preparation of light-emitting diodes.

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