Memory access device, memory access method, chip and computer equipment

Abstract

The embodiment of the invention discloses a memory access device, a memory access method, a chip and computer equipment, and relates to the field of processors. The memory access device comprises a memory access interface, a storage unit, a data processing unit, a memory access request bus and a read data bus, the memory access interface is used for sending a data read-write signal to each data processing unit through the memory access request bus based on the data memory access request; the data processing unit is used for shielding a data read-write signal from the connected storage unit or sending the data read-write signal to the connected storage unit; the data processing unit is also used for receiving read data output by the previous data processing unit and read data output by the storage unit connected with the data processing unit; performing data merging on each path of read data, and outputting merged read data to a next data processing unit through a read data bus; and the memory access interface is also used for receiving target read data output by the last data processing unit through the read data bus, and sending a data memory access response to the master device based on the target read data.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of processors, and in particular to a memory access device, a memory access method, a chip, and a computer device. Background Art

[0002] Modern high-performance processors often integrate large-capacity data buffers to store data or instructions. For example, AI (Artificial Intelligence) processors need to process large amounts of data, so large-capacity data buffers are needed to store the data needed for calculations.

[0003] Due to the limited capacity of a single memory, the data buffer is typically composed of dozens of SRAM (Static Random Access Memory) blocks. In related technologies, the input and output pins (IO) of all SRAMs are typically connected to a central memory access request entry point, and the SRAM required for the current memory access request is determined from multiple SRAMs.

[0004] However, using the above method to access data will introduce a large number of data interconnection lines, resulting in wiring congestion near the main entrance of the memory access request. Summary of the Invention

[0005] The present invention provides a memory access device, a memory access method, a chip, and a computer device. The technical solution is as follows:

[0006] In one aspect, an embodiment of the present application provides a memory access device, comprising:

[0007] Memory access interface, storage unit, data processing unit, memory access request bus and read data bus;

[0008] The memory access interface is connected to the memory access request bus and the read data bus respectively;

[0009] At least two of the data processing units are connected in series via the memory access request bus, and at least two of the data processing units are connected in series via the read data bus;

[0010] A single data processing unit is connected to at least one storage unit;

[0011] The memory access interface is used to send data read and write signals to each of the data processing units through the memory access request bus based on the data memory access request of the master device;

[0012] The data processing unit is used to shield the data read and write signal from the connected storage unit, or to send the data read and write signal to the connected storage unit;

[0013] The data processing unit is further configured to receive read data output by a previous data processing unit and read data output by a connected storage unit; merge the read data from each channel, and output the merged read data to the next data processing unit via the read data bus;

[0014] The memory access interface is further configured to receive target read data output by the last data processing unit via the read data bus, and to send a data memory access response to the master device based on the target read data.

[0015] On the other hand, an embodiment of the present application provides a memory access method, the method comprising:

[0016] The memory access interface sends data read and write signals to each data processing unit via a memory access request bus based on a data memory access request from a master device; wherein the memory access interface is connected to the memory access request bus and the read data bus respectively; at least two of the data processing units are connected in series via the memory access request bus, and at least two of the data processing units are connected in series via the read data bus;

[0017] The data processing unit shields the data read and write signals from the connected storage unit, or sends the data read and write signals to the connected storage unit; wherein a single data processing unit is connected to at least one storage unit;

[0018] The data processing unit receives the read data output by the previous data processing unit and the read data output by the connected storage unit; merges the read data of each channel, and outputs the merged read data to the next data processing unit through the read data bus;

[0019] The memory access interface receives the target read data output by the last data processing unit through the read data bus, and sends a data memory access response to the master device based on the target read data.

[0020] On the other hand, an embodiment of the present application provides a chip, which is provided with a memory access device as described in the above aspect.

[0021] On the other hand, an embodiment of the present application provides a computer device, which is provided with the chip described in the above aspect.

[0022] In an embodiment of the present application, at least two data processing units are connected in series through a memory access request bus, so that the data read and write signals sent by the memory access interface can be transmitted to each data processing unit; at least two data processing units are connected in series through a read data bus, and the data processing unit receives the read data output by the previous data processing unit and the connected storage unit, and merges the read data of each channel, and outputs the merged read data to the next data processing unit through the read data bus, so that the read data bus can pass the target read data output by the last data processing unit to the memory access interface to return the data access response to the master device. Using the memory access device provided by the present application, since the wiring method is not a method in which each storage unit is directly connected to the memory access interface, but is connected to the storage unit through the data processing unit, and the data processing units are connected in series through the memory access request bus and the read data bus, it is possible to reduce the wiring density in the memory access device, reduce the chip's occupied area, and thus improve the chip's surface efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0024] Figure 1 It is a structural diagram of a memory access device in the related art;

[0025] Figure 2 is a structural diagram of a memory access device provided by an exemplary embodiment of the present application;

[0026] Figure 3 is a structural diagram of a memory access device provided by another exemplary embodiment of the present application;

[0027] Figure 4 is a structural diagram of a data processing unit provided by an exemplary embodiment of the present application;

[0028] Figure 5 is a schematic diagram of a merging module provided by an exemplary embodiment of the present application as a bitwise OR operator;

[0029] Figure 6 This is a schematic structural diagram of a memory access device with an irregular structure provided by an exemplary embodiment of the present application;

[0030] Figure 7 This is a schematic structural diagram of an S-shaped memory access device provided by an exemplary embodiment of the present application;

[0031] Figure 8This is a schematic structural diagram of a memory access device with two rows of SRAM structure provided by an exemplary embodiment of the present application;

[0032] Figure 9 1 is a schematic diagram of a memory access device according to an exemplary embodiment of the present application using a pipeline to process multiple data memory access requests;

[0033] Figure 10 is a flowchart of a memory access method provided by an exemplary embodiment of the present application;

[0034] Figure 11 It is a structural block diagram of a computer device provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0035] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0036] Artificial Intelligence (AI) refers to the theories, methods, techniques, and application systems that use digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, to perceive the environment, acquire knowledge, and use that knowledge to achieve optimal results. In other words, AI is a comprehensive technology within computer science that seeks to understand the essence of intelligence and produce new intelligent machines that can respond in a manner similar to human intelligence. AI also studies the design principles and implementation methods of various intelligent machines, enabling them to possess the capabilities of perception, reasoning, and decision-making.

[0037] Artificial intelligence (AI) technology is a comprehensive discipline encompassing a wide range of fields, encompassing both hardware and software technologies. Foundational AI technologies generally include sensors, specialized AI chips, cloud computing, distributed storage, big data processing, operating / interaction systems, and mechatronics. AI software technologies primarily encompass computer vision, speech processing, natural language processing, and machine learning / deep learning.

[0038] Because storage and processing are integrated in neural networks, while they are separated in classical computer architectures (implemented by memory and an ALU, respectively), running neural networks on classical computers is inevitably constrained by the separate storage and processing architecture, affecting processing efficiency. To improve neural network processing efficiency, neural network processors (NPUs), also known as AI processors, have emerged.

[0039] The AI processor needs to perform a large number of calculations during operation. Due to the limited capacity of a single SRAM, the data buffer is usually composed of multiple SRAMs, and each SRAM is responsible for storing data in a certain address space. Since the master device (such as an arithmetic unit) only accesses one of the SRAMs when accessing data, and each SRAM may be accessed, a multiplexer (data mux) is usually set in the relevant technology. The multiplexer needs to be connected to the input and output pins of all SRAMs, so that the multiplexer can collect the read data stored in all SRAMs and select the read data corresponding to the SRAM required by the master device through address decoding. When writing data, the multiplexer is also required to be connected to the input and output pins of all SRAMs, and the data write request is transmitted to the SRAM required by the master device through address decoding.

[0040] See also Figure 1 , Figure 1 It is a structural diagram of a memory access device in the related art.

[0041] like Figure 1 As shown, the memory access device in the related art is provided with a multiplexer 110 and 16 SRAMs ( Figure 1 The multiplexer 110 is connected to the input and output pins (io) of each SRAM.

[0042] It should be noted that, in this application, the number of SRAMs is 16 for illustrative purposes, and the actual number of SRAMs may be more or less. For example, usually the number of SRAMs in an AI processor is as many as dozens.

[0043] Since the multiplexer is connected to the input and output pins (IO) of each SRAM, a large number of wiring is generated in the memory access device, and the pressure of layout and routing will be very high, especially for the intersection of the area where the multiplexer is located (also called the core area or core area) and the area where the SRAM is located (also called the memory area or memory area). The wiring is most dense near this intersection.

[0044] In addition to the wiring congestion problem near the junction of the core area and the memory area, related technologies such as Figure 1 The wiring method may also cause the chip to occupy too large an area.

[0045] On the one hand, the excessive length of SRAM traces away from the core area can lead to poor data timing. Related technologies typically introduce registers between each SRAM and multiplexer trace to improve timing. However, using this wiring method, coupled with the large number of registers, occupies a large chip area.

[0046] On the other hand, due to severe wiring congestion, a spread operation is usually performed in related technologies to increase the spacing between SRAMs, which also results in a larger chip area being occupied.

[0047] Therefore, the present application proposes a memory access device for improving the wiring congestion problem in the memory access device and improving the chip area efficiency.

[0048] See also Figure 2 , Figure 2 1 is a schematic diagram of the structure of a memory access device provided by an exemplary embodiment of the present application. The memory access device includes a memory access interface 210, storage units (200-1, 200-2, ..., 200-n, n in total), data processing units (220-1, 220-2, ..., 220-n, n in total), a memory access request bus 201, and a read data bus 202. The memory access request bus 201 is indicated by a solid arrow, and the read data bus 202 is indicated by a dashed arrow.

[0049] The memory access interface 210 (interface) is used to receive a data memory access request sent by the master device and return a data memory access response corresponding to the data memory access request to the master device. Figure 2 In FIG, the request channel 203 is a channel for a master device outside the memory to send a data access request to the memory access interface 210, and the response channel 204 is a channel for the memory access interface 210 to return a data access response to the master device outside the memory.

[0050] Among them, the main device outside the memory includes an arithmetic unit, or an arithmetic and logic unit (ALU).

[0051] In some embodiments, the data memory access request is a data read request, and the memory access interface 210 is used to receive the data read request and return the read data corresponding to the data read request to the master device.

[0052] In some embodiments, the data memory access request is a data storage request, and the memory access interface 210 is used to receive the data storage request and does not return data to the master device.

[0053] The memory access interface 210 is connected to the memory access request bus 201 and the read data bus 202 respectively.

[0054] like Figure 2 In the embodiment, the memory access interface 210 is connected to the memory access request bus 201 (req_bus) and the read data bus 202 (rdata_bus).

[0055] Among them, the memory access request bus 201 is used to send data read and write signals transmitted by the memory access interface to each data processing unit, and the read data bus 202 is used to receive the merged read data output by each data processing unit, and return the target read data output by the last data processing unit to the memory access interface.

[0056] The memory access interface 210 can be used to send data read / write signals to each data processing unit based on a data memory access request from the master device via the memory access request bus 201. For example, the memory access interface 210 can convert the data memory access request into a data read / write signal and send the data read / write signal to the data processing units 220-1 to 220-n.

[0057] The data processing unit is also referred to as a CDU (Channel Data Processing Unit) in this application.

[0058] A single data processing unit is connected to at least one storage unit, that is, a single data processing unit can be connected to two or more storage units, or only to one storage unit. The storage unit is connected to the data processing unit through input and output pins (IO).

[0059] For example, Figure 2 In the embodiment, the data processing unit 220-1 is connected to only one storage unit 200-1. The storage unit 200-1 is connected to the data processing unit 220-1 through its input and output pins (io).

[0060] The storage unit is a device used to store data in the data buffer.

[0061] Optionally, the storage unit is SRAM, or other types of memory, such as dynamic random access memory (DRAM), etc. This application does not limit the specific type of the storage unit.

[0062] In some embodiments, the data processing unit is configured to shield data read and write signals to the connected storage units, or to send data read and write signals to the connected storage units.

[0063] Among them, when the read / write target of the data read / write signal is not the connected storage unit, the data processing unit stops sending the data read / write signal to the connected storage unit to shield the data read / write signal to the connected storage unit; when the read / write target of the data read / write signal is the connected storage unit, the data processing unit sends the data read / write signal to the connected storage unit.

[0064] Regarding the way in which the data processing unit shields or sends data read and write signals to the connected storage unit, in some embodiments, it can be implemented by an address decoder. More details about the address decoder can be found in the following embodiments and will not be repeated here.

[0065] At least two data processing units are connected in series via a memory access request bus 201 , and at least two data processing units are connected in series via a read data bus 202 .

[0066] Among them, at least two data processing units are connected in series through the memory access request bus 201, which means that the data read and write signals can be transmitted to at least two data processing units in sequence through the memory access request bus 201; at least two data processing units are connected in series through the read data bus 202, which means that the merged read data output by the previous data processing unit can be transmitted to the next data processing unit through the read data bus 202 as input data of the next data processing unit.

[0067] like Figure 2 In the embodiment, the memory access device includes n data processing units 220 - 1 , 220 - 2 , . . . , 220 - n , and the n data processing units are connected in series via a memory access request bus 201 and a read data bus 202 .

[0068] In some embodiments, the data processing unit is used to receive read data output by the previous data processing unit and read data output by the connected storage unit; merge the read data from each channel, and output the merged read data to the next data processing unit through the read data bus.

[0069] For example Figure 2 In the embodiment, the previous data processing unit of the data processing unit 220-2 is the data processing unit 220-1. The data processing unit 220-2 is used to receive the read data output by the data processing unit 220-1 and the read data output by the connected storage unit 200-2 through the read data bus 202, merge the above two read data, and output the merged read data to the next data processing unit through the read data bus 202... until the last data processing unit 220-n merges the read data output by its previous data processing unit 220-(n-1) and the storage unit 200-n to obtain the final target read data.

[0070] The memory access interface 210 is further configured to receive the target read data output by the last data processing unit 220 - n through the read data bus 202 , and send a data memory access response to the master device based on the target read data.

[0071] In some embodiments, when the data access request is a data read request, the data access response may include not only the target read data but also other data such as a verification result of the target read data.

[0072] The memory access request bus and the read data bus are respectively used to connect at least two data processing units in series.

[0073] like Figure 2 In the embodiment, the memory access request bus 201 is used to connect the data processing units 220-1, 220-2, ... 220-n in series to transmit the data read and write signals to each data processing unit; the read data bus 202 is used to connect the data processing units 220-1, 220-2, ... 220-n in series to transmit the read data output by the data processing units to the memory access interface 210.

[0074] Since the memory access request bus is used to send the data read and write signals transmitted by the memory access interface to each data processing unit, the starting point of the memory access request bus is the memory access interface, and the end point of the memory access request bus is the last data processing unit. Figure 2 In FIG, the memory access request bus 201 starts at the memory access interface 210 and ends at the last data processing unit 220 - n. The memory access request bus 201 is shown by a solid arrow.

[0075] Since the read data bus is used to transmit the read data output by the data processing unit to the memory access interface, the starting point of the read data bus is the first data processing unit, and the end point of the read data bus is the memory access interface. Figure 2 In FIG, the starting point of the read data bus 202 is the first data processing unit 220 - 1 , and the end point of the read data bus 202 is the memory access interface 210 . The read data bus 202 is shown by a dotted arrow.

[0076] By using the memory access device proposed in this application, those skilled in the art can set the number of storage units and data processing units in any feasible manner, for example, Figure 2 In the example, n can be 4, 5, 6, 7, etc. or other positive integers. For example, n can be dozens. Even if the number of storage units and data processing units in the memory access device is increased, Figure 2The memory access device also only includes two lines: a memory access request bus and a read data bus. Compared with the related art in which each SRAM is connected to a multiplexer, the number of lines of the memory access device of the present application is greatly reduced, thereby effectively reducing wiring congestion.

[0077] In summary, in the embodiment of the present application, at least two data processing units are connected in series through a memory access request bus, so that the data read and write signals sent by the memory access interface can be transmitted to each data processing unit; at least two data processing units are connected in series through a read data bus, and the data processing unit receives the read data output by the previous data processing unit and the connected storage unit, and merges the read data of each channel, and outputs the merged read data to the next data processing unit through the read data bus, so that the read data bus can pass the target read data output by the last data processing unit to the memory access interface to return the data access response to the master device. Using the memory access device provided by the present application, since the wiring method is not that each storage unit is directly connected to the memory access interface, but is connected to the storage unit through the data processing unit, and the data processing units are connected in series through the memory access request bus and the read data bus, it is possible to reduce the wiring density in the memory access device, reduce the chip's occupied area, and thus improve the chip's surface efficiency.

[0078] To further reduce wiring congestion and improve chip area efficiency, in some embodiments, a single data processing unit may be connected to two storage units.

[0079] See also Figure 3 , Figure 3 This is a schematic diagram of the structure of a memory access device provided by another exemplary embodiment of the present application. This memory access device is described using an SRAM as an example. The memory access device includes a memory access interface 310, memory cells (SRAM0 to SRAM15, a total of 16), data processing units (data processing units 321 to 328, a total of 8), a memory access request bus 301, and a read data bus 302.

[0080] The memory access interface 310 (interface) is used to receive a data memory access request sent by a master device, and return a data memory access response corresponding to the data memory access request to the master device.

[0081] The memory access interface 310 is connected to the memory access request bus 301 (req_bus) and the read data bus 302 (rdata_bus).

[0082] like Figure 3 The memory access device shown includes 16 storage units (SRAM) and 8 data processing units (CDU), wherein a single data processing unit is connected to two storage units, and the two storage units are distributed on both sides of the data processing unit.

[0083] For example, the data processing unit 321 is connected to SRAM0 and SRAM1, and SRAM0 and SRAM1 are distributed on both sides of the data processing unit 321; the data processing unit 322 is connected to SRAM2 and SRAM3, and SRAM2 and SRAM3 are distributed on both sides of the data processing unit 322,..., the data processing unit 328 is connected to SRAM14 and SRAM15, and SRAM14 and SRAM15 are distributed on both sides of the data processing unit 328.

[0084] The data processing unit can form a U-shaped structure by connecting the memory request bus and the read data bus in series.

[0085] like Figure 3 As shown, data processing units 321-328 form a U-shaped structure with the memory access request bus 301 and the read data bus 302 connected in series. The memory access request bus 301 is used to connect the data processing units 321-328 in series to transmit data read and write signals to each data processing unit; the read data bus 302 is used to connect the data processing units 321-328 in series to transmit the target read data output by the data processing units to the memory access interface 310.

[0086] Figure 3 , the memory access request bus 301 starts at the memory access interface 310 and ends at the last data processing unit 328. The read data bus 302 starts at the first data processing unit 321 and ends at the memory access interface 310.

[0087] In order to improve the timing problem, the memory access device may further include a register (d flip-flop, dff). In some embodiments, a register is provided on the memory access request bus and the read data bus.

[0088] Regarding the register configuration, in one possible implementation, a register is provided for every n data processing units on the memory access request bus and the read data bus, wherein the register is used for beat processing, and n is a positive integer.

[0089] For example, in Figure 3 In the memory access device shown, a register is provided for every two data processing units on the memory access request bus 301 and the read data bus 302. Therefore, the memory access device is provided with registers 341, 342, and 343. The registers function to clock data read / write signals or read data, delaying their output by k clock cycles, thereby improving timing, where k is a positive integer.

[0090] It should be noted that the register setting method can also be any other method, for example, setting a register every 4 or 5 data processing units, or setting a register between any two data processing units, or setting registers between data processing units at irregular intervals, etc. This application does not impose any restrictions on this.

[0091] Since the memory access request bus and read data bus provided by the present application are used to connect at least two data processing units in series, and each data processing unit is connected to at least one storage unit, when setting registers in the memory access device, the number of registers to be set can be reduced compared to the related art. For example, in the related art, it is usually necessary to set registers on the lines between the multiplexer and each memory, such as Figure 1 It is necessary to set one register on each of the lines between the multiplexer and the 16 SRAMs, for a total of 16 registers. Figure 3 The chip also contains 16 SRAMs, but one register is set for every two data processing units, for a total of three registers. Therefore, the method of the embodiment of the present application can reduce the number of registers, thereby reducing the chip's occupied area and improving the chip's area-efficiency ratio.

[0092] In order to improve the accuracy of data reading and writing, the memory access device may further include a check bit generator and a checker, wherein the check bit generator is used to generate a check bit for write data, and the checker is used to check the read data based on the check bit.

[0093] Optionally, the check bit generator is a parity check bit generator (parity generator).

[0094] Optionally, the checker is a parity checker.

[0095] Regarding the setting method of the check bit generator and the verifier in the memory access device, in one possible implementation method, a check bit generator and a verifier connected to each data processing unit can be set, wherein the input end of the check bit generator is connected to the previous data processing unit or the memory access interface through the memory access request bus, and the output end of the check bit generator is connected to the next data processing unit through the read data bus; the input end of the verifier is connected to the data processing unit through the read data bus, and the output end of the verifier is connected to the next data processing unit or the memory access interface through the read data bus.

[0096] In order to reduce the number of parity bit generators and checkers, thereby reducing the occupied area of the chip, in another possible implementation, only one parity bit generator and one checker may be provided in the memory access device.

[0097] In some embodiments, an input end of the check bit generator is connected to the memory access interface, and an output end of the check bit generator is connected to the first data processing unit via a memory access request bus.

[0098] like Figure 3 In the embodiment, the input end of the check bit generator 331 is connected to the memory access interface 310 , and the output end of the check bit generator 331 is connected to the first data processing unit 321 through the memory access request bus 301 .

[0099] Among them, the check bit generator is used to generate a check bit based on the write data in the data write signal when receiving the data write signal input by the memory access interface, and input the data write signal containing the write data and the check bit to the first data processing unit through the memory access request bus.

[0100] For example Figure 3 In the example, when the data write signal input from the memory access interface 310 contains write data 0001, the parity bit generator 331 generates a corresponding parity bit of 1 based on the write data, and inputs a data write signal containing the write data 0001 and the parity bit 1 to the first data processing unit 321 via the memory access request bus 301. If the connected storage unit (SRAM0 or SRAM1) of the data processing unit 321 is the read / write target of the data write signal, SRAM0 or SRAM1 will store the write data 0001 and the parity bit 1. If neither SRAM0 nor SRAM1 is the read / write target of the data write signal, SRAM0 or SRAM1 will mask the write data 0001 and the parity bit 1, and the memory access request bus 301 will pass the write data 0001 and the parity bit 1 to the next data processing unit 322, until the write data 0001 and the parity bit 1 are stored in the read / write target of the data write signal.

[0101] In some embodiments, the input end of the checker is connected to the last data processing unit via a read data bus, and the output end of the checker is connected to the memory access interface.

[0102] like Figure 3 In the embodiment, the input end of the checker 332 is connected to the last data processing unit 328 through the read data bus 302, and the output end of the checker 332 is connected to the memory access interface 310.

[0103] The checker is used to receive the target read data and the check bit corresponding to the target read data output by the last data processing unit through the read data bus, and perform read data check on the target read data based on the check bit.

[0104] For example Figure 3In the example, when the memory access interface 310 transmits a data read signal corresponding to a data read request to each data processing unit CDU via the memory access request bus 301, the read data bus 302 transmits the target read data and the corresponding check bit output by the last data processing unit to the checker 332. The checker 332 checks the target read data and the check bit. For example, if the target read data is 0001 and the check bit is 1, the check result is that the target read data passes the read data check; if the target read data is 0001 and the check bit is 0, the check result is that the target read data fails the read data check.

[0105] In some embodiments, the verifier is further configured to input the target read data to the memory access interface if the target read data passes the read data verification; and to stop inputting the target read data to the memory access interface if the target read data fails the read data verification.

[0106] For example, for target read data 0001 and check bit 1, the checker 332 returns the target read data 0001 to the memory access interface 310 ; for target read data 0001 and check bit 0, the checker 332 stops inputting the target read data 0001 to the memory access interface 310 .

[0107] In this embodiment, under the premise of adopting the wiring method provided in the embodiment of the present application, it is possible to set only one check bit generator and one checker in the memory access device. While being able to realize data verification and improve the accuracy of data reading and writing, it is also possible to reduce the number of device layouts in the memory access device, thereby reducing the chip's occupied area and improving the chip's surface area efficiency.

[0108] In order to determine whether the read / write target of the data read / write signal is a connected storage unit, the data processing unit may, in some embodiments, perform address decoding on the data read / write signal through an address decoder to obtain an address decoding result.

[0109] See also Figure 4 , Figure 4 It is a structural diagram of a data processing unit provided by an exemplary embodiment of the present application.

[0110] Regarding the internal structure of the data processing unit, in some embodiments, the data processing unit includes an address decoder (addr dec) and a read write request module (rd wr req).

[0111] In a possible scenario, when the data processing unit is connected to only one storage unit, the data processing unit may include only one address decoder and one read / write request module.

[0112] In another possible scenario, when the connected storage units of the data processing unit are two storage units, the data processing unit may include two address decoders and two read / write request modules for processing the two storage units respectively.

[0113] Figure 4 is Figure 3 FIG. 3 is a schematic diagram of an enlarged view of the internal structure of the data processing unit 322 and the data processing unit 323 based on FIG. Figure 4 In the embodiment, the connected storage units of the data processing unit 322 are two storage units (SRAM2 and SRAM3). Therefore, the data processing unit 322 includes an address decoder 411 and an address decoder 421, a read / write request module 412 and a read / write request module 422, which are used to process SRAM2 and SRAM3 respectively.

[0114] The address decoder is used to decode the data read / write signal and obtain the address decoding result. The function of the address decoder is to translate the address code contained in the data read / write signal into the physical space of the read / write target corresponding to the data read / write signal.

[0115] When the address decoding result indicates that the read / write target of the data read / write signal is a connected storage unit, the address decoder sends the data read / write signal to the connected storage unit through the read / write request module.

[0116] When the address decoding result indicates that the read / write target of the data read / write signal is not the connected storage unit, the address decoder shields the data read / write signal to the read / write request module.

[0117] For example Figure 4 In the figure, assuming that the data read / write signal transmitted through the memory access request bus 401 is used to read the data in SRAM2, the address decoder 411 performs address decoding on the data read / write signal, and the obtained address decoding result indicates that the read / write target of the data read / write signal is the connected storage unit SRAM2; while the address encoder 421 performs address decoding on the data read / write signal, and the obtained address decoding result indicates that the read / write target of the data read / write signal is not the connected storage unit SRAM3.

[0118] Since the address decoding result obtained by the address decoder 411 indicates that the read / write target of the data read / write signal is the connected storage unit SRAM2 , the address decoder 411 will send the data read / write signal to the connected storage unit SRAM2 through the read / write request module 412 .

[0119] The read / write request module 412 may be used to process the data read / write signal to obtain a data read / write signal suitable for inputting into the SRAM 2 , so as to obtain read data outputted by the SRAM 2 .

[0120] Since the address decoding result obtained by the address decoder 421 indicates that the read / write target of the data read / write signal is not the connected storage unit SRAM3 , the address decoder 421 shields the data read / write signal to the read / write request module 422 .

[0121] When the address decoder 421 masks the data read and write signal to the read and write request module 422, the read and write request module 422 will not pass the data read and write signal to SRAM3. Due to the characteristics of SRAM, SRAM will output the last read data corresponding to the last received signal. Since the last read data is not the data required by the data read and write signal, the last read data needs to be masked.

[0122] Regarding the internal structure of the data processing unit, in some embodiments, the data processing unit further includes a mask module and a merging module.

[0123] In some embodiments, when there are two connected storage units in the data processing unit, the data processing unit may include two shielding modules, one for processing the two connected storage units respectively; but the merging module may only include one, for merging the two connected storage units.

[0124] In some embodiments, when a single data processing unit is connected to at least two storage units, the data processing unit includes address decoders, read / write request modules, and shielding modules corresponding to different storage units, and the shielding modules corresponding to different storage units are connected to the same merging module.

[0125] For example Figure 4 In the embodiment, the data processing unit 322 further includes a shielding module 413 and a shielding module 423 for processing SRAM2 and SRAM3 respectively, but the merging module 431 only includes one for merging SRAM2 and SRAM3.

[0126] When the address decoding result indicates that the read / write target of the data read / write signal is not a connected storage unit, the address decoder is used to send an enable signal to the shielding module.

[0127] In the case where the address decoding result indicates that the read / write target of the data read / write signal is a connected storage unit, the address decoder will not send an enable signal to the shielding module.

[0128] The enable signal is used to instruct the shielding module to shield the output result of the storage unit.

[0129] For example Figure 4The address decoder 411 in the address decoding result indicates that the read and write target of the data read and write signal is the connected storage unit SRAM2. Therefore, the address decoder 411 will not send an enable signal to the corresponding screen module 413.

[0130] As for the address decoder 421, its address decoding result indicates that the read / write target of the data read / write signal is not the connected storage unit SRAM3. Therefore, the address decoder 421 is also used to send an enable signal to the corresponding shielding module 423 to instruct the shielding module 423 to shield the last read data output by SRAM3 to obtain shielded read data.

[0131] The shielding module is used to input the read data output by the connected storage unit into the merging module when the enable signal sent by the address decoder is not received.

[0132] The masking module is used to mask the read data output by the connected storage unit when receiving the enable signal sent by the address decoder, and input the masked read data into the merging module.

[0133] For example Figure 4 In the shielding module 413 , since the address decoder 411 does not send an enable signal to the shielding module 413 , the shielding module 413 inputs the read data output by the SRAM2 into the merging module 431 .

[0134] As for the masking module 423 , since the address decoder 421 sends an enable signal to the masking module 423 , the masking module 423 masks the last read data output by the SRAM 3 and inputs the masked read data to the merging module 431 .

[0135] The merging module is used to merge the read data output by the previous data processing unit and the read data output by the shielding module, and output the merged read data to the next data processing unit through the read data bus.

[0136] For example Figure 4 In the embodiment, the merging module 431 is used to merge the read data output by the previous data processing unit (data processing unit 321) through the read data bus 402, the read data output by the shielding module 413, and the masked read data output by the shielding module 423, and pass the merged read data to the next data processing unit (data processing unit 323) through the read data bus 402.

[0137] In this embodiment, through the address decoder and read / write request module in the data processing unit, it is possible to input a data read / write signal to the storage unit when the storage unit is the read / write target of the data read / write signal; and to shield the data read / write signal from the storage unit when the storage unit is not the read / write target of the data read / write signal; and through the shielding module and the merging module in the data processing unit, it is possible to merge the read data output by different storage units when reading data, so that the merging module of the last data processing unit can feed back the final target read data to the memory access interface through the read data bus.

[0138] Those skilled in the art will appreciate that various feasible specific methods may be used for the shielding module to shield the data output by the storage unit, and for the merging module to merge the read data output by the previous data processing unit and the shielding module.

[0139] In one possible implementation, the last read data output by SRAM3 can be converted into a mask indication signal after being processed by mask module 423. The merging module 431 can merge the mask indication signal output by mask module 423, the read data output by mask module 413, and the mask indication signal output by the previous data processing unit. The mask indication signal is ignored during the merging process. Therefore, the merged result is still the read data output by SRAM2, and the read data output by SRAM2 is then passed to the next data processing unit.

[0140] In another possible implementation, the merging module is a bitwise OR operator. The masking module is configured to, upon receiving an enable signal from the address decoder, mask the read data output by the connected storage unit into all-0 read data, where each bit value in the all-0 read data is 0. The bitwise OR operator is configured to perform a bitwise OR operation on the read data output by the previous data processing unit and the read data output by the masking module, and output the resulting read data via a read data bus to the next data processing unit.

[0141] See also Figure 5 , Figure 5 It is a schematic diagram of an exemplary embodiment of the present application in which the merging module is a bitwise OR operator.

[0142] exist Figure 5 In the example, it is assumed that the read and write target of the data read and write signals is SRAM6.

[0143] Since SRAM4, SRAM5 and the connected storage units of the previous data processing unit are not the read and write targets of the data read and write signals, the mask modules corresponding to SRAM4 and SRAM5 receive the enable signal sent by the address decoder and mask the read data output by SRAM4 and SRAM5 into all-0 read data.

[0144] Therefore, the read data output by the previous data processing unit corresponding to the bitwise OR operator 511 is the all-0 read data 0000, and the read data output by the shielding module corresponding to SRAM4 and SRAM5 is also the all-0 read data 0000. Then the combined result obtained after the bitwise OR transporter performs a bitwise OR operation on the above three read data is also the all-0 read data 0000. The all-0 read data 0000 is passed to the next data processing unit through the read data bus.

[0145] Since SRAM6 is the read / write target of the data read / write signal and SRAM7 is not the read / write target of the data read / write signal, the masking module corresponding to SRAM6 directly inputs the read data F3D0 (hexadecimal representation) output by SRAM6 into the bitwise OR operator 512; the masking module corresponding to SRAM7 masks the read data output by SRAM7 into the all-0 read data 0000 and then inputs the masking module into the bitwise OR operator 512.

[0146] Therefore, the bitwise OR operator 512 performs a bitwise OR operation on the all-0 read data output by the previous data processing unit, F3D0, and the all-0 read data output by the mask module corresponding to SRAM7 to obtain the merged read data F3D0, and continues to pass it to the next data processing unit through the read data bus.

[0147] Since a data read / write signal has only one read / write target, when the read data merged by the bitwise OR operator is not all-0 read data, in another possible implementation, the bitwise OR operator can also directly return the merged read data to the memory access interface.

[0148] It should be noted that Figure 3 The memory access device shown includes 16 storage units and 8 data processing units, and the 8 data processing units form a U-shaped structure under the series connection of the memory access request bus and the read data bus. Figure 3 The number and shape of the storage units and data processing units in the memory access device are not limited. In fact, the memory access device may have more or fewer storage units and data processing units. Figure 3 On this basis, the number of rows or columns of storage units can be increased so that the memory access device includes more storage units. In addition, the shape of the data processing unit can also be various. For example, the data processing unit can form an S-shaped structure, an irregular structure, a polygonal structure, or other types of structures under the series connection of the memory access request bus and the read data bus. This application does not limit this.

[0149] The number of connected storage units of the data processing unit may be one, two, or more; the memory access device may include registers or not, and the number and position of registers may be set by those skilled in the art as needed; the memory access device may include a check bit generator and a checker or not. Such variations are all within the scope of protection of this application.

[0150] See also Figure 6 , Figure 6 It is a structural diagram of an irregularly structured memory access device provided by an exemplary embodiment of the present application.

[0151] Figure 6 The memory access device shown includes a memory access interface 610, 19 storage units (respectively storage units 600-0, 600-1, ..., 600-18), and 10 data processing units (respectively data processing units 621, 622, ..., 6210).

[0152] The first nine data processing units are connected to two storage units, and the last data processing unit is connected to a single storage unit 600-18. The ten data processing units form an irregular structure under the series connection of the memory access request bus 601 and the read data bus 602. A register is set every three data processing units on the memory access request bus 601 and the read data bus 602 to perform beat processing on the data read and write signals and read data. Figure 6 The memory access device shown is provided with a register 641, a register 642 and a register 643.

[0153] The memory access device is further provided with a check bit generator 631 and a checker 632 for improving the accuracy of data reading and writing.

[0154] See also Figure 7 , Figure 7 It is a structural diagram of an S-shaped memory access device provided by an exemplary embodiment of the present application.

[0155] Figure 7 The memory access device shown includes a memory access interface 710, 18 memory cells (memory cells 700-0, 700-1, ..., 700-17), and 9 data processing units (data processing units 721, 722, ..., 729). Each data processing unit is connected to two memory cells. The 18 data processing units form an S-shaped structure with a memory access request bus 701 and a read data bus 702 connected in series. Figure 7 In the memory access device shown, registers 741, 742, 743, and 744 are further provided at intervals of every two data processing units. Figure 7The memory access device shown also includes a check bit generator 731 and a checker 732.

[0156] See also Figure 8 , Figure 8 1 is a schematic structural diagram of a memory access device with a two-row SRAM structure provided by an exemplary embodiment of the present application.

[0157] Figure 8 The memory access device shown includes a memory access interface 810, eight memory units (memory units 800-0, 800-1, ..., 800-7), and four data processing units (data processing units 821-824), each of which is connected to two memory units. The memory access device includes registers 841 and 842, with one register provided for every two data processing units.

[0158] To reduce wiring congestion, in some embodiments, when a single data processing unit is connected to at least two storage units, the at least two storage units are distributed on both sides of the data processing unit, and the input and output ports of the at least two storage units are set near the data processing unit.

[0159] like Figure 8 In the example, the input / output port 811 of the connected storage unit 800-0 of the data processing unit 821 is located proximal to the data processing unit 821; the input / output port 812 of the connected storage unit 800-1 is also located proximal to the data processing unit 810. Therefore, the data processing unit 821 is located between the two connected storage units, and the two connected storage units are arranged "back to back".

[0160] By adopting the above arrangement of data processing units and storage units, one data processing unit can be responsible for accessing two storage units, the resulting wiring is concentrated in the channel, and the number of wiring is greatly reduced, thereby reducing the wiring congestion in the memory access device.

[0161] When there are at least two data processing units in the memory access device, the data processing units may process different data memory access requests in a pipeline manner to improve data memory access efficiency.

[0162] See also Figure 9 , Figure 9 This is a schematic diagram of a memory access device provided by an exemplary embodiment of the present application using a pipeline to process multiple data memory access requests.

[0163] Figure 9 As Figure 3Taking the data processing units in the memory access device shown as an example, during time period T0, the first data access request instr0 transmitted by the memory access interface is processed by the data processing units corresponding to SRAM0-SRAM3; during time period T1, data access request instr0 is processed by the data processing units corresponding to SRAM4-SRAM7; during time period T2, data access request instr0 is processed by the data processing units corresponding to SRAM8-SRAM11; and during time period T3, data access request instr0 is processed by the data processing units corresponding to SRAM12-SRAM15. After time period T3 ends, the first data access request instr0 has been fully executed by all data processing units.

[0164] After the end of the T0 time period, since the data processing units corresponding to SRAM0~SRAM3 have completed processing instr0, in the T1 time period, the data processing units corresponding to SRAM0~SRAM3 can continue to process the second data access request instr1... Similarly, the subsequent third data access request instr2 and the fourth data access request instr3 can be processed in turn by different data processing units in the above-mentioned pipeline manner, until the end of the T6 time period, all four data access requests instr0~instr3 have been processed by all data processing units.

[0165] See also Figure 10 , Figure 10 This is a flow chart of a memory access method provided by an exemplary embodiment of the present application. The method is executed by a memory access device and includes the following steps.

[0166] Step 1001: Based on a data access request from a master device, a memory access interface sends a data read / write signal to each data processing unit via a memory access request bus. The memory access interface is connected to the memory access request bus and the read data bus, respectively. At least two data processing units are connected in series via the memory access request bus, and at least two data processing units are connected in series via the read data bus.

[0167] The memory access interface receives data access requests from a master device and returns corresponding data access responses to the master device. The request channel is the channel through which a master device external to the memory sends data access requests to the memory access interface, and the response channel is the channel through which the memory access interface returns data access responses to the master device external to the memory.

[0168] Among them, the main device outside the memory includes an arithmetic unit, or an arithmetic and logic unit (ALU).

[0169] In some embodiments, the data memory access request is a data read request, and the memory access interface is used to receive the data read request and return read data corresponding to the data read request to the master device.

[0170] In some embodiments, the data memory access request is a data storage request, and the memory access interface is used to receive the data storage request and does not return data to the master device.

[0171] The memory access interface is connected to the memory access request bus and the read data bus respectively.

[0172] Among them, the memory access request bus is used to send data read and write signals transmitted by the memory access interface to each data processing unit, and the read data bus is used to receive the merged read data output by each data processing unit, and return the target read data output by the last data processing unit to the memory access interface.

[0173] The memory access interface can be used to send data read and write signals to each data processing unit through the memory access request bus based on the data access request of the master device. For example, the memory access interface can convert the data access request into a data read and write signal and send the data read and write signal to the data processing unit.

[0174] Step 1002: The data processing unit shields the data read and write signals to the connected storage unit, or sends the data read and write signals to the connected storage unit; wherein a single data processing unit is connected to at least one storage unit.

[0175] The data processing unit is also referred to as a CDU (Channel Data Processing Unit) in this application.

[0176] A single data processing unit is connected to at least one storage unit, that is, a single data processing unit can be connected to two or more storage units, or only to one storage unit. The storage unit is connected to the data processing unit through input and output pins (IO).

[0177] The storage unit is a device used to store data in the data buffer.

[0178] Optionally, the storage unit is SRAM, or other types of memory, such as dynamic random access memory (DRAM), etc. This application does not limit the specific type of the storage unit.

[0179] In some embodiments, the data processing unit is configured to shield data read and write signals to the connected storage units, or to send data read and write signals to the connected storage units.

[0180] Among them, when the read / write target of the data read / write signal is not the connected storage unit, the data processing unit stops sending the data read / write signal to the connected storage unit to shield the data read / write signal to the connected storage unit; when the read / write target of the data read / write signal is the connected storage unit, the data processing unit sends the data read / write signal to the connected storage unit.

[0181] At least two data processing units are connected in series via a memory access request bus, and at least two data processing units are connected in series via a read data bus.

[0182] Among them, at least two data processing units can be connected in series through a memory access request bus, which means that data read and write signals can be transmitted to at least two data processing units in sequence through the memory access request bus; at least two data processing units can be connected in series through a read data bus, which means that the merged read data output by the previous data processing unit can be transmitted to the next data processing unit through the read data bus as input data for the next data processing unit.

[0183] In step 1003 , the data processing unit receives the read data output by the previous data processing unit and the read data output by the connected storage unit; merges the read data from each channel, and outputs the merged read data to the next data processing unit via the read data bus.

[0184] In some embodiments, the data processing unit internally includes an address decoder, a read / write request module, a mask module, and a merge module.

[0185] Step 1004 : The memory access interface receives the target read data output by the last data processing unit through the read data bus, and sends a data memory access response to the master device based on the target read data.

[0186] In some embodiments, when the data access request is a data read request, the data access response may include not only the target read data but also other data such as a verification result of the target read data.

[0187] The memory access request bus and the read data bus are respectively used to connect at least two data processing units in series.

[0188] Since the memory access request bus is used to send the data read and write signals transmitted by the memory access interface to each data processing unit, the starting point of the memory access request bus is the memory access interface and the end point of the memory access request bus is the last data processing unit.

[0189] Since the read data bus is used to transmit the read data output by the data processing unit to the memory access interface, the starting point of the read data bus is the first data processing unit, and the end point of the read data bus is the memory access interface.

[0190] In some embodiments, the data processing unit includes an address decoder and a read / write request module.

[0191] In some embodiments, the address decoder performs address decoding on the data read and write signals.

[0192] When the address decoding result indicates that the read / write target of the data read / write signal is a connected storage unit, the address decoder sends the data read / write signal to the connected storage unit through the read / write request module.

[0193] When the address decoding result indicates that the read / write target of the data read / write signal is not the connected storage unit, the address decoder shields the data read / write signal to the read / write request module.

[0194] In some embodiments, the data processing unit further includes a shielding module and a merging module.

[0195] When the address decoding result indicates that the read / write target of the data read / write signal is not a connected storage unit, the address decoder sends an enable signal to the shielding module.

[0196] In some embodiments, upon receiving an enable signal sent by the address decoder, the masking module masks the read data output by the connected storage unit and inputs the masked read data into the merging module;

[0197] In some embodiments, the shielding module inputs the read data output by the connected storage unit into the merging module when the enable signal sent by the address decoder is not received;

[0198] In some embodiments, the merging module is used to merge the read data output by the previous data processing unit and the read data output by the shielding module, and output the merged read data to the next data processing unit through the read data bus.

[0199] In some embodiments, the merge module is a bitwise OR operator;

[0200] When the mask module receives the enable signal sent by the address decoder, it masks the read data output by the connected storage unit into all-0 read data, and the value of each bit in the all-0 read data is 0;

[0201] The bitwise OR operator performs a bitwise OR operation on the read data output by the previous data processing unit and the read data output by the mask module, and outputs the read data after the bitwise operation to the next data processing unit through the read data bus.

[0202] In some embodiments, when a single data processing unit is connected to at least two storage units, the data processing unit includes address decoders, read / write request modules, and shielding modules corresponding to different storage units, and the shielding modules corresponding to different storage units are connected to the same merging module.

[0203] In some embodiments, a dff register is provided for every n data processing units on the memory access request bus and the read data bus. The dff register is used for beat processing, where n is a positive integer.

[0204] In some embodiments, when a single data processing unit is connected to at least two storage units, the at least two storage units are distributed on both sides of the data processing unit, and the input and output ports of the at least two storage units are arranged proximal to the data processing unit.

[0205] In some embodiments, the check bit generator generates check bits for write data; and the checker performs check on read data based on the check bits.

[0206] In some embodiments, an input end of the check bit generator is connected to the memory access interface, and an output end of the check bit generator is connected to the first data processing unit via a memory access request bus;

[0207] The input end of the checker is connected to the last data processing unit through a read data bus, and the output end of the checker is connected to the memory access interface;

[0208] When receiving a data write signal input from the memory access interface, the check bit generator generates a check bit based on the write data in the data write signal, and inputs the data write signal including the write data and the check bit to the first data processing unit through the memory access request bus;

[0209] The checker receives the target read data and the check bit corresponding to the target read data output by the last data processing unit through the read data bus, and performs read data check on the target read data based on the check bit;

[0210] The verifier inputs the target read data to the memory access interface when the target read data passes the read data verification; and stops inputting the target read data to the memory access interface when the target read data fails the read data verification.

[0211] In some embodiments, the memory access device includes 16 storage units and 8 data processing units;

[0212] A single data processing unit is connected to two storage units, and the two storage units are distributed on both sides of the data processing unit;

[0213] The eight data processing units form a U-shaped structure with the memory request bus and the read data bus connected in series.

[0214] In some embodiments, the memory cell is an SRAM.

[0215] The detailed process of data access by the memory access device in the above memory access method can be referred to the above device embodiment, which will not be described in detail in this embodiment.

[0216] In some embodiments, the memory access device in the embodiments of the present application may be integrated into a chip. The embodiments of the present application provide a chip, which includes the memory access device provided in any of the above embodiments.

[0217] Optionally, the chip may be a processor, such as an AI processor, a CPU processor, or other processor with data access requirements. The chip may also be a storage chip, which is not limited in the embodiments of the present application.

[0218] The present application also provides a computer device, which is provided with the chip described in the above aspects.

[0219] See also Figure 11 , Figure 11 It is a structural block diagram of a computer device provided by an exemplary embodiment of the present application.

[0220] The computer device 1100 may be a smart phone, a tablet computer, a laptop computer, a desktop computer, or a vehicle-mounted terminal. The computer device 1100 may also be called a user device, a portable terminal, a workstation, a server, or other names.

[0221] Specifically, the computer device 1100 includes a central processing unit (CPU) 1101, a system memory 1104 including a random access memory 1102 and a read-only memory 1103, and a system bus 1105 connecting the system memory 1104 and the CPU 1101. The computer device 1100 also includes a basic input / output system (I / O system) 1106 for facilitating information transmission between various components within the computer, and a mass storage device 1107 for storing an operating system 1113, application programs 1114, and other program modules 1115.

[0222] The basic input / output system 1106 includes a display 1108 for displaying information and an input device 1109 such as a mouse and keyboard for user input. The display 1108 and the input device 1109 are both connected to the central processing unit 1101 via an input / output controller 1110 connected to the system bus 1105. The basic input / output system 1106 may also include an input / output controller 1110 for receiving and processing input from a variety of other devices such as a keyboard, mouse, or electronic stylus. Similarly, the input / output controller 1110 also provides output to a display screen, printer, or other types of output devices.

[0223] The mass storage device 1107 is connected to the central processing unit 1101 via a mass storage controller (not shown) connected to the system bus 1105. The mass storage device 1107 and its associated computer-readable media provide non-volatile storage for the computer device 1100. In other words, the mass storage device 1107 may include a computer-readable medium (not shown) such as a hard disk or drive.

[0224] Without loss of generality, the computer-readable medium may include computer storage media and communication media. Computer storage media include volatile and non-volatile, removable and non-removable media implemented by any method or technology for storing information such as computer-readable instructions, data structures, program modules or other data. Computer storage media include random access memory (RAM), read-only memory (ROM), flash memory or other solid-state storage technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, tape cassette, magnetic tape, disk storage or other magnetic storage devices. Of course, those skilled in the art will appreciate that the computer storage medium is not limited to the above-mentioned ones. The above-mentioned system memory 1104 and mass storage device 1107 can be collectively referred to as memory.

[0225] The memory stores one or more programs, and the one or more programs are configured to be executed by one or more central processing units 1101. The one or more programs contain instructions for implementing the above-mentioned methods. The central processing unit 1101 executes the one or more programs to implement the methods provided by the above-mentioned various method embodiments.

[0226] According to various embodiments of the present application, the computer device 1100 may also be connected to a remote computer on a network such as the Internet for operation. That is, the computer device 1100 may be connected to a network 1112 via a network interface unit 1111 connected to the system bus 1105. Alternatively, the network interface unit 1111 may be used to connect to other types of networks or remote computer systems (not shown).

[0227] The memory also includes one or more programs, which are stored in the memory and include steps executed by a computer device in the method provided in the embodiment of the present application.

[0228] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A memory access device, characterized in that: The memory access device includes: Memory access interface, storage unit, data processing unit, memory access request bus and read data bus; The memory access interface is connected to the memory access request bus and the read data bus respectively; At least two of the data processing units are connected in series via the memory access request bus, and at least two of the data processing units are connected in series via the read data bus; A single data processing unit is connected to at least one storage unit; The memory access interface is used to send data read and write signals to each of the data processing units through the memory access request bus based on the data memory access request of the master device; The data processing unit is configured to shield the data read and write signals from the connected storage unit, or to send the data read and write signals to the connected storage unit; The data processing unit is further configured to receive read data output by a previous data processing unit and read data output by a connected storage unit; merge the read data from each channel, and output the merged read data to the next data processing unit via the read data bus; The memory access interface is further configured to receive target read data output by the last data processing unit via the read data bus, and to send a data memory access response to the master device based on the target read data.

2. The memory access device according to claim 1, wherein: The data processing unit includes: an address decoder and a read / write request module; The address decoder is configured to perform address decoding on the data read / write signal, and send the data read / write signal to the connected storage unit via the read / write request module when the address decoding result indicates that the read / write target of the data read / write signal is the connected storage unit; When the address decoding result indicates that the read / write target of the data read / write signal is not a connected storage unit, the data read / write signal is shielded from the read / write request module.

3. The memory access device according to claim 2, wherein: The data processing unit further includes: a shielding module and a merging module; The address decoder is configured to send an enable signal to the shielding module when the address decoding result indicates that the read / write target of the data read / write signal is not a connected storage unit; The masking module is configured to mask the read data output by the connected storage unit upon receiving the enable signal sent by the address decoder, and input the masked read data into the merging module; The shielding module is further configured to input the read data output by the connected storage unit into the merging module when the enable signal sent by the address decoder is not received; The merging module is used to merge the read data output by the previous data processing unit and the read data output by the shielding module, and output the merged read data to the next data processing unit through the read data bus.

4. The memory access device according to claim 3, wherein: The merging module is a bitwise OR operator; The masking module is configured to mask the read data output by the connected storage unit into all-0 read data when receiving the enable signal sent by the address decoder, wherein the value of each bit in the all-0 read data is 0; The bitwise OR operator is used to perform a bitwise OR operation on the read data output by the previous data processing unit and the read data output by the shielding module, and output the read data after the bitwise operation to the next data processing unit through the read data bus.

5. The memory access device according to claim 3, wherein: In the case where a single data processing unit is connected to at least two storage units, the data processing unit includes address decoders, read / write request modules, and shielding modules corresponding to different storage units, and the shielding modules corresponding to different storage units are connected to the same merging module.

6. The memory access device according to any one of claims 1 to 5, characterized in that: On the memory access request bus and the read data bus, a dff register is provided for every n data processing units, and the dff register is used for performing beat processing, where n is a positive integer.

7. The memory access device according to any one of claims 1 to 5, characterized in that: When a single data processing unit is connected to at least two storage units, the at least two storage units are distributed on both sides of the data processing unit, and the input and output ports of the at least two storage units are arranged proximal to the data processing unit.

8. The memory access device according to any one of claims 1 to 5, characterized in that: The memory access device further includes: a check bit generator and a checker; The check bit generator is used to generate a check bit for write data; The checker is used to perform read data verification based on the check bit.

9. The memory access device according to claim 8, wherein: The input end of the check bit generator is connected to the memory access interface, and the output end of the check bit generator is connected to the first data processing unit through the memory access request bus; The input end of the checker is connected to the last data processing unit via the read data bus, and the output end of the checker is connected to the memory access interface; The check bit generator is configured to, upon receiving a data write signal input by the memory access interface, generate a check bit based on the write data in the data write signal, and input the data write signal including the write data and the check bit to the first data processing unit via the memory access request bus; The checker is configured to receive the target read data and the check bit corresponding to the target read data output by the last data processing unit through the read data bus, and perform read data check on the target read data based on the check bit; The verifier is further configured to input the target read data to the memory access interface if the target read data passes the read data verification; If the target read data fails the read data verification, inputting the target read data to the memory access interface is stopped.

10. The memory access device according to any one of claims 1 to 5, characterized in that: The memory access device includes 16 storage units and 8 data processing units; A single data processing unit is connected to two storage units, and the two storage units are distributed on both sides of the data processing unit; The eight data processing units form a U-shaped structure under the series connection of the memory access request bus and the read data bus.

11. The memory access device according to any one of claims 1 to 5, characterized in that: The storage unit is an SRAM.

12. A memory access method, characterized in that: The method comprises: The memory access interface sends data read and write signals to each data processing unit via a memory access request bus based on a data memory access request from a master device; wherein the memory access interface is connected to the memory access request bus and the read data bus respectively; at least two of the data processing units are connected in series via the memory access request bus, and at least two of the data processing units are connected in series via the read data bus; The data processing unit shields the data read and write signals from the connected storage unit, or sends the data read and write signals to the connected storage unit; wherein a single data processing unit is connected to at least one storage unit; The data processing unit receives the read data output by the previous data processing unit and the read data output by the connected storage unit; merges the read data of each channel, and outputs the merged read data to the next data processing unit through the read data bus; The memory access interface receives the target read data output by the last data processing unit through the read data bus, and sends a data memory access response to the master device based on the target read data.

13. The memory access method according to claim 12, wherein: The data processing unit includes: an address decoder and a read / write request module; the data processing unit shields the data read / write signal to the connected storage unit, or sends the data read / write signal to the connected storage unit, including: The address decoder performs address decoding on the data read / write signal; When the address decoding result indicates that the read / write target of the data read / write signal is a connected storage unit, the address decoder sends the data read / write signal to the connected storage unit through the read / write request module; In a case where the address decoding result indicates that the read / write target of the data read / write signal is not a connected storage unit, the address decoder shields the data read / write signal from the read / write request module.

14. The memory access method according to claim 13, wherein: The data processing unit further includes: a shielding module and a merging module; the method further includes: The address decoder sends an enable signal to the shielding module when the address decoding result indicates that the read / write target of the data read / write signal is not a connected storage unit; The masking module, upon receiving the enable signal sent by the address decoder, masks the read data output by the connected storage unit, and inputs the masked read data into the merging module; The shielding module inputs the read data output by the connected storage unit into the merging module when the enable signal sent by the address decoder is not received; The merging module merges the read data output by the previous data processing unit and the read data output by the shielding module, and outputs the merged read data to the next data processing unit through the read data bus.

15. The memory access method according to claim 14, wherein: The merging module is a bitwise OR operator; the masking module, upon receiving the enable signal sent by the address decoder, masks the read data output by the connected storage units, including: When receiving the enable signal sent by the address decoder, the masking module masks the read data output by the connected storage unit into all-0 read data, where the value of each bit in the all-0 read data is 0; The merging module merges the read data output by the previous data processing unit and the read data output by the shielding module, and outputs the merged read data to the next data processing unit through the read data bus, including: The bitwise OR operator performs a bitwise OR operation on the read data output by the previous data processing unit and the read data output by the masking module, and outputs the read data after the bitwise operation to the next data processing unit through the read data bus.

16. The memory access method according to any one of claims 12 to 15, characterized in that: The memory access device further includes: a check bit generator and a checker; the method further includes: The check bit generator generates a check bit for write data; The checker performs read data verification based on the check bit.

17. The memory access method according to claim 16, wherein: The input end of the check bit generator is connected to the memory access interface, and the output end of the check bit generator is connected to the first data processing unit through the memory access request bus; The input end of the checker is connected to the last data processing unit via the read data bus, and the output end of the checker is connected to the memory access interface; The check bit generator generates a check bit for write data, including: The check bit generator generates a check bit based on the write data in the data write signal when receiving the data write signal input by the memory access interface, and inputs the data write signal including the write data and the check bit to the first data processing unit through the memory access request bus; The checker performs read data verification based on the check bit, including: The checker receives the target read data and the check bit corresponding to the target read data output by the last data processing unit through the read data bus, and performs read data check on the target read data based on the check bit; The method further comprises: The verifier inputs the target read data to the memory access interface if the target read data passes the read data verification; and stops inputting the target read data to the memory access interface if the target read data fails the read data verification.

18. A chip, characterized in that: The chip is provided with a memory access device as claimed in any one of claims 1 to 11.

19. A computer device, characterized in that: The computer device is provided with the chip according to claim 18.

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