Method, device, DAC and storage medium for improving DAC accuracy

Abstract

The present application discloses a method, device, DAC and storage medium for improving DAC accuracy, belonging to the field of signal processing technology. The method includes: obtaining a digital data group to be processed, which includes at least one data to be processed. Each data to be processed is adjusted to obtain a target data group, including: splitting the data to be processed according to a preset extended bit width and the bit width of the DAC to obtain a first split data with a high bit and a second split data with a low bit; determining the high bit value corresponding to the first split data and the low bit value corresponding to the second split data; determining the data group based on the carry relationship between the first split data and the second split data; performing a preset adjustment on the high bit value of the data group to obtain the target data group. The present application improves the processing accuracy of the DAC by splitting the data to be processed, so that the DAC can process data with a bit width larger than its own bit width.

Description

Technical Field

[0001] The present application relates to the field of signal processing technology, and in particular to a method, device, DAC and storage medium for improving DAC accuracy. Background Art

[0002] With the development of DACs (Digital-to-Analog Converters) in the electronics industry, DACs are being applied to high-speed, high-precision devices. Because the speed and accuracy of these devices are primarily related to the accuracy of the DAC, these devices often have higher DAC specifications, such as higher sampling rates, higher resolutions, and lower costs. In related technologies, a main control chip is typically connected to the DAC to configure the DAC's sampling rate and resolution, directly controlling the DAC's output. Therefore, these devices can directly use DACs with high sampling rates and high resolutions to improve their own accuracy. However, due to structural and process issues with DACs, high precision and cost cannot be achieved at the same time. The higher the precision of the DAC, the higher the cost. Therefore, there is an urgent need for a method to improve DAC accuracy that can achieve both high precision and cost. Summary of the Invention

[0003] This application provides a method, device, DAC, and storage medium for improving DAC accuracy, which can improve the DAC's processing accuracy while processing data with a bit width larger than its own bit width. The technical solution is as follows:

[0004] In one aspect, a method for improving DAC accuracy is provided, the method comprising:

[0005] Acquire a digital data group to be processed, wherein the data group to be processed includes at least one data to be processed, and the bit width of the data to be processed is greater than the bit width of the DAC;

[0006] Adjust each data to be processed to obtain a target data group;

[0007] The step of adjusting each data to be processed to obtain a target data group includes:

[0008] Splitting the data to be processed according to a preset extended bit width and a bit width of the DAC to obtain high-order first split data and low-order second split data, wherein the bit width of the first split data is equal to the bit width of the DAC, and the bit width of the second split data is equal to the preset extended bit width;

[0009] Determine a high-order value corresponding to the first split data and a low-order value corresponding to the second split data;

[0010] Based on a carry relationship between the first split data and the second split data, determining a number of the first split data corresponding to the carry relationship to obtain a data group;

[0011] A preset adjustment is made to the high-order value of the data group to obtain the target data group, and the sum of the high-order values ​​of each of the first split data in the target data group is increased by the low-order value corresponding to the second split data compared with the sum of the high-order values ​​of each of the first split data in the data group, so that the DAC performs digital-to-analog conversion on each of the first split data in the target data group to obtain a corresponding analog signal, and the filtering module performs a preset smoothing process on each of the analog signals to obtain an output signal.

[0012] Optionally, performing preset adjustment on the high value of the data group includes:

[0013] Performing an increase adjustment on the high-order values ​​of the first split data separated by intervals in the data group; and / or,

[0014] The high-order values ​​of the first split data other than the spaced first split data are adjusted to be reduced or maintained.

[0015] Optionally, a preset adjustment of a high-order value is performed on the data group based on a preset adjustment data group, the adjustment data group including first adjustment values ​​corresponding one-to-one to the first split data separated from each other in the data group, and second adjustment values ​​corresponding one-to-one to the first split data other than the first split data separated from each other;

[0016] Based on each of the first adjustment values, an increase adjustment is performed on the high-order values ​​of the first split data separated from each other in the data group; and / or based on each of the second adjustment values, a decrease adjustment is performed on or the high-order values ​​of the first split data other than the separated first split data are maintained;

[0017] The sum of each of the first adjustment values ​​and each of the second adjustment values ​​is the low-order value corresponding to the second split data.

[0018] Optionally, performing a preset adjustment on the high value of the data group to obtain a target data group further comprises:

[0019] Obtaining the target data group corresponding to the previous data to be processed;

[0020] According to the target data group and the adjustment data group corresponding to the previous data to be processed, the data group corresponding to the current data to be processed is adjusted by a preset high-order value to obtain a target data group.

[0021] Optionally, performing a preset high-order value adjustment on the data group corresponding to the current data to be processed based on the target data group and the adjustment data group corresponding to the previous data to be processed to obtain the target data group includes:

[0022] Determining the maximum target data and the minimum target data corresponding to the current data to be processed according to the data group corresponding to the current data to be processed, and each first adjustment value and / or each second adjustment value;

[0023] Determine an absolute difference between the maximum target data and the last target data in the target data group corresponding to the previous data to be processed, and determine an absolute difference between the minimum target data and the last target data in the target data group corresponding to the data to be processed;

[0024] If the absolute difference between the maximum target data and the last target data in the target data group corresponding to the previous data to be processed is greater than the absolute difference between the minimum target data and the last target data in the target data group corresponding to the previous data to be processed, then a preset high-order value adjustment is performed on the data group starting from the position corresponding to the first adjustment value corresponding to the maximum target data in the adjustment data group; otherwise, a preset high-order value adjustment is performed on the data group starting from the position corresponding to the second adjustment value corresponding to the minimum target data in the adjustment data group.

[0025] In another aspect, a device for improving DAC accuracy is provided, comprising:

[0026] DAC, used to convert digital signals into analog signals;

[0027] A filtering module, configured to perform a preset smoothing process on the analog signal output by the DAC to obtain an output signal;

[0028] Memory for storing data, and computer programs and / or instructions;

[0029] A processor is configured to implement the above-mentioned method for improving DAC accuracy when executing the computer program and / or instructions stored in the memory.

[0030] In another aspect, a method for improving DAC accuracy is provided, comprising:

[0031] Acquire multiple target data groups of numbers, each of the target data groups includes multiple first split data;

[0032] Performing digital-to-analog conversion on each of the first split data in the plurality of target data groups to obtain a corresponding analog signal, so that the filtering module performs a preset smoothing process on each of the analog signals to obtain an output signal; wherein the target data group is obtained based on the following method:

[0033] The processor obtains a digital data group to be processed, wherein the data group to be processed includes at least one data to be processed, and the bit width of the data to be processed is greater than the bit width of the DAC;

[0034] For each data to be processed: the processor splits the data to be processed according to a preset extended bit width and a bit width of the DAC to obtain first split data of high bits and second split data of low bits, wherein the bit width of the first split data is equal to the bit width of the DAC, and the bit width of the second split data is equal to the preset extended bit width;

[0035] The processor determines a high-order value corresponding to the first split data and a low-order value corresponding to the second split data;

[0036] The processor determines, based on a carry relationship between the first split data and the second split data, a number of the first split data corresponding to the carry relationship, to obtain a data group;

[0037] The processor performs preset adjustment on the high-order value of the data group to obtain the target data group, wherein the sum of the high-order values ​​of each of the first split data in the target data group is increased by the low-order value corresponding to the second split data compared with the data group.

[0038] On the other hand, a DAC is provided, which can implement the above-mentioned method for improving DAC accuracy.

[0039] On the other hand, a computer-readable storage medium is provided, wherein a computer program is stored in the storage medium. The computer program can be executed by a processor to implement the steps of the above-mentioned method for improving DAC accuracy.

[0040] On the other hand, a computer program product comprising instructions is provided. When the instructions are executed on a computer, the computer is caused to perform the steps of the above-mentioned method for improving DAC accuracy.

[0041] The technical solution provided by this application can at least bring the following beneficial effects:

[0042] The present application can obtain high-order first split data and low-order second split data by processing each data to be processed, wherein the bit width of the first split data is equal to the bit width of the DAC, and the bit width of the second split data is equal to the preset extended bit width. Afterwards, the data group is preset-adjusted to the high-order value to obtain the target data group, and the sum of the high-order values ​​of each first split data in the target data group is increased by the low-order value corresponding to the second split data compared to the sum of the high-order values ​​of each first split data in the data group. It can be seen that the extended bit width is equivalent to being able to expand the bit width of the DAC. In this way, the DAC can improve the processing accuracy of the DAC while processing data with a bit width larger than its own bit width; the filtering module will then smooth the analog signal corresponding to the target data group, which can improve the accuracy of the output signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A schematic diagram of the structure of a device for improving DAC accuracy provided in an embodiment of the present application;

[0044] Figure 2 A schematic structural diagram of another device for improving DAC accuracy provided in an embodiment of the present application;

[0045] Figure 3 A schematic structural diagram of another device for improving DAC accuracy provided in an embodiment of the present application;

[0046] Figure 4 A flowchart of a method for improving DAC accuracy provided in an embodiment of the present application;

[0047] Figure 5 A schematic diagram of a digital signal corresponding to a target data group provided in an embodiment of the present application;

[0048] Figure 6 A schematic diagram of an output signal provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] The present invention will be further described in detail below by means of specific embodiments in conjunction with the accompanying drawings. Similar elements in different embodiments are numbered with associated similar elements. In the following embodiments, many detailed descriptions are provided to enable the present application to be better understood. However, those skilled in the art will readily appreciate that some of the features may be omitted in different circumstances, or may be replaced by other elements, materials, or methods. In some cases, some operations related to the present application are not shown or described in the specification. This is to avoid the core portion of the present application being overwhelmed by excessive descriptions, and for those skilled in the art, it is not necessary to describe these related operations in detail. They will fully understand the related operations based on the description in the specification and the general technical knowledge in the art.

[0050] In addition, the features, operations, or characteristics described in the specification may be combined in any appropriate manner to form various embodiments. Furthermore, the steps or actions in the method description may be reordered or adjusted in a manner readily apparent to those skilled in the art. Therefore, the various sequences in the specification and drawings are provided solely for the purpose of clearly describing a particular embodiment and are not intended to be mandatory, unless otherwise specified.

[0051] Component numbers used herein, such as "first" and "second," are used solely to distinguish the components being described and do not convey any sequential or technical meaning. References to "connection" and "coupling" in this application, unless otherwise specified, include both direct and indirect connections (couplings).

[0052] Before explaining in detail the method for improving DAC accuracy provided by the present application, the implementation environment involved in the embodiments of the present application is first introduced.

[0053] Please refer to Figure 1 , Figure 1 1 is a schematic diagram of a device for improving DAC accuracy provided by an embodiment of the present application. The device includes a DAC 101, a filter module 102, a memory 103, and a processor 104.

[0054] The DAC 101 is used to convert digital signals into analog signals. In some embodiments, the DAC 101 also has an interface to connect to the processor 104, thereby enabling the DAC 101 to obtain multiple digital target data sets from the processor 104. The DAC 101 is also connected to the filter module 102, so that after the DAC 101 obtains the analog signal, it can send the analog signal to the filter module 102.

[0055] Filter module 102 is configured to perform a preset smoothing process on the analog signal output by DAC 101 to obtain an output signal. In some embodiments, filter module 102 may include an analog low-pass filter. Because discrete analog signals contain high-frequency quantization steps and image frequency components, the analog low-pass filter can smooth these steps and restore a continuous analog waveform.

[0056] The memory 103 is used to store data, computer programs and / or instructions. For example, the memory can store digital data groups to be processed, data groups and target data groups.

[0057] The processor 104 is configured to obtain a digital data group to be processed, where the data group to be processed includes at least one data to be processed, the bit width of which is greater than the bit width of the DAC 101 . Furthermore, for each data to be processed: the processor 104 splits the data to be processed according to the preset extended bit width and the bit width of DAC101 to obtain high-order first split data and low-order second split data, the bit width of the first split data is equal to the bit width of DAC101, and the bit width of the second split data is equal to the preset extended bit width, then, the high-order value corresponding to the first split data and the low-order value corresponding to the second split data are determined, and based on the carry relationship between the first split data and the second split data, the number of first split data corresponding to the carry relationship is determined to obtain a data group, and then the data group is adjusted by a preset high-order value to obtain a target data group, the sum of the high-order values ​​of each first split data in the target data group is increased by the low-order value corresponding to the second split data compared to the sum of the high-order values ​​of each first split data in the data group, so that DAC101 performs digital-to-analog conversion on each first split data in the target data group to obtain a corresponding analog signal, and performs preset smoothing processing on each analog signal to obtain an output signal.

[0058] In some embodiments, please refer to Figure 2 The processor 104 may include an FPGA (Field-Programmable Gate Array).

[0059] In addition, in some embodiments, please refer to Figure 3 The filtering module 102 may also be provided in the DAC 101. Thus, the DAC 101 can obtain a digital target data group, and then perform digital-to-analog conversion on each first split data in the target data group to obtain a corresponding analog signal, and perform a preset smoothing process on each analog signal to obtain an output signal.

[0060] Those skilled in the art should understand that the above-mentioned DAC101, filtering module 102, memory 103, and processor 104 are only examples. Other existing or future DACs, memories, processors, and filtering modules that are applicable to the embodiments of the present application should also be included in the scope of protection of the embodiments of the present application and are included here by reference.

[0061] Next, a method for improving DAC accuracy provided in an embodiment of the present application is explained in detail.

[0062] Figure 4 This is a flow chart of a method for improving DAC accuracy provided by an embodiment of the present application. Figure 4 , the method comprises the following steps:

[0063] Step 401: The processor obtains a digital data group to be processed, where the data group to be processed includes at least one data to be processed, and the bit width of the data to be processed is greater than the bit width of the DAC.

[0064] Among them, the bit width of the data to be processed refers to the number of binary bits of the data to be processed; the bit width of the DAC refers to the number of binary bits of its input digital signal, which determines how many discrete analog output levels the DAC can divide the digital signal into. The bit width of the DAC is a key parameter for measuring the resolution of the DAC and directly affects the accuracy and dynamic range of the output analog signal.

[0065] For example, the bit width of the DAC may be 14 bits, the to-be-processed data group includes 3 to-be-processed data, and the bit width of each to-be-processed data may be 17 bits.

[0066] It should be noted that the above-mentioned DAC bit width, the number of to-be-processed data included in the to-be-processed data group, the bit width of the to-be-processed data, and the extended bit width are merely examples and are not limited in the present embodiment.

[0067] Step 402: The processor adjusts each data to be processed to obtain a target data group.

[0068] Based on the above description, it can be seen that the bit width of the data to be processed is larger than the bit width of the DAC. A DAC can only process data equal to its own bit width without error. Errors will occur if it processes data larger than its own bit width. Therefore, after obtaining a set of digital data to be processed, it is necessary to adjust each data point to reduce errors in the DAC's processing of the data and improve its accuracy.

[0069] In some embodiments, each data to be processed may be adjusted according to the following steps (1)-(4);

[0070] (1) The data to be processed is split according to the preset extended bit width and the bit width of the DAC to obtain the first split data of the high bit and the second split data of the low bit. The bit width of the first split data is equal to the bit width of the DAC, and the bit width of the second split data is equal to the preset extended bit width.

[0071] In some embodiments, since the bit width of the data to be processed is greater than the bit width of the DAC, the data to be processed can be split according to a preset extended bit width and the bit width of the DAC. The extended bit width is equivalent to being able to expand the bit width of the DAC, which can be preset by a technician.

[0072] After the data to be processed is split according to the preset extended bit width and the bit width of the DAC, high-order first split data and low-order second split data can be obtained. The DAC does not produce errors when processing data with a bit width equal to its own bit width. Therefore, the bit width of the high-order first split data can be made equal to the bit width of the DAC. However, because the bit width of the data to be processed is greater than the bit width of the DAC, in addition to the first split data, low-order second split data with a bit width equal to the preset extended bit width can be obtained.

[0073] In some embodiments, the bit width of the data to be processed is equal to the sum of the bit width of the DAC and the extended bit width, so it can be directly split into first split data and second split data.

[0074] As an example, assuming that the bit width of the data to be processed is 17 bits, the bit width of the DAC is 14 bits, and the extended bit width is 3 bits, then the data to be processed can be split into high-order 14-bit data, that is, the first split data, and low-order 3-bit data, that is, the second split data; for example, if the data to be processed is 00000001101001101, then its corresponding first split data is 00000001101001, and the second split data is 101.

[0075] In addition, in some embodiments, the bit width of the data to be processed may be smaller than the sum of the bit width of the DAC and the extended bit width. In this case, the first split data having a bit width equal to the bit width of the DAC can be obtained first, and then the data corresponding to the remaining bit width can be padded with zeros to obtain the second split data having a bit width equal to the extended bit width.

[0076] As an example, assuming that the bit width of the data to be processed is 17 bits, the bit width of the DAC is 14 bits, and the extended bit width is 4 bits, then the data to be processed can be first split into 14-bit high-order data, that is, the first split data, and then the remaining 3-bit low-order data is padded with zeros to fill its bit width to 4 bits, and the low-order 4-bit data is obtained, that is, the second split data; for example, if the data to be processed is 00000001101001101, then its corresponding first split data is 00000001101001, and the remaining 101 is padded with zeros to obtain the second split data 0101.

[0077] As another example, assuming that the bit width of the data to be processed is 17 bits, the bit width of the DAC is 14 bits, and the extended bit width is 5 bits, then the data to be processed can be first split into 14-bit high-order data, that is, the first split data, and then the remaining 3-bit low-order data is padded with zeros to fill its bit width to 5 bits, and the low-order 5-bit data is obtained, that is, the second split data; for example, if the data to be processed is 00000001101001101, then its corresponding first split data is 00000001101001, and the remaining 101 is padded with zeros to obtain the second split data 00101.

[0078] In some embodiments, the bit width of the data to be processed may be greater than the sum of the bit width of the DAC and the extended bit width. In this case, the first split data with a bit width equal to the bit width of the DAC can be obtained first. However, since the bit width of the remaining data is greater than the extended bit width, the lowest one or more bits of the remaining data can be discarded to obtain the second split data with a bit width equal to the extended bit width.

[0079] As an example, assuming that the bit width of the data to be processed is 17 bits, the bit width of the DAC is 14 bits, and the extended bit width is 2 bits, then the data to be processed can be first split into 14-bit high-order data, that is, the first split data, and then the lowest bit of the remaining 3-bit low-order data is discarded to make its bit width equal to 2 bits, and the low-order 2-bit data is obtained, that is, the second split data; for example, if the data to be processed is 00000001101001101, then its corresponding first split data is 00000001101001, and the lowest bit of the remaining 101 is discarded to obtain the second split data 10.

[0080] As another example, assuming that the bit width of the data to be processed is 18 bits, the bit width of the DAC is 14 bits, and the extended bit width is 2 bits, then the data to be processed can be first split into high-order 14-bit data, that is, the first split data, and then the lowest two bits of the remaining low-order 4-bit data are discarded to make its bit width equal to 2 bits, and the low-order 2-bit data is obtained, that is, the second split data; for example, if the data to be processed is 000000001101001101, then its corresponding first split data is 00000000110100, and the lowest two bits of the remaining 1101 are discarded to obtain the second split data 11.

[0081] (2) Determine the high-order value corresponding to the first split data and the low-order value corresponding to the second split data.

[0082] Based on the above description, it can be known that the first split data and the second split data are both binary numbers. Therefore, the decimal high-order value corresponding to the first split data and the decimal low-order value corresponding to the second split data can be obtained.

[0083] For example, if the first split data is 00000001101001 and the second split data is 101, then the high-order value corresponding to the first split data is 105, and the low-order value corresponding to the second split data is 5.

[0084] (3) Based on the carry relationship between the first split data and the second split data, determine the number of first split data corresponding to the carry relationship to obtain a data group.

[0085] Based on the above description, the first split data and the second split data are both binary numbers, and the bit width of the first split data is greater than the bit width of the second split data. Therefore, it can be seen that there is a carry relationship between the first split data and the second split data, that is, to add 1 to the high-order first split data, it is necessary to add the corresponding number to the low-order second split data. For example, assuming that the bit width of the second split data is 2 bits, then the high-order first split data plus 1 is equal to the low-order second split data plus 4. For another example, assuming that the bit width of the second split data is 3 bits, then the high-order first split data plus 1 is equal to the low-order second split data plus 8.

[0086] Continuing with the above description, after obtaining the carry relationship between the first split data and the second split data, it is necessary to determine the number of first split data corresponding to the carry relationship to obtain a data group. As an example, assuming that the carry relationship between the first split data and the second split data is 4, then it is necessary to use 4 first split data as a data group; for example, if the first split data is 101010, then the data group includes 4 101010. As another example. Assuming that the carry relationship between the first split data and the second split data is 8, then it is necessary to use 8 first split data as a data group; for example, if the first split data is 101010, then the data group includes 8 101010.

[0087] (4) A preset adjustment is made to the high-order value of the data group to obtain a target data group, and the sum of the high-order values ​​of each first split data in the target data group is increased by the low-order value corresponding to the second split data compared with the sum of the high-order values ​​of each first split data in the data group, so that the DAC performs digital-to-analog conversion on each first split data in the target data group to obtain a corresponding analog signal, and performs preset smoothing processing on each analog signal to obtain an output signal.

[0088] That is to say, the high order value of each first split data in the data group needs to be preset adjusted, and the sum of the high order values ​​of each first split data after adjustment is increased by the low order value corresponding to the second split data compared with the sum of the high order values ​​of the first split data before adjustment.

[0089] As an example, assume that the data group includes 3 first split data, and the first split data is 00000001101001, and its corresponding high-order value is 105, then the data group is {105, 105, 105}. If the second split data is 101, and its corresponding low-order value is 5, then the sum of the three first split data in the target data group obtained after the preset adjustment of the high-order value of the data group is 5 greater than the sum of the three 105s in the above data group, that is, the sum of the three first split data in the target data = 105×3+5; similarly, if the second split data is 001, and its corresponding low-order value is 1, then the sum of the three first split data in the target data group obtained after the preset adjustment of the high-order value of the data group is 1 greater than the sum of the three 105s in the above data group, that is, the sum of the three first split data in the target data = 105×3+1.

[0090] Continuing with the above description, after obtaining the target data set, since the target data set is a digital signal, it is necessary to have the DAC perform digital-to-analog conversion on each of the first split data in the target data set to obtain a corresponding analog signal. Each analog signal is then subjected to a preset smoothing process and output. This allows the accuracy of the signal output by the DAC to approach the accuracy corresponding to the bit width of the data to be processed. Furthermore, since the bit width of the data to be processed is larger than the bit width of the DAC, and a larger bit width results in higher accuracy, the accuracy of the DAC can be improved through the above steps.

[0091] In some embodiments, in order to reduce the waveform fluctuation of the output signal during subsequent smoothing processing, the high-order values ​​of the first split data spaced apart in the data group can be increased; and / or, the high-order values ​​of the first split data other than the first split data spaced apart can be decreased or maintained.

[0092] As an example, assuming that the data group is {105, 105, 105, 105, 105}, then the first 105, the third 105 and the fifth 105 can be adjusted by increase, and the second 105 and the fourth 105 can be adjusted by decrease or maintained; it is also possible to only increase the first 105, the third 105 and the fifth 105, or only decrease or maintain the second 105 and the fourth 105.

[0093] In some embodiments, a preset adjustment of the high-order value of the data group can be performed based on a preset adjustment data group, the adjustment data group including first adjustment values ​​corresponding one-to-one to the first split data spaced apart in the data group, and second adjustment values ​​corresponding one-to-one to the first split data other than the first split data spaced apart. In this way, the high-order value of the first split data spaced apart in the data group can be increased based on each first adjustment value, and / or the high-order value of the first split data other than the first split data spaced apart can be decreased or maintained based on each second adjustment value, and the sum of each first adjustment value and each second adjustment value is the low-order value corresponding to the second split data.

[0094] That is, an adjustment data set can be preset, and the adjustment data set is used to perform a preset adjustment on the high-order value of the data set to obtain the target data set. The adjustment data set includes first adjustment values ​​corresponding one-to-one to the first split data separated from each other in the data set. In other words, the adjustment data set includes multiple first adjustment values, and each first adjustment value is used to perform a corresponding adjustment on the high-order value of the first split data separated from each other in the first data set to obtain the corresponding first split data in the target data set.

[0095] In some embodiments, the adjustment data group also includes second adjustment values ​​that correspond one-to-one to the first split data other than the spaced first split data, that is, the adjustment data group includes at least one second adjustment value, and each second adjustment value is used to adjust the corresponding high-order value of the first split data other than the spaced first split data to obtain the corresponding first split data in the target data group.

[0096] Based on the above description, it is known that the high-order value of the first split data in the data group can be increased, and the adjustment data group includes first adjustment values ​​that correspond one-to-one to the first split data in the data group. Then, the high-order value of the first split data in the data group can be increased accordingly based on the multiple first adjustment values, and the multiple first adjustment values ​​are all greater than 0.

[0097] Based on the above description, it is possible to increase or maintain the high-order values ​​of the first split data other than the spaced first split data in the data group, and the adjusted data group also includes second adjustment values ​​that correspond one-to-one to the first split data other than the spaced first split data. Then, based on the at least one second adjustment value, the high-order values ​​of the first split data between the spaced first split data in the data group can be decreased or maintained accordingly, and the multiple second adjustment values ​​are adjusted to be less than or equal to 0.

[0098] In addition, based on the above description, it can be seen that the sum of the high-order values ​​of each first split data in the target data set is increased by the low-order value corresponding to the second split data compared to the data set, and the high-order values ​​of the first split data are adjusted based on the first adjustment value and the second adjustment value. Therefore, the sum of all the first adjustment values ​​and all the second adjustment values ​​must be equal to the low-order value corresponding to the second split data, thereby ensuring that the sum of the high-order values ​​of each first split data in the target data set is increased by the low-order value corresponding to the second split data compared to the data set.

[0099] As an example, please refer to Table 1, which is an adjustment data group provided in an embodiment of the present application. The adjustment data group includes the correspondence between the second split data and the adjustment value. Therefore, in the subsequent process, the first adjustment value and the second adjustment value corresponding to the first split data can be determined from the adjustment data group based on the second split data in the data to be processed.

[0100] Table 1

[0101] Second split data Serial number 0 No. 1 No. 2 No. 3 No. 4 No. 5 No. 6 No. 7 000 +1 -1 +1 -1 +1 -1 +1 -1 001 +1 +0 +1 -1 +1 -1 +1 -1 010 +1 +0 +1 +0 +1 -1 +1 -1 011 +1 +0 +1 +0 +1 +0 +1 -1 100 +1 +0 +1 +0 +1 +0 +1 +0 101 +2 +0 +1 +0 +1 +0 +1 +0 110 +2 +0 +2 +0 +1 +0 +1 +0 111 +2 +0 +2 +0 +2 +0 +1 +0

[0102] As shown in Table 1 above, the values ​​below sequence numbers 0, 2, 4, and 6 are first adjustment values, and the values ​​below sequence numbers 1, 3, 5, and 7 are second adjustment values. It can be seen from Table 1 that when the second split data is 000, the sum of all first adjustment values ​​and all second adjustment values ​​is equal to 0, i.e., the low-order value corresponding to 000; when the second split data is 001, the sum of all first adjustment values ​​and all second adjustment values ​​is equal to 1, i.e., the low-order value corresponding to 001; when the second split data is 010, the sum of all first adjustment values ​​and all second adjustment values ​​is equal to 2, i.e., the low-order value corresponding to 010; when the second split data is 011, the sum of all first adjustment values ​​and all second adjustment values ​​is equal to 3, i.e., the low-order value corresponding to 010; similarly, when the second split data is other values, the sum of all first adjustment values ​​and second adjustment values ​​is equal to the corresponding low-order value.

[0103] Assume that the data group includes 8 first split data, and the first split data is 00000001101001, and its high-order value is 105. If the second split data is 101, then the adjustment values ​​corresponding to 101 can be found from the adjustment data group shown in Table 1 as +2, +0, +1, +0, +1, +0, +1, +0, and the high-order values ​​of the data group are adjusted in sequence according to the above adjustment values. The resulting target data group is {107, 105, 106, 105, 106, 105, 106, 106}. If the second split data is 111, then the adjustment values ​​corresponding to 111 can be found from the adjustment data group shown in Table 1, which are +2, +0, +2, +0, +2, +0, +1, +0 in sequence. According to the above adjustment values, the data group is adjusted to the preset high-order values ​​in sequence, and the target data group obtained is {107, 105, 107, 105, 107, 105, 106, 105}.

[0104] It should be noted that the adjustment data group corresponding to Table 1 above is described with an extended bit width of 3 bits, that is, the bit width of the second split data is 3 bits. Alternatively, in application, the bit width of the second split data in the adjustment data group can also be 4 bits or other values, and the adjustment value in the adjustment data group can also be set according to actual conditions. In other words, the embodiment of the present application does not limit the adjustment data group.

[0105] In some embodiments, in order to make the signal more continuous and smooth in subsequent processes, when performing preset adjustments to the high-order values ​​of the data to be processed other than the first data to be processed, the target data group corresponding to the previous data to be processed can be obtained first, and then, based on the target data group and adjustment data group corresponding to the previous data to be processed, the data group corresponding to the current data to be processed is preset adjusted to the high-order value to obtain the target data group.

[0106] In addition, in some embodiments, the following steps ac may be performed to adjust the preset high-order value of the data group corresponding to the current data to be processed according to the target data group and the adjustment data group corresponding to the previous data to be processed, so as to obtain the target data group;

[0107] a. Determine the maximum target data and the minimum target data corresponding to the current data to be processed based on the data group corresponding to the current data to be processed, and each first adjustment value and / or each second adjustment value.

[0108] Based on the above description, it can be seen that after determining the data group, the data group can be adjusted to a preset high-order value based on the first adjustment value and / or the second adjustment value, and the first adjustment value and / or the second adjustment value can be determined based on the adjusted data group. Therefore, after determining the first adjustment value and / or the second adjustment value, the corresponding maximum target data and minimum target data can be determined based on the first split data in the data group of the current data to be processed and their corresponding first adjustment value and / or second adjustment value.

[0109] As an example, assuming that the data group corresponding to the current data to be processed includes eight data with high-order values ​​of 105, and its second split data is 111, it can be obtained from Table 1 above that the adjustment values ​​corresponding to the current data to be processed are +2, +0, +2, +0, +2, +0, +1, +0. The current maximum adjustment value is the first adjustment value +2, the minimum adjustment value is the second adjustment value +2, and the high-order value of the first split data is 105. Then, it can be determined that the current corresponding maximum target data is 107 and the minimum target data is 105.

[0110] b. Determine the absolute difference between the maximum target data and the last target data in the target data group corresponding to the previous data to be processed, and determine the absolute difference between the minimum target data and the last target data in the target data group corresponding to the data to be processed.

[0111] Based on the above description, it can be seen that for each data to be processed, a number of first split data corresponding to the carry relationship between the first split data and the second split data is determined as a data group. In other words, the data group corresponding to each data to be processed includes multiple first split data in sequential order. Accordingly, after the data group is subjected to a preset adjustment of the high-order value, the target data group obtained also includes multiple adjusted first split data in sequential order, i.e., the target data.

[0112] In order to maximize the gap between the first target data in the target data group corresponding to the current data to be processed and the last target data in the target data group corresponding to the previous data to be processed, so as to perform better smoothing processing on it, it is also necessary to determine the absolute difference between the maximum target data corresponding to the current data to be processed and the last target data in the target data group corresponding to the previous data to be processed, as well as to determine the absolute difference between the minimum target data corresponding to the current data to be processed and the last target data in the target data group corresponding to the previous data to be processed, so as to determine the order of preset adjustment of high-order values ​​in the subsequent process.

[0113] As an example, assume that the target data group corresponding to the previous data to be processed is {107, 105, 106, 105, 106, 105, 106, 105}, the last target data is 105, the maximum target data corresponding to the current data to be processed is 107, and the minimum target data is 105. Then, the absolute difference between the maximum target data and the last target data in the target data group corresponding to the previous data to be processed is 2, and the absolute difference between the minimum target data and the last target data in the target data group corresponding to the previous data to be processed is 0.

[0114] c. If the absolute difference between the maximum target data and the last target data in the target data group corresponding to the previous data to be processed is greater than the absolute difference between the minimum target data and the last target data in the target data group corresponding to the previous data to be processed, then the data group is subjected to a preset high-order value adjustment starting from the position corresponding to the first adjustment value corresponding to the maximum target data in the adjustment data group; otherwise, the data group is subjected to a preset high-order value adjustment starting from the position corresponding to the second adjustment value corresponding to the minimum target data in the adjustment data group.

[0115] After obtaining the absolute difference between the maximum target data and the last target data in the target data group corresponding to the previous data to be processed, and the absolute difference between the minimum target data and the last target data in the target data group corresponding to the previous data to be processed, it is also necessary to judge the size of the absolute difference corresponding to the above-mentioned maximum target data and the absolute difference corresponding to the minimum target data to determine the order of preset adjustments to the high-order values ​​corresponding to the current data to be processed.

[0116] In some embodiments, if the absolute difference corresponding to the maximum target data is greater than the absolute difference corresponding to the minimum target data, it means that adjusting the data group corresponding to the current data to be processed starting from the first adjustment value corresponding to the maximum target data can ensure that the absolute difference between the first target data in the target data group corresponding to the current data to be processed and the last target data in the target data corresponding to the previous data to be processed is the largest. Therefore, the data group should be adjusted to a preset high value starting from the position corresponding to the first adjustment value in the adjustment data group.

[0117] As an example, assume that the last target data in the target data corresponding to the previous data to be processed is 105. If the absolute difference value corresponding to the maximum target data is 2, the absolute difference value corresponding to the minimum target data is 0, and if the second split data of the current data to be processed is 101, then it can be seen from Table 1 above that the first adjustment value corresponding to the maximum target data is sequence number 0 in the adjustment data group, then the data group can be adjusted to the preset high value in the order of sequence number 0, sequence number 1, sequence number 2, sequence number 3, sequence number 4, sequence number 5, sequence number 6, sequence number 7, sequence number 0, sequence number 1, and the resulting target data group is {107, 105, 106, 105, 106, 105, 106, 106}; similarly, if the first adjustment value corresponding to the maximum target data is sequence number 2 in the adjustment data group, then the data group can be adjusted to the preset high value in the order of sequence number 2, sequence number 3, sequence number 4, sequence number 5, sequence number 6, sequence number 7, sequence number 0, and sequence number 1.

[0118] In some embodiments, if the absolute difference corresponding to the maximum target data is smaller than the absolute difference corresponding to the minimum target data, it means that adjusting the data group corresponding to the current data to be processed starting from the second adjustment value corresponding to the minimum target data can ensure that the absolute difference between the first target data in the target data group corresponding to the current data to be processed and the last target data in the target data corresponding to the previous data to be processed is the largest. Therefore, the data group should be adjusted to a preset high value starting from the position corresponding to the second adjustment value in the adjustment data group.

[0119] As an example, if the absolute difference value corresponding to the maximum target data is 0, the absolute difference value corresponding to the minimum target data is 1, and the second adjustment value corresponding to the minimum target data is sequence number 5 in the adjustment data group, then the data group can be preset for the high-order value in the order of sequence number 5, sequence number 6, sequence number 7, sequence number 0, sequence number 1, sequence number 2, sequence number 3, and sequence number 4; similarly, if the second adjustment value corresponding to the minimum target data is sequence number 7 in the adjustment data group, then the data group can be preset for the high-order value in the order of sequence number 7, sequence number 0, sequence number 1, sequence number 2, sequence number 3, sequence number 4, sequence number 5, and sequence number 6.

[0120] In some embodiments, if the absolute difference corresponding to the maximum target data is greater than the absolute difference corresponding to the minimum target data, and the first adjustment value corresponding to the maximum target data corresponds to multiple positions in the adjustment data group, then the data group can be adjusted to the preset high-order value starting from the position corresponding to the first adjustment value at the previous position. For example, assuming that the first adjustment value corresponding to the maximum target data is +2, and the first adjustment values ​​of sequence numbers 0, 2, and 4 in the adjustment data group are all +2, then the data group currently to be processed can be adjusted to the preset high-order value starting from sequence number 0.

[0121] In addition, in some embodiments, if the absolute difference corresponding to the minimum target data is greater than the absolute difference corresponding to the maximum target data, and the second adjustment value corresponding to the minimum target data corresponds to multiple positions in the adjusted data group, then the preset high-order value adjustment can be performed on the data group starting from the position corresponding to the second adjustment value at the previous position. For example, assuming that the second adjustment value corresponding to the minimum target data is -1, and the second adjustment values ​​of sequence numbers 3, 5, and 7 in the adjusted data group are all -1, then the preset high-order value adjustment can be performed on the data group of the current data to be processed starting from sequence number 3.

[0122] Similarly to the above, if the absolute difference corresponding to the maximum target data is equal to the absolute difference corresponding to the minimum target data, the data group can be adjusted to the preset high value according to the first adjustment value corresponding to the maximum target data in front or the second adjustment value corresponding to the minimum target data.

[0123] Step 403: The DAC obtains multiple digital target data groups, each target data group including multiple first split data.

[0124] In some embodiments, after the processor obtains a target data set corresponding to each data to be processed in the data set to be processed, the processor can send the multiple target data sets to the DAC, so that the DAC can obtain a digital target data set. Based on the above description, it can be seen that the target data set is obtained by performing a preset adjustment on the high-order values ​​of the data set including the multiple first split data. Therefore, the target data set also includes multiple first split outputs.

[0125] As an example, the DAC receives three target data groups, and the multiple target data groups are respectively a first target data group {107, 105, 106, 105, 106, 105, 106, 105}, a second target data group {107, 105, 106, 105, 106, 105, 106, 105} and a third target data group {107, 105, 1076, 105, 107, 105, 106, 105}. The digital signals corresponding to the above three target data groups are as follows: Figure 5 shown.

[0126] Step 404: The DAC performs digital-to-analog conversion on each of the first split data in the plurality of target data groups to obtain a corresponding analog signal.

[0127] It should be noted that the DAC can use existing methods to perform digital-to-analog conversion, which will not be described in detail here.

[0128] Step 405: The filtering module performs preset smoothing processing on each analog signal to obtain an output signal.

[0129] In some embodiments, the preset smoothing process is averaging. For example, assuming that the multiple target data groups are a first target data group {107, 105, 106, 105, 106, 105, 106, 105}, a second target data group {107, 105, 106, 105, 106, 105, 106, 105} and a third target data group {107, 105, 107, 105, 107, 105, 106, 105}, after the DAC performs digital-to-analog conversion on the above data, the DAC averages the above data, i.e., performs smoothing process, and the output signal obtained after smoothing is as follows Figure 6 As shown by the solid line in the figure, its value is 105.71. Figure 6 It can be seen that after the above processing, the output signal is smooth and can be accurate to several decimal places, which can improve the accuracy of the DAC and the output resolution.

[0130] It should be noted that the above description is based on the preset smoothing process being averaged, or in application, the smoothing process may be performed in other ways, which is not limited in the present embodiment.

[0131] The embodiment of the present application can obtain high-order first split data and low-order second split data by processing each data to be processed, wherein the bit width of the first split data is equal to the bit width of the DAC, and the bit width of the second split data is equal to the preset extended bit width. Afterwards, the data group is preset-adjusted to the high-order value to obtain the target data group, and the sum of the high-order values ​​of each first split data in the target data group is increased by the low-order value corresponding to the second split data compared to the sum of the high-order values ​​of each first split data in the data group. It can be seen that the extended bit width is equivalent to being able to expand the bit width of the DAC. In this way, the DAC can improve the processing accuracy of the DAC while processing data with a bit width larger than its own bit width; the filtering module will then smooth the analog signal corresponding to the target data group, which can improve the accuracy of the output signal.

[0132] Those skilled in the art will appreciate that all or part of the functions of the various methods in the above embodiments can be implemented by hardware or by computer program. When all or part of the functions in the above embodiments are implemented by computer program, the program can be stored in a computer-readable storage medium, and the storage medium can include: read-only memory, random access memory, disk, optical disk, hard disk, etc., and the program is executed by a computer to implement the above functions. For example, the program is stored in the memory of the device, and when the program in the memory is executed by the processor, all or part of the above functions can be implemented. In addition, when all or part of the functions in the above embodiments are implemented by computer program, the program can also be stored in a storage medium such as a server, another computer, disk, optical disk, flash disk or mobile hard disk, and saved in the memory of the local device by downloading or copying, or the system of the local device is updated. When the program in the memory is executed by the processor, all or part of the functions in the above embodiments can be implemented.

[0133] The above examples are used to illustrate the present invention, which are only used to help understand the present invention and are not intended to limit the present invention. Those skilled in the art can make several simple deductions, modifications or substitutions based on the concept of the present invention.

Claims

1. A method for improving DAC accuracy, characterized in that: The method comprises: Acquire a digital data group to be processed, wherein the data group to be processed includes at least one data to be processed, and the bit width of the data to be processed is greater than the bit width of the DAC; Adjust each data to be processed to obtain a target data group; The step of adjusting each data to be processed to obtain a target data group includes: Splitting the data to be processed according to a preset extended bit width and a bit width of the DAC to obtain high-order first split data and low-order second split data, wherein the bit width of the first split data is equal to the bit width of the DAC, and the bit width of the second split data is equal to the preset extended bit width; Determine a high-order value corresponding to the first split data and a low-order value corresponding to the second split data; Based on a carry relationship between the first split data and the second split data, determining a number of the first split data corresponding to the carry relationship to obtain a data group; performing an increase adjustment on the high-order values ​​of the spaced first split data in the data group, and / or performing a decrease adjustment or maintaining on the high-order values ​​of the first split data other than the spaced first split data, to obtain the target data group, wherein the sum of the high-order values ​​of each of the first split data in the target data group is increased by the low-order value corresponding to the second split data compared with the sum of the high-order values ​​of each of the first split data in the data group, so that the DAC performs digital-to-analog conversion on each of the first split data in the target data group to obtain a corresponding analog signal, and the filtering module performs a preset smoothing process on each of the analog signals to obtain an output signal; In which, a preset adjustment of the high-order value of the data group is performed based on a preset adjustment data group, and the adjustment data group includes a first adjustment value corresponding one-to-one to the first split data spaced apart in the data group, and a second adjustment value corresponding one-to-one to the first split data other than the spaced apart first split data; based on each of the first adjustment values, the high-order value of the first split data spaced apart in the data group is increased, and / or, based on each of the second adjustment values, the high-order value of the first split data other than the spaced apart first split data is decreased or maintained; the sum of each of the first adjustment values ​​and each of the second adjustment values ​​is the low-order value corresponding to the second split data.

2. The method for improving DAC accuracy according to claim 1, wherein: The step of increasing the high-order values ​​of the first split data separated from each other in the data group, and / or decreasing or maintaining the high-order values ​​of the first split data other than the first split data separated from each other, to obtain the target data group further comprises: Obtaining the target data group corresponding to the previous data to be processed; According to the target data group corresponding to the previous data to be processed and the adjustment data group, the data group corresponding to the current data to be processed is adjusted by a preset high-order value to obtain a target data group.

3. The method for improving DAC accuracy according to claim 2, wherein: The step of performing a preset high-order adjustment on the data group corresponding to the current data to be processed based on the target data group corresponding to the previous data to be processed and the adjustment data group to obtain the target data group includes: Determining the maximum target data and the minimum target data corresponding to the current data to be processed according to the data group corresponding to the current data to be processed, and each first adjustment value and / or each second adjustment value; Determine an absolute difference between the maximum target data and the last target data in the target data group corresponding to the previous data to be processed, and determine an absolute difference between the minimum target data and the last target data in the target data group corresponding to the data to be processed; If the absolute difference between the maximum target data and the last target data in the target data group corresponding to the previous data to be processed is greater than the absolute difference between the minimum target data and the last target data in the target data group corresponding to the previous data to be processed, then a preset high-order value adjustment is performed on the data group starting from the position corresponding to the first adjustment value corresponding to the maximum target data in the adjustment data group; otherwise, a preset high-order value adjustment is performed on the data group starting from the position corresponding to the second adjustment value corresponding to the minimum target data in the adjustment data group.

4. A device for improving DAC accuracy, characterized in that: include: DAC, used to convert digital signals into analog signals; A filtering module, configured to perform a preset smoothing process on the analog signal output by the DAC to obtain an output signal; Memory for storing data, and computer programs and / or instructions; A processor, configured to implement the method according to any one of claims 1 to 3 when executing the computer program and / or instructions stored in the memory.

5. A method for improving DAC accuracy, characterized in that: include: Acquire multiple target data groups of numbers, each of the target data groups includes multiple first split data; Performing digital-to-analog conversion on each of the first split data in the plurality of target data groups to obtain a corresponding analog signal, so that the filtering module performs a preset smoothing process on each of the analog signals to obtain an output signal; wherein the target data group is obtained based on the following method: The processor obtains a digital data group to be processed, wherein the data group to be processed includes at least one data to be processed, and the bit width of the data to be processed is greater than the bit width of the DAC; For each data to be processed: the processor splits the data to be processed according to a preset extended bit width and a bit width of the DAC to obtain first split data of high bits and second split data of low bits, wherein the bit width of the first split data is equal to the bit width of the DAC, and the bit width of the second split data is equal to the preset extended bit width; The processor determines a high-order value corresponding to the first split data and a low-order value corresponding to the second split data; The processor determines, based on a carry relationship between the first split data and the second split data, a number of the first split data corresponding to the carry relationship, to obtain a data group; The processor increases the high-order values ​​of the first split data that are spaced apart in the data group, and / or decreases or maintains the high-order values ​​of the first split data other than the spaced-apart first split data, to obtain the target data group, wherein the sum of the high-order values ​​of the first split data in the target data group is increased by the low-order value corresponding to the second split data compared with the data group; In which, the processor performs a preset adjustment of the high-order value of the data group based on a preset adjustment data group, and the adjustment data group includes a first adjustment value corresponding one-to-one to the first split data spaced apart in the data group, and a second adjustment value corresponding one-to-one to the first split data other than the spaced apart first split data; based on each of the first adjustment values, the high-order value of the first split data spaced apart in the data group is increased, and / or, based on each of the second adjustment values, the high-order value of the first split data other than the spaced apart first split data is decreased or maintained; the sum of each of the first adjustment values ​​and each of the second adjustment values ​​is the low-order value corresponding to the second split data.

6. A DAC, characterized in that: Used to implement the method described in claim 5.

7. A computer-readable storage medium, characterized in that A computer program is stored on the medium, and the computer program can be executed by a processor to implement the method according to any one of claims 1 to 3 and claim 5.

8. A computer program product comprising a computer program and / or instructions, characterized in that When the computer program and / or the instructions are executed by a processor, the method according to any one of claims 1 to 3 and claim 5 is implemented.

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