Optoelectronic co-packaged device and method of manufacturing the same

Abstract

The application discloses an optoelectronic co-packaged device and a preparation method thereof. The optoelectronic co-packaged device comprises a diamond adapter plate, the diamond adapter plate comprising opposite first and second surfaces; the diamond adapter plate is provided with a first through hole and a second through hole penetrating the first and second surfaces; the first and second through holes are independently arranged; a diamond optical waveguide through hole is arranged in the first through hole, the diamond optical waveguide through hole comprising a core layer and a cladding layer covering the outer wall of the core layer, the refractive index of the core layer being greater than that of the cladding layer; a diamond through hole is filled with a conductive metal in the second through hole, the diamond through hole being electrically connected with the diamond adapter plate. The diamond adapter plate simultaneously serves as a carrier of an electrical module and an optical module, and internally integrates a diamond through hole (TDV) and a diamond optical waveguide through hole (OTDV), thereby providing a basis for efficient conversion of optical and electrical signals; meanwhile, with the aid of the super-high thermal conductivity of diamond, the adapter plate can quickly conduct away the heat of a chip, thereby significantly improving the heat management capability of the device.

Description

Technical Field

[0001] This application relates to the field of optoelectronic integration technology, specifically to an optoelectronic co-packaged device and its fabrication method. Background Technology

[0002] With the rapid development of artificial intelligence, cloud computing, and 5G communication technologies, traditional electronic interconnect technologies are facing the dual challenges of bandwidth limitations and power consumption barriers, making it difficult to meet the demands of high-density data transmission and processing. Optical interconnect technology, with its high bandwidth, low latency, and resistance to electromagnetic interference, has become a key technology for overcoming performance bottlenecks in data centers, high-performance computing (HPC), and communication networks. However, traditional optical modules (such as pluggable optical modules) are limited by discrete packaging architectures, resulting in large size, high power consumption, and low electro-optical conversion efficiency, making it difficult to meet the high-density, low-power, and ultra-high bandwidth requirements of next-generation systems.

[0003] Against this backdrop, Co-Packaged Optics (CPO) technology has emerged. CPO integrates electrical chips (such as ASIC / Switch chips and EIC chips) and optical chips (PIC) into the same package, which can not only significantly shorten the electro-optical signal path, but also significantly improve the data transmission rate and energy efficiency.

[0004] It should be noted that the above statements are only used to provide background information related to this application and do not necessarily constitute prior art. Summary of the Invention

[0005] In a first aspect, this application provides an optoelectronic co-packaged device, comprising: a diamond adapter plate, the diamond adapter plate including a first surface and a second surface opposite to each other; a first through hole and a second through hole penetrating the first surface and the second surface; the first through hole and the second through hole being independently disposed; a diamond waveguide through hole, the first through hole having a core layer and a cladding layer covering the outer wall of the core layer to form the diamond waveguide through hole, the refractive index of the core layer being greater than the refractive index of the cladding layer; and a diamond through hole, the second through hole being filled with conductive metal to form the diamond through hole, the diamond through hole being electrically connected to the diamond adapter plate.

[0006] Therefore, the diamond adapter board serves as a carrier for both electrical and optical modules, integrating diamond through-hole (TDV) and diamond optical waveguide (OTDV) vias to provide a foundation for efficient conversion of photoelectric signals. At the same time, thanks to the ultra-high thermal conductivity of diamond, the adapter board can quickly dissipate heat from the chip, thereby significantly improving the thermal management capability of the device.

[0007] In some embodiments, the core layer comprises one or more of diamond, polymer, germanium-doped silicon dioxide, silicon carbide, silicon, and air; the cladding layer comprises one or more of amorphous diamond, graphitized diamond, aluminum and its alloys, gold and its alloys, silver and its alloys, chromium and its alloys, and silicon dioxide; and / or, the conductive metal comprises one or more of copper and its alloys, tungsten and its alloys, silver and its alloys, nickel and its alloys, titanium and its alloys, and tantalum and its alloys.

[0008] In some embodiments, a redistribution layer is also included, located on the first and / or second surfaces of the diamond adapter plate and electrically connected to the diamond adapter plate. This allows the chip's I / O interfaces to be redistributed to suitable locations for connection with diamond vias, thereby resolving the density mismatch issue when connecting the chip's I / O interfaces to external circuits, making the connection between the chip and the diamond adapter plate more convenient, and improving the flexibility of circuit layout.

[0009] In some embodiments, a horizontal optical waveguide is also included, located on the side surface of the redistribution layer away from the diamond adapter plate. Thus, the horizontal optical waveguide enables horizontal transmission of optical signals within the device, reducing signal loss and distortion during transmission, thereby improving signal quality and transmission efficiency. Simultaneously, the horizontal optical waveguide can efficiently couple internal optoelectronic structures to external optical fibers, providing flexible interconnection methods to adapt to different application scenarios.

[0010] In some embodiments, an electrical chip layer and an optical chip layer are also included; the electrical chip layer is located on the side of the redistribution layer away from the diamond adapter plate and is electrically connected to the redistribution layer and / or the diamond via; the optical chip layer is located on the surface of the redistribution layer away from the diamond adapter plate and is coupled to the diamond waveguide via and / or the horizontal waveguide.

[0011] In some embodiments, a laser is also included, comprising an edge-emitting laser and / or a vertical-cavity surface-emitting laser (VCSEL). The edge-emitting laser is located on the surface of the redistribution layer away from the diamond interposer and is coupled to the horizontal waveguide. The VCSEL is located on the surface of the diamond interposer away from the optical chip layer and is coupled to the diamond waveguide via. Thus, the coupling between the edge-emitting laser and the horizontal waveguide supports horizontal transmission of optical signals, while the coupling between the VCSEL and the diamond waveguide via supports vertical transmission of optical signals. This flexible optical interconnect method can adapt to different application scenarios and requirements.

[0012] In some embodiments, a heat dissipation module is also included, comprising microfluidic channels embedded within the diamond adapter plate, and / or microjets disposed on the first and / or second surfaces of the diamond adapter plate. Thus, the microfluidic channels and / or microjets can effectively dissipate the heat generated by the optical and electrical chips during operation, reducing the impact of thermal stress on device performance, thereby improving the overall thermal stability and reliability of the device.

[0013] In a second aspect, this application provides a method for fabricating an optoelectronic co-packaged device, including fabricating the diamond waveguide via. The method for fabricating the diamond waveguide via includes: forming a core layer and a cladding layer covering the outer wall of the core layer within a first via, thereby forming the diamond waveguide via. Thus, by forming a diamond waveguide via by providing a core layer and a cladding layer within the first via of a diamond adapter plate, optical signals can propagate within the core layer, while the optical signals are confined within the core layer by the cladding layer, thereby reducing transmission loss of the optical signal.

[0014] In some embodiments, the core layer position is selected on the surface of the diamond adapter plate; the diamond adapter plate surrounding the outer region of the core layer is subjected to femtosecond laser processing to form the cladding; one end of the core layer is located on the first surface of the diamond adapter plate, and the other end of the core layer is located on the second surface.

[0015] In some embodiments, a first through-hole penetrating the first surface and the second surface is formed on the diamond adapter plate; a reflective metal is deposited on the inner wall of the first through-hole to form the cladding; the reflective metal includes one or more of aluminum and its alloys, gold and its alloys, silver and its alloys, and chromium and its alloys; and / or, silicon dioxide is deposited on the inner wall of the first through-hole to form the cladding; the region within the cladding is filled with one or more of polymer, germanium-doped silicon dioxide, silicon carbide, and silicon to form the core layer. Attached Figure Description

[0016] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0017] Figure 1 This is a schematic diagram of the structure of an optoelectronic co-packaged device according to one embodiment of this application.

[0018] Figure 2 This is a schematic diagram of the structure of a diamond waveguide via in one embodiment of this application.

[0019] Figure 3 This is a schematic diagram of the structure of a diamond waveguide via in another embodiment of this application.

[0020] Figure 4 This is a schematic diagram of the structure of a diamond waveguide via in another embodiment of this application.

[0021] Figure 5 This is a schematic diagram of the structure of a horizontal optical waveguide in one embodiment of this application.

[0022] Explanation of reference numerals in the attached figures:

[0023] 11. Diamond adapter board; 111. First surface; 112. Second surface; 12. Diamond waveguide via; 121. Core layer; 122. Cladding layer; 13. Diamond via; 14. First redistribution layer; 15. Second redistribution layer; 16. ASIC / Switch; 17. EIC; 18. Horizontal waveguide; 181. Upper cladding layer; 182. Horizontal waveguide core layer; 183. Lower cladding layer; 19. PIC; 20. Laser; 21. Microfluidic channel; 22. Packaging substrate; 23. PCB board. Detailed Implementation

[0024] The following detailed description, with appropriate reference to the accompanying drawings, discloses an embodiment of an optoelectronic co-packaged device and its fabrication method. However, unnecessary details may be omitted. For example, detailed descriptions of well-known matters and repetitive descriptions of essentially identical structures may be omitted. This is to avoid unnecessarily lengthy descriptions and to facilitate understanding by those skilled in the art. Furthermore, the accompanying drawings and the following description are provided for the purpose of enabling those skilled in the art to fully understand this application and are not intended to limit the subject matter of the claims.

[0025] The "range" disclosed in this application is defined by a lower limit and an upper limit. A given range is defined by selecting a lower limit and an upper limit, which define the boundaries of a particular range. Ranges defined in this way can include or exclude endpoints and can be arbitrarily combined; that is, any lower limit can be combined with any upper limit to form a range. For example, if ranges of 60-120 and 80-110 are listed for a specific parameter, it is also expected that ranges of 60-110 and 80-120 are also included. Furthermore, if minimum range values ​​of 1 and 2 are listed, and if maximum range values ​​of 3, 4, and 5 are listed, then the following ranges are all expected: 1-3, 1-4, 1-5, 2-3, 2-4, and 2-5. In this application, unless otherwise stated, the numerical range "ab" represents a shortened representation of any combination of real numbers between a and b, where a and b are real numbers. For example, the numerical range "0-5" indicates that all real numbers between "0-5" have been listed in this article; "0-5" is simply a shortened representation of these numerical combinations. Furthermore, when a parameter is stated as an integer ≥2, it is equivalent to disclosing that the parameter is, for example, an integer such as 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc.

[0026] Unless otherwise specified, all embodiments and optional embodiments of this application can be combined to form new technical solutions.

[0027] Unless otherwise specified, all technical features and optional technical features of this application may be combined to form new technical solutions.

[0028] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit this application; unless otherwise stated, the values ​​of the parameters mentioned in this application can be measured using various measurement methods commonly used in the art (e.g., they can be tested according to the methods given in the embodiments of this application).

[0029] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. "First feature" and "second feature" may include one or more of the indicated feature.

[0030] In the description of this application, "A and / or B" can include any of the cases of A alone, B alone, or A and B, where A and B are merely examples and can be any technical feature connected by "and / or" in this application.

[0031] CPO technology mainly includes two technical paths: 2.5D packaging and 3D packaging. 2.5D packaging involves flip-chip bonding of an electrical integrated circuit (EIC) and an optical component (PIC) side-by-side on an interposer, with the PIC and EIC interconnected via metal on the interposer. The bottom of the interposer is then electrically connected to the packaging substrate or printed circuit board (PCB), thus creating a system architecture for optoelectronic collaboration. Compared to 2.5D packaging, 3D packaging employs a three-dimensional stacking integration mode, using vertical interconnect technologies such as through-silicon vias (TSVs) and micro-bumps to stack the optical and electrical components in a three-dimensional manner. This architecture, with its shorter interconnect distance and higher interconnect density, exhibits excellent signal integrity in high-frequency signal transmission while also offering lower power consumption. Furthermore, this architecture boasts higher system integration and a more compact packaging form factor, making it a current research hotspot and a core future development direction for CPO technology.

[0032] In the CPO architecture, the adapter board serves as the core carrier for the collaborative operation of electrical chips (ASIC or EIC) and optical chips (PIC), undertaking multiple functions such as electrical signal interconnection, optical signal routing, and thermal management.

[0033] Commonly used silicon interconnects are based on mature silicon-based semiconductor processes (such as complementary metal-oxide-semiconductor processes), utilizing through-silicon vias (TSVs) and redistribution layers (RDLs) to construct high-density electrical interconnect networks. Meanwhile, silicon photonics technology has successfully achieved monolithic integration of core optical devices such as optical modulators and detectors, providing technical support for the construction of large-scale optical interconnect networks. However, the dielectric loss of silicon (dielectric loss tangent tanδ≈0.01) causes significant signal attenuation and crosstalk in high-frequency bands such as millimeter waves or terahertz, limiting the bandwidth expansion capability of high-frequency signals. Furthermore, silicon exhibits nonlinear losses such as two-photon absorption in the communication band (1550nm), which further reduces the transmission efficiency of optical signals.

[0034] Glass adapters offer high transparency in communication bands, supporting low-loss optical waveguide transmission and efficient fiber-to-chip coupling, making them ideal for long-distance optical signal interconnection scenarios. The dielectric loss of glass (tanδ≈0.001) is significantly lower than that of silicon, exhibiting lower signal attenuation and crosstalk characteristics in high-frequency signal transmission, thus becoming an ideal carrier for high-frequency electrical interconnects.

[0035] However, in the CPO architecture, the high-density integration of electrical and optical chips generates significant thermal effects. Specifically, the high-speed signal processing of the electrical chips is accompanied by Joule losses, while the photoelectric conversion process of the optical chips is limited by quantum efficiency. Both factors contribute to a substantial increase in heat flux density per unit area. Silicon-based interposers (thermal conductivity approximately 145 W / (m·K)) and glass-based interposers (thermal conductivity only 1.1 W / (m·K)) have poor thermal conductivity, making it difficult to solve the complex thermal management problems encountered in optoelectronic co-packaging scenarios.

[0036] Based on this, in a first aspect of this application, an optoelectronic co-packaged device is provided, comprising: a diamond adapter plate 11, the diamond adapter plate 11 including a first surface 111 and a second surface 112 opposite to each other; a first through hole and a second through hole penetrating the first surface 111 and the second surface 112 are provided on the diamond adapter plate 11; the first through hole and the second through hole are independently arranged; a diamond waveguide through hole 12, the first through hole being provided with a core layer 121 and a cladding layer 122 covering the outer wall of the core layer 121 to form a diamond waveguide through hole 12, the refractive index of the core layer 121 being greater than the refractive index of the cladding layer 122; and a diamond through hole 13, the second through hole being filled with conductive metal to form a diamond through hole 13, the diamond through hole 13 being electrically connected to the diamond adapter plate 11.

[0037] The diamond adapter board 11 serves as a carrier for both the electrical and optical modules. It integrates diamond through-holes 13 (TDV) and diamond optical waveguide through-holes 12 (OTDV), providing a foundation for efficient conversion of photoelectric signals. At the same time, thanks to the ultra-high thermal conductivity of diamond, the adapter board can quickly dissipate heat from the chip, thereby significantly improving the thermal management capability of the device.

[0038] The following provides a further explanation of the structure and connection relationship of the optoelectronic co-packaged device based on the diamond adapter plate 11.

[0039] In some implementations, combined Figure 1 The optoelectronic co-packaged device includes a diamond adapter plate 11.

[0040] Diamond is a wide bandgap material that combines ultra-high hardness, ultra-high thermal conductivity, low dielectric constant, and a wide optical transparency window. The diamond adapter plate 11 offers the following advantages when used in CPO technology:

[0041] (1) With the help of the ultra-high thermal conductivity of diamond (thermal conductivity of about 2000W / (m·K)), the diamond adapter board 11 can quickly dissipate the Joule heat generated by the operation of the electrical chip, effectively reduce the chip junction temperature, and thus improve the reliability of the system in long-term operation; at the same time, the diamond adapter board 11 can be adapted to kilowatt-level optical communication modules (such as lidar, supercomputing optical interconnect system, etc.) to meet the needs of high-power application scenarios.

[0042] (2) The low dielectric constant (ε≈5.7) and ultra-low dielectric loss (tanδ≈0.0001) of diamond enable the diamond adapter board 11 to be adapted to high-speed channels of serializer / deserializer at 112Gbps and above. Compared with silicon-based (tanδ≈0.01) and glass-based (tanδ≈0.001) materials, the diamond adapter board 11 can reduce signal attenuation and crosstalk by 1-2 orders of magnitude, thereby significantly improving the integrity and bandwidth expansion capability of high-frequency signals.

[0043] (3) The high breakdown field strength (>10MV / cm) of diamond provides a carrier for the synergistic integration of high voltage driving circuits and high power lasers, reducing the design limitations caused by the insufficient voltage resistance of traditional materials; at the same time, the wide optical transparency window of diamond (covering the ultraviolet to far-infrared band), especially the extremely low loss characteristics in the 1310nm / 1550nm communication band, can be used to directly construct a low-loss optical waveguide network using the diamond adapter plate 11, thereby simplifying the optical interconnect architecture and optimizing the optical signal transmission efficiency.

[0044] (4) The ultra-high hardness of diamond can be used to prepare vertical grating couplers through femtosecond laser direct writing or precision cutting processes, which can enable the efficient coupling of optical signals in three-dimensional space. At the same time, combined with the high precision of material processing, the number of optical signal couplings and coupling loss between layers can be greatly reduced.

[0045] In some embodiments, the diamond adapter plate 11 includes a first surface 111 and a second surface 112 opposite to each other; the diamond adapter plate 11 is provided with a first through hole and a second through hole penetrating the first surface 111 and the second surface 112; the first through hole and the second through hole are independently arranged. Thus, the first through hole and the second through hole are used for the transmission of optical signals and electrical signals, respectively, enabling the optoelectronic co-packaged device to complete efficient optoelectronic signal interconnection within a limited space, improving the integration and performance of the device.

[0046] As an example, such as Figure 1 and Figure 2 As shown, the first surface 111 and the second surface 112 are disposed opposite each other along the first direction, and the central axes of the first through hole and the second through hole are independently parallel to the first direction.

[0047] In some embodiments, the optoelectronic co-packaged device further includes a diamond through-hole 13, which is filled with conductive metal to form a diamond through-hole 13, and the diamond through-hole 13 is electrically connected to the diamond adapter plate 11.

[0048] Therefore, the diamond via 13 constructs a vertical conductive channel, enabling efficient electrical interconnection between different layers. This supports high-frequency electrical signal transmission while reducing signal loss and crosstalk during transmission. The design of the diamond via 13 allows optoelectronic co-packaged devices to form higher-density multilayer electrical interconnections within a limited space, thereby improving device integration and supporting complex circuit designs and functional integration. Furthermore, the conductive metal of the diamond via 13 can quickly dissipate heat generated by the electronic chip through the diamond adapter plate 11, effectively alleviating the problem of localized heat accumulation caused by high-density integration.

[0049] In some embodiments, the conductive metal includes one or more of copper and its alloys, tungsten and its alloys, silver and its alloys, nickel and its alloys, titanium and its alloys, and tantalum and its alloys.

[0050] In some embodiments, the optoelectronic co-packaged device further includes a redistribution layer located on the first surface 111 and / or the second surface 112 of the diamond adapter plate 11 and electrically connected to the diamond adapter plate 11.

[0051] Therefore, the redistribution layer can redistribute the chip's I / O interfaces to suitable locations for connection with the diamond vias 13, thereby solving the density mismatch problem when connecting the chip's I / O interfaces to external circuits, making the connection between the chip and the diamond adapter board 11 more convenient and improving the flexibility of circuit layout. At the same time, the redistribution layer can provide more wiring space, shorten the electrical signal transmission path, reduce the loss and delay of electrical signal transmission, thereby improving electrical performance. In addition, the electrical connection between the redistribution layer and the diamond adapter board 11 improves the reliability of the electrical connection between the chip and the diamond adapter board 11, thereby improving the stability and reliability of the entire device.

[0052] As an example, such as Figure 1 and Figure 2 As shown, a first redistribution layer 14 is provided on the first surface 111 of the diamond adapter plate 11, and a second redistribution layer 15 is provided on the second surface 112 of the diamond adapter plate 11. Both the first redistribution layer 14 and the second redistribution layer 15 are electrically connected to the diamond adapter plate 11.

[0053] The diamond via 13 and the redistribution layer together form the electrical signal transmission channel of the optoelectronic co-packaged device to complete the transmission of electrical signals in the vertical direction (defined as the first direction) and the horizontal direction (defined as the direction perpendicular to the first direction).

[0054] In some embodiments, the optoelectronic co-packaged device further includes an electrical chip layer; the electrical chip layer is located on the side of the redistribution layer away from the diamond adapter plate 11 and is electrically connected to the redistribution layer and / or the diamond via 13.

[0055] The electrical chip layer serves as the core processing unit, with an application-specific integrated circuit / switch chip (ASIC / Switch) handling complex logic operations and signal processing, and an electrical interface chip (EIC) responsible for receiving / transmitting electrical signals. Simultaneously, the electrical connections between the electrical chip layer, the redistribution layer, and the diamond via 13 construct an efficient electrical interconnect structure, thereby supporting high-frequency electrical signal transmission while reducing losses and crosstalk, and improving signal integrity. The electrical chip layer can support various functions such as signal processing, data conversion, and control logic, making it adaptable to different application scenarios such as LiDAR and supercomputing optical interconnects.

[0056] As an example, such as Figure 1 As shown, an ASIC / Switch 16 and an EIC 17 are disposed on the side of the first rewiring layer 14 away from the diamond adapter plate 11. Both the ASIC / Switch 16 and the EIC 17 are electrically connected to the first rewiring layer 14.

[0057] In some embodiments, the optoelectronic co-packaged device further includes a diamond waveguide via 12. A core layer 121 and a cladding layer 122 covering the outer wall of the core layer 121 are disposed within the first via, forming the diamond waveguide via 12. The refractive index of the core layer 121 is greater than that of the cladding layer 122. Thus, in the optoelectronic co-packaged device, optical components with different functions (such as lasers, modulators, detectors, etc.) are typically distributed in different layers. The diamond waveguide via 12 supports vertical optical coupling between optical components in different layers. For example, the optical signal emitted by the bottom-layer laser can be vertically coupled to the upper-layer modulator through the diamond waveguide via 12. The optical signal can propagate within the core layer 121, while being confined within the core layer 121 by the cladding layer 122, thereby reducing transmission loss.

[0058] In some embodiments, the core layer 121 comprises one or more of diamond, polymer, germanium-doped silicon dioxide, silicon carbide, silicon, and air; the cladding layer 122 comprises one or more of amorphous diamond, graphitized diamond, aluminum and its alloys, gold and its alloys, silver and its alloys, chromium and its alloys, and silicon dioxide.

[0059] As an example, such as Figure 2 As shown, the core layer 121 may include diamond, and the cladding layer 122 may include amorphous diamond and / or graphitized diamond.

[0060] As an example, such as Figure 3 As shown, the core layer 121 may include one or more of polymer, germanium-doped silicon dioxide, silicon carbide, and silicon, and the cladding layer 122 may include silicon dioxide.

[0061] As an example, such as Figure 4As shown, the core layer 121 may include air, and the cladding layer 122 may include one or more of aluminum and its alloys, gold and its alloys, silver and its alloys, and chromium and its alloys.

[0062] In some embodiments, the diamond waveguide via 12 can be circular or square. For example, when the diamond waveguide via 12 is circular, stress concentration can be reduced and the risk of material fatigue lowered, enhancing the reliability and lifespan of the via. For example, when the diamond waveguide via 12 is square, it helps provide more stable and reliable optical coupling, reducing optical signal loss.

[0063] In some embodiments, the optoelectronic co-packaged device further includes a horizontal optical waveguide 18, located on the side of the redistribution layer away from the diamond adapter plate 11. Thus, the horizontal optical waveguide 18 enables horizontal transmission of optical signals within the device, reducing signal loss and distortion during transmission, thereby improving signal quality and transmission efficiency. Simultaneously, the horizontal optical waveguide 18 can efficiently couple internal optoelectronic structures to external optical fibers, providing flexible interconnection methods to adapt to different application scenarios.

[0064] As an example, such as Figure 1 As shown, a horizontal optical waveguide 18 is provided on the surface of the first redistribution layer 14 away from the diamond adapter plate 11.

[0065] The diamond waveguide via 12 and the horizontal waveguide 18 together form the optical signal transmission channel of the optoelectronic co-packaged device to complete the transmission of optical signals in the vertical direction (defined as the first direction) and the horizontal direction (defined as the direction perpendicular to the first direction).

[0066] In some embodiments, the horizontal optical waveguide 18 includes one or more of silicon-based optical waveguides, polymer optical waveguides, glass optical waveguides, and lithium niobate optical waveguides.

[0067] In some embodiments, the optoelectronic co-packaged device further includes an optical chip layer located on the side of the redistribution layer away from the diamond adapter plate 11 and coupled to the diamond waveguide via 12 and / or the horizontal waveguide 18.

[0068] As the core optical processing unit, the optical chip layer integrates multiple optical functions such as optical modulation, optical detection, and optical amplification through a photonic integrated circuit (PIC) to achieve efficient processing and high-speed transmission of optical signals. The integrated design of the optical chip layer combines the PIC with an optical waveguide structure, enabling complex optical functions to be performed within a limited space, thereby improving the device's integration density. Furthermore, through coupling with the diamond waveguide via 12 and the horizontal waveguide 18, the optical chip layer supports flexible optical interconnection methods, adapting to the application requirements of different high-performance optical communication modules such as lidar and supercomputing optical interconnects, and meeting the requirements of high-bandwidth, low-latency, high-speed optical communication signal transmission.

[0069] As an example, such as Figure 1 As shown, a PIC 19 is disposed on the side of the first rewiring layer 14 away from the diamond adapter plate 11. One end of the horizontal waveguide 18 is coupled to the PIC 19, and the other end of the horizontal waveguide 18 can be interconnected with an external optical fiber. The side of the PIC 19 away from the first rewiring layer 14 is integrated with the EIC 17, and the EIC 17 and the PIC 19 are connected by micro-bumps.

[0070] In some embodiments, the optoelectronic co-packaged device further includes a laser, including an edge-emitting laser (EEL) and / or a vertical-cavity surface-emitting laser (VCSEL); wherein the edge-emitting laser is located on the side surface of the redistribution layer away from the diamond adapter plate 11 and is coupled to the horizontal optical waveguide 18; the vertical-cavity surface-emitting laser is located on the side surface of the diamond adapter plate 11 away from the optical chip layer and is coupled to the diamond optical waveguide via 12.

[0071] The EEL (Electronic Optical Array) boasts high output power and good beam quality, making it suitable for long-distance optical signal transmission. Through coupling with the horizontal optical waveguide 18, the EEL can efficiently couple optical signals into the horizontal waveguide 18, achieving horizontal transmission of the optical signal. The VCSEL (Vibration CSEL) offers advantages such as low power consumption, high integration, and low cost, making it suitable for short-distance optical signal transmission. Through coupling with the diamond waveguide via 12, the VCSEL can efficiently couple optical signals into the diamond waveguide via 12, achieving vertical transmission of the optical signal.

[0072] Thus, the coupling connection between the EEL and the horizontal optical waveguide 18 supports the horizontal transmission of optical signals, and the coupling connection between the VCSEL and the diamond optical waveguide via 12 supports the vertical transmission of optical signals. This flexible optical interconnection method can adapt to different application scenarios and needs.

[0073] As an example, such as Figure 1 The laser 20 (VCSEL) is located on the side surface of the diamond adapter plate 11 away from the first redistribution layer 14 and is coupled to the diamond waveguide via 12.

[0074] In some embodiments, the optoelectronic co-packaged device further includes a heat dissipation module, which includes microfluidic channels 21 embedded within the diamond adapter plate 11, and / or microjets disposed on the first surface 111 and / or the second surface 112 of the diamond adapter plate 11. Thus, the microfluidic channels 21 and / or the microjets can effectively dissipate the heat generated by the optical and electrical chips during operation, reducing the impact of thermal stress on device performance, thereby improving the overall thermal stability and reliability of the device.

[0075] As an example, such as Figure 1 As shown, the heat dissipation module includes multiple microfluidic channels 21, which are uniformly embedded in the diamond adapter plate 11 along the horizontal direction. This allows for maximum heat dissipation from the device. It is understood that the microfluidic channels 21 on the diamond adapter plate 11 are independently configured from the diamond through-holes 13 and the diamond waveguide through-holes 12.

[0076] The diamond adapter board 11 serves as an integrated carrier for the electrical module and the optical module. It simultaneously integrates a redistribution layer, diamond vias 13, a horizontal optical waveguide 18, and diamond optical waveguide vias 12, providing a foundation for efficient conversion between photoelectric signals. At the same time, relying on the ultra-high thermal conductivity of diamond, it integrates an efficient heat dissipation path to achieve high-performance thermal management functions.

[0077] In some implementations, such as Figure 1 As shown, the optoelectronic co-packaged device also includes a packaging substrate 22 and a PCB board 23. The packaging substrate 22 is located on the side of the second wiring layer 15 away from the diamond adapter plate 11, and is connected to the second wiring layer 15 through microbumps; the PCB board 23 is located on the side of the packaging substrate 22 away from the diamond adapter plate 11, and is connected to the packaging substrate 22 through microbumps.

[0078] Thus, the packaging substrate 22 provides a stable electrical connection platform for optoelectronic co-packaged devices; the PCB board 23 serves as the interface between the optoelectronic co-packaged devices and external systems, enabling the devices to be connected to external power supplies, control signals, or data transmission devices.

[0079] In a second aspect, this application provides a method for fabricating an optoelectronic co-packaged device, including fabricating a diamond waveguide via 12. The method for fabricating the diamond waveguide via 12 includes: forming a diamond waveguide via 12 by providing a core layer 121 and a cladding layer 122 covering the outer wall of the core layer 121 within a first via. Thus, by providing the core layer 121 and the cladding layer 122 within the first via of the diamond adapter plate 11 to form the diamond waveguide via 12, optical signals can propagate within the core layer 121, while the optical signals are confined within the core layer 121 by the cladding layer 122, thereby reducing the transmission loss of the optical signals.

[0080] In some implementations, such as Figure 2 As shown, the position of the core layer 121 is selected on the surface of the diamond adapter plate 11; the diamond adapter plate 11 surrounding the outer region of the core layer 121 is subjected to femtosecond laser processing to form a cladding 122; one end of the core layer 121 is located on the first surface 111 of the diamond adapter plate 11, and the other end of the core layer 121 is located on the second surface 112.

[0081] Femtosecond laser processing induces local amorphization or graphitization within diamond through multiphoton absorption and avalanche ionization mechanisms, forming refractive index modulation regions. The diamond crystalline structure in these modulation regions is destroyed by the laser energy, resulting in a decrease in the refractive index of the diamond compared to the untreated state. At this point, the original diamond region that has not been treated by the laser serves as the core layer 121, and the modified amorphized or graphitized region serves as the cladding layer 122. The difference in refractive index between the two forms a graded refractive index waveguide structure.

[0082] Femtosecond laser-treated diamond can be annealed at high temperatures in an argon atmosphere to eliminate the amorphous carbon phase induced by the laser treatment and restore part of the diamond lattice, thereby reducing scattering centers. The modified region still retains some amorphization or graphitization characteristics, and its refractive index is still lower than that of natural diamond.

[0083] As an example, femtosecond laser processing satisfies at least one of the following parameters:

[0084] The laser wavelength is 800nm ​​or 1030nm;

[0085] Pulse width less than 300 fs;

[0086] The repetition frequency is 100kHz-1MHz;

[0087] The focusing NA is 0.65-1.4;

[0088] The focusing depth is 20μm-100μm.

[0089] As an example, the pulse width can be 50fs, 100fs, 150fs, 200fs, 250fs, 300fs, etc., or a range consisting of any two of the above values.

[0090] As an example, the repetition frequency can be 100kHz, 200kHz, 300kHz, 400kHz, 500kHz, 600kHz, 700kHz, 800kHz, 900kHz, 1MHz, etc., or a range consisting of any two of the above values.

[0091] As an example, the focal length NA can be 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1, 1.05, 1.1, 1.15, 1.2, 1.25, 1.3, 1.35, 1.4, etc., or a range consisting of any two of the above values.

[0092] As an example, the focusing depth can be 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, etc., or a range consisting of any two of the above values.

[0093] In some embodiments, the steps prior to femtosecond laser processing include: cleaning the diamond surface, specifically: selecting type IIa single-crystal diamond (type IIa single-crystal diamond has low impurity content and high optical transparency); and subjecting the diamond surface to oxygen plasma treatment to remove residual hydrocarbons on the diamond surface and activate the surface.

[0094] In some embodiments, the oxygen plasma treatment power is 10W-200W, and the oxygen plasma treatment time is 1min-20min.

[0095] As an example, the power of oxygen plasma treatment can be 10W, 20W, 30W, 40W, 50W, 60W, 70W, 80W, 90W, 100W, 110W, 120W, 130W, 140W, 150W, 160W, 170W, 180W, 190W, 200W, etc., or a range of any two of the above values.

[0096] As an example, the oxygen plasma treatment time can be 1 min, 2 min, 3 min, 4 min, 5 min, 6 min, 7 min, 8 min, 9 min, 10 min, 11 min, 12 min, 13 min, 14 min, 15 min, 16 min, 17 min, 18 min, 19 min, 20 min, etc., or a range of any two of the above values.

[0097] In some implementations, such as Figure 3 As shown, a first through-hole penetrating the first surface 111 and the second surface 112 is formed on the diamond adapter plate 11; silicon dioxide is deposited on the inner wall of the first through-hole to form a cladding layer 122; the region within the cladding layer 122 is filled with one or more of polymer, germanium-doped silicon dioxide, silicon carbide, and silicon to form a core layer 121. At this time, the core layer 121 is one or more of polymer, germanium-doped silicon dioxide, silicon carbide, and silicon, and the cladding layer 122 is silicon dioxide.

[0098] In some implementations, such as Figure 4As shown, a first through-hole penetrating the first surface 111 and the second surface 112 is formed on the diamond adapter plate 11; a reflective metal is deposited on the inner wall of the first through-hole to form a cladding 122; the reflective metal includes one or more of aluminum and its alloys, gold and its alloys, silver and its alloys, and chromium and its alloys. At this time, the core layer 121 is air, and the cladding 122 is one or more of aluminum and its alloys, gold and its alloys, silver and its alloys, and chromium and its alloys.

[0099] In some embodiments, a method for fabricating an optoelectronic co-packaged device further includes fabricating a horizontal optical waveguide 18; combined with Figure 5 The method for fabricating the horizontal optical waveguide 18 includes the following steps:

[0100] S100. The diamond surface is subjected to chemical mechanical polishing to reduce the roughness of the diamond surface and reduce light scattering loss; then the diamond surface is subjected to oxygen plasma treatment to enhance the activity of the diamond surface, so as to obtain pretreated diamond.

[0101] S200. A silicon dioxide layer is grown on the pretreated diamond surface using plasma-enhanced chemical vapor deposition (PECVD) as the lower cladding layer 183; then a silicon nitride layer is deposited on the silicon dioxide layer surface using low-pressure chemical vapor deposition (LPCVD).

[0102] S300: A photoresist layer is coated on the surface of a silicon nitride layer using spin coating; then, a waveguide pattern is defined using an electron beam direct writing system, and the photoresist in the non-waveguide areas is exposed; finally, the photoresist in the exposed areas is removed using tetramethylammonium hydroxide solution.

[0103] S400. Using dry or wet etching, a ridge structure is selectively etched to form a horizontal waveguide core layer 182.

[0104] S500. A silicon dioxide layer with a thickness of 2μm is deposited on the surface of the horizontal optical waveguide core layer 182 by PECVD, which is the upper cladding 181. The upper cladding 181 is subjected to chemical mechanical polishing to planarize the surface of the upper cladding 181. The upper cladding 181, the horizontal optical waveguide core layer 182, and the lower cladding 183 together form the horizontal optical waveguide 18.

[0105] In some embodiments, a method for fabricating an optoelectronic co-packaged device further includes fabricating a horizontal optical waveguide 18; the method for fabricating the horizontal optical waveguide 18 includes:

[0106] A horizontal waveguide core layer 182 region is selected in the diamond adapter plate 11, extending horizontally. The upper and lower regions of the horizontal waveguide core layer 182 in the vertical direction are subjected to femtosecond laser processing to form an upper cladding layer 181 and a lower cladding layer 183, respectively. The diamond in the femtosecond laser-processed regions of the upper and lower cladding layers 181 and 183 induces defect states or stress zones, thereby controlling the refractive index so that the refractive indices of both the upper and lower cladding layers 181 and 183 are lower than the refractive index of the horizontal waveguide core layer 182 region. Therefore, optical signals can propagate horizontally within the horizontal waveguide core layer 182, while the optical signals are confined within the horizontal waveguide core layer 182 by the upper and lower cladding layers 181 and 183, thus reducing transmission loss.

[0107] As an example, femtosecond laser processing satisfies at least one of the following parameters:

[0108] The laser wavelength is 800nm ​​or 1030nm;

[0109] Pulse width less than 300 fs;

[0110] The repetition frequency is 100kHz-1MHz;

[0111] The focusing NA is 0.65-1.4;

[0112] The focusing depth is 20μm-100μm.

[0113] As an example, the pulse width can be 50fs, 100fs, 150fs, 200fs, 250fs, 300fs, etc., or a range consisting of any two of the above values.

[0114] As an example, the repetition frequency can be 100kHz, 200kHz, 300kHz, 400kHz, 500kHz, 600kHz, 700kHz, 800kHz, 900kHz, 1MHz, etc., or a range consisting of any two of the above values.

[0115] As an example, the focal length NA can be 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1, 1.05, 1.1, 1.15, 1.2, 1.25, 1.3, 1.35, 1.4, etc., or a range consisting of any two of the above values.

[0116] As an example, the focusing depth can be 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, etc., or a range consisting of any two of the above values.

[0117] It should be noted that this application is not limited to the above-described embodiments. The above embodiments are merely examples, and any embodiments with the same structure and effect as the technical concept within the scope of this application are included in the technical scope of this application. Furthermore, various modifications that can be conceived by those skilled in the art to the embodiments, and other ways of constructing by combining some of the constituent elements of the embodiments, without departing from the spirit of this application, are also included in the scope of this application.

Claims

1. A photoelectric co-packaged device, characterized in that, include: A diamond adapter plate, comprising a first surface and a second surface opposite to each other; the diamond adapter plate is provided with a first through hole and a second through hole penetrating the first surface and the second surface; the first through hole and the second through hole are independently provided. A diamond waveguide via, wherein a core layer and a cladding layer covering the outer wall of the core layer are disposed in the first via, forming the diamond waveguide via, wherein the refractive index of the core layer is greater than the refractive index of the cladding layer; A diamond through-hole is formed by filling the second through-hole with conductive metal, and the diamond through-hole is electrically connected to the diamond adapter plate.

2. The optoelectronic co-packaged device according to claim 1, characterized in that, The core layer comprises one or more of diamond, polymer, germanium-doped silicon dioxide, silicon carbide, silicon, and air; the cladding layer comprises one or more of amorphous diamond, graphitized diamond, aluminum and its alloys, gold and its alloys, silver and its alloys, chromium and its alloys, and silicon dioxide; and / or, The conductive metal includes one or more of the following: copper and its alloys, tungsten and its alloys, silver and its alloys, nickel and its alloys, titanium and its alloys, and tantalum and its alloys.

3. The optoelectronic co-packaged device according to claim 1 or 2, characterized in that, It also includes a redistribution layer, which is located on the first surface and / or the second surface of the diamond adapter plate and is electrically connected to the diamond adapter plate.

4. The optoelectronic co-packaged device according to claim 3, characterized in that, It also includes a horizontal optical waveguide located on the side surface of the redistribution layer away from the diamond adapter plate.

5. The optoelectronic co-packaged device according to claim 4, characterized in that, It also includes electrical chip layers and optical chip layers; The electrical chip layer is located on the side of the redistribution layer away from the diamond adapter plate, and is electrically connected to the redistribution layer and / or the diamond via. The optical chip layer is located on the side of the redistribution layer away from the diamond adapter plate, and is coupled to the diamond waveguide via and / or the horizontal waveguide.

6. The optoelectronic co-packaged device according to claim 5, characterized in that, It also includes lasers, which include edge-emitting lasers and / or vertical-cavity surface-emitting lasers; wherein, The edge-emitting laser is located on the side of the redistribution layer away from the diamond adapter plate and is coupled to the horizontal waveguide. The vertical cavity surface-emitting laser is located on the side of the diamond adapter plate away from the optical chip layer and is coupled to the diamond waveguide via.

7. The optoelectronic co-packaged device according to claim 1, characterized in that, It also includes a heat dissipation module, which includes microfluidic channels embedded inside the diamond adapter plate, and / or includes microjet components disposed on the first surface and / or the second surface of the diamond adapter plate.

8. A method for preparing the optoelectronic co-packaged device according to any one of claims 1-7, characterized in that, This includes fabricating the diamond waveguide via; The method for preparing the diamond waveguide via includes: providing a core layer and a cladding layer covering the outer wall of the core layer in the first via to form the diamond waveguide via.

9. The method according to claim 8, characterized in that, Select the core layer position on the surface of the diamond adapter plate; The diamond adapter plate surrounding the outer region of the core layer is subjected to femtosecond laser processing to form the cladding; one end of the core layer is located on the first surface of the diamond adapter plate, and the other end of the core layer is located on the second surface.

10. The method according to claim 8, characterized in that, The diamond adapter plate has a first through hole that penetrates the first surface and the second surface; A reflective metal is deposited on the inner wall of the first through-hole to form the cladding; the reflective metal includes one or more of aluminum and its alloys, gold and its alloys, silver and its alloys, and chromium and its alloys; and / or, Silicon dioxide is deposited on the inner wall of the first through-hole to form the cladding; the region within the cladding is filled with one or more of polymer, germanium-doped silicon dioxide, silicon carbide, and silicon to form the core layer.

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