PCIe ATE test method and system based on JTAG
CN120469868APending Publication Date: 2025-08-12WUHAN LINGJIU MICROELECTRONICS CO LTD
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Patent Information
- Application Number
- CN202510546381.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-28
- Publication Date
- 2025-08-12
AI Technical Summary
Technical Problem
In existing PCIe ATE tests, it is necessary to manually adjust the effective starting position of the output response signal, resulting in low testing efficiency, especially during the mass production test stage.
Method used
By recording the waiting delay information and bit delay information before the test, generating configuration files, controlling the ATE test equipment to output the enable signal at a specified time point, automatically locate the starting position of the output response signal, and masking data bits that do not need to be compared during the mass production test stage, reducing manual adjustments.
Benefits of technology
It improves the accuracy of test ratio alignment, reduces the workload of test engineers, and greatly improves testing efficiency.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN120469868A_ABST
Abstract
The invention is suitable for the technical field of ATE testing, and provides a PCIe ATE testing method and system based on JTAG, and the method comprises the steps: extracting waiting delay information of each output response data and bit delay information of each data bit according to a simulation excitation file before testing, and generating a corresponding configuration file, and taking the input simulation excitation file and the configuration file as test vectors, simultaneously importing the test vectors into the ATE test equipment, and automatically acquiring output data at a time point corresponding to the delay information of the configuration file by the ATE test equipment for comparison. Through the method, the comparison accuracy is improved, the workload of manual adjustment of a test engineer is greatly reduced, and the test efficiency is greatly improved.
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